Sanyo ENA1227 Cmos ic 2-cell lithium-ion secondary battery protection ic Datasheet

Ordering number : ENA1227
CMOS IC
LV51130T
2-Cell Lithium-Ion Secondary Battery
Protection IC
Overview
The LV51130T is a protection IC for 2-cell lithium-ion secondary batteries.
Features
• Monitoring function for each cell:
• High detection voltage accuracy:
• Hysteresis cancel function:
• Discharge current monitoring function:
• Low current consumption:
• 0V cell charging function:
Detects overcharge and over-discharge conditions and controls the
charging and discharging operation of each cell.
Over-charge detection accuracy
±25mV
Over-discharge detection accuracy ±100mV
The hysteresis of over-discharge detection voltage is made small by
sensing the connection of a load after overcharging has been detected.
Detects over-currents, load shorting, and excessively high voltage of a
charger and regulates charging and discharging operations.
Normal operation mode typ. 6.0µA
Stand by mode
max. 0.2µA
Charging is enabled even when the cell voltage is 0V by giving a
potential difference between the VDD pin and V- pin.
Any and all SANYO Semiconductor Co.,Ltd. products described or contained herein are, with regard to
"standard application", intended for the use as general electronics equipment (home appliances, AV equipment,
communication device, office equipment, industrial equipment etc.). The products mentioned herein shall not be
intended for use for any "special application" (medical equipment whose purpose is to sustain life, aerospace
instrument, nuclear control device, burning appliances, transportation machine, traffic signal system, safety
equipment etc.) that shall require extremely high level of reliability and can directly threaten human lives in case
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Specifications of any and all SANYO Semiconductor Co.,Ltd. products described or contained herein stipulate
the performance, characteristics, and functions of the described products in the independent state, and are not
guarantees of the performance, characteristics, and functions of the described products as mounted in the
customer' s products or equipment. To verify symptoms and states that cannot be evaluated in an independent
device, the customer should always evaluate and test devices mounted in the customer' s products or
equipment.
60408 MS PC 20080522-S00003 No.A1227-1/8
LV51130T
Specifications
Absolute Maximum Ratings at Ta = 25°C
Parameter
Power supply voltage
Symbol
Conditions
Ratings
VDD
Input voltage
Unit
-0.3 to +12
V
V-
VDD-28 to VDD+0.3
V
Vcout
VDD-28 to VDD+0.3
V
Charger minus voltage
Output voltage
Cout pin voltage
Dout pin voltage
Allowable power dissipation
Vdout
Pd max
VSS-0.3 to VDD+0.3
Independent IC
170
V
mW
Operating ambient temperature
Topr
-30 to +85
°C
Storage temperature
Tstg
-40 to +125
°C
Electrical Characteristics at Ta = 25°C, unless especially specified.
Parameter
Symbol
Conditions
Operation input voltage
Vcell
Between VDD and VSS
0V cell charging minimum operation
Vmin
Between VDD-VSS =0 and VDD-V-
Ratings
min
typ
Unit
max
1.5
10
V
1.5
V
voltage
Over-charge detection voltage
Vd1
Over-charge reset voltage
Vh1
4.325
4.350
4.375
V
VM ≤ Vd3
4.100
4.150
4.200
V
VM > Vd3
4.250
4.360
V
Over-charge detection delay time
td1
VDD-Vc=3.5V→4.5V, Vc-VSS=3.5V
0.5
1.0
1.5
s
Over-charge reset delay time
tr1
VDD-Vc=4.5V→3.5V, Vc-VSS=3.5V
20.0
40.0
60.0
ms
Over-discharge detection voltage
Vd2
2.20
2.30
2.40
V
Over-discharge reset hysteresis voltage
Vh2
10.0
20.0
40.0
mV
Over-discharge detection delay time
td2
VDD-Vc=3.5V→2.2V, Vc-VSS=3.5V
50
100
150
ms
Over-discharge reset delay time
tr2
VDD-Vc=2.2V→3.5V, Vc-VSS=3.5V
0.5
1.0
1.5
ms
0.28
0.30
0.32
V
mV
Over-current detection voltage
Vd3
VDD-Vc=3.5V, Vc-VSS=3.5V
Over-current reset hysteresis voltage
Vh3
VDD-Vc=3.5V, Vc-VSS=3.5V
5.0
10.0
20.0
Over-current detection delay time
td3
VDD-Vc=3.5V, Vc-VSS=3.5V
10.0
20.0
30.0
ms
Over-current reset delay time
tr3
VDD-Vc=3.5V, Vc-VSS=3.5V
0.5
1.0
1.5
ms
Short circuit detection voltage
Vd4
VDD-Vc=3.5V, Vc-VSS=3.5V
1.0
1.3
1.6
V
Short circuit detection delay time
td4
VDD-Vc=3.5V, Vc-VSS=3.5V
0.125
0.25
0.50
ms
Over-charger detection voltage
Vd5
Between VDD-Vc=3.5V, Vc-VSS=3.5V
(V-)-VSS
-0.60
-0.45
-0.30
V
Overcharge reset hysteresis voltage
Vh5
VDD-Vc=3.5V, Vc-VSS=3.5V
mV
Standby reset voltage
Vstb
Between VDD-Vc=2.0V, Vc-VSS=2.0V
(V-)-VSS
Excessively high voltage charger
td5
VDD-Vc=3.5V, Vc-VSS=3.5V
detection delay time
Excessively high voltage charger reset
25.0
50.0
100.0
VDD×0.4
VDD×0.5
VDD×0.6
0.5
1.5
3.0
ms
0.5
1.5
3.0
ms
V
*
tr5
VDD-Vc=3.5V, Vc-VSS=3.5V
delay time
Reset resistance (connected to VDD)
RDD
100
200
400
kΩ
Reset resistance (connected to VSS)
RSS
15
30
60
kΩ
Cout Nch ON voltage
VOL1
IOL=50µA, VDD-Vc=4.4V, Vc-VSS=4.4V
0.5
V
Cout Pch ON voltage
VOH1
IOL=50µA, VDD-Vc=3.9V, Vc-VSS=3.9V
Dout Nch ON voltage
VOL2
IOL=50µA, VDD-Vc=2.2V, Vc-VSS=2.2V
Dout Pch ON voltage
VOH2
IOL=50µA, VDD-Vc=3.9V, Vc-VSS=3.9V
VDD-0.5
V
0.5
VDD-0.5
V
V
Vc input current
Ivc
VDD-Vc=3.5V, Vc-VSS=3.5V
0.0
1.0
µA
Current drain
IDD
VDD-Vc=3.5V, Vc-VSS=3.5V
6.0
13.0
µA
Standby current
Istb
VDD-Vc=2.2V, Vc-VSS=3.5V
0.2
µA
Vtest
VDD-Vc=3.5V, Vc-VSS=3.5V
VDD×0.6
V
T-terminal input ON voltage
VDD×0.4
VDD×0.5
* Upon connecting to charger upon over-discharge, the delay time after recovery from over-discharge.
No.A1227-2/8
LV51130T
Package Dimensions
unit : mm (typ)
3245B
Pd max -- Ta
Allowable power dissipation, Pd max -- mW
200
3.0
0.5
3.0
4.9
8
1
(0.53)
2
0.65
0.125
1.1MAX
(0.85)
0.25
Independent IC
170
150
100
68
50
0
-30 -20
0
20
40
60
80
100
0.08
Ambient temperature, Ta -- °C
SANYO : MSOP8(150mil)
Pin Assignment
Dout
T
8
7
1
2
VDD Cout
Vc Sense
6
5
3
V-
4
Top view
VSS
Pin Functions
Pin No.
1
Symbol
VDD
Description
VDD pin
2
Cout
Overcharge detection output pin
3
V-
Charger minus voltage input pin
4
VSS
VSS pin
5
Sense
Sense pin
6
Vc
Intermediate voltage input pin
7
T
Pin to shorten detection time (“H”:Shortening mode, “L”:Normal mode)
8
Dout
Overdischarge detection output pin
No.A1227-3/8
LV51130T
Block Diagram
Sence
5
VDD
1
Level shift
+
-
+
+
-
Vc 6
td5,tr5
2 Cout
td1,tr1
Delay
control
logic
+
-
td2,tr2
8 Dout
+
+
-
td3,tr3
+
-
4
VSS
3
V-
td4
7
T
No.A1227-4/8
LV51130T
Functional Description
Over-charge detection
If either of the cell voltage is equal to or more than the over-charge detection voltage, stop further charging by
turning “L” the Cout pin and turning off external Nch MOS FET after the over-charge detection delay time. This
delay time is set by the internal counter.
The over-charge detection comparator has the hysteresis function. Note that this hysteresis can be cancelled by
connecting the load after detection of over-charge detection. and it becomes small to hysteresis peculiar to a
comparator.
Over-charge release
If both cell voltages become equal to or less than the over-charge release voltage (VM ≤ Vd3) when charger is
connected, or if it become equal to or less than the over-charge release voltage (VM > Vd3) when load is connected,
the Cout pin returns to “H” after the over-charge release delay time set by the internal counter.
When load is connected and either cell or both cell voltages are equal to or more than the over-charge release voltage
(VM > Vd3), the Cout pin does not return to “H”. But the load current flows through the parasitic diode of external
Nch MOS FET on Cout, consequently each cell voltage becomes equal to or less than over-charge release voltage,
(VM > Vd3) the Cout pin returns to “H.” after the over-charge release delay time.
However, excessive voltage charger is connected as mentioned below, Cout pin does not return to “H” because
excessive charger detection starts after over-charge release operation.
Over-discharge detection
When either cell voltage is equal to or less than over-discharge voltage, the IC stops further discharging by turning
the Dout pin “L” and turning off external Nch MOS FET after the over-charge detection delay time.
The IC goes into stand-by mode after detecting over-discharge and its consumption current is kept at about 0A. After
over-discharge detection, the V- pin will be connected to VDD pin via internal resistor (typ 200kΩ).
Over-discharge release
Release from over-discharge is made by only connecting charger. If the V- pin voltage becomes equal to or lower
than the stand-by release voltage by connecting charger after detecting over-discharge, The IC is released from the
stand-by state to start cell voltage monitoring. If both cell voltages become equal to or more than the over-discharge
detection voltage by charging, the Dout pin returns to “H” after the over-discharge release delay time set by the
internal counter.
Over-current detection
When excessive current flows through the battery, the V- pin voltage rises by the ON resister of external MOS FET
and becomes equal to or more than the over-current detection voltage, the Dout pin turns to “L” after the over-current
detection delay time and the external Nch MOS FET is turned off to prevent excessive current in the circuit. The
detection delay time is set by the internal counter. After detection, the V- pin will be connected to VSS via internal
resistor (typ 30kΩ). It will not go into stand-by mode after detecting over-current.
Short circuit detection
If greater discharging current flows through the battery and the V- pin voltage becomes equal to or more than the
short-circuit detection voltage, it will go into short-circuit detection state after the short circuit delay time shorter than
the over-current detection delay time. When short-circuit is detected, just like the time of over-current detection, the
Dout pin turns to “L” and external Nch MOS FET is turned off to prevent high current in the circuit. The V- pin will
be connected to VSS after detection via internal resistor (typ. 30kΩ). It will not go into stand-by mode after detecting
short circuit.
Over-current/short-detection release
After detecting over-current or short circuit, the internal resistor (typ. 30kΩ) between V- pin and VSS pin becomes
effective. If the load resistor is removed, the V- pin voltage will be pulled down to the VSS level. Thereafter, the IC
will be released from the over-current/short-circuit detection state when the V- pin voltage becomes equal to or less
than the over-current detection voltage, and the Dout pin returns to “H” after over-current release delay time set by
the internal counter.
No.A1227-5/8
LV51130T
Excessive charger detection/release
If the voltage between V- pin and VSS pin becomes equal to or less than the excessive charger detection voltage by
connecting a charger, no charging can be made by turning the Cout pin “L” after delay time and turning off the
external Nch MOS FET. If that voltage returns to equal to or more than the excessive charger detection voltage
during detection delay time, the excessive charger detection will be stopped. If the voltage between V- pin and VSS
pin becomes equal to or more than the excessive charger detection voltage after excessive charger detection, the Cout
returns to “H” after delay time. The detection/return delay time is set internally.
If Dout pin is “L”, charging will be made through the parasitic diode of external Nch FET on Dout pin. In that case,
the voltage between V- pin and VSS pin is nearly -Vf which is less than the over-charger detection voltage, therefore
no excessive charger detection will be made during over-discharge, over-current and short-circuit detection.
Furthermore, if excessive voltage charger is connected to the over-discharged battery, no excessive charger detection
is made while the Dout pin is “L”. But the battery is continued charging through the parasitic diode. If the battery
voltage rises to the over-discharge detection voltage and the voltage between V- pin and VSS pin remains equal to or
less than the excessive charger detection voltage, the delay operation will be started after Dout pin turns to “H.”
0V cell charging operation
If voltage between VDD and V becomes equal to or more than the 0V cell charging lowest operation voltage when
the cell voltage is 0V, the Cout pin turns to “H” and charging is enabled.
Shorten the test time
By turning T pin to the VDD , the delay times set by the internal counter can be cut. If T pin is open, the delay times
are normal. Delay time not set by the counter just like as short circuit detection delay cannot be controlled by this pin.
And we recommend that T pin is connected to VSS to prevent malfunction when excessive current flows in short
circuit operation.
Operation in case of detection overlap
Operation in case of
detection overlap
Overlap state
State after detection
When, during over-
Over-discharge
Over-charge detection is preferred. If over-
When over-charge detection is made first, V- is
charge detection,
detection is made,
discharge state continues even after over-
released. When over-discharge is detected after
charge detection, over-discharge detection is
resumed.
over-charge detection, the standby state is not
effectuated. Note that V- is connected to VDD
via 200kΩ.
Over-current
(*1) Both detections’ can be made in parallel.
(*2) When over-current is detected first, V- is
detection is made,
Over-charge detection continues even when the
connected to VSS via 30kΩ. When over-charge
detection is made first, V- is released.
over-current state occurs. If the over-charge
state occurs first, over-current detection is
interrupted.
When, during over-
Over-charge detection
Over-discharge detection is interrupted and
The standby state is not effectuated when over-
discharge detection,
is made,
over-charge detection is preferred. When over-
discharge detection is made after over-charge
detection. Note that V- is connected to VDD via
200kΩ.
discharge state continues even after overcharge detection, over-discharge detection is
resumed.
Over-current
(*3) Both detections can be made in parallel.
(*4) If over-current is detected in advance, V will
detection is made,
Over-discharge detection continues even when
be connected to VSS via 30kΩ. After detecting
the over-current state is effectuated first. Over-
over-discharge, V will be connected to VDD via
current detection is interrupted when the over-
200kΩ to get into standby state. If over-
discharge state is effectuated first,
discharge is detected in advance, V will be
connected to VDD via 200kΩ to get into standby
state.
When, during over-
Over-charge detection
current detection,
is made,
Over-discharge
(*1)
(*2)
(*3)
(*4)
detection is made,
(Note) Short-circuit detection can be made independently.
Over-charger detection does not work during over-discharge, over-current or short-circuit detection and
the delay time starts after return from these states.
No.A1227-6/8
LV51130T
Timing Chart
[Cout Output System]
Charger
connection
Hysteresis cancellation
by load connection
Load
connection
Charger
connection
Load
connection
Over-charger
connection
Charger
connection
Load
connection
Vd1
Vr1
Charging recovery
depends on charger voltage
when connecting charger.
VDD Vd2
VDD
Discharging via FETparasite Di
Vd4
V-
Discharging via FETparasite Di
Vd3
VSS
Vd5
VDD
td1
Cout
tr1
td1
tr1
td5
tr5
VOver-charge detection state
Over-charge detection state
Over-charger detection state
[Dout Output System]
Load
connection
Charger
connection
Load
connection
Load
connection
Over-current
occurrence
Load
connection
Over-charger
connection
Load short-circuit
occurrence
Vd1
Vr1
VDD Vd2
To standby
To standby
VDD
Vd4
V-
Vd3
VSS
Vd5
Charging via FETparasite Di
VDD
Dout
td2
tr2
td3
tr3
td4
tr3
td2
tr2
VSS
Over-discharge detection state
Over-current detection state
Short-circuit detection state
VDD
Cout
V-
Over-charger detection
upon charging over-discharged
battery is activated after return
from over-charge.
td5
No.A1227-7/8
LV51130T
Application Circuit Example
+
R4
R1
C1
VDD
Sense
C3
T
R2
Vc
C2
VSS
LV51130T
V-
VSS
Dout
Cout
R3
−
Components
Recommended value
max
unit
R1, R2
100
1k
Ω
R3
2k
4k
Ω
R4
100
10k
Ω
C1, C2, C3
0.1µ
1µ
F
* These numbers don't mean to guarantee the characteristic of the IC.
* In addition to the components in the upper diagram, it is necessary to insert a capacitor with enough capacity between
VDD and VSS of the IC as near as possible to stabilize the power supply voltage to the IC.
SANYO Semiconductor Co.,Ltd. assumes no responsibility for equipment failures that result from using
products at values that exceed, even momentarily, rated values (such as maximum ratings, operating condition
ranges, or other parameters) listed in products specifications of any and all SANYO Semiconductor Co.,Ltd.
products described or contained herein.
SANYO Semiconductor Co.,Ltd. strives to supply high-quality high-reliability products, however, any and all
semiconductor products fail or malfunction with some probability. It is possible that these probabilistic failures or
malfunction could give rise to accidents or events that could endanger human lives, trouble that could give rise
to smoke or fire, or accidents that could cause damage to other property. When designing equipment, adopt
safety measures so that these kinds of accidents or events cannot occur. Such measures include but are not
limited to protective circuits and error prevention circuits for safe design, redundant design, and structural
design.
In the event that any or all SANYO Semiconductor Co.,Ltd. products described or contained herein are
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No part of this publication may be reproduced or transmitted in any form or by any means, electronic or
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Any and all information described or contained herein are subject to change without notice due to
product/technology improvement, etc. When designing equipment, refer to the "Delivery Specification" for the
SANYO Semiconductor Co.,Ltd. product that you intend to use.
Information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed
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Upon using the technical information or products described herein, neither warranty nor license shall be granted
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party. SANYO Semiconductor Co.,Ltd. shall not be liable for any claim or suits with regard to a third party's
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This catalog provides information as of June, 2008. Specifications and information herein are subject
to change without notice.
PS No.A1227-8/8
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