SBAS279D − AUGUST 2003 − REVISED JULY 2005
FEATURES
D Dual, 12-Bit, 40MSPS Current Output DAC
D Four 12-Bit Voltage Output DACs—for
Transmit Control
D Single +3V Operation
D Very Low Power: 29mW
D High SFDR: 75dB at fOUT = 5MHz
D Low-Current Standby or Full Power-Down
Modes
D Internal Reference
D Optional External Reference
D Adjustable Full-Scale Range: 0.5mA to 2mA
APPLICATIONS
D Transmit Channels
D
D
D
− I and Q
− PC Card Modems: GPRS, CDMA
− Wireless Network Cards (NICs)
Signal Synthesis (DDS)
Portable Medical Instumentation
Arbitrary Waveform Generation (AWG)
DESCRIPTION
The DAC2932 is a dual 12-bit, current-output
digital-to-analog converter (DAC) designed to combine the
features of high dynamic range and very low power
consumption. The DAC2932 converter supports update
rates of up to 40MSPS. In addition, the DAC2932 features
four 12-bit voltage output DACs, which can be used to
perform system control functions.
The advanced segmentation architecture of the DAC2932
is optimized to provide a high spurious-free dynamic range
(SFDR).
The DAC2932 has a high impedance (> 200kΩ) differential
current output with a nominal range of 2mA and a
compliance voltage of up to 0.8V. The differential outputs
allow for either a differential or single-ended analog signal
interface. The close matching of the current outputs
ensures superior dynamic performance in the differential
configuration, which can be implemented with a
transformer. Using a small geometry CMOS process, the
monolithic DAC2932 is designed to operate within a
single-supply range of 2.7V to 3.3V. Low power
consumption makes it ideal for portable and
battery-operated systems. Further optimization by
lowering the output current can be realized with the
adjustable full-scale option. The full-scale output current
can be adjusted over a span of 0.5mA to 2mA.
For noncontinuous operation of the DAC2932, a full
power-down mode can reduce the power dissipation to as
little as 25μW.
The DAC2932 is designed to operate with a single parallel
data port. While it alternates the loading of the input data
into separate input latches for both current output DACs
(I-DACs), the updating of the analog output signal occurs
simultaneously. The DAC2932 integrates a temperature
compensated 1.22V bandgap reference. The DAC2932
also allows for additional flexibility of using an external reference.
The DAC2932 is available in a TQFP-48 package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments
semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
Copyright © 2003−2005, Texas Instruments Incorporated
!"# ! $% & ' & $ () ' * + *' &
'$% &(' $ ' & ( , %& $ !-& "& % & & ** . /+
*' ('&& *& '&& / '* & $ (% &+
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SBAS279D − AUGUST 2003 − REVISED JULY 2005
ORDERING INFORMATION
PRODUCT
PACKAGE-LEAD
PACKAGE
DESIGNATOR(1)
SPECIFIED
TEMPERATURE
RANGE
PACKAGE
MARKING
DAC2932
TQFP 48
TQFP-48
PFB
−40°C
40°C to +85°C
85°C
DAC2932
ORDERING
NUMBER
TRANSPORT
MEDIA, QUANTITY
DAC2932PFBT
Tape and Reel, 250
DAC2932PFBR
Tape and Reel, 2000
(1) For the most current specification and package information, refer to our web site at www.ti.com.
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range unless otherwise noted
+VA to AGND
+VD to DGND
AGND to DGND
DAC2932
UNIT
−0.3 to +4
V
−0.3 to +4
V
−0.2 to +0.2
V
+VA to +VD
CLK, PD, STBY, CS to DGND
−0.7 to +0.7
V
−0.3 to VD + 0.3
V
D0−D11 to DGND
−0.3 to VD + 0.3
V
IOUT, IOUT to AGND
REFV to AGNDV
−0.5 to VA + 0.3
V
−0.3 to VAV + 0.3
V
GSET, REFIN, FSA to AGND
−0.3 to VA + 0.3
V
VOUTx to AGNDV
DIN to DGNDV
−0.3 to VAV + 0.3
V
Junction temperature
Case temperature
Storage temperature range
This integrated circuit can be damaged by ESD. Texas
Instruments recommends that all integrated circuits be
handled with appropriate precautions. Failure to observe
proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to
complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could
cause the device not to meet its published specifications.
−0.3 to VDV + 0.3
V
+150
°C
+100
°C
−40 to +150
°C
FUNCTIONAL BLOCK DIAGRAM
REFIN
STBY
GSET
+1.22V Reference
FSA1
FSA2
+VA
AGND
+VD
DGND
DAC2932
Reference Control Amp
CS
Parallel Data Input,
[D11:D0]
Data1
Clock
Input Latch
and
De−Multiplexer
PD
CLK
12−Bit Data,
Interleaved
CLK1
Data2
CLK2
DAC
Latch 1
12−Bit
40MSPS
I−DAC1
IOUT1
DAC
Latch 2
12−Bit
40MSPS
I−DAC2
IOUT2
I−DAC Section
DIN
SCLK
SYNC
Serial−to−Parallel
Shift Register
12
IOUT2
V−DAC Section
Dx
A0
Latch
12−Bit
String−DAC1
A1
Latch
12−Bit
String−DAC2
A
VOUT2
A2
Latch
12−Bit
String−DAC3
A
VOUT3
A3
Latch
12−Bit
String−DAC4
A
VOUT4
REFV
2
IOUT1
PDV
A
VOUT1
+VDV DGNDV +VAV AGNDV
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SBAS279D − AUGUST 2003 − REVISED JULY 2005
ELECTRICAL CHARACTERISTICS: I-DAC
At TA = TMIN to TMAX (typical values are at TA = 25°C), +VA = +3V, +VD = +3V, Update Rate = 40MSPS, IOUTFS = 2mA, RL = 250Ω, CL ≤ 10pF,
GSET = H, and internal reference, unless otherwise noted.
DAC2932
PARAMETER
Resolution
Output update rate (fCLOCK)
Specified temperature range, operating
Static Accuracy(1)(2)
TEST CONDITIONS
MIN
MAX
UNITS
+85
Bits
MSPS
°C
+3.5
+8
LSB
LSB
12
40
Ambient, TA
Differential nonlinearity (DNL)
Integral nonlinearity (INL)
Dynamic Performance(3)
−40
−3.5
−8
Spurious-free dynamic range (SFDR)
fOUT = 0.2MHz, fCLOCK = 20MSPS
fOUT = 0.55MHz, fCLOCK = 40MSPS
fOUT = 1MHz, fCLOCK = 25MSPS(4)
To Nyquist, 0dBFS
fOUT = 2.2MHz, fCLOCK = 40MSPS
fOUT = 10MHz, fCLOCK = 40MSPS
Total harmonic distortion (THD)
fOUT = 0.55MHz, fCLOCK = 40MSPS
fOUT = 1MHz, fCLOCK = 25MSPS(4)
fOUT = 2.2MHz, fCLOCK = 40MSPS
Signal-to-noise and distortion (SINAD)
fOUT = 1MHz, fCLOCK = 25MSPS(4)
Output settling time(1)
Output rise time(1)
Output fall time(1)
1MHz span
2MHz span
58
fOUT = 2.2MHz, fCLOCK = 40MSPS
fOUT = 5MHz, fCLOCK = 40MSPS
fOUT = 10MHz, fCLOCK = 40MSPS
fOUT = 20MHz, fCLOCK = 40MSPS
Spurious-free dynamic range within a
window
DC Accuracy
Full-scale output range(5)(6) (FSR)
Output compliance range(7), VCO
Gain error (Full-Scale)
Gain error drift
Gain matching
Offset error
Power-supply rejection, +VA
Power-supply rejection, +VD
Output resistance
Output capacitance
TYP
−58
52
to 0.1%
10% to 90%
10% to 90%
All bits high, IOUT1, IOUT2
0.5
−0.5
−2
−2.5
+3V, ±10%, at 25°C
+3V, ±10%, at 25°C
IOUT, IOUT to Ground
−0.9
−0.12
±0.5
±1.5
68
71
70
72
75
69
57
dBc
dBc
dBc
dBc
dBc
dBc
dBc
76
74
dBc
dBc
−70
−69
−70
dBc
dBc
dBc
61
20
7.7
7.4
dBc
ns
ns
ns
+0.5
±0.5
70
+0.6
±0.001
+0.5
+0.03
200
5
2
+0.8
+2
mA
V
%FSR
ppmFSR/°C
+2.5
+0.9
+0.12
%FSR
%FSR
%FSR/V
%FSR/V
kΩ
pF
(1) At output IOUT1, IOUT2, while driving a 250Ω load, transition from 000h to FFFh.
(2) Measured at fCLOCK = 25MSPS and fOUT = 1.0MHz.
(3) Differential, transformer (n = 4:1) coupled output, RL = 400Ω.
(4) Differential outputs with a 250Ω load.
V REF
(5) Nominal full−scale output current is I
IREF + 32
; with V REF + 1.22V (typ) and R SET + 19.6kW (1%)
OUTFS + 32
R SET
(6) Ensured by design and characterization; not production tested.
(7) Gain error to remain ≤10% FSR over the full compliance range.
(8) Combined power dissipation of I-DAC and V-DAC.
3
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SBAS279D − AUGUST 2003 − REVISED JULY 2005
ELECTRICAL CHARACTERISTICS: I-DAC (continued)
At TA = TMIN to TMAX (typical values are at TA = 25°C), +VA = +3V, +VD = +3V, Update Rate = 40MSPS, IOUTFS = 2mA, RL = 250Ω, CL ≤ 10pF,
GSET = H, and internal reference, unless otherwise noted.
DAC2932
PARAMETER
Reference
Voltage, VREF
Tolerance
Voltage drift
Output current
Input resistance
Input compliance range
Small-signal bandwidth
Digital Inputs(6)
TEST CONDITIONS
PD
PD
PD
Thermal resistance
TQFP-48
Q
θJA
θJC
TYP
MAX
UNITS
+1.14
+1.22
±30
−40
10
1
+1.22
0.1
+1.26
V
mV
ppm/°C
μA
MΩ
V
MHz
External VREF
Logic coding
Logic high voltage, VIH
Logic low voltage, VIL
Logic high current
Logic low current
Input capacitance
Power Supply
Analog supply voltage, +VA, +VAV
Digital supply voltage, +VD, +VDV
Analog supply current, IVA
IVA
IVA
Digital supply current, IVD
lVD
IVD
IVD
Power dissipation, PD(8)
MIN
+2
2.7
2.7
fCLOCK = 25MSPS, digital inputs at 0
fCLOCK = 40MSPS, fOUT = 2.2MHz
Standby mode
fCLOCK = 25MSPS, digital inputs at 0
fCLOCK = 40MSPS, fOUT = 2.2MHz
Standby mode, clock off
Standby mode, CS = 0, fCLOCK = 25MSPS
fCLOCK = 25MSPS, digital inputs at 0
fCLOCK = 40MSPS, fOUT = 2.2MHz
Standby mode, fCLOCK = 25MSPS
Power-down mode, clock off, digital inputs at 0
Straight binary
+3
0
±1
±1
5
3
3
4.7
5.4
0.4
2
4.3
0.02
1.3
20
29
5.5
25
+0.8
3.3
3.3
25
7
97.5
20
(1) At output IOUT1, IOUT2, while driving a 250Ω load, transition from 000h to FFFh.
(2) Measured at fCLOCK = 25MSPS and fOUT = 1.0MHz.
(3) Differential, transformer (n = 4:1) coupled output, RL = 400Ω.
(4) Differential outputs with a 250Ω load.
V REF
(5) Nominal full−scale output current is I
IREF + 32
; with V REF + 1.22V (typ) and R SET + 19.6kW (1%)
OUTFS + 32
R SET
(6) Ensured by design and characterization; not production tested.
(7) Gain error to remain ≤10% FSR over the full compliance range.
(8) Combined power dissipation of I-DAC and V-DAC.
4
V
V
μA
μA
pF
V
V
mA
mA
mA
mA
mA
mA
mA
mW
mW
mW
μW
°C/W
°C/W
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SBAS279D − AUGUST 2003 − REVISED JULY 2005
ELECTRICAL CHARACTERISTICS: V-DAC
At TA = TMIN to TMAX (typical values are at TA = 25°C), +VAV = +3V, +VDV = +3V, RL = 2kΩ to GND, and CL = 40pF, unless otherwise noted.
DAC2932
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNITS
At 25°C
−16
±8
+16
LSB
Tested; monotonic by design
−1
±0.2
+1
LSB
0.2
+0.8
%FSR
−3
+2
%FSR
Static Performance(1)
Resolution
Relative accuracy
12
Differential nonlinearity, DNL
Zero code error(2)
All 0s loaded to DAC register
Full-scale error(2)
All 1s loaded to DAC register
−10
Bits
Zero code error drift
5
μV/°C
Full-scale error drift
−15
ppmFSR/°C
Output Characteristics(3)
Reference voltage setting, REFV
Output voltage settling time
0
Code change glitch impulse
V
3
μs
CL = 470pF
5
μs
1
V/μs
RL = 2kΩ
1LSB change around major carry
470
pF
11
nV-s
0.5
nV-s
Slew rate
Capacitive load stability
+VAV
1/4 scale to 3/4 scale change (400h to C00h)
Digital feedthrough
DC output impedance
4
Ω
Short-circuit current
20
mA
8
μs
Power-up time
Logic Inputs(3)
Coming out of power-down mode
Input current
±1
Input low voltage, VIL
0
Input high voltage, VIH
Input capacitance
2
μA
0.8
V
3
V
5
pF
(1) Linearity calculated using a reduced code range of 48 to 3976.
(2) Full-scale range (FSR) based on reference REFV = +VAV = +3.0V.
(3) Ensured by design and characterization; not production tested.
5
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SBAS279D − AUGUST 2003 − REVISED JULY 2005
TIMING INFORMATION
tCP
tCL
tCH
CLK
Data In
[D11:D0]
DAC1 (n − 1)
DAC2 (n − 1)
tS1
DAC1 (n)
tS2
t H1
(n − 2)
I−DAC OUT1
DAC2 (n)
DAC1 (n +1)
DAC2 (n + 1)
tH2
(n − 1)
(n)
(n − 1)
(n)
t DO1
I−DAC OUT2
(n − 2)
tDO2
Figure 1. Timing Diagram of I-DAC
TIMING REQUIREMENTS(1,2): I-DAC
PARAMETER
DESCRIPTION
tCP
tCL
Clock cycle time (period)
Clock low time
10
tCH
tS1
Clock high time
10
tS2
tH1
Data setup time, I-DAC2
Data hold time, I-DAC1
tH2
tDO1(3)
tDO2(3)
Data hold time, I-DAC2
3.35
Data setup time, I-DAC1
MIN
25
STBY rise time to IOUT
ns
ns
ns
ns
1
5
ns
3.35
5
ns
5
ns
tS1 + tCP
tS2+(tCP/2)
ns
2.49
ns
ns
0.52
ns
17
μs
PD fall time to IOUT (I-DAC coming out of power-down mode)
22
(1) Based on design simulation and characterization; not production tested.
(2) All input signals are specified with tr = tf ≤ 2ns (10% to 90% of +VDV) and timed from a voltage level of (VIL + VIH)/2.
(3) Output delay time measured from 50% of rising clock edge to 50% point of full-scale transition.
6
UNIT
5
Output delay time, I-DAC2
CS to clock rising or falling edge setup time
MAX
1
Output delay time, I-DAC1
CS hold time (pulse width)
TYP
μs
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SBAS279D − AUGUST 2003 − REVISED JULY 2005
t1
SCLK
t8
t2
t3
t4
t7
SYNC
t6
t5
DIN
DB15
DB0
Figure 2. Serial Write Operation of V-DAC
TIMING REQUIREMENTS(1,2): V-DAC
PARAMETER
t1(3)
DESCRIPTION
SCLK cycle time
MIN
50
ns
t2
t3
SCLK high time
13
ns
22.5
ns
t4
t5
SYNC to SCLK rising edge setup time
0
Data setup time
5
t6
t7
Data hold time
t8
Minimum SYNC high time
SCLK low time
TYP
MAX
UNIT
ns
7.5
ns
1.5
2.5
ns
0
−6.0
ns
8
μs
SCLK falling edge to SYNC rising edge
50
ns
PDV fall time to VOUT (V-DAC coming out of power-down mode)
(1) All input signals are specified with tr = tf ≤ 2ns (10% to 90% of +VDV) and timed from a voltage level of (VIL + VIH)/2.
(2) Based on design simulation and characterization; not production tested.
(3) Maximum SCLK frequency is 20MHz at +VAV = +VDV = +2.7V to 3.3V.
V−DAC: SERIAL DATA INPUT FORMAT
DB15
DB14
DB13
DB12
DB11
DB10
DB9
DB8
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
A0
DAC1
A1
DAC2
A2
DAC3
A3
DAC4
D11
(MSB)
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
(LSB)
Address Bits
12-Bit Data Word
NOTE: A logic high in the address bit will select the corresponding V-DAC and write the data word into its register. If more than one address bit
is set high, the selected V-DACs are updated with the same data word simultaneously.
7
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SBAS279D − AUGUST 2003 − REVISED JULY 2005
D11 (MSB)
DGNDV
SYNC
SCLK
DIN
PDV
+VDV
REFV
AGNDV
VOUT4
VOUT3
VOUT2
VOUT1
PIN ASSIGNMENTS
48
47
46
45
44
43
42
41
40
39
38
37
36
NC
D10 2
35
+VAV
D9 3
34
IOUT2
D8 4
33
IOUT2
D7 5
32
AGND
31
AGND
30
+VA
D4 8
29
+VA
D3 9
28
AGND
D2 10
27
IOUT1
D1 11
26
IOUT1
D0 (LSB) 12
25
REFIN
1
(V−DAC Section)
D6 6
DAC2932
16
17
18
19
20
21
22
23
24
STBY
CS
GSET
DGND
AGND
AGND
FSA2
FSA1
+VD
15
PD
14
CLK
13
DGND
D5 7
Terminal Functions
TERMINAL
NAME
NO.
I/O
D11:D0
1:12
I
DGND
13
Digital ground of I-DAC
+VD
14
Digital supply of I-DAC; 2.7V to 3.3V
CLK
15
I
Clock input of I-DAC
PD
16
I
Power-down pin; active high; a logic high initiates power-down mode.
STBY
17
I
Standby pin of I-DAC; active low; a logic low initiates Standby mode with PD = Low.
A logic high configures the I-DAC for normal operation; pin will resume a high state if left open.
CS
18
I
Chip select; active low; enables the parallel data port of the I−DACs; if used as chip select in applications
using multiple DAC2932 devices, the parallel port data must be scrambled for proper functionality. Pin will
resume a low state if left open.
GSET
19
I
Gain-setting mode. A logic high enables the use of two separate full-scale adjust resistors on pins FSA1
and FSA2. A logic low allows the use of a common full-scale adjust resistor connected to FSA1. The
function of the FSA2 pin is disabled, and any remaining resistor has no effect. The value for the RSET
resistor remains the same for a given full-scale range, regardless of the selected GSET mode. Pin will
resume a low state if left open.
DGND
20
Digital ground of I-DAC
AGND
21
Analog ground of I-DAC
AGND
22
Analog ground of I-DAC
FSA2
23
I
Full-scale adjust of I-DAC2; connect external gain setting resistor RSET2 = 19.6kΩ.
FSA1
24
I
Full-scale adjust of I-DAC1; connect external gain setting resistor RSET1 = 19.6kΩ.
8
DESCRIPTION
Parallel data input port for the dual I-DACs; MSB = D11, LSB = D0; interleaved operation.
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Terminal Functions (continued)
TERMINAL
NAME
NO.
I/O
DESCRIPTION
REFIN
25
I
External reference voltage input; internal reference voltage output; bypass with 0.1μF to AGND for internal
reference operation.
IOUT1
26
O
Complementary current ouput of I-DAC1
IOUT1
27
O
Current output of I-DAC1
AGND
28
Analog ground of I-DAC
+VA
29
Analog supply of I-DAC; 2.7V to 3.3V
+VA
30
Analog supply of I-DAC; 2.7V to 3.3V
AGND
31
Analog ground of I-DAC
AGND
32
IOUT2
33
O
Current output of I-DAC2
IOUT2
34
O
Complementary current ouput of I-DAC2
+VAV
35
Analog supply of V-DAC; 2.7V to 3.3V
NC
36
No internal connection
VOUT1
37
O
Voltage output of V-DAC1
VOUT2
38
O
Voltage output of V-DAC2
VOUT3
39
O
Voltage output of V-DAC3
VOUT4
40
O
Voltage output of V-DAC4
AGNDV
41
REFV
42
+VDV
43
PDV
44
I
Power-down of V-DACs; active high; a logic high initiates the power-down mode
DIN
45
I
Serial digital input for V−DAC; see timing and application sections for details
SCLK
46
I
Clock input of V-DAC
SYNC
47
I
Frame synchronization signal for the serial data at DIN. Refer to timing section for details.
DGNDV
48
Analog ground of I-DAC
Analog ground of V-DAC
I
Reference voltage input for V-DACs; typically connected to supply (+VAV)
Digital supply of V-DAC; 2.7V to 3.3V
Digital ground of V-DAC.
9
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TYPICAL CHARACTERISTICS
TA = +25°C, +VA = +VAV = +3V, +VD = +VDV = +3V, IOUTFS = 2mA, differential transformer-coupled output (n = 4:1), RL = 400Ω on I-DAC,
RL = 2kΩ on V-DAC, and GSET = H unless otherwise noted.
I−DAC, DNL
1.0
1.6
0.8
1.2
0.6
0.8
0.4
0.4
0.2
DNL (LSB)
INL (LSB)
I−DAC, INL
2.0
0
−0.4
0
−0.2
−0.8
−0.4
−1.2
−0.6
−1.6
−0.8
−2.0
−1.0
0
500
1000
1500
2000
2500
3000
0
3500 4000
500
1000
1500
2000
Codes
Figure 3
75
76
SFDR (dBc)
SFDR (dBc)
74
72
70
68
66
64
70
65
60
55
62
60
50
0.5
0
1.0
1.5
2.0
2.5
0
0.5
1.0
1.5
fOUT (MHz)
2.5
3.0
3.5
4.0
4.5
5.0
16
18
20
Figure 6
SFDR vs fOUT AT 20MSPS
80
2.0
fOUT (MHz)
Figure 5
SFDR vs fOUT AT 40MSPS
80
75
75
70
70
SFDR (dBc)
SFDR (dBc)
3500 4000
SFDR vs fOUT AT 10MSPS
80
78
65
60
55
65
60
55
50
50
0
1
2
3
4
5
6
fOUT (MHz)
Figure 7
10
3000
Figure 4
SFDR vs fOUT AT 5MSPS
80
2500
Codes
7
8
9
10
0
2
4
6
8
10
12
fOUT (MHz)
Figure 8
14
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SBAS279D − AUGUST 2003 − REVISED JULY 2005
TYPICAL CHARACTERISTICS (continued)
TA = +25°C, +VA = +VAV = +3V, +VD = +VDV = +3V, IOUTFS = 2mA, differential transformer-coupled output (n = 4:1), RL = 400Ω on I-DAC,
RL = 2kΩ on V-DAC, and GSET = H unless otherwise noted.
SFDR vs IOUT FS AND fOUT AT 40MSPS, 0dBFS
80
SFDR vs TEMPERATURE
80
1mA
75
SFDR (dBc)
70
1.5mA
0.5mA
SFDR (dBc)
75
2mA
65
60
2.2MHz, 40MSPS
70
1MHz, 20MSPS
65
10MHz, 40MSPS
60
55
55
50
50
−40 −30 −20 −10
19.9MHz, 40MSPS
0
2
4
6
8
10
12
14
16
18
20
0
Figure 9
20
30 40
50 60
70 80 85
Figure 10
TOTAL HARMONIC DISTORTION vs
fCLK AT fOUT = 2.2MHZ
−60
10
Temperature (_C)
fOUT (MHz)
TOTAL HARMONIC DISTORTION vs TEMPERATURE
f OUT = 1MHz at 20MSPS
−50
−55
−60
THD (dBc)
THD (dBc)
−65
−70
−75
−65
−70
−75
−80
−85
−80
10
5
15
20
25
30
35
−90
−40 −30 −20 −10
40
f CLK (MSPS)
10
20
30 40
50 60
70 80 85
Temperature (_C)
Figure 11
Figure 12
REFERENCE VOLTAGE vs TEMPERATURE
1.223
0
REFERENCE VOLTAGE vs SUPPLY VOLTAGE
1.2201
1.222
1.220
VREF (V)
VREF (V)
1.221
1.219
1.2200
1.218
1.217
1.216
1.2199
1.215
−40
−20
0
20
40
Temperature (_C)
Figure 13
60
80 85
2.7
2.8
2.9
3.0
3.1
3.2
3.3
Supply Voltage (V)
Figure 14
11
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SBAS279D − AUGUST 2003 − REVISED JULY 2005
TYPICAL CHARACTERISTICS (continued)
TA = +25°C, +VA = +VAV = +3V, +VD = +VDV = +3V, IOUTFS = 2mA, differential transformer-coupled output (n = 4:1), RL = 400Ω on I-DAC,
RL = 2kΩ on V-DAC, and GSET = H unless otherwise noted.
IA vs TEMPERATURE
5.60
5.55
6.0
5.50
5.5
19.9MHz, 40MSPS
10MHz, 40MSPS
5.0
ID (mA)
5.45
IA (mA)
ID vs TEMPERATURE AT fOUT AND fCLK
6.5
5.40
5.35
2.2MHz, 40MSPS
4.5
4.0
3.5
5.30
1MHz, 20MSPS
3.0
5.25
2.5
5.20
2.0
−40
−20
0
20
40
60
80 85
−40
−20
0
Temperature (_C)
Figure 15
5.42
6.0
5.41
5.5
ID (mA)
IA (mA)
80 85
19.9MHz, 40MSPS
10MHz, 40MSPS
5.0
5.39
5.38
4.5
4.0
2.2MHz, 40MSPS
3.5
5.37
3.0
5.36
1MHz, 20MSPS
2.5
5.35
2.0
2.7
2.8
2.9
3.0
3.1
3.2
3.3
2.7
2.8
2.9
Supply Voltage (V)
3.1
3.2
3.3
Figure 18
I−DAC1 OUTPUT SPECTRUM
0
3.0
Supply Voltage (V)
Figure 17
−20
I−DAC2 OUTPUT SPECTRUM
0
f OUT = 2.2MHz
fCLK = 40MSPS
−10
−30
−40
−50
−60
−70
f OUT = 2.2MHz
fCLK = 40MSPS
−10
−20
Magnitude (dBm)
Magnitude (dBm)
60
ID vs SUPPLY VOLTAGE AT fOUT AND f CLK
6.5
5.40
−30
−40
−50
−60
−70
−80
−80
−90
−90
−100
−100
0
12
40
Figure 16
IA vs SUPPLY VOLTAGE
5.43
20
Temperature (_ C)
2
4
6
8
10
12
14
16
18
20
0
2
4
6
8
10
12
Frequency (MHz)
Frequency (MHz)
Figure 19
Figure 20
14
16
18
20
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SBAS279D − AUGUST 2003 − REVISED JULY 2005
TYPICAL CHARACTERISTICS (continued)
TA = +25°C, +VA = +VAV = +3V, +VD = +VDV = +3V, IOUTFS = 2mA, differential transformer-coupled output (n = 4:1), RL = 400Ω on I-DAC,
RL = 2kΩ on V-DAC, and GSET = H unless otherwise noted.
DUAL−TONE OUTPUT SPECTRUM
−10
f1 = 1.2MHz
f2 = 2.2MHz
fCLK = 40MSPS
−20
−40
−50
−60
−70
−80
−30
−40
−50
−60
−70
−80
−90
−90
−100
−100
−110
0
2
4
6
8
10
12
14
16
18
−110
20
0
6
8
10
12
Figure 21
Figure 22
14
16
18
20
V−DAC, INL
16
12
8
Channel 2
−80
Channel 1
−90
−100
INL (LSB)
Channel Isolation (dBc)
4
Frequency (MHz)
−70
4
0
−4
−8
−110
−12
−120
−16
0
2
4
6
8
10
12
14
16
18
20
0
500
1000
1500
2000
2500
Frequency (MHz)
Codes
Figure 23
Figure 24
V−DAC, DNL
1.0
3.00
0.8
2.75
3000
3500 4000
3000
3500 4000
VOUT vs CODE
2.50
2.25
0.6
0.4
2.00
0.2
VOUT (V)
DNL (LSB)
2
Frequency (MHz)
I−DAC CHANNEL ISOLATION vs fOUT AT 40MSPS
−60
f1 = 1.2MHz
f2 = 2.2MHz
f3 = 3.2MHz
f4 = 4.2MHz
f CLK = 40MSPS
−20
Magnitude (dBm)
Magnitude (dBm)
−30
FOUR−TONE OUTPUT SPECTRUM
−10
0
−0.2
−0.4
1.75
1.50
1.25
1.00
0.75
−0.6
0.50
0.25
−0.8
0
−1.0
0
500
1000
1500
2000
2500
Codes
Figure 25
3000
3500 4000
0
500
1000
1500
2000
2500
Codes
Figure 26
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SBAS279D − AUGUST 2003 − REVISED JULY 2005
APPLICATION INFORMATION
The segmented architecture results in a significant
reduction of the glitch energy, and improves the dynamic
performance (SFDR) and DNL. The current outputs
maintain a very high output impedance of greater than
200kΩ.
THEORY OF OPERATION
The architecture of the DAC2932 uses the current steering
technique to enable fast switching and a high update rate.
The core element within the monolithic DAC is an array of
segmented current sources that are designed to deliver a
full-scale output current of up to 2mA, as shown in
Figure 27. An internal decoder addresses the differential
current switches each time the DAC is updated and a
corresponding output current is formed by steering all
currents to either output summing node, IOUT or IOUT. The
complementary outputs deliver a differential output signal,
which improves the dynamic performance through
reduction of even-order harmonics and common-mode
signals (noise), and doubles the peak-to-peak output
signal swing by a factor of two, compared to single-ended
operation.
REFIN
STBY
GSET
+1.22V Reference
FSA1
The full-scale output current is determined by the ratio of
the internal reference voltage (approximately +1.2V) and
an external resistor, RSET. The resulting IREF is internally
multiplied by a factor of 32 to produce an effective DAC
output current that can range from 0.5mA to 2mA,
depending on the value of RSET.
The DAC2932 is split into a digital and an analog portion,
each of which is powered through its own supply pin. The
digital section includes edge-triggered input latches and
the decoder logic, while the analog section comprises the
current source array with its associated switches, and the
reference circuitry.
FSA2
+VA
AGND
+VD
DGND
DAC2932
Reference Control Amp
CS
CLK
Parallel Data Input
[D11:D0]
Data1
Clock
Input Latch
and
De−Multiplexer
PD
12−Bit Data,
Interleaved
CLK1
Data2
CLK2
DAC
Latch 1
12−Bit
40MSPS
I−DAC1
IOUT1
DAC
Latch 2
12−Bit
40MSPS
I−DAC2
IOUT2
I−DAC Section
DIN
SCLK
SYNC
Serial−to−Parallel
Shift Register
12
IOUT2
V−DAC Section
Dx
A0
Latch
12−Bit
String−DAC1
A
VOUT1
A1
Latch
12−Bit
String−DAC2
A
VOUT2
A2
Latch
12−Bit
String−DAC3
A
VOUT3
A3
Latch
12−Bit
String−DAC4
A
VOUT4
REFV
PDV
+VDV DGNDV +VAV AGNDV
Figure 27. Block Diagram of the DAC2932
14
IOUT1
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SBAS279D − AUGUST 2003 − REVISED JULY 2005
DAC TRANSFER FUNCTION
Each of the I-DACs in the DAC2932 has a complementary
current output, IOUT1 and IOUT2. The full-scale output
current, IOUTFS, is the summation of the two
complementary output currents:
I OUTFS + I OUT ) I OUT
V OUTDIFF + VOUT * VOUT
(2 Code * 4095)
+
4096
I OUTFS
R LOAD
(7)
(1)
The individual output currents depend on the DAC code
and can be expressed as:
I OUT + I OUTFS
(Codeń4096)
(2)
I OUT + I OUTFS
(4095 * Code)ń4096
(3)
where Code is the decimal representation of the DAC data
input word (0 to 4095).
Additionally, IOUTFS is a function of the reference current
IREF, which is determined by the reference voltage and the
external setting resistor, RSET.
I OUTFS + 32
The two single-ended output voltages can be combined to
find the total differential output swing:
I REF + 32
VREF
R SET
(4)
In most cases, the complementary outputs will drive
resistive loads or a terminated transformer. A signal
voltage will develop at each output according to:
V OUT + I OUT
RLOAD
(5)
V OUT + I OUT
RLOAD
(6)
The value of the load resistance is limited by the output
compliance specification of the DAC2932. To maintain
optimum linearity performance, the compliance voltage at
IOUT and IOUT should be limited to +0.5V or less.
POWER-DOWN MODES
The DAC2932 has several modes of operation. Besides
normal operation, the I-DAC section features a Standby
mode and a full power-down mode, while the V-DAC
section has one power-down mode. All modes are
controlled by appropriate logic levels on the assigned pins
of the DAC2932. Table 1 lists all pins and possible modes.
The pins have internal pull-ups or pull-downs; if left open,
all pins will resume logic levels that place the I-DAC and
V-DAC in a normal operating mode (fully functional).
When in Standby mode the analog functions of the I-DAC
section are powered down. The internal logic is still active
and will consume some power if the clock remains applied.
To further reduce the power in Standby mode the CS pin
may be pulled high, which disables the internal logic from
being clocked, even with the clock signal applied.
If CS remains low during the Standby mode and a running
clock remains applied, any new data on the parallel data
port will be latched into the DAC. The analog output,
however, will not be updated as long as the I-DACs remain
in Standby mode.
Table 1. Power-Down Modes
PD (16)
STBY(17)
CS (18)
PDV (44)
DAC
MODE
DAC OUTPUTS
0
0
0
X
I-DAC enabled
Standby; data can still be written into the DACs
with running clock applied
High-Z
0
0
1
X
I-DAC disabled
Standby; writing into DAC disabled—clock input
disabled by CS
High-Z
0
1
0
X
I-DAC enabled
Normal operation (return from Standby)
0
1
1
X
I-DAC disabled
Data input and clock input disabled; use when
multiple devices on one bus
Last data held
1
X
X
X
I-DAC disabled
Full power-down; STBY and CS have no effect
High-Z
0
X
X
0
V-DAC enabled
V-DAC normal operation
X
X
X
1
V-DAC disabled
V-DAC in power-down mode; independent
operation of any I-DAC power-down
configuration
Last state prior to
Standby
All outputs; High-Z
NOTE: X = don’t care.
15
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SBAS279D − AUGUST 2003 − REVISED JULY 2005
CHIP SELECT OPERATION
a high condition, ignoring the CLK edges and thus not
latching the bus data. In order to enable data latching, the
CS pin must be returned to a low state. The change of state
in CS is latched into the clock interface on the first rising
CLK edge; this enables the internal clock which causes the
data in channel 2 to be latched on the first falling edge of
CLK. The next rising edge of CLK causes the DAC to
output the old data from channel 1 and the new data just
latched into channel 2 as well as to latch the new data into
channel 1.
The I−DAC clock is controlled by PD and CS through a
digital clock interface that generates an internal clock
which controls the data latches. Under normal operation
PD and CS are kept low and the internal clock is just a
delayed version of the clock signal present at the CLK pin.
The data for channel 1 and channel 2 are latched by the
rising and falling edges of CLK, respectively. The rising
edge of CLK also causes the DAC to output the previously
latched data pair.
The operation previously described causes problems in
those situations that have two or more DAC2932 devices
sharing the same data bus with each DAC2932 reading
every nth data pair. The (channel1, channel2) data pairs
appearing at the DAC output correspond to (channel1 from
the previous read cycle, channel2 data from the current
read cycle) pairs. In order for the data bus pairs to be
output correctly it is necessary to scramble the (channel1,
channel2) data pairs so that the bus data corresponds to
. . ., channel1, data for other DACs, channel2, . . . for each
DAC2932.
The CS pin can be used to synchronize the latching of data
from a single data bus connected to multiple DAC2932
devices, however in order for this operation to work
correctly the data pairs on the bus have to be scrambled
so that they are arranged correctly at the DAC outputs. The
reason for this is explained in the following:
Figure 28 shows a timing diagram of the CS operation.
When the CS pin is pulled high, the data in the parallel
input port is not latched. The high condition on the CS pin
is latched into the clock interface on the first rising edge of
CLK following the CS edge; this holds the internal clock in
CLK
CS
Data In 1_0
[D11:D0]
I−DAC OUT
2_0
1_1
2_1
1_2
2_2
1_3
1_0
2_3
1_4
2_4
2_1
Figure 28. Timing Diagram of the CS Pin
16
1_5
1_2
2_3
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ANALOG OUTPUTS
The DAC2932 provides two sets of complementary
current outputs, IOUT and IOUT. The simplified circuit of the
analog output stage representing the differential topology
is shown in Figure 29. The output impedance of IOUT and
IOUT results from the parallel combination of the differential
switches, along with the current sources and associated
parasitic capacitances.
0.5mA may be considered for applications that require low
power consumption, but can tolerate a slightly reduced
performance level.
The current-output DACs of the DAC2932 have a straight
offset binary coding format. With all bits high, the full-scale
output current (for example, 2mA) will be sourced at pins
IOUT1 and IOUT2, as shown in Table 2.
Table 2. Input Coding vs Analog Output Current
+VA
DAC2932
INPUT CODE
(D11−D0)
IOUT
(mA)
IOUT
(mA)
1111 1111 1111
2
0
1000 0000 0000
1
1
0000 0000 0000
0
2
OUTPUT CONFIGURATIONS
I OUT
IOUT
RL
RL
Figure 29. Equivalent Analog Output
The signal voltage swing that develops at the two outputs,
IOUT and IOUT, is limited by a negative and positive
compliance. The negative limit of –0.5V is given by the
breakdown voltage of the CMOS process, and exceeding
it will compromise the reliability of the DAC2932, or even
cause permanent damage. With the full-scale output set to
2mA, the positive compliance equals 0.8V, operating with
an analog supply of +VA = 3V. To avoid degradation of the
distortion performance and integral linearity, care must be
taken so that the configuration of the DAC2932 does not
exceed the compliance range.
Best distortion performance is typically achieved with the
maximum full-scale output signal limited to approximately
0.5VPP. This is the case for a 250Ω load and a 2mA
full-scale output current. A variety of loads can be adapted
to the output of the DAC2932 by selecting a suitable
transformer while maintaining optimum voltage levels at
IOUT and IOUT. Furthermore, using the differential output
configuration in combination with a transformer is
instrumental
in
achieving
excellent
distortion
performance. Common-mode errors, such as even-order
harmonics or noise, can be substantially reduced. This is
particularly the case with high output frequencies.
For those applications requiring the optimum distortion
and noise performance, it is recommended to select a
full-scale output of 2mA. A lower full-scale range down to
As mentioned previously, utilizing the differential outputs
of the converter yields the best dynamic performance.
Such a differential output circuit may consist of an RF
transformer or a differential amplifier configuration. The
transformer configuration is ideal for most applications
with ac coupling, while op amps are suitable for a
dc-coupled configuration.
The single-ended configuration may be considered for applications requiring a unipolar output voltage. Connecting a
resistor from either one of the outputs to ground converts the
output current into a ground-referenced voltage signal. To improve on the dc linearity by maintaining a virtual ground, an
I-to-V or op-amp configuration may be considered.
DIFFERENTIAL WITH TRANSFORMER
Using an RF transformer provides a convenient way of
converting the differential output signal into a single-ended
signal while achieving excellent dynamic performance
(see Figure 3). The appropriate transformer should be
carefully selected based on the output frequency spectrum
and impedance requirements. The differential transformer
configuration has the benefit of significantly reducing
common-mode signals, thus improving the dynamic
performance over a wide range of frequencies.
Furthermore, by selecting a suitable impedance ratio
(winding ratio), the transformer can be used to provide
optimum impedance matching while controlling the
compliance voltage for the converter outputs. The model
shown, ADT16-6T (by Mini-Circuits), has a 16:1 ratio and
may be used to interface the DAC2932 to a 50Ω load. This
results in a 200Ω load for each of the outputs, IOUT and
IOUT. The output signals are ac coupled and inherently
isolated by the transformer.
17
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SBAS279D − AUGUST 2003 − REVISED JULY 2005
As shown in Figure 30, the transformer center tap is
connected to ground. This forces the voltage swing on
IOUT and IOUT to be centered at 0V. In this case the two
resistors, RL, may be replaced with one, RDIFF, or omitted
altogether. Alternatively, if the center tap is not connected,
the signal swing will be centered at RL × IOUTFS/2.
However, in this case, the two resistors (RL) must be used
to enable the necessary dc-current flow for both outputs.
16:1
IOUT
DAC2932
RL
400Ω
RDIFF
RS
IOUT
RL
400Ω
Figure 30. Differential Output Configuration
Using an RF Transformer
DIFFERENTIAL CONFIGURATION USING AN OP AMP
If the application requires a dc−coupled output, a difference
amplifier may be considered, as shown in Figure 31. Four
external resistors are needed to configure the OPA690
voltage-feedback op amp as a difference amplifier
performing the differential to single-ended conversion. Under
the configuration shown, the DAC2932 generates a
differential output signal of 0.5VPP at the load resistors, RL.
This configuration typically delivers a lower level of ac
performance than the previously discussed transformer
solution because the amplifier introduces another source
of distortion. Suitable amplifiers should be selected based
on their slew-rate, harmonic distortion, and output swing
capabilities. A high-speed amplifier like the OPA690 may
be considered. The ac performance of this circuit can be
improved by adding a small capacitor (CDIFF) between the
outputs IOUT and IOUT, as shown in Figure 31. This will
introduce a real pole to create a low-pass filter in order to
slew-limit the fast output signal steps of the DAC, which
otherwise could drive the amplifier into slew-limitations or
into an overload condition; both would cause excessive
distortion. The difference amplifier can easily be modified
to add a level shift for applications requiring the
single-ended output voltage to be unipolar (that is, swing
between 0V and +2V).
DUAL TRANSIMPEDANCE OUTPUT
CONFIGURATION
The circuit example of Figure 32 shows the signal output
currents connected into the summing junctions of the
OPA2690 dual voltage-feedback op amp, which is set up as
a transimpedance stage or I-to-V converter. With this circuit,
the DAC output will be kept at a virtual ground, minimizing the
effects of output impedance variations, which results in the
best dc linearity (INL). As mentioned previously, care should
be taken not to drive the amplifier into slew-rate limitations
and produce unwanted distortion.
+5V
50Ω
R2
499Ω
1/2
OPA 2 6 9 0
R1
249Ω
DAC2932
IOUT
OPA690
C OPT
RL
249Ω
R3
249Ω
RL
249Ω
R F1
DAC 2932
IOUT
VOUT
IOUT
CD1
−5V +5V
IOUT
CD2
Figure 31. Difference Amplifier Provides
Differential-to-Single-Ended Conversion and
DC-Coupling
18
CF1
RF2
R4
499Ω
The OPA690 is configured for a gain of two. Therefore,
operating the DAC2932 with a 2mA full-scale output
produces a voltage output of ±1V. This requires the
amplifier to operate from a dual power supply (±5V). The
tolerance of the resistors typically sets the limit for the
achievable common-mode rejection. An improvement can
be obtained by fine tuning resistor R4.
−VOUT = IOUT • RF1
CF2
1/2
OPA 2 6 9 0
50Ω
−VOUT = IOUT • RF2
−5V
Figure 32. The OPA2690 Dual, Voltage-Feedback
Amplifier Forms a Transimpedance Amplifier
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SBAS279D − AUGUST 2003 − REVISED JULY 2005
The DC gain for this circuit is equal to feedback resistor RF.
At high frequencies, the DAC output impedance (CD1, CD2)
produces a zero in the noise gain for the OPA2690 that can
cause peaking in the closed-loop frequency response. CF is
added across RF to compensate for this noise gain peaking.
To achieve a flat transimpedance frequency response, the
pole in each feedback network should be set to:
ǸGBP
1
+
2pR FCF
4pR FC F
IOUTFS = 2mA
IOUT
VOUT = 0V to +0.5V
DAC2932
IOUT
250Ω
250Ω
(8)
where GBP = gain bandwidth product of the op amp, which
gives a corner frequency f−3dB of approximately:
f *3dB +
ǸGBP
2pRFC D
(9)
The full-scale output voltage is simply defined by the
product of IOUTFS • RF, and has a negative unipolar
excursion. To improve on the ac performance of this circuit,
adjustment of RF and/or IOUTFS should be considered.
Further extensions of this application example may
include adding a differential filter at the OPA2690 output
followed by a transformer, in order to convert to a
single-ended signal.
SINGLE-ENDED CONFIGURATION
Using a single load resistor connected to one of the DAC
outputs, a simple current-to-voltage conversion can be
accomplished. The circuit in Figure 33 shows a 250Ω
resistor connected to IOUT. Therefore, with a nominal
output current of 2mA, the DAC produces a total signal
swing of 0V to 0.5V.
VOUT ~ 0VP to 0.5VP
DAC2932
INTERFACING ANALOG QUADRATURE
MODULATORS
One of the main applications for the dual-channel DAC is
baseband I- and Q-channel transmission for digital
communications. In this application, the DAC is followed
by an analog quadrature modulator, modulating an IF
carrier with the baseband data, as shown in Figure 34.
Often, the input stages of these quadrate modulators
consist of npn-type transistors that require a dc bias (base)
voltage of > 0.8V.
IIN
IREF
IIN
IREF
I OUT1
Signal
Conditioning
I OUT2
Different load resistor values may be selected, as long as
the output compliance range is not exceeded. Additionally,
the output current (IOUTFS) and the load resistor can be
mutually adjusted to provide the desired output signal
swing and performance.
VIN ~ 0.6VP to 1.8VP
I OUT1
I OUT2
Figure 33. Differential Output Configuration
Using an RF Transformer
∑
RF
QIN
QREF
Quadrature Modulator
Figure 34. Generic Interface to a Quadrature Modulator. Signal conditioning (level shifting) may be
required to ensure correct dc common-mode levels at the input of the quadrature modulator.
19
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SBAS279D − AUGUST 2003 − REVISED JULY 2005
Figure 35 shows an example of a dc-coupled interface
with dc level-shifting, using a precision resistor network.
An ac-coupled interface, as shown in Figure 36, has the
advantage in that the common-mode levels at the input of
the modulator can be set independently of those at the
output of the DAC. Furthermore, no voltage loss occurs in
this setup.
The external resistor RSET connects to the FSA pin
(full-scale adjust) as shown in Figure 37. The reference
control amplifier operates as a V-to-I converter producing
a reference current, IREF, which is determined by the ratio
of VREF and RSET, as shown in Equation 10. The full-scale
output current, IOUTFS, results from multiplying IREF by a
fixed factor of 32.
VDC
+3V
R3
VOUT1
I REF =
VREF
RSET
R4
IOUT1
DAC2932
+VA
DAC2932
VOUT1
RSET
19.6kΩ
I OUT1
IOUT1
FSA
REFIN
Ref
Control
Amp
Current
Sources
0.1μF
I OUT1
+1.22V Ref.
R5
Figure 35. DC-Coupled Interface to a Quadrature
Modulator Applying Level Shifting
VDC
R1
DAC2932
IOUT1
0.01μF
IOUT1
VOUT1
IOUT1
VOUT1
0.01μF
RLOAD
250Ω
Using the internal reference, a 19.6kΩ resistor value
results in a full-scale output of approximately 2mA.
Resistors with a tolerance of 1% or better should be
considered. Selecting higher values, the output current
can be adjusted from 2mA down to 0.5mA. Operating the
DAC2932 at lower than 2mA output currents may be
desirable for reasons of reducing the total power
consumption or observing the output compliance voltage
limitations for a given load condition.
It is recommended to bypass the REFIN pin with a ceramic
chip capacitor of 0.1μF or more. The control amplifier is
internally compensated, and its small signal bandwidth is
approximately 0.1MHz.
IOUT1
RLOAD
250Ω
Figure 37. Internal Reference Configuration
R2
GAIN SETTING OPTIONS
Figure 36. AC-Coupled Interface to a Quadrature
Modulator Applying Level Shifting
INTERNAL REFERENCE OPERATION
The DAC2932 has an on-chip reference circuit that
comprises a 1.22V bandgap reference and two control
amplifiers, one for each DAC. The full-scale output current,
IOUTFS, of the DAC2932 is determined by the reference
voltage, VREF, and the value of resistor RSET. IOUTFS can
be calculated by:
I OUTFS + 32
20
I REF + 32
VREF
R SET
(10)
The full-scale output current on the DAC2932 can be set
two ways: either for each of the two DAC channels
independently or for both channels simultaneously. For the
independent gain set mode, GSET (pin 19) must be high
(that is, connected to +VA). In this mode, two external
resistors are required—one RSET connected to the FSA1
pin (pin 24) and the other to the FSA2 pin (pin 23). In this
configuration, the user has the flexibility to set and adjust
the full-scale output current for each DAC independently,
allowing for the compensation of possible gain
mismatches elsewhere within the transmit signal path.
www.ti.com
SBAS279D − AUGUST 2003 − REVISED JULY 2005
Alternatively, bringing GSET low (that is, connected to
AGND), switches the DAC2932 into the simultaneous gain
set mode. Now the full-scale output current of both DAC
channels is determined by only one external RSET resistor
connected to the FSA1 pin. The resistor at the FSA2 pin
may be removed; however, this is not required since this
pin is not functional in this mode and the resistor has no
effect on the gain equation. The formula for deriving the
correct RSET remains unchanged. For example,
RSET = 19.6kΩ will result in a 2mA output for both DACs.
The DAC2932 is specified with GSET being high and
operating in inpendent gain mode. It should be noted that
when using the simultaneous gain mode, the gain error
and gain matching error will increase.
V−DAC
The architecture consists of a resistor string DAC followed
by an output buffer amplifier. Figure 39 shows a block
diagram of the DAC architecture.
REFV
(+VDV)
REF (+)
Resistor
String
REF(−)
DAC Register
VOUT
Output
Amplifier
GND
EXTERNAL REFERENCE OPERATION
The internal reference can be disabled by simply applying
an external reference voltage into the REFIN pin, which in
this case functions as an input, as shown in Figure 38. The
use of an external reference may be considered for
applications that require higher accuracy and drift
performance.
+3V
Figure 39. V-DAC Architecture
The input coding to the V-DAC is straight binary, so the
ideal output voltage is given by:
V OUT + REFV
D
4096
(11)
where D = decimal equivalent of the binary code that is
loaded to the DAC register; it can range from 0 to 4095.
SERIAL INTERFACE
+VA
DAC2932
IREF =
VREF
RSET
FSA
REFIN
External
Reference
Ref
Control
Amp
Current
Sources
RSET
+1.22V Ref.
Figure 38. External Reference Configuration
While a 0.1μF capacitor is recommended for use with the
internal reference, it is optional for the external reference
operation. The reference input, REFIN, has a high input
impedance and can easily be driven by various sources.
The V−DACs have a three-wire serial interface (SYNC,
SCLK, and DIN), which is compatible with SPI, QSPI, and
Microwire interface standards as well as most Digital
Signal Processors (DSPs).
The write sequence begins by bringing the SYNC line low.
Data from the DIN line is clocked into the 16-bit shift
register on the falling edge of SCLK. The serial clock
frequency can be as high as 20MHz, making the V-DACs
compatible with high-speed DSPs. On the 16th falling
edge of the serial clock, the last data bit is clocked in and
the programmed function is executed (that is, a change in
DAC register contents and/or a change in the mode of
operation).
At this point, the SYNC line may be kept low or brought
high. In either case, it must be brought high for a minimum
of 50ns before the next write sequence so that a falling
edge of SYNC can initiate the next write sequence. Since
the SYNC buffer draws more current when the SYNC
signal is high than it does when it is low, SYNC should be
idled low between write sequences for lowest power
operation of the part. As mentioned above, however, it
must be brought high again just before the next write
sequence.
21
www.ti.com
SBAS279D − AUGUST 2003 − REVISED JULY 2005
INPUT SHIFT REGISTER
The input shift register is 16 bits wide. The first four bits are
the address bits to the four V-DACs. The next 12 bits are
the data bits. These are transferred to the DAC register on
the 16th falling edge of the clock (SCLK).
SYNC INTERRUPT
In a normal write sequence, the SYNC line is kept low for
at least 16 falling edges of SCLK and the DAC is updated
on the 16th falling edge. However, if SYNC is brought high
before the 16th falling edge, this acts as an interrupt to the
write sequence. The shift register is reset and the write
sequence is seen as invalid. Neither an update of the DAC
register contents nor a change in the operating mode
occurs, as shown in Figure 40.
POWER-ON RESET
The V-DACs contain a power-on reset circuit that controls
the output voltage during power-up. On power-up, the
DAC register is filled with zeros and the output voltage is
0V; it remains there until a valid write sequence is made to
the DAC. This is useful in applications where it is important
to know the state of the output of the DAC while it is in the
process of powering up.
GROUNDING, DECOUPLING, AND LAYOUT
INFORMATION
Proper grounding and bypassing, short lead length, and
the use of ground planes are particularly important for
high-frequency designs. Multilayer printed circuit boards
(PCBs) are recommended for best performance since they
offer distinct advantages such as minimization of ground
impedance, separation of signal layers by ground layers,
etc.
The DAC2932 uses separate pins for its analog and digital
supply and ground connections. The placement of the
decoupling capacitor should be such that the analog
supply (+VA) is bypassed to the analog ground (AGND),
and the digital supply bypassed to the digital ground
(DGND). In most cases, 0.1μF ceramic chip capacitors at
each supply pin are adequate to provide a low impedance
decoupling path. Keep in mind that their effectiveness
largely depends on the proximity to the individual supply
and ground pins. Therefore, they should be located as
close as physically possible to those device leads.
Whenever possible, the capacitors should be located
immediately under each pair of supply/ground pins on the
reverse side of the PCB. This layout approach minimizes
the parasitic inductance of component leads and PCB
runs.
Further supply decoupling with surface-mount tantalum
capacitors (1μF to 4.7μF) can be added as needed in
proximity of the converter.
Low noise is required for all supply and ground
connections to the DAC2932. It is recommended to use a
multilayer PCB with separate power and ground planes.
Mixed signal designs require particular attention to the
routing of the different supply currents and signal traces.
Generally, analog supply and ground planes should only
extend into analog signal areas, such as the DAC output
signal and the reference signal. Digital supply and ground
planes must be confined to areas covering digital circuitry,
including the digital input lines connecting to the converter,
as well as the clock signal. The analog and digital ground
planes should be joined together at one point underneath
the DAC. This can be realized with a short track of
approximately 1/8” (3mm).
The power to the DAC2932 should be provided through
the use of wide PCB runs or planes. Wide runs present a
lower trace impedance, further optimizing the supply
decoupling. The analog and digital supplies for the
converter should only be connected together at the supply
connector of the PCB. In the case of only one supply
voltage being available to power the DAC, ferrite beads
along with bypass capacitors can be used to create an LC
filter. This will generate a low-noise analog supply voltage
that can then be connected to the +VA supply pin of the
DAC2932.
While designing the layout, it is important to keep the analog
signal traces separated from any digital line, in order to
prevent noise coupling onto the analog signal path.
CLK
SYNC
DIN
DB 1 5
D B0
Invalid Write Sequence:
SYNC high before 16th falling edge
D B1 5
Figure 40. SYNC Interrupt Facility
22
D B0
Valid Write Sequence:
Output updates on the 16th falling edge
www.ti.com
SBAS279D − AUGUST 2003 − REVISED JULY 2005
Revision History
DATE
JUL 05
AUG 03
REV
D
*
PAGE
SECTION
DESCRIPTION
6
Timing Requirements
Changed tS1, tS2, tH1, tH2 min values, CS hold time (pulse width) min value,
and CS to clock rising or falling edge setup time typ value.
8
Pin Assignments
Changed pin names for pins 1 − 12
8
Terminal Functions
Changed CS description.
15
Power−Down Modes
In Table 1, changed column 1 row 7 from X to 0.
16
Chip Select Operation
Added Chip Select Operation section with figure
17
Differential With
Transformer
Changed ratio and load in first paragraph. Changed ratio and load in Figure 30.
—
—
Original version
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
23
PACKAGE OPTION ADDENDUM
www.ti.com
21-May-2010
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package
Drawing
Pins
Package Qty
Eco Plan
(2)
Lead/
Ball Finish
MSL Peak Temp
(3)
DAC2932PFBR
ACTIVE
TQFP
PFB
48
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-2-260C-1 YEAR
DAC2932PFBRG4
ACTIVE
TQFP
PFB
48
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-2-260C-1 YEAR
DAC2932PFBT
ACTIVE
TQFP
PFB
48
250
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-2-260C-1 YEAR
DAC2932PFBTG4
ACTIVE
TQFP
PFB
48
250
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-2-260C-1 YEAR
Samples
(Requires Login)
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
14-Jul-2012
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
DAC2932PFBR
TQFP
PFB
48
2000
330.0
16.8
9.6
9.6
1.5
12.0
16.0
Q2
DAC2932PFBT
TQFP
PFB
48
250
177.8
16.4
9.6
9.6
1.5
12.0
16.0
Q2
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
14-Jul-2012
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
DAC2932PFBR
TQFP
PFB
48
2000
367.0
367.0
38.0
DAC2932PFBT
TQFP
PFB
48
250
210.0
185.0
35.0
Pack Materials-Page 2
MECHANICAL DATA
MTQF019A – JANUARY 1995 – REVISED JANUARY 1998
PFB (S-PQFP-G48)
PLASTIC QUAD FLATPACK
0,27
0,17
0,50
36
0,08 M
25
37
24
48
13
0,13 NOM
1
12
5,50 TYP
7,20
SQ
6,80
9,20
SQ
8,80
Gage Plane
0,25
0,05 MIN
0°– 7°
1,05
0,95
Seating Plane
0,75
0,45
0,08
1,20 MAX
4073176 / B 10/96
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Falls within JEDEC MS-026
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