FAN1655 3A DDR Bus Termination Regulator Description Features The FAN1655 is a low-cost bi-directional LDO specifically designed for terminating DDR memory bus. It can both sink and source up to 2.1A continuous, 3A peak, providing enough current for most DDR applications. Load regulation meets the JEDEC spec, VTT = VREFOUT ± 40mV. ■ Sinks and sources 2.1A continuous, 3A peak ■ 0 to +125°C operating temperature range ■ 5mA Buffered VREFOUT = VDDQ/2 ■ Load regulation: VTT = VREFOUT ± 40mV ■ On-chip thermal limiting ■ Low Cost SO-14, Power-Enhanced eTSSOP or The FAN1655 includes a buffered reference voltage capable of supplying up to 5mA current. On-chip thermal limiting provides protection against a combination of power overload and ambient temperature that would create an excessive junction temperature. A shutdown input puts the FAN1655 into a low power mode. 8-pin 5x6mm MLP packages ■ Low-Current Shutdown Mode ■ Output Short Circuit Protection Applications ■ DDR Terminator VTT supply The FAN1655 regulator is available in a power-enhanced eTSSOP™-16, standard SOIC-14, and an 8-Lead MLP package. Ordering Information Part Number Temperature Range Package Packing FAN1655M 0°C to 125°C SOIC-14 Rails FAN1655MX 0°C to 125°C SOIC-14 Tape and Reel FAN1655MTF 0°C to 125°C eTSSOP-16 Rails FAN1655MTFX 0°C to 125°C eTSSOP-16 Tape and Reel FAN1655MPX 0°C to 125°C MLP-8 Tape and Reel Block Diagram VDDQ VDD VDD VDD SHDN 200k – VREFOUT + VTTFORCE + VREFIN VTTFORCE – 200k VTTSENSE FAN1655 VSSQ ©2006 Fairchild Semiconductor Corporation FAN1655 Rev. 1.1.5 VSS VSS 1 VSS www.fairchildsemi.com FAN1655 3A DDR Bus Termination Regulator January 2006 VDD 1 14 VDDQ VDD VTTFORCE 2 3 13 12 VREFOUT VSSQ VSS 11 SHDN SHDN VSS VTTFORCE 6 10 9 VREFIN 6 12 11 4 5 7 8 10 9 VTTSENSE VDD 7 8 VDD 1 16 NC VDD VTTFORCE 2 15 14 VDDQ VSS VSS 4 5 13 VTTFORCE VDD VSS 3 FAN1655 VREFOUT VREFIN NC FAN1655M VSSQ VTTSENSE VSS 14-Lead Plastic SOIC θJC = 37˚C/W, θJA = 88˚C/W 16-Lead Plastic eTSSOP-16 θJC = 4˚C/W* *Thermal impedance is measured with the power pad soldered to a 0.5 square inch copper area. The copper area should be connected to Vss (ground) and positioned over an internal power or ground plane to assist in heat dissipation. VDD 1 8 VDDQ VTTFORCE 2 7 VREFOUT VTTFORCE 3 6 SHDN VDD 4 5 VTTSENSE GND 8-Lead MLP Package (5x6mm) θJC = 4˚C/W, θJA = 34˚C/W as measured on FAN1655MP Eval Board Pin Definitions Pin MLP eTSSOP SOIC-14 Pin Name 1, 4 1, 2, 7 1, 2, 7 VDD 2, 3 3, 6 3, 6 VTTFORCE PAD 4, 5, 8 4, 5, 8 VSS 5 Pin Function Input power for the LDO. The VTT output voltage. IC Ground. 10 9 VTTSENSE 11 10 VREFIN 12 11 SHDN Shutdown. This active low shutdown turns off both VTT and VREFOUT. This pin has an internal pull-down, and must be externally driven high for the IC to be on. 13 12 VSSQ Signal Ground. 7 14 13 VREFOUT 8 15 14 VDDQ 6 9, 16 PAD PAD NC Feedback for remote sense of the VTT voltage. Alternative input for direct control of VTTOUT and VREFOUT. Buffered Voltage Reference Output. VDDQ Input. Attach this pin to the VDDQ supply to generate VTT and VREFOUT. No Internal Connection Connect PAD to Vss Ground Plane 2 FAN1655 Rev. 1.1.5 www.fairchildsemi.com FAN1655 3A DDR Bus Termination Regulator Pin Assignments FAN1655 3A DDR Bus Termination Regulator Typical Application VDDQ VDD VTTFORCE 470µF 100µF 6V GND 1 2 3 4 5 6 7 8 16 10µF 10k 15 14 FAN1655 VREFOUT 13 12 11 10 9 1nF SHDN VTTSENSE (connect to VTTFORCE at the load) 1nF 10µF GND Figure 1. (eTSSOP pinout shown) Typical Performance Characteristics Quiescent Current vs. Temperature VREF Output Change vs. IREF 9 1.0 VDD = VDDQ = 2.5V TA = 25˚C 0.5 ∆ VREFOUT (mV) QUIESCENT CURRENT (mA) 7.5 6 4.5 3 0 -0.5 1.5 -1.0 -6 0 -60 -40 -20 0 20 40 60 80 100 120 140 -5 -4 -3 -2 -1 0 1 2 3 4 5 6 VREF LOAD CURRENT (mA) AMBIENT TEMPERATURE (˚C) Figure 3. Reference Output Load Regulation Figure 2. Quiescent Current vs. Ambient Temperature 100.0 Current Pulse Duration (S) 1.260 VTT OUTPUT (V) 1.255 1.250 1.245 1.240 -3000 TA=70°C 10.0 TA=25°C 1.0 -2000 -1000 0 1000 2000 1 3000 2 2.5 3 Figure 5. Maximum Non-Repetitive Output Current vs. Pulse Width (FAN1655M SO-14 Package) Figure 4. VTT Load Regulation 3 FAN1655 Rev. 1.1.5 1.5 Peak Load Current (A) VTT Load Current (mA) www.fairchildsemi.com Supply Voltage VDD, VDDQ 6V 150˚C Junction Temperature, TJ Storage Temperature -65 to 150˚C Lead Soldering Temperature, 10 seconds 300˚C Power Dissipation, PD FAN1655M (SOIC-14) 1.4W FAN1655MTF (e-TSSOP) FAN1655MP (MLP) See “Power Dissipation and Derating” Recommended Operating Conditions Min. Typ. Max. Units Supply Voltage VDD Parameter Conditions 2.3 2.5 3.6 V Supply Voltage VDDQ 2.2 2.5 Ambient Operating Temperature 0 VREFIN 1.1 1.25 3.0 V 125 ˚C 1.5 V Electrical Characteristics (VDD = VDDQ = 2.5V ± 0.2V, and TA = 25˚C using circuit in Figure 1, unless otherwise noted.) The • denotes specifications which apply over the specified operating temperature range. Parameter VTT Output Voltage Conditions Min. Typ. Max. Units 1.135 1.235 1.335 1.150 1.250 1.350 1.165 1.265 1.365 V V V 1.110 1.210 1.310 1.150 1.250 1.350 1.190 1.290 1.390 V V V IOUT = 0A, VREFIN = open VDDQ = 2.3V • VDDQ = 2.5V • VDDQ = 2.7V • IOUT = ±2.1A, VREFIN = open VDDQ = 2.3V VDDQ = 2.5V VDDQ = 2.7V VTT Output Slew Rate Cload = 10µF VTT Leakage Current SHDN = 0V 0.3 • VTT Current Limit -50 ±3.1 VREFIN Input Impedance VREFOUT Output Voltage V/µS 50 µA A KΩ 100 No load VREFIN = 1.150V • VREFIN = 1.250V • VREFIN = 1.350V • 1.145 1.245 1.345 1.150 1.250 1.350 1.155 1.255 1.355 V V V VREFOUT Output Current VDDQ = 2.3V • -5 5 mA VREFOUT Leakage Current SHDN = 0V • -10 10 µA SHDN Logic High • 1.667 SHDN Logic Low • 0.800 V V No load, SHDN = 2.7V • 7.5 20 mA VDDQ Leakage Current SHDN = 0V • 6 10 µA VDD Leakage Current SHDN = 0V • 3 50 µA SHDN Input Current SHDN = 2.7V • 50 75 µA IDD Supply Current Over-Temperature Shutdown 155 ˚C Over-Temperature Hysteresis 30 ˚C 4 FAN1655 Rev. 1.1.5 www.fairchildsemi.com FAN1655 3A DDR Bus Termination Regulator Absolute Maximum Ratings Output Capacitor selection Power Dissipation and Derating The JEDEC specification for DDR termination requires that VTT stay within ±40mV of VREF, which must track VDDQ/2 within 1%. During the initial load transient, the output capacitor keeps the output within spec. To stay within the 40mV window, the “load step” due to the load transient current dropping across the output capacitor’s ESR should be kept to around 25mV: where ESR < The maximum output current (sink or source) for a 1.25V output is: P D ( MAX ) I OUT ( MAX ) = --------------------1.25 where PD(MAX) is the maximum power dissipation which is: 25 ------ is given in mΩ, and ∆I is the maximum load current. ∆I T J ( MAX ) – T A P D ( MAX ) = ---------------------------------θ JA For example, to handle a 3A maximum load transient, the ESR should be no greater than 8mΩ. Furthermore, the output capacitor must be able to hold the load in spec while the regulator recovers (about 15µS). A minimum value of 470µF is recommended. where TJ(MAX) is the maximum die temperature of the IC and TA is the operating ambient temperature. FAN1655 has an internal thermal limit at 150°C, which defines TJ(MAX). For the SOIC-14 package, θJA is given at 88°C/W. Using equation 2, the maximum dissipation at TA = 25°C is 1.4W, which is its rated maximum dissipation. The FAN1655 requires a minimum of 100µF of input capacitance with a maximum ESR value of 100mΩ to insure stability. The e-TSSOP or MLP package, however, use the PCB copper to cool the IC through the thermal pad on the package bottom. For maximum dissipation, this pad should be soldered to the PCB copper, with as much copper area as possible surrounding it to cool the package. Thermal vias should be placed as close to the thermal pad as possible to transfer heat to other layers of copper on the PCB. With large areas of PCB copper for heat sinking, a θJA of under 40°C/W can easily be achieved. 5 FAN1655 Rev. 1.1.5 www.fairchildsemi.com FAN1655 3A DDR Bus Termination Regulator Applications Information 16-Lead eTSSOP 5.0 ± 0.1 0.10 TYP -A4.00 9 16 16 -B- 9 6.4 4.4 ± 0.1 7.72 3.40 4.16 3.2 1 8 0.2 C B A ALL LEAD TIPS PIN #1 IDENT. (1.78) 1 1.2 MAX ALL LEAD TIPS 0.1 C +0.15 (0.90) –0.10 -C- 8 0.42 TYP 0.65 TYP LAND PATTERN RECOMMENDATION 0.10±0.05 TYP (0.19–0.30) 0.65 TYP 0.10 M C B A SEE DETAIL A 1.7 MIN 9 (0.09–0.20) 16 1.5 MIN 12° TOP & BOTTOM GAGE PLANE R0.09MIN 0.25 0°–8° 8 1 SEATING PLANE 0.75 0.45 BOTTOM VIEW (1.00) DETAIL A NOTES: A. CONFORMS TO JEDEC REGISTRATION MO-153, VARIATION ABT, DATED 10/97. B. DIMENSIONS ARE IN MILLIMETERS. C. DIMENSIONS ARE EXCLUSIVE OF BURRS, MOLD FLASH, AND THE BAR EXTENSIONS. D. DIMENSIONS AND TOLERANCES PER ASME Y14.5M, 1994. 6 FAN1655 Rev. 1.1.5 www.fairchildsemi.com FAN1655 3A DDR Bus Termination Regulator Mechanical Dimensions 14-Lead SOIC 0.50 S8.71-8.51; 7.62 12 13 14 11 10 8 9 5.75 1.00 S4.00-3.80 S6.20-5.80; 1 2 3 4 1.27 5 6 1.27 7 7.62 S0.51-0.35; LAND PATTERN RECOMMENDATION S0.50-0.25;X45˚ S0.25-0.10;z S0.25-0.19; S8˚-0˚ S1.75-1.35; S1.27-0.40; SEATING PLANE Notes: 1. This package conforms to JEDEC MS-012, variation AB, ISSUEC dated May, 1990. 2. All dimensions are in millimeters 3. Standard lead finished 200 microinches / 5.08 microns min. Lead/Tin (solder) oncopper 7 FAN1655 Rev. 1.1.5 www.fairchildsemi.com FAN1655 3A DDR Bus Termination Regulator Mechanical Dimensions 5mm x 6mm 8-Lead MLP 5.0 A 4.50 B 6.25 3.50 6.0 4.25 0.25 (1.00) C 2X 0.25 TOP VIEW C 0.65 TYP 1.27 TYP 2X LAND PATTERN RECOMMENDATION 0.10 C (0.25) 1.0 MAX 0.08 C SIDE VIEW 0.05 0.00 C SEATING PLANE 4.25 A 1.75 1 2 3 4 0.75 A 0.35 PIN #1 IDENT. (OPTIONAL) 3.25 A 1.25 8 7 6 1.27 5 NOTES: A) DOES NOT FULLY CONFORM TO JEDEC REGISTRATION MO-229, DATED 11/2001. B) DIMENSIONS ARE IN MILLIMETERS. C) DIMENSIONING AND TOLERANCES PER ASME Y14.5–1994. 0.28–0.40 A 0.10 M C A B 3.81 A 0.05 M C BOTTOM VIEW 8 FAN1655 Rev. 1.1.5 www.fairchildsemi.com FAN1655 3A DDR Bus Termination Regulator Mechanical Dimensions The following are registered and unregistered trademarks Fairchild Semiconductor owns or is authorized to use and is not intended to be an exhaustive list of all such trademarks. ACEx™ FAST® ActiveArray™ FASTr™ Bottomless™ FPS™ Build it Now™ FRFET™ CoolFET™ GlobalOptoisolator™ CROSSVOLT™ GTO™ DOME™ HiSeC™ EcoSPARK™ I2C™ E2CMOS™ i-Lo™ EnSigna™ ImpliedDisconnect™ FACT™ IntelliMAX™ FACT Quiet Series™ Across the board. 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PRODUCT STATUS DEFINITIONS Definition of Terms Datasheet Identification Product Status Definition Advance Information Formative or In Design This datasheet contains the design specifications for product development. Specifications may change in any manner without notice. Preliminary First Production This datasheet contains preliminary data, and supplementary data will be published at a later date. Fairchild Semiconductor reserves the right to make changes at any time without notice in order to improve design. No Identification Needed Full Production This datasheet contains final specifications. Fairchild Semiconductor reserves the right to make changes at any time without notice in order to improve design. Obsolete Not In Production This datasheet contains specifications on a product that has been discontinued by Fairchild semiconductor. The datasheet is printed for reference information only. Rev. I17 9 FAN1655 Rev. 1.1.5 www.fairchildsemi.com FAN1655 3A DDR Bus Termination Regulator TRADEMARKS