Anpec APL3208BQB-TRG Li charger protection ic with integrated p-mosfet Datasheet

APL3208A/B/C
Li+ Charger Protection IC with Integrated P-MOSFET
Features
General Description
•
Input Over-Voltage Protection
•
Current-Limit Protection
The APL3208A/B/C provides complete Li+ charger protection against Input over-voltage, battery over-voltage,
•
Battery Over-Voltage Protection
•
High Immunity of False Triggering
•
High Accuracy Protection Threshold
•
A Built-In P-MOSFET
•
Available with 3 Versions of Charging Current:
and the charge current limit. When the input OVP or the
battery OVP is over the threshold, the IC removes the
power from the charging system by turning off an internal
switch. When the current via the internal switch surpasses
the current limit threshold, the current will be clamped in
a constant level to provide a constant current for battery
450mA, 550mA, 650mA
charging usage. All protections also have deglitch time
against false triggering due to voltage spikes or current
•
Thermal Shutdown Protection
•
Available in TDFN2x2-8 and TSOT-23-6A Packages
•
“Lithium-Safe” Criteria
•
Lead Free and Green Devices Available
transients.
The APL3208A/B/C integrates a P-MOSFET with the body
diode reverse protection to replace the external power
bipolar transistor and Schottky diode for charger function
(RoHS Compliant)
of the Infineon ULC2 mobile phones. When the CHG_DET
voltage drops below VBAT+20mV, the internal power se-
Applications
•
lect circuit will reverse the body diode’s terminal to prevent a reverse current flowing from the battery back to the
CHG_DET pin.
The APL3208A/B/C provides complete Li+ charger pro-
Cell Phones for Infineon
tections and save the external MOSFET and Schottky diode for the Infineon ULC2 mobile phones. The above
Pin Configuration
ACIN 1
ACIN 2
GND 3
VBAT 4
EP
features and small package make the APL3208A/B/C an
ideal part for cell phones applications.
8 OUT
7 OUT
6 CHG_DET
5 CHG_SW
Simplified Application Circuit
TDFN2x2-8
(Top View)
EP
5V Adapter
or USB
= Exposed Pad
(Connected to the ground plane for better heat
dissipation)
OUT 1
6 ACIN
CHG_DET 2
5 GND
CHG_SW 3
4 VBAT
R
VCHG_DET
ACIN CHG_DET
APL3208A/B/C
CHG_SW
OUT
GND
CHG_SW
VBAT
Li+
Battery
TSOT-23-6A
(Top View)
ANPEC reserves the right to make changes to improve reliability or manufacturability without notice, and
advise customers to obtain the latest version of relevant information to verify before placing orders.
Copyright  ANPEC Electronics Corp.
Rev. A.2 - Nov., 2009
1
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APL3208A/B/C
Ordering and Marking Information
APL3208A
APL3208B
APL3208C
Package Code
QB : TDFN2x2-8 CT : TSOT-23-6A
Operating Ambient Temperature Range
I : -40 to 85 oC
Handling Code
TR : Tape & Reel
Assembly Material
G : Halogen and Lead Free Device
Assembly Material
Handling Code
Temperature Range
Package Code
APL3208A
QB:
L08A
X
X - Date Code
APL3208B
QB:
L08B
X
X - Date Code
APL3208C
QB:
L08C
X
X - Date Code
APL3208A
CT:
L8AX
X - Date Code
APL3208B
CT:
L8BX
X - Date Code
APL3208C
CT:
L8CX
X - Date Code
Note: ANPEC lead-free products contain molding compounds/die attach materials and 100% matte tin plate termination finish; which
are fully compliant with RoHS. ANPEC lead-free products meet or exceed the lead-free requirements of IPC/JEDEC J-STD-020D for
MSL classification at lead-free peak reflow temperature. ANPEC defines “Green” to mean lead-free (RoHS compliant) and halogen
free (Br or Cl does not exceed 900ppm by weight in homogeneous material and total of Br and Cl does not exceed 1500ppm by
weight).
Absolute Maximum Ratings (Note 1)
Symbol
VACIN
Parameter
ACIN Input Voltage (ACIN to GND)
Rating
Unit
-0.3 ~ 30
V
VCHG_DET
CHG_DET to GND Voltage
-0.3 ~ 7
V
VCHG_SW
CHG_SW to GND Voltage
-0.3 ~ VCHG_DET
V
VBAT
VBAT to GND Voltage
-0.3 ~ 7
V
VOUT
OUT to GND Voltage
-0.3 ~ 7
V
IOUT
TJ
TSTG
TSDR
OUT Output Current
1.5
Maximum Junction Temperature
150
o
-65 ~ 150
o
260
o
Storage Temperature
Maximum Lead Soldering Temperature, 10 Seconds
A
C
C
C
Note 1: Absolute Maximum Ratings are those values beyond which the life of a device may be impaired. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
Thermal Characteristics
Symbol
Parameter
Junction-to-Ambient Resistance in Free Air
Typical Value
Unit
(Note 2)
θJA
TDFN2x2-8
80
TSOT-23-6A
235
o
C/W
Note 2: θJA is measured with the component mounted on a high effective thermal conductivity test board in free air. The exposed pad
of TDFN2x2-8 is soldered directly on the PCB.
Copyright  ANPEC Electronics Corp.
Rev. A.2 - Nov., 2009
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APL3208A/B/C
Recommended Operating Conditions (Note 3)
Symbol
VACIN
Parameter
Range
ACIN Input Voltage
Unit
4.5 ~ 5.5
V
TA
Ambient Temperature
-40 ~ 85
o
TJ
Junction Temperature
-40 ~ 125
o
C
C
Note 3: Refer to the typical application circuit
Electrical Characteristics
Unless otherwise specified, these specifications apply over VACIN=5V, VBAT=3.8V and TA= -40 ~ 85 oC. Typical values are at TA=25oC.
Symbol
Parameter
Test Conditions
APL3208A/B/C
Min.
Typ.
Max.
Unit
ACIN INPUT CURRENT AND POWER-ON-RESET (POR)
IACIN
ACIN Supply Current
IOUT=0A, ICHG_DET=0A
VACIN
ACIN POR Threshold
VACIN rising
ACIN POR Hysteresis
TB(ACIN)
ACIN Power-On Blanking Time
-
250
350
µA
2.4
-
2.8
V
200
250
300
mV
-
8
-
ms
-
500
-
Ω
INTERNAL SWITCH ON RESISTANCE
CHG_DET Discharge On
Resistance
INPUT OVER-VOLTAGE PROTECTION (OVP)
VOVP
Input OVP Threshold
VACIN rising
6
6.17
6.35
V
200
300
400
mV
Input OVP Propagation Delay
-
-
1
µs
Input OVP Recovery Time
-
8
-
ms
APL3208A, TA=25°C
400
450
500
APL3208B, TA=25°C
500
550
600
APL3208C, TA=25°C
600
650
700
VBAT rising
4.32
4.35
4.38
V
220
270
320
mV
-
-
20
nA
-
176
-
µs
VCHG_DET from low to high, P-MOSFET is
controlled by CHG_SW
-
120
-
VCHG_DET from high to low, P-MOSFET is off
-
20
-
OUT Input Current
VCHG_DET=0V, VOUT=4.2V, CHG_SW =GND
-
-
1
µA
CHG_SW Leakage Current
VACIN=VCHG_DET= VOUT=5V, VCHG_SW=0V
-
7.5
13
µA
OUT Leakage Current
VACIN=VCHG_DET= VCHG_SW =5V, VOUT=0V
-
-
1
µA
Input OVP Hysteresis
TON(OVP)
CURRENT-LIMIT PROTECTION
ILIM
Current Limit Threshold
mA
BATTERY OVER-VOLTAGE PROTECTION
VBOVP
Battery OVP Threshold
Battery OVP Hysteresis
IVBAT
VBAT Pin Leakage Current
TB(BOVP)
Battery OVP Blanking Time
VBAT = 4.4V
INTERNAL P-MOSFET (CHG_DET, OUT AND CHG_SW PINS)
VCHG_DET-VBAT Lockout Threshold
Copyright  ANPEC Electronics Corp.
Rev. A.2 - Nov., 2009
3
mV
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APL3208A/B/C
Electrical Characteristics (Cont.)
Unless otherwise specified, these specifications apply over VACIN=5V, VBAT=3.8V and TA= -40 ~ 85 oC. Typical values are at
TA=25oC.
Symbol
Parameter
Test Conditions
APL3208A/B/C
Unit
Min.
Typ.
Max.
P-MOSFET Input Capacitance
-
200
-
pF
CHG_SW Input Resistance
-
15
-
Ω
-
160
-
°C
-
40
-
°C
INTERNAL P-MOSFET (CHG_DET, OUT AND CHG_SW PINS) (CONT.)
OVER-TEMPERATURE PROTECTION (OTP)
TOTP
Over-Temperature Threshold
TJ rising
Over-Temperature Hysteresis
Copyright  ANPEC Electronics Corp.
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APL3208A/B/C
Operating Waveforms
The test condition is VACIN=5V, VBAT=3.8V, TA= 25oC unless otherwise specified.
Normal Power On
OVP at Power On
VACIN
VACIN
1
VOUT
1
VCHG_DET
2
VCHG_DET
VOUT
2,3
IOUT
4
3
CACIN =1µF, COUT =1µF, VCHG_SW = VCHG_DET
CH1: VACIN, 5V/Div, DC
CH2: VOUT, 2V/Div, DC
CH3: VCHG_DET, 2V/Div, DC
CH4: I OUT, 0.2A/Div, DC
TIME: 2ms/Div
CACIN =1µF, COUT =1µF
CH1: VACIN, 10V/Div, DC
CH2: VCHG_DET, 1V/Div, DC
CH3: VOUT, 2V/Div, DC
TIME: 2ms/Div
Input Over-Voltage Protection
Recovery from Input OVP
VACIN
VACIN
1
1
VCHG_DET
VCHG_DET
2
2
VOUT
3
VACIN= 12V to 5V, VCHG_SW = VCHG_DET
CACIN =1µF, COUT =1µF
CH1: VACIN, 5V/Div, AC
CH2: VCHG_DET, 2V/Div, DC
CH3: VOUT, 2V/Div, DC
TIME: 2ms/Div
VACIN =5V to 12V, VCHG_SW = 0V, No Load
CACIN =1µF, COUT =1µF
CH1: VACIN, 5V/Div, AC
CH2: VCHG_DET, 2V/Div, DC
TIME:20µs/Div
Copyright  ANPEC Electronics Corp.
Rev. A.2 - Nov., 2009
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APL3208A/B/C
Operating Waveforms (Cont.)
The test condition is VACIN=5V, VBAT=3.8V, TA= 25oC unless otherwise specified.
Battery Over-Voltage Protection
Battery Over-Voltage Protection
VBAT
VBAT
1
1
VCHG_DET
VCHG_DET
2
2
VBAT = 3.6V to 4.4V
CACIN=1µF, COUT =1µF
CH1: VBAT, 2V/Div, DC
CH2: VCHG_DET, 2V/Div, DC
TIME: 200µs/Div
VBAT = 3.6V to 4.4V to 3.6V
CACIN =1µF, COUT =1µF
CH1: VBAT, 2V/Div, DC
CH2: VCHG_DET, 2V/Div, DC
TIME: 50ms/Div
Pin Description
PIN
NO.
FUNCTION
NAME
TDFN2x2-8 TSOT-23-6A
1, 2
6
ACIN
Power Supply Input. Connect this pin to external DC supply. Bypass to GND with a 1µF
(minimum) ceramic capacitor.
3
5
GND
Ground Terminal.
4
4
VBAT
Battery Voltage Sense Input. Connect this pin to pack positive terminal through a
resistor.
5
3
CHG_SW
Internal P-MOSFET Gate Input.
6
2
CHG_DET
Output Pin. This pin provides supply voltage to the Infineon ULC2 input. Bypass to GND
with a 1µF (minimum) ceramic capacitor.
7, 8
1
OUT
Output Pins. These pins provide supply source current in series with a resistor to battery.
Exposed
Pad
-
EP
Exposed Thermal Pad. Must be electrically connected to the GND pin.
Copyright  ANPEC Electronics Corp.
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APL3208A/B/C
Block Diagram
ACIN
CHG_DET
POR
OUT
Charge
Pump
ACIN
OVP
Gate Driver and
Control Logic
VBAT
OVP
0.5V
CHG_SW
1V
GND
VBAT
Thermal
Shutdown
Typical Application Circuit
5V Adapter or USB
1, 2
CACIN
1µF
ACIN
CHG_DET
6
CHG_SW
OUT
GND
R1
R2
2.2kΩ
20~100kΩ
1µF
APL3208A/B/C
3
CHG_DET
C1
VBAT
5
C2
33nF
Infineon
ULC2
CHG_SW
7, 8
4
VBAT
RBAT
(Optional)
Li+
Battery
200kΩ
Designation
Description
CACIN
1µF, 50V, X7R, 0805
Murata GRM21BR71H105K
C1
1µF, 10V, X7R, 0805
Murata GRM21BR71A105K
Murata website: www.murata.com
Figure 1. Infineon ULC2 Application Circuit
Copyright  ANPEC Electronics Corp.
Rev. A.2 - Nov., 2009
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APL3208A/B/C
Typical Application Circuit (Cont.)
1, 2
ACIN
CACIN
1µF
CHG_DET
6
CHG_DET
COUT
1µF
APL3208
CHG_SW
OUT
3
GND
VBAT
PMIC
5
CHG_SW
7, 8
4
VBAT
RBAT
200kΩ
(Optional)
Designation
Li+
Battery
Description
CACIN
1µF, 50V, X7R, 0805
Murata GRM21BR71H105K
COUT
1µF, 10V, X7R, 0805
Murata GRM21BR71A105K
Murata website: www.murata.com
Figure 2. General Application Circuit
Copyright  ANPEC Electronics Corp.
Rev. A.2 - Nov., 2009
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APL3208A/B/C
Function Description
ACIN Power-On-Reset (POR)
Over-Temperature Protection
The APL3208A/B/C has a built-in power-on-reset circuit
to keep the output shutting off until internal circuitry is
When the junction temperature exceeds 160oC, the internal thermal sense circuit turns off the power FET and
allows the device to cool down. When the device’s junc-
operating properly. The POR circuit has hysteresis and a
de-glitch feature so that it will typically ignore undershoot
tion temperature cools by 40 oC, the internal thermal
sense circuit will enable the device, resulting in a pulsed
transients on the input. When the input voltage exceeds
the POR threshold and after 8ms blanking time, the out-
output during continuous thermal protection. Thermal protection is designed to protect the IC in the event of over
put voltage starts a soft-start to reduce the inrush current.
temperature conditions. For normal operation, the junction temperature cannot exceed TJ=+125oC.
ACIN Over-Voltage Protection (OVP)
The input voltage is monitored by the internal OVP circuit.
Internal P-MOSFET
When the input voltage rises above the input OVP
threshold, the internal FET will be turned off within 1ms to
The APL3208A/B/C integrates a P-channel MOSFET with
protect the connected system on OUT pin. When the input voltage returns below the input OVP threshold minus
the body diode reverse protection to replace the external
power bipolar transistor and Schottky diode for the Infineon
the hysteresis, the FET is turned on again after 8ms recovery time. The input OVP circuit has a 200mV hyster-
ULC2 mobile. The body diode reverse protection prevents a reverse current flowing from the battery back to
esis and a recovery time of TON(OVP) to provide noise immunity against transient conditions.
the CHG_DET pin. During power-on, when CHG_DET
voltage rises above the VBAT voltage by more than
Battery Over-Voltage Protection
120mV, the body diode of the P-channel MOSFET is forward biased from OUT to CHG_DET, and P-MOSFET is
The APL3208A/B/C monitors the VBAT pin voltage for bat-
controlled by the external CHG_SW voltage. When the
tery over-voltage protection. The battery OVP threshold is
internally set to 4.35V. When the VBAT pin voltage ex-
CHG_DET voltage drops below VBAT+20mV, the body diode of the P-channel MOSFET is forward biased from
ceeds the battery OVP threshold for a blanking time of TB
, the internal power FET is turned off. When the VBAT
(BOVP)
CHG_DET to OUT and P-channel MOSFET is turned off.
When any of input OVP, battery OVP, is detected,the inter-
voltage returns below the battery OVP threshold minus
the hysteresis, the FET is turned on again. The APL3208A/
nal P-channel MOSFET is also turned off.
B/C has a built-in counter. When the total count of battery
OVP fault reaches 16, the FET is turned off permanently,
requiring a VACIN POR again to restart.
Current-Limit Protection
The APL3208A/B/C provides a current-limit protection
function. When the current via the internal switch surpasses the current limit threshold, the current will be
clamped to a constant level to provide external battery
charging current.
Copyright  ANPEC Electronics Corp.
Rev. A.2 - Nov., 2009
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APL3208A/B/C
Function Description (Cont.)
VOVP
VPOR
VACIN
VCHG_DET -VBAT = 120mV
VCHG_DET -VBAT = 120mV
VCHG_DET
VOUT
CHG_SW is pulled low
P-MOS Gate
Control
Turn Off Internal
P-MOSFET
Controlled
by CHG_SW
Controlled by
CHG_SW
Turn Off Internal P-MOSFET
TB(ACIN)
ACIN OVP
TON(OVP)
Figure 3. OVP Timing Diagram
VBAT
VBOVP
VBOVP
VCHG_DET -VOUT = 120mV
VCHG_DET
Count 13
times
P-MOS Gate Controlled
Control
by CHG_SW
Turn Off Internal
P-MOSFET
TB(BOVP)
Controlled by
CHG_SW
Turn Off
Internal
P-OSFET
TB(BOVP)
Controlled by
CHG_SW
Turn Off Internal
P-MOSFET
TB(BOVP)
Total count 16
times, IC is
latched off
Figure 4. Battery OVP Timing Diagram
Copyright  ANPEC Electronics Corp.
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APL3208A/B/C
Application Information
RBAT Selection
Connect the VBAT pin to the positive terminal of battery
through a resistor RBAT for battery OVP function. The RBAT
limits the current flowing from VBAT to battery in case of
VBAT pin is shortened to ACIN pin under a failure mode.
The recommended value of RBAT is 200kΩ. In the worse
case of an IC failure, the current flowing from the VBAT
pin to the battery is:
(30V-3V)/ 200kΩ =135µA
where the 30V is the maximum ACIN voltage and the 3V
is the minimum battery voltage. The current is so small
and can be absorbed by the charger system.
Capacitor Selection
The input capacitor is for decoupling and prevents the
input voltage from overshooting to dangerous levels. In
the AC adapter hot plug-in applications or load current
step-down transient, the input voltage has a transient
spike due to the parasitic inductance of the input cable. A
50V, X7R, dielectric ceramic capacitor with a value between 1µF and 4.7µF placed close to the ACIN pin is
recommended.
The output capacitor of CHG_DET is for CHG_DET voltage decoupling. And also can be as the input capacitor of
the charging circuit. At least, a 1µF, 10V, X7R capacitor is
recommended.
Layout Consideration
In some failure modes, a high voltage may be applied to
the device. Make sure the clearance constraint of the PCB
layout must satisfy the design rule for high voltage. The
exposed pad of the TDFN2x2-8 performs the function of
channeling heat away. It is recommended that connect
the exposed pad to a large copper ground plane on the
backside of the circuit board through several thermal vias
to improve heat dissipation. The input and output capacitors should be placed close to the IC. The high current
traces like input trace and output trace must be wide and
short.
Copyright  ANPEC Electronics Corp.
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APL3208A/B/C
Package Information
TDFN2x2-8
A
b
E
D
D2
A1
E2
A3
L
Pin 1 Corner
e
S
Y
M
B
O
L
MIN.
MAX.
MIN.
MAX.
A
0.70
0.80
0.028
0.031
A1
0.00
0.05
0.000
0.002
TDFN2x2-8
MILLIMETERS
A3
INCHES
0.20 REF
0.008 REF
b
0.18
0.30
0.007
0.012
D
1.90
2.10
0.075
0.083
0.063
D2
1.00
1.60
0.039
E
1.90
2.10
0.075
0.083
1.00
0.024
0.039
0.45
0.012
E2
0.60
e
L
0.50 BSC
0.30
0.020 BSC
0.018
Note : 1. Follow from JEDEC MO-229 WCCD-3.
Copyright  ANPEC Electronics Corp.
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APL3208A/B/C
Package Information
TSOT-23-6A
D
e
E
E1
SEE VIEW A
b
c
0.25
A
GAUGE PLANE
SEATING PLANE
L
A1
A2
e1
VIEW A
S
Y
M
B
O
L
TSOT-23-6A
INCHES
MILLIMETERS
MIN.
MAX.
0.70
A1
A2
A
MIN.
MAX.
1.00
0.028
0.039
0.01
0.10
0.000
0.004
0.70
0.90
0.028
0.035
0.020
b
0.30
0.50
0.012
c
0.08
0.20
0.003
0.008
D
2.70
3.10
0.106
0.122
E
2.60
3.00
0.102
0.118
E1
1.40
1.80
0.055
0.071
e
0.95 BSC
e1
1.90 BSC
L
0
0.037 BSC
0.075 BSC
0.30
0.60
0°
8°
0.012
0.024
0°
8°
Note : Dimension D and E1 do not include mold flash, protrusions or gate
burrs. Mold flash, protrusion or gate burrs shall not exceed 10 mil
per side.
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APL3208A/B/C
Carrier Tape & Reel Dimensions
P0
P2
P1
A
B0
W
F
E1
OD0
K0
A0
A
OD1 B
B
T
SECTION A-A
SECTION B-B
H
A
d
T1
Application
TDFN2x2-8
Application
TSOT-23-6A
A
H
T1
C
d
D
W
E1
F
178.0±2.00
50 MIN.
8.4+2.00
-0.00
13.0+0.50
-0.20
1.5 MIN.
20.2 MIN.
8.0±0.20
1.75±0.10
3.50±0.05
P0
P1
P2
D0
D1
T
A0
B0
K0
1.5 MIN.
0.6+0.00
-0.4
3.35 MIN
3.35 MIN
1.30±0.20
4.0±0.10
4.0±0.10
2.0±0.05
1.5+0.10
-0.00
A
H
T1
C
d
D
W
E1
F
178.0±2.00
50 MIN.
8.4+2.00
-0.00
13.0+0.50
-0.20
1.5 MIN.
20.2 MIN.
8.0±0.30
1.75±0.10
3.5±0.05
P0
P1
P2
D0
D1
T
A0
B0
K0
4.0±0.10
4.0±0.10
2.0±0.05
1.5+0.10
-0.00
1.0 MIN.
0.6+0.00
-0.40
3.20±0.20
3.10±0.20
1.50±0.20
(mm)
Devices Per Unit
Package Type
Unit
Quantity
TDFN2x2-8
Tape & Reel
3000
TSOT-23-6A
Tape & Reel
3000
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APL3208A/B/C
Taping Direction Information
TDFN2x2-8
USER DIRECTION OF FEED
TSOT-23-6A
USER DIRECTION OF FEED
AAAX
AAAX
Copyright  ANPEC Electronics Corp.
Rev. A.2 - Nov., 2009
AAAX
AAAX
15
AAAX
AAAX
AAAX
www.anpec.com.tw
APL3208A/B/C
Classification Profile
Classification Reflow Profiles
Profile Feature
Sn-Pb Eutectic Assembly
Pb-Free Assembly
100 °C
150 °C
60-120 seconds
150 °C
200 °C
60-120 seconds
3 °C/second max.
3°C/second max.
183 °C
60-150 seconds
217 °C
60-150 seconds
See Classification Temp in table 1
See Classification Temp in table 2
Time (tP)** within 5°C of the specified
classification temperature (Tc)
20** seconds
30** seconds
Average ramp-down rate (Tp to Tsmax)
6 °C/second max.
6 °C/second max.
6 minutes max.
8 minutes max.
Preheat & Soak
Temperature min (Tsmin)
Temperature max (Tsmax)
Time (Tsmin to Tsmax) (ts)
Average ramp-up rate
(Tsmax to TP)
Liquidous temperature (TL)
Time at liquidous (tL)
Peak package body Temperature
(Tp)*
Time 25°C to peak temperature
* Tolerance for peak profile Temperature (Tp) is defined as a supplier minimum and a user maximum.
** Tolerance for time at peak profile temperature (tp) is defined as a supplier minimum and a user maximum.
Copyright  ANPEC Electronics Corp.
Rev. A.2 - Nov., 2009
16
www.anpec.com.tw
APL3208A/B/C
Classification Reflow Profiles (Cont.)
Table 1. SnPb Eutectic Process – Classification Temperatures (Tc)
Package
Thickness
<2.5 mm
≥2.5 mm
Volume mm
<350
235 °C
220 °C
3
Volume mm
≥350
220 °C
220 °C
3
Table 2. Pb-free Process – Classification Temperatures (Tc)
Package
Thickness
<1.6 mm
1.6 mm – 2.5 mm
≥2.5 mm
Volume mm
<350
260 °C
260 °C
250 °C
3
Volume mm
350-2000
260 °C
250 °C
245 °C
3
Volume mm
>2000
260 °C
245 °C
245 °C
3
Reliability Test Program
Test item
SOLDERABILITY
HOLT
PCT
TCT
HBM
MM
Latch-Up
Method
JESD-22, B102
JESD-22, A108
JESD-22, A102
JESD-22, A104
MIL-STD-883-3015.7
JESD-22, A115
JESD 78
Description
5 Sec, 245°C
1000 Hrs, Bias @ 125°C
168 Hrs, 100%RH, 2atm, 121°C
500 Cycles, -65°C~150°C
VHBM≧2KV
VMM≧200V
10ms, 1tr≧100mA
Customer Service
Anpec Electronics Corp.
Head Office :
No.6, Dusing 1st Road, SBIP,
Hsin-Chu, Taiwan, R.O.C.
Tel : 886-3-5642000
Fax : 886-3-5642050
Taipei Branch :
2F, No. 11, Lane 218, Sec 2 Jhongsing Rd.,
Sindian City, Taipei County 23146, Taiwan
Tel : 886-2-2910-3838
Fax : 886-2-2917-3838
Copyright  ANPEC Electronics Corp.
Rev. A.2 - Nov., 2009
17
www.anpec.com.tw
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