PRELIMINARY DATA SHEET 128MB DDR SDRAM S.O. DIMM HB54A1288KM (16M words × 64 bits, 1 Bank) Features The HB54A1288KM is a 16M × 64 × 1 bank Double Data Rate (DDR) SDRAM Module, mounted 4 pieces of 256Mbits DDR SDRAM (HM5425161BTT) sealed in TSOP package and 1 piece of serial EEPROM (2k bits EEPROM) for Presence Detect (PD). Read and write operations are performed at the cross points of the CK and the /CK. This high-speed data transfer is realized by the 2-bit prefetch-pipelined architecture. Data strobe (DQS) both for read and write are available for high speed and reliable data bus design. By setting extended mode register, the on-chip Delay Locked Loop (DLL) can be set enable or disable. An outline of the products is 200-pin socket type package (dual lead out). Therefore, it makes high density mounting possible without surface mount technology. It provides common data inputs and outputs. Decoupling capacitors are mounted beside each TSOP on the module board. • 200-pin socket type package (dual lead out) Outline: 67.6mm (Length) × 31.75mm (Height) × 3.80mm (Thickness) Lead pitch: 0.6mm • 2.5V power supply (VCC/VCCQ) • SSTL-2 interface for all inputs and outputs • Clock frequency: 133MHz/100MHz (max.) • Data inputs and outputs are synchronized with DQS • 4 banks can operate simultaneously and independently (Component) • Burst read/write operation • Programmable burst length: 2, 4, 8 Burst read stop capability • Programmable burst sequence Sequential Interleave • Start addressing capability Even and Odd • Programmable /CAS latency (CL): 2, 2.5 • 8192 refresh cycles: 7.8µs (8192/64ms) • 2 variations of refresh Auto refresh Self refresh L EO Description t uc od Pr Document No. E0190H10 (Ver. 1.0) Date Published September 2001 (K) Printed in Japan URL: http://www.elpida.com This product became EOL in May, 2004. C Elpida Memory, Inc. 2001 Elpida Memory, Inc. is a joint venture DRAM company of NEC Corporation and Hitachi, Ltd. HB54A1288KM Ordering Information Part number Clock frequency MHz (max.) /CAS latency Package HB54A1288KM-A75B*1 HB54A1288KM-B75B*2 HB54A1288KM-10B* 133 133 100 2.0 2.5 2.0 200-pin dual lead out socket Gold type Contact pad Notes: 1. 143MHz operation at /CAS latency = 2.5 2. 100MHz operation at /CAS latency = 2.0 3. 125MHz operation at /CAS latency = 2.5 Pin Configurations Front side EO 1 pin 39 pin 41 pin 199 pin 2 pin 40 pin 42 pin 200 pin Back side Pin name Pin No. Pin name Pin No. Pin name Pin No. Pin name 1 VREF 51 VSS 2 VREF 52 VSS 3 VSS 53 DQ19 4 VSS 54 DQ23 5 DQ0 55 DQ24 6 DQ4 56 DQ28 7 DQ1 57 VCC 8 DQ5 58 VCC 9 VCC 59 DQ25 10 VCC 60 DQ29 11 DQS0 61 DQS3 12 DM0 62 DM3 13 DQ2 63 15 VSS 65 17 DQ3 67 19 DQ8 69 21 VCC 71 23 DQ9 73 25 DQS1 75 VSS 27 VSS 77 NC L Pin No. Pr 14 DQ6 64 VSS 16 VSS 66 DQ30 DQ27 18 DQ7 68 DQ31 VCC 20 DQ12 70 VCC NC 22 VCC 72 NC NC 24 DQ13 74 NC 26 DM1 76 VSS 28 VSS 78 NC 30 DQ14 80 NC 32 DQ15 82 VCC 34 VCC 84 NC 36 VCC 86 NC 88 VSS 90 VSS od VSS DQ26 DQ10 79 NC 31 DQ11 81 VCC 33 VCC 83 NC 35 CK0 85 NC 37 /CK0 87 VSS 38 VSS 39 VSS 89 CK2 40 VSS 41 DQ16 91 /CK2 42 DQ20 92 VCC 43 DQ17 93 VCC 44 DQ21 94 VCC 45 VCC 95 NC 46 VCC 96 CKE0 47 DQS2 97 NC 48 DM2 98 NC 49 DQ18 99 A12 50 DQ22 100 A11 Preliminary Data Sheet E0190H10 (Ver. 1.0) 2 t uc 29 HB54A1288KM Pin No. Pin name Pin No. Pin name Pin No. Pin name Pin No. Pin name 101 A9 151 DQ42 102 A8 152 DQ46 103 VSS 153 DQ43 104 VSS 154 DQ47 105 A7 155 VCC 106 A6 156 VCC 107 A5 157 VCC 108 A4 158 /CK1 A3 159 VSS 110 A2 160 CK1 111 A1 161 VSS 112 A0 162 VSS 113 VCC 163 DQ48 114 VCC 164 DQ52 115 A10/AP 165 DQ49 116 BA1 166 DQ53 117 BA0 167 VCC 118 /RAS 168 VCC 119 /WE 169 DQS6 120 /CAS 170 DM6 121 /S0 171 DQ50 122 NC 172 DQ54 123 NC 173 VSS 124 NC 174 VSS 125 VSS 175 DQ51 126 VSS 176 DQ55 127 DQ32 177 DQ56 128 DQ36 178 DQ60 129 DQ33 179 VCC 130 DQ37 180 VCC 131 VCC 181 DQ57 132 VCC 182 DQ61 133 DQS4 183 DQS7 134 DM4 184 DM7 135 DQ34 185 VSS 136 DQ38 186 VSS 137 VSS 187 DQ58 138 VSS 188 DQ62 139 DQ35 189 DQ59 140 DQ39 190 DQ63 141 DQ40 191 VCC 142 DQ44 192 VCC 143 VCC 193 SDA 144 VCC 194 SA0 145 DQ41 195 SCL 146 DQ45 196 SA1 147 DQS5 197 VCCSPD 148 DM5 198 SA2 149 VSS 199 VCCID 150 VSS 200 NC L EO 109 t uc od Pr Preliminary Data Sheet E0190H10 (Ver. 1.0) 3 HB54A1288KM Pin Description Pin name Function A0 to A12 Address input Row address Column address BA0, BA1 Bank select address DQ0 to DQ63 Data input/output /RAS Row address strobe command /CAS Column address strobe command A0 to A12 A0 to A8 Write enable /S0 Chip select CKE0 Clock enable CK0 to CK2 Clock input /CK0 to /CK2 Differential clock input DQS0 to DQS7 Input and output data strobe EO /WE DM0 to DM7 Input mask SCL Clock input for serial PD SDA Data input/output for serial PD SA0 to SA2 Serial address input VCCSPD VREF VSS L VCC VCCID Power for serial EEPROM Input reference voltage Ground VCC indentication flag Pr NC Power for internal circuit No connection t uc od Preliminary Data Sheet E0190H10 (Ver. 1.0) 4 HB54A1288KM 1 Serial PD Matrix* Byte No. 0 1 Function described Number of bytes utilized by module manufacturer Total number of bytes in serial PD device Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Hex value Comments 1 0 0 0 0 0 0 0 80 128 0 0 0 0 1 0 0 0 08 256 byte 2 Memory type 0 0 0 0 0 1 1 1 07 SDRAM DDR 3 Number of row address 0 0 0 0 1 1 0 1 0D 13 Number of column address 0 0 0 0 1 0 0 1 09 9 5 Number of DIMM banks 0 0 0 0 0 0 0 1 01 1 6 Module data width 0 1 0 0 0 0 0 0 40 64 bits 7 Module data width continuation 0 0 0 0 0 0 0 0 00 0 (+) 8 Voltage interface level of this assembly 0 0 0 0 0 1 0 0 04 SSTL 2.5V 9 DDR SDRAM cycle time, CL = X -A75B 0 1 1 1 0 0 0 0 70 CL = 2.5*5 -B75B 0 1 1 1 0 1 0 1 75 -10B 1 0 0 0 0 0 0 0 80 0 1 1 1 0 0 0 0 70 0.7ns*5 1 0 0 0 0 0 0 0 80 0.8ns*5 EO 4 10 SDRAM access from clock (tAC) -A75B/B75B -10B DIMM configuration type 0 0 0 0 0 0 0 0 00 Non-parity 12 Refresh rate/type 1 0 0 0 0 0 1 0 82 7.8 µs Self refresh 13 Primary SDRAM width 0 0 0 1 0 0 0 0 10 × 16 14 Error checking SDRAM width 0 0 0 0 0 0 0 0 00 Not used 16 17 18 20 0 0 0 0 0 0 0 1 01 1 CLK 0 0 0 0 1 1 1 0 0E 2, 4, 8 0 0 0 0 0 1 0 0 04 4 0 0 0 0 1 1 0 0 0C 2/2.5 0 0 0 0 od 19 SDRAM device attributes: Minimum clock delay back-to-back column access SDRAM device attributes: Burst length supported SDRAM device attributes: Number of banks on SDRAM device SDRAM device attributes: /CAS latency SDRAM device attributes: /CS latency SDRAM device attributes: /WE latency Pr 15 L 11 0 0 0 0 1 01 0 0 0 0 0 1 0 02 1 1 0 0 0 0 0 20 Unbuffered 0 0 0 0 0 0 00 ± 0.2V 1 1 0 1 0 1 75 CL = 2*5 0 0 A0 0 0 70 0.7ns*5 0 0 80 0.8ns*5 0 0 00 0 0 00 0 0 50 21 SDRAM module attributes 0 0 22 SDRAM device attributes: General 0 0 23 Minimum clock cycle time at CLX - 1 -A75B 0 1 1 0 1 0 0 0 24 Maximum data access time (tAC) from 0 clock at CLX - 1 -A75B/B75B 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 -B75B/10B -10B 25 26 27 1 Minimum clock cycle time at 0 CLX - 1 Maximum data access time (tAC) from 0 clock at CLX - 1 Minimum row precharge time (tRP) 0 Preliminary Data Sheet E0190H10 (Ver. 1.0) 5 t uc 0 20ns HB54A1288KM Byte No. Function described Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Hex value Comments 28 Minimum row active to row active delay (tRRD) 0 0 1 1 1 1 0 0 3C 15ns 29 Minimum /RAS to /CAS delay (tRCD) 0 1 0 1 0 0 0 0 50 20ns 30 Minimum active to precharge time (tRAS) -A75B/B75B 0 0 1 0 1 1 0 1 2D 45ns 0 0 1 1 0 0 1 0 32 50ns -10B 31 Module bank density 0 0 1 0 0 0 0 0 20 1 bank 128MB 32 Address and command setup time before clock (tIS) -A75B/B75B 1 0 1 1 0 0 0 0 B0 1.1ns*5 1 1 0 0 0 0 0 0 C0 1.2ns*5 Address and command hold time after 1 clock (tIH) -A75B/B75B 0 1 1 0 0 0 0 B0 1.1ns*5 1 1 0 0 0 0 0 0 C0 1.2ns*5 0 1 0 1 0 0 0 0 50 0.5ns*5 0 1 1 0 0 0 0 0 60 0.6ns*5 0 1 0 1 0 0 0 0 50 0.5ns*5 0 1 1 0 0 0 0 0 60 0.6ns*5 -10B EO 33 -10B 34 Data input setup time before clock (tDS) -A75B/B75B -10B 35 Data input hold time after clock (tDH) -A75B/B75B L -10B 36 to 40 Superset information 0 0 0 0 0 0 0 0 00 Future use 41 Active command period (tRC) -A75B/B75B 0 1 0 0 0 0 0 1 41 65ns*5 0 1 0 0 0 1 1 0 46 70ns*5 -10B Pr 42 Auto refresh to active/ Auto refresh command cycle (tRFC) -A75B/B75B -10B 0 1 0 0 1 0 1 1 4B 75ns*5 0 1 0 1 0 0 0 0 50 80ns*5 SDRAM tCK cycle max. (tCK max.) 0 0 1 1 1 1 0 0 3C 15ns*5 44 Dout to DQS skew -A75B/B75B 0 0 1 1 0 0 1 0 32 500ps*5 0 0 0 1 1 0 -10B 45 Data hold skew (tQHS) -A75B/B75B -10B od 43 1 1 1 1 0 0 3C 600ps*5 1 1 0 1 0 1 75 750ps*5 1 0 0 0 0 0 A0 1000ps*5 0 0 0 0 0 0 00 Future use 0 0 0 0 0 0 00 Initial 0 1 1 0 1 1 1B 27 Superset information 0 0 62 SPD revision 0 0 63 Checksum for bytes 0 to 62 -A75B 0 0 -B75B 0 1 0 0 1 0 -10B 1 1 1 1 1 0 64 Manufacturer’s JEDEC ID code 0 0 0 0 0 1 65 to 71 Manufacturer’s JEDEC ID code 0 0 0 0 0 0 72 Manufacturing location × × × × × × 73 Module part number 0 1 0 0 1 0 74 Module part number 0 1 0 0 0 0 75 Module part number 0 0 1 1 0 1 Preliminary Data Sheet E0190H10 (Ver. 1.0) 6 t uc 46 to 61 1 1 4B 75 1 0 FA 250 HITACHI 1 1 07 0 0 00 × × ×× *2 (ASCII-8bit code) 0 0 48 H 1 0 42 B 0 1 35 5 HB54A1288KM Function described Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Hex value Comments 76 Module part number 0 0 1 1 0 1 0 0 34 4 77 Module part number 0 1 0 0 0 0 0 1 41 A 78 Module part number 0 0 1 1 0 0 0 1 31 1 79 Module part number 0 0 1 1 0 0 1 0 32 2 80 Module part number 0 0 1 1 1 0 0 0 38 8 81 Module part number 0 0 1 1 1 0 0 0 38 8 82 Module part number 0 1 0 0 1 0 1 1 4B K 83 Module part number 0 1 0 0 1 1 0 1 4D M 84 Module part number 0 0 1 0 1 1 0 1 2D — 85 Module part number -A75B 0 1 0 0 0 0 0 1 41 A -B75B 0 1 0 0 0 0 1 0 42 B -10B 0 0 1 1 0 0 0 1 31 1 0 0 1 1 0 1 1 1 37 7 0 0 1 1 0 0 0 0 30 0 0 0 1 1 0 1 0 1 35 5 0 1 0 0 0 0 1 0 42 B 0 1 0 0 0 0 1 0 42 B 0 0 1 0 0 0 0 0 20 (Space) EO Byte No. 86 Module part number -A75B/B75B 87 Module part number -A75B/B75B 88 Module part number -A75B/B75B -10B -10B L -10B Module part number 0 0 1 0 0 0 0 0 20 (Space) 91 Revision code 0 0 1 1 0 0 0 0 30 Initial 92 Revision code 0 0 1 0 0 0 0 0 20 (Space) 93 Manufacturing date × × × × × × × × ×× 94 Manufacturing date × × × × × × × × ×× Year code (BCD) Week code (BCD) Pr 89 to 90 95 to 98 Module serial number 99 to 127 Manufacturer specific data * 3 *4 t uc od Notes: 1. All serial PD data are not protected. 0: Serial data, “driven Low”, 1: Serial data, “driven High” These SPD are based on JEDEC Committee Ballot JC-42.5-99-129. 2. Byte72 is manufacturing location code. (ex: In case of Japan, byte72 is 4AH. 4AH shows “J” on ASCII code.) 3. Bytes 95 through 98 are assembly serial number. 4. All bits of 99 through 127 are not defined (“1” or “0”). 5. These specifications are defined based on component specification, not module. Preliminary Data Sheet E0190H10 (Ver. 1.0) 7 HB54A1288KM Block Diagram /S0 RS DQS0 RS /S LDQS DQS4 LDM DM0 8 DM4 I/O0 to I/O7 RS D0 DQS5 UDM DM1 DM5 EO DQS6 RS LDM DM6 I/O0 to I/O7 RS RS DQ48 to DQ55 UDQS DQS3 I/O0 to I/O7 RS D1 DQS7 D3 UDQS RS RS UDM DM3 DM7 UDM RS 8 DQ24 to DQ31 RS DQ56 to DQ63 I/O8 to I/O15 I/O8 to I/O15 * D0 to D3 : HM5425161 L U0 : 2-kbit EEPROM BA0 to BA1 SDRAMs (D0 to D3) A0 to AN SDRAMs (D0 to D3) /RAS SDRAMs (D0 to D3) /CAS SDRAMs (D0 to D3) /WE SDRAMs (D0 to D3) Rs : 22 W Serial PD SCL SCL SA0 A0 SA1 A1 SA2 A2 Pr SDRAMs (D0 to D3) SDA SDA U0 WP N.C. SPD SDRAMs (D0 to D3) SDRAMs (D0 to D3) VCC and VCCQ SDRAMs (D0 to D3), SPD VCCID CK0 /CK0 2 loads CK1 /CK1 2 loads CK2 10 pF /CK2 od VSS LDM 8 RS DQ16 to DQ23 VCC /S LDQS RS DM2 VREF I/O8 to I/O15 RS /S LDQS RS DQ40 to DQ47 I/O8 to I/O15 RS VCCSPD UDM 8 DQS2 CKE1 D2 UDQS RS DQ8 to DQ15 CKE0 I/O0 to I/O7 RS RS RS 8 RS DQ32 to DQ39 UDQS DQS1 8 LDM 8 RS DQ0 to DQ7 8 /S LDQS RS RS Notes : Open 1. DQ wiring may differ from that described in this drawing; however DQ/DM/DQS relationships are maintained as shown. VCCID strap connections: (for memory device VCC, VCCQ) Strap out (open): VCC = VCCQ Strap in (closed): VCC ≠ VCCQ 2. The SDA pull-up registor is reguired due to t uc the open-drain/open-collector output. 3. The SCL pull-up registor is recommended, because of the normal SCL lime inactive "high" state. Preliminary Data Sheet E0190H10 (Ver. 1.0) 8 HB54A1288KM Differential Clock Net Wiring (CK, /CK) 2DRAM loads DRAM1 Capacitance 120Ω DIMM connector DRAM2 Capacitance L EO t uc od Pr Preliminary Data Sheet E0190H10 (Ver. 1.0) 9 HB54A1288KM Pin Functions (1) CK (CLK), /CK (/CLK) (input pin): The CK and the /CK are the master clock inputs. All inputs except DMs, DQSs and DQs are referred to the cross point of the CK rising edge and the VREF level. When a read operation, DQSs and DQs are referred to the cross point of the CK and the /CK. When a write operation, DMs and DQs are referred to the cross point of the DQS and the VREF level. DQSs for write operation are referred to the cross point of the CK and the /CK. /S (/CS) (input pin): When /S is Low, commands and data can be input. When /S is High, all inputs are ignored. However, internal operations (bank active, burst operations, etc.) are held. /RAS, /CAS, and /WE (input pins): These pins define operating commands (read, write, etc.) depending on the combinations of their voltage levels. See "Command operation". EO A0 to A12 (input pins): Row address (AX0 to AX12) is determined by the A0 to the A12 level at the cross point of the CK rising edge and the VREF level in a bank active command cycle. Column address (AY0 to AY8) is loaded via the A0 to the A8, the A11 at the cross point of the CK rising edge and the VREF level in a read or a write command cycle. This column address becomes the starting address of a burst operation. L A10 (AP) (input pin): A10 defines the precharge mode when a precharge command, a read command or a write command is issued. If A10 = High when a precharge command is issued, all banks are precharged. If A10 = Low when a precharge command is issued, only the bank that is selected by BA1, BA0 is precharged. If A10 = High when read or write command, auto-precharge function is enabled. While A10 = Low, auto-precharge function is disabled. BA0, BA1 (input pin): BA0/BA1 are bank select signals. The memory array is divided into bank 0, bank 1, bank 2 and bank 3. If BA1 = Low and BA0 = Low, bank 0 is selected. If BA1 = High and BA0 = Low, bank 1 is selected. If BA1 = Low and BA0 = High, bank 2 is selected. If BA1 = High and BA0 = High, bank 3 is selected. od Pin Functions (2) Pr CKE (input pin): CKE controls power down and self-refresh. The power down and the self-refresh commands are entered when the CKE is driven Low and exited when it resumes to High. The CKE level must be kept for 1 CK cycle (= LCKEPW) at least, that is, if CKE changes at the cross point of the CK rising edge and the VREF level with proper setup time tIS, at the next CK rising edge CKE level must be kept with proper hold time tIH. DM (input pins): DM is the reference signals of the data input mask function. DMs are sampled at the cross point of DQS and VREF. DQ, CB (input and output pins): Data are input to and output from these pins. DQS (input and output pin): DQS provide the read data strobes (as output) and the write data strobes (as input). t uc VCC and VCCQ (power supply pins): 2.5V is applied. (VCC is for the internal circuit and VCCQ is for the output buffer.) VCCSPD (power supply pin): 2.5V is applied (For serial EEPROM). VSS (power supply pin): Ground is connected. Detailed Operation Part, AC Characteristics and Timing Waveforms Refer to the HM5425161B/HM5425801B/HM5425401B Series datasheet (E0086H10). DM pins of component device fixed to VSS level on the module board. DIMM /CAS latency = Device CL + 1 for registered type. Preliminary Data Sheet E0190H10 (Ver. 1.0) 10 HB54A1288KM Electrical Specifications Absolute Maximum Ratings Parameter Symbol Value Unit Note Voltage on any pin relative to VSS VT –1.0 to +4.6 V 1 Supply voltage relative to VSS VCC, VCCQ –1.0 to +4.6 V 1 Short circuit output current IOUT 50 mA Power dissipation PT 4 W Operating temperature Topr 0 to +65 °C Storage temperature Tstg –50 to +100 °C Notes: 1. Respect to VSS. EO Caution Exposing the device to stress above those listed in Absolute Maximum Ratings could cause permanent damage. The device is not meant to be operated under conditions outside the limits described in the operational section of this specification Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. DC Operating Conditions (TA = 0 to +65°C) Symbol min. Typ max. Unit Notes Supply voltage VCC 2.3 2.5 2.7 V 1, 2 VSS 0 0 0 V L Parameter Input reference voltage VREF 1.15 1.25 1.35 V 1 Termination voltage VTT VREF – 0.04 VREF VREF + 0.04 V 1 DC Input high voltage VIH VREF + 0.18 — VCCQ + 0.3 V 1, 3 DC Input signal voltage DC differential input voltage –0.3 — VREF – 0.18 V 1, 4 –0.3 — VCCQ + 0.3 V 5 VSWING (dc) 0.36 — VCCQ + 0.6 V 6 All parameters are referred to VSS, when measured. VCCQ must be lower than or equal to VCC. VIH is allowed to exceed VCC up to 4.6V for the period shorter than or equal to 5ns. VIL is allowed to outreach below VSS down to –1.0V for the period shorter than or equal to 5ns. VIN (dc) specifies the allowable dc execution of each differential input. VSWING (dc) specifies the input differential voltage required for switching. t uc od Notes: 1. 2. 3. 4. 5. 6. VIL VIN (dc) Pr DC Input low voltage Preliminary Data Sheet E0190H10 (Ver. 1.0) 11 HB54A1288KM DC Characteristics (TA = 0 to 65°C, VCC, VCCQ = 2.5V ± 0.2V, VSS = 0V) Parameter Symbol Operating current (ACTV-PRE) ICC0 Operating current (ACTV-READICC1 PRE) Idle power down standby current ICC2P Idle standby current ICC2N EO ICC3P Active standby current ICC3N Operating current (Burst read operation) ICC4R Operating current (Burst write operation) ICC4W Auto refresh current ICC5 Self refresh current ICC6 L Active power down standby current max. 400 380 320 620 580 520 72 60 48 160 140 120 100 80 60 200 180 160 1020 980 940 960 920 880 820 800 720 12 12 12 Unit Test condition mA CKE ≥ VIH, tRC = min. 1, 2, 5 mA CKE ≥ VIH, BL = 2, CL = 2.5, tRC = min. 1, 2, 5 mA CKE ≤ VIL 4 mA CKE ≥ VIH, /CS ≥ VIH 4 mA CKE ≤ VIL 3 mA CKE ≥ VIH, /CS ≥ VIH tRAS = max. 3 mA CKE ≥ VIH, BL = 2, CL = 2.5 1, 2, 5, 6 mA CKE ≥ VIH, BL = 2, CL = 2.5 1, 2, 5, 6 mA tRFC = min., Input ≤ VIL or ≥ VIH mA Input ≥ VCC – 0.2V Input ≤ 0.2V. Pr Notes These ICC data are measured under condition that DQ pins are not connected. One bank operation. One bank active. All banks idle. Command/Address transition once per one cycle. Data/Data mask transition twice per one cycle. The ICC data on this table are measured with regard to tCK = min. in general. od Notes. 1. 2. 3. 4. 5. 6. 7. Grade -A75B -B75B -10B -A75B -B75B -10B -A75B -B75B -10B -A75B -B75B -10B -A75B -B75B -10B -A75B -B75B -10B -A75B -B75B -10B -A75B -B75B -10B -A75B -B75B -10B -A75B -B75B -10B DC Characteristics2 (TA = 0 to 65°C, VCC, VCCQ = 2.5V ± 0.2V, VSS = 0V) Parameter Symbol min. Input leakage current ILI –10 Output leakage current ILO –10 max. Unit Test condition 10 µA VCC ≥ VIN ≥ VSS 10 µA VCC ≥ VOUT ≥ VSS VOH VTT + 0.76 — V Output low voltage VOL — VTT – 0.76 V Preliminary Data Sheet E0190H10 (Ver. 1.0) 12 t uc Output high voltage Notes IOH (max.) = –15.2mA IOL (min.) = 15.2mA HB54A1288KM Pin Capacitance (TA = 25°C, VCC, VCCQ = 2.5V ± 0.2V) Parameter Symbol Pins max. Unit Notes Input capacitance CI1 Address, /RAS, /CAS, /WE 48 pF 1, 3 Input capacitance CI2 CK, /CK, /S, CKE 40 pF 1, 3 Data and DQS input/output capacitance CO DQ, DQS, CB 22 pF 1, 2, 3 Notes: 1. These parameters are measured on conditions: f = 100MHz, VOUT = VCCQ/2, ∆VOUT = 0.2V. 2. Dout circuits are disabled. 3. This parameter is sampled and not 100% tested. Timing Parameter Measured in Clock Cycle for Registered DIMM Number of clock cycle EO Symbol min. Write to pre-charge command delay (same bank) tWPD 3 + BL/2 Read to pre-charge command delay (same bank) tRPD BL/2 Write to read command delay (to input all data) tWRD 2 + BL/2 Burst stop command to write command delay (CL = 2) tBSTW 2 (CL = 2.5) tBSTW 3 Burst stop command to DQ High-Z (CL = 2) tBSTZ 2 (CL = 2.5) tBSTZ 2.5 Read command to write command delay (to output all data) (CL = 2) tRWD 2 + BL/2 (CL = 2.5) tRWD 3 + BL/2 Pre-charge command to High-Z (CL = 2) tHZP 2 tHZP 2.5 tWCD 1 L Parameter Write command to data in latency Write recovery DM to data in latency Pr (CL = 2.5) Register set command to active or register set command Self refresh exit to read command Power down entry Power down exit to command input CKE minimum pulse width 2 0 tMRD 2 od Self refresh exit to non-read command tWR tDMD max. tSNR 10 tSRD 200 tPDEN 1 tPDEX 1 tCKEPW 1 t uc Preliminary Data Sheet E0190H10 (Ver. 1.0) 13 HB54A1288KM Physical Outline 67.60 Unit: mm 63.60 11.55 18.45 3.80 (DATUM -A-) 4x Full R 47.40 2.45 1.00 ± 0.10 4.20 1.50 11.40 2.15 47.40 R0.50 ± 0.20 L R0.50 ± 0.20 B 4.20 2 2.45 A 11.40 200 2.15 4.00 199 1 6.00 EO 20.0 31.75 Component area (Front) 2x φ 1.80 Pr (DATUM -A-) Detail A 4.00 ± 0.10 Component area (Back) 2.00 Min. Detail B 2.55 4.00 ± 0.10 od FULL R 0.25 Max (DATUM -A-) 0.60 t uc 0.45 ± 0.03 1.80 1.00 ± 0.10 Preliminary Data Sheet E0190H10 (Ver. 1.0) 14 HB54A1288KM CAUTION FOR HANDLING MEMORY MODULES When handling or inserting memory modules, be sure not to touch any components on the modules, such as the memory IC, chip capacitors and chip resistors. It is necessary to avoid undue mechanical stress on these components to prevent damaging them. When re-packing memory modules, be sure the modules are NOT touching each other. Modules in contact with other modules may cause excessive mechanical stress, which may damage the modules. MDE0107 NOTES FOR CMOS DEVICES EO 1 PRECAUTION AGAINST ESD FOR MOS DEVICES 2 L Exposing the MOS devices to a strong electric field can cause destruction of the gate oxide and ultimately degrade the MOS devices operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it, when once it has occurred. Environmental control must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using insulators that easily build static electricity. MOS devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work bench and floor should be grounded. The operator should be grounded using wrist strap. MOS devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with semiconductor MOS devices on it. HANDLING OF UNUSED INPUT PINS FOR CMOS DEVICES STATUS BEFORE INITIALIZATION OF MOS DEVICES od 3 Pr No connection for CMOS devices input pins can be a cause of malfunction. If no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected to VDD or GND with a resistor, if it is considered to have a possibility of being an output pin. The unused pins must be handled in accordance with the related specifications. Power-on does not necessarily define initial status of MOS devices. Production process of MOS does not define the initial operation status of the device. Immediately after the power source is turned ON, the MOS devices with reset function have not yet been initialized. Hence, power-on does not guarantee output pin levels, I/O settings or contents of registers. MOS devices are not initialized until the reset signal is received. Reset operation must be executed immediately after power-on for MOS devices having reset function. t uc CME0107 Preliminary Data Sheet E0190H10 (Ver. 1.0) 15 HB54A1288KM The information in this document is subject to change without notice. Before using this document, confirm that this is the latest version. No part of this document may be copied or reproduced in any form or by any means without the prior written consent of Elpida Memory, Inc. Elpida Memory, Inc. does not assume any liability for infringement of any intellectual property rights (including but not limited to patents, copyrights, and circuit layout licenses) of Elpida Memory, Inc. or third parties by or arising from the use of the products or information listed in this document. No license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of Elpida Memory, Inc. or others. Descriptions of circuits, software and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. The incorporation of these circuits, software and information in the design of the customer's equipment shall be done under the full responsibility of the customer. Elpida Memory, Inc. assumes no responsibility for any losses incurred by customers or third parties arising from the use of these circuits, software and information. EO [Product applications] Elpida Memory, Inc. makes every attempt to ensure that its products are of high quality and reliability. However, users are instructed to contact Elpida Memory's sales office before using the product in aerospace, aeronautics, nuclear power, combustion control, transportation, traffic, safety equipment, medical equipment for life support, or other such application in which especially high quality and reliability is demanded or where its failure or malfunction may directly threaten human life or cause risk of bodily injury. L [Product usage] Design your application so that the product is used within the ranges and conditions guaranteed by Elpida Memory, Inc., including the maximum ratings, operating supply voltage range, heat radiation characteristics, installation conditions and other related characteristics. Elpida Memory, Inc. bears no responsibility for failure or damage when the product is used beyond the guaranteed ranges and conditions. Even within the guaranteed ranges and conditions, consider normally foreseeable failure rates or failure modes in semiconductor devices and employ systemic measures such as fail-safes, so that the equipment incorporating Elpida Memory, Inc. products does not cause bodily injury, fire or other consequential damage due to the operation of the Elpida Memory, Inc. product. [Usage environment] This product is not designed to be resistant to electromagnetic waves or radiation. This product must be used in a non-condensing environment. M01E0107 t uc od Pr If you export the products or technology described in this document that are controlled by the Foreign Exchange and Foreign Trade Law of Japan, you must follow the necessary procedures in accordance with the relevant laws and regulations of Japan. Also, if you export products/technology controlled by U.S. export control regulations, or another country's export control laws or regulations, you must follow the necessary procedures in accordance with such laws or regulations. If these products/technology are sold, leased, or transferred to a third party, or a third party is granted license to use these products, that third party must be made aware that they are responsible for compliance with the relevant laws and regulations. Preliminary Data Sheet E0190H10 (Ver. 1.0) 16