Data Sheet A m p l i fy t h e H u m a n E x p e r i e n c e Comlinear CLC1603, CLC3603, CLC3613 ® Single and Triple, 1.1mA, 200MHz Amplifiers Applications n RGB video line drivers n Portable Video n Line drivers n Set top box n Active filters n Cable drivers n Imaging applications n Radar/communication receivers General Description The COMLINEAR CLC1603 (single with disable), CLC3603 (triple with disable), and CLC3613 (triple) are high-performance, current feedback amplifiers that provide 240MHz unity gain bandwidth, ±0.1dB gain flatness to 30MHz, and 450V/μs slew rate while consuming only 1.1mA of supply current. This high performance exceeds the requirements of NTSC/PAL/HDTV video applications. These COMLINEAR high-performance amplifiers also provide ample output current to drive multiple video loads. The COMLINEAR CLC1603, CLC3603, and CLC3613 are designed to operate from ±5V or +5V supplies. The CLC1603 and CLC3603 offer a enable/disable feature to save power. While disabled, the outputs are in a high-impedance state to allow for multiplexing applications. The combination of high-speed, low-power, and excellent video performance make these amplifiers well suited for use in many general purpose, high-speed applications including set top boxes, high-definition video, active filters, and cable driving applications. Typical Application - Driving Dual Video Loads Ordering Information Package Disable Option Pb-Free RoHS Compliant Operating Temperature Range Packaging Method CLC1603IST6X SOT23-6 Yes Yes Yes -40°C to +85°C Reel CLC3613ISO14X SOIC-14 No Yes Yes -40°C to +85°C Reel CLC3613ISO14 SOIC-14 No Yes Yes -40°C to +85°C Rail CLC3603ISO16X SOIC-16 Yes Yes Yes -40°C to +85°C Reel CLC3603ISO16 SOIC-16 Yes Yes Yes -40°C to +85°C Rail Rev 1A Part Number Moisture sensitivity level for all parts is MSL-1. ©2007-2008 CADEKA Microcircuits LLC Comlinear CLC1603, CLC3603, CLC3613 Single and Triple, 1.1mA, 200MHz Amplifiers features n 0.1dB gain flatness to 30MHz n 0.01%/0.03˚ differential gain/phase n 200MHz -3dB bandwidth at G = 2 n 140MHz large signal bandwidth n 450V/μs slew rate n 1.1mA supply current (enabled) n 0.35mA supply current (disabled) n 100mA output current n Fully specified at 5V and ±5V supplies n CLC1603: Pb-free SOT23-6 n CLC3603: Pb-free SOIC-16 n CLC3613: Pb-free SOIC-14 www.cadeka.com Data Sheet CLC1603 Pin Assignments CLC1603 Pin Configuration 1 -V S 2 +IN 3 + - 6 +VS 5 DIS -IN 4 CLC3603 Pin Configuration Pin Name Description 1 OUT Output 2 -VS Negative supply 3 +IN Positive input 4 -IN Negative input 5 DIS Disable. Enabled if pin is left floating or pulled above VON, disabled if pin is grounded or pulled below VOFF. 6 +VS Positive supply CLC3603 Pin Assignments Pin No. Pin Name 1 -IN1 Description Negative input, channel 1 2 +IN1 Positive input, channel 1 -IN1 1 16 DIS1 +IN1 2 15 OUT1 3 -VS Negative supply 4 -IN2 Negative input, channel 2 5 +IN2 Positive input, channel 2 -VS 3 14 +VS -IN2 4 13 DIS2 6 -VS +IN2 5 12 OUT2 7 +IN3 Positive input, channel 3 8 -IN3 Negative input, channel 3 9 DIS3 Disable pin for channel 3. Enabled if pin is left floating or pulled above VON, disabled if pin is grounded or pulled below VOFF. 10 OUT3 Output, channel 3 -VS 6 11 +VS +IN3 7 10 OUT3 -IN3 8 9 DIS3 Comlinear CLC1603, CLC3603, CLC3613 Single and Triple, 1.1mA, 200MHz Amplifiers OUT Pin No. Negative supply 11 +VS 12 OUT2 Positive supply Output, channel 2 13 DIS2 Disable pin for channel 2. Enabled if pin is left floating or pulled above VON, disabled if pin is grounded or pulled below VOFF. 14 +VS Positive supply 15 OUT1 Output, channel 1 16 DIS1 Disable pin for channel 2. Enabled if pin is left floating or pulled above VON, disabled if pin is grounded or pulled below VOFF. Disable Pin Truth Table Pin High* ( > (+Vs - 1.5V)) Low ( < (+Vs - 3.5V)) DIS Enabled Disabled Rev 1A *Default Open State ©2007-2008 CADEKA Microcircuits LLC www.cadeka.com 2 Data Sheet CLC3613 Pin Configuration CLC3613 Pin Assignments Pin No. Pin Name Description 1 NC No Connect 2 NC No Connect 1 14 OUT2 NC 2 13 -IN2 3 NC No Connect NC 3 12 +IN2 4 +VS Positive supply +VS 4 11 -VS 5 +IN1 Positive input, channel 1 6 -IN1 Negative input, channel 1 +IN1 5 10 +IN3 7 OUT1 Output, channel 1 -IN1 6 9 -IN3 8 OUT3 Output, channel 3 7 8 OUT3 9 -IN3 Negative input, channel 3 10 +IN3 Positive input, channel 3 11 -VS 12 +IN2 Positive input, channel 2 13 -IN2 Negative input, channel 2 14 OUT2 Output, channel 2 OUT1 Comlinear CLC1603, CLC3603, CLC3613 Single and Triple, 1.1mA, 200MHz Amplifiers NC Negative supply Rev 1A ©2007-2008 CADEKA Microcircuits LLC www.cadeka.com 3 Data Sheet Absolute Maximum Ratings The safety of the device is not guaranteed when it is operated above the “Absolute Maximum Ratings”. The device should not be operated at these “absolute” limits. Adhere to the “Recommended Operating Conditions” for proper device function. The information contained in the Electrical Characteristics tables and Typical Performance plots reflect the operating conditions noted on the tables and plots. Supply Voltage Input Voltage Range Continuous Output Current Min Max Unit 0 -Vs -0.5V 14 +Vs +0.5V 100 V V mA Comlinear CLC1603, CLC3603, CLC3613 Single and Triple, 1.1mA, 200MHz Amplifiers Parameter Reliability Information Parameter Junction Temperature Storage Temperature Range Lead Temperature (Soldering, 10s) Package Thermal Resistance 6-Lead SOT23 14-Lead SOIC 16-Lead SOIC Min Typ -65 Max Unit 150 150 300 °C °C °C 177 88 68 °C/W °C/W °C/W Notes: Package thermal resistance (qJA), JDEC standard, multi-layer test boards, still air. ESD Protection Product SOT23-6 SOIC-14 SOIC-16 2kV 1kV 2kV 1kV 2kV 1kV Parameter Min Typ Max Unit Operating Temperature Range Supply Voltage Range -40 4.5 +85 12 °C V Human Body Model (HBM) Charged Device Model (CDM) Recommended Operating Conditions Rev 1A ©2007-2008 CADEKA Microcircuits LLC www.cadeka.com 4 Data Sheet Electrical Characteristics at +5V TA = 25°C, +Vs = 5V, -VS = GND, Rf = Rg =1.2kΩ, RL = 100Ω to +VS/2, G = 2; unless otherwise noted. Symbol Parameter Conditions Min Typ Max Units Frequency Domain Response Unity Gain Bandwidth G = +1, VOUT = 0.5Vpp, Rf = 2.5kΩ 210 MHz -3dB Bandwidth G = +2, VOUT = 0.5Vpp 180 MHz BWLS Large Signal Bandwidth G = +2, VOUT = 1Vpp 160 MHz BW0.1dBSS 0.1dB Gain Flatness G = +2, VOUT = 0.5Vpp 15 MHz Time Domain Response tR, tF tS Rise and Fall Time VOUT = 1V step; (10% to 90%) 3 ns Settling Time to 0.1% VOUT = 1V step 18 ns Settling Time to 0.01% VOUT = 1V step 40 ns OS Overshoot VOUT = 0.2V step 1 % SR Slew Rate 1V step 350 V/µs Distortion/Noise Response HD2 2nd Harmonic Distortion VOUT = 1Vpp, 5MHz -60 dBc HD3 3rd Harmonic Distortion VOUT = 1Vpp, 5MHz -51 dBc THD Total Harmonic Distortion VOUT = 1Vpp, 5MHz 50 dB DG Differential Gain NTSC (3.58MHz), AC-coupled, RL = 150Ω 0.01 % DP Differential Phase NTSC (3.58MHz), AC-coupled, RL = 150Ω 0.04 ° IP3 Third Order Intercept VOUT = 1Vpp, 10MHz 26 dBm SFDR Spurious Free Dynamic Range VOUT = 1Vpp, 5MHz 58 dBc en Input Voltage Noise > 1MHz 4 nV/√Hz in Input Current Noise > 1MHz, Inverting 15 pA/√Hz > 1MHz, Non-Inverting 15 pA/√Hz Channel-to-channel 5MHz 56 dB XTALK Crosstalk DC Performance VIO Input Offset Voltage 0.5 mV dVIO Average Drift 6 µV/°C Ibn dIbn Ibi dIbi Input Bias Current - Non-Inverting Average Drift Input Bias Current - Inverting Average Drift 2 µA 40 nA/°C 0.4 µA 10 nA/°C PSRR Power Supply Rejection Ratio DC 60 dB IS Supply Current per channel 0.9 mA Disable Characteristics - CLC1603, CLC3603 TON Turn On Time 100 ns TOFF Turn Off Time 2.25 μs VOFF Power Down Input Voltage DIS pin, disabled if pin is grounded or pulled below VOFF = +Vs - 3.5V Disabled if < (+Vs - 3.5V) V VON Enable Input Voltage DIS pin, enabled if pin is left open or pulled above VON = +Vs - 1.5V Enabled if > (+Vs - 1.5V) V ISD Disable Supply Current DIS pin is grounded 0.15 mA 4 MΩ Input Characteristics Input Resistance CIN Input Capacitance CMIR Common Mode Input Range CMRR Common Mode Rejection Ratio ©2007-2008 CADEKA Microcircuits LLC Non-inverting Inverting DC 350 Ω 1.0 pF 1.5 to 3.5 V 55 dB www.cadeka.com Rev 1A RIN Comlinear CLC1603, CLC3603, CLC3613 Single and Triple, 1.1mA, 200MHz Amplifiers UGBW BWSS 5 Data Sheet Electrical Characteristics at +5V continued TA = 25°C, +Vs = 5V, -VS = GND, Rf = Rg =1.2kΩ, RL = 100Ω to +VS/2, G = 2; unless otherwise noted. Symbol Parameter Conditions Min Typ Max Units Output Characteristics Output Resistance Closed Loop, DC 0.02 Ω VOUT Output Voltage Swing RL = 100Ω 1.4 to 3.6 V IOUT Output Current ±140 mA Comlinear CLC1603, CLC3603, CLC3613 Single and Triple, 1.1mA, 200MHz Amplifiers RO Rev 1A ©2007-2008 CADEKA Microcircuits LLC www.cadeka.com 6 Data Sheet Electrical Characteristics at ±5V TA = 25°C, +Vs = 5V, -VS = -5V, Rf = Rg =1.2kΩ, RL = 100Ω to GND, G = 2; unless otherwise noted. Symbol Parameter Conditions Min Typ Max Units Frequency Domain Response G = +1, VOUT = 0.5Vpp, Rf = 2.5kΩ 240 MHz G = +2, VOUT = 0.5Vpp 200 MHz BWLS Large Signal Bandwidth G = +2, VOUT = 2Vpp 120 MHz BW0.1dBSS 0.1dB Gain Flatness G = +2, VOUT = 0.5Vpp 30 MHz TON Turn On Time 250 ns TOFF Turn Off Time 2.25 μs VOFF Power Down Input Voltage DIS pin, disabled if pin is grounded or pulled below VOFF = +Vs - 3.5V Disabled if < (+Vs - 3.5V) V VON Enable Input Voltage DIS pin, enabled if pin is left open or pulled above VON = +Vs - 1.5V Enabled if > (+Vs - 1.5V) V ISD Disable Supply Current (1) DIS pin is grounded, CLC1603 0.11 0.5 mA DIS pin is grounded, CLC3603 0.3 0.5 mA MΩ Rev 1A Unity Gain Bandwidth -3dB Bandwidth Comlinear CLC1603, CLC3603, CLC3613 Single and Triple, 1.1mA, 200MHz Amplifiers UGBW BWSS Time Domain Response tR, tF tS Rise and Fall Time VOUT = 2V step; (10% to 90%) 4 ns Settling Time to 0.1% VOUT = 2V step 18 ns Settling Time to 0.01% VOUT = 2V step 35 ns OS Overshoot VOUT = 0.2V step 1 % SR Slew Rate 2V step 450 V/µs Distortion/Noise Response HD2 2nd Harmonic Distortion VOUT = 2Vpp, 5MHz -67 dBc HD3 3rd Harmonic Distortion VOUT = 2Vpp, 5MHz -57 dBc THD Total Harmonic Distortion VOUT = 2Vpp, 5MHz, RL = 150Ω 55 dB DG Differential Gain NTSC (3.58MHz), AC-coupled, RL = 150Ω 0.01 % DP Differential Phase NTSC (3.58MHz), AC-coupled, RL = 150Ω 0.03 ° IP3 Third Order Intercept VOUT = 0.5Vpp, 10MHz 35 dBm SFDR Spurious Free Dynamic Range VOUT = 1Vpp, 5MHz 58 dBc en Input Voltage Noise > 1MHz 4 nV/√Hz in Input Current Noise > 1MHz, Inverting 15 pA/√Hz > 1MHz, Non-Inverting 15 pA/√Hz Channel-to-channel 5MHz 56 dB XTALK Crosstalk DC Performance VIO dVIO Ibn dIbn Ibi dIbi PSRR IS Input Offset Voltage (1) -4 Average Drift -5 Average Drift 2 -5 Average Drift 2 µV/°C 50 µA nA/°C 5 10 DC mV 5 40 Input Bias Current - Inverting (1) Supply Current (1) 4 6 Input Bias Current - Non-Inverting (1) Power Supply Rejection Ratio (1) 0.7 µA nA/°C 75 dB CLC1603 1.1 2.5 mA CLC3603, CLC3613 3.3 6.5 mA Disable Characteristics - CLC1603, CLC3603 Input Characteristics RIN Input Resistance CIN Input Capacitance CMIR Common Mode Input Range ©2007-2008 CADEKA Microcircuits LLC Non-inverting Inverting 4 350 Ω 1.0 pF ±4.0 V www.cadeka.com 7 Data Sheet Electrical Characteristics at ±5V continued TA = 25°C, +Vs = 5V, -VS = -5V, Rf = Rg =1.2kΩ, RL = 100Ω to GND, G = 2; unless otherwise noted. Symbol CMRR Parameter Common Mode Rejection Ratio Conditions (1) DC Min Typ 50 60 -3.0 ±3.5 Max Units dB RO Output Resistance Closed Loop, DC VOUT Output Voltage Swing RL = 100Ω (1) IOUT Output Current 0.1 Comlinear CLC1603, CLC3603, CLC3613 Single and Triple, 1.1mA, 200MHz Amplifiers Output Characteristics Ω +3.0 ±270 V mA Notes: 1. 100% tested at 25°C Rev 1A ©2007-2008 CADEKA Microcircuits LLC www.cadeka.com 8 Data Sheet Typical Performance Characteristics TA = 25°C, +Vs = 5V, -VS = -5V, Rf = Rg =1.2kΩ, RL = 100Ω to GND, G = 2; unless otherwise noted. Inverting Frequency Response 1 1 0 0 -1 -1 Normalized Gain (dB) G=1 Rf = 2.5kΩ -2 G=2 -3 -4 G=5 -5 G = -2 -2 G = -10 -3 -4 G = -5 -5 G = 10 -6 G = -1 -6 VOUT = 0.5Vpp -7 VOUT = 0.5Vpp -7 0.1 1 10 100 1000 0.1 1 Frequency (MHz) 10 1000 Frequency Response vs. CL 100 1000 100 1000 Frequency Response vs. RL 1 2 0 1 CL = 1000pF Rs = 5Ω -1 Normalized Gain (dB) Normalized Gain (dB) RL = 5kΩ CL = 500pF Rs = 5Ω -2 -3 CL = 100pF Rs = 15Ω -4 CL = 50pF Rs = 15Ω -5 -6 -1 -2 RL = 150Ω -3 RL = 50Ω -4 -5 CL = 20pF Rs = 20Ω VOUT = 0.5Vpp RL = 1kΩ 0 -7 VOUT = 0.5Vpp RL = 25Ω -6 0.1 1 10 100 1000 0.1 1 Frequency (MHz) Frequency Response vs. VOUT Frequency Response vs. Temperature 1 2 0 1 0 -1 Normalized Gain (dB) Normalized Gain (dB) 10 Frequency (MHz) VOUT = 4Vpp -2 -3 VOUT = 2Vpp -4 -5 + 25degC -1 - 40degC -2 + 85degC -3 -4 -5 VOUT = 1Vpp -6 VOUT = 0.2Vpp -6 -7 -7 0.1 1 10 Frequency (MHz) ©2007-2008 CADEKA Microcircuits LLC 100 1000 0.1 1 10 Frequency (MHz) www.cadeka.com 9 Rev 1A 100 Frequency (MHz) Comlinear CLC1603, CLC3603, CLC3613 Single and Triple, 1.1mA, 200MHz Amplifiers Normalized Gain (dB) Non-Inverting Frequency Response Data Sheet Typical Performance Characteristics TA = 25°C, +Vs = 5V, -VS = -5V, Rf = Rg =1.2kΩ, RL = 100Ω to GND, G = 2; unless otherwise noted. Inverting Frequency Response at +Vs = 5V, -VS = GND 1 1 0 0 -1 -1 Normalized Gain (dB) G=1 Rf = 2.5kΩ -2 G=2 -3 -4 G=5 -5 G = -2 -2 G = -10 -3 -4 G = -5 -5 G = 10 -6 G = -1 -6 VOUT = 0.5Vpp -7 VOUT = 0.5Vpp -7 0.1 1 10 100 1000 0.1 1 Frequency (MHz) 10 100 1000 Frequency (MHz) Frequency Response vs. CL at +Vs = 5V, -VS = GND Frequency Response vs. RL at +Vs = 5V, -VS = GND 1 2 0 1 CL = 1000pF Rs = 5Ω -1 Normalized Gain (dB) Normalized Gain (dB) RL = 5kΩ CL = 500pF Rs = 5Ω -2 -3 CL = 100pF Rs = 15Ω -4 CL = 50pF Rs = 15Ω -5 -6 VOUT = 0.5Vpp RL = 1kΩ 0 -1 -2 RL = 150Ω -3 RL = 50Ω -4 -5 CL = 20pF Rs = 20Ω -7 VOUT = 0.5Vpp RL = 25Ω -6 0.1 1 10 100 1000 0.1 1 Frequency (MHz) Frequency Response vs. VOUT at +Vs = 5V, -VS = GND 100 1000 Frequency Response vs. Temp. at +Vs = 5V, -VS = GND 1 2 0 1 0 -1 Normalized Gain (dB) Normalized Gain (dB) 10 Frequency (MHz) VOUT = 3Vpp -2 -3 VOUT = 2Vpp -4 -5 + 25degC -1 - 40degC -2 + 85degC -3 -4 -5 VOUT = 1Vpp -6 VOUT = 0.2Vpp -6 -7 0.1 1 10 Frequency (MHz) ©2007-2008 CADEKA Microcircuits LLC 100 1000 0.1 1 10 100 1000 Frequency (MHz) www.cadeka.com 10 Rev 1A -7 Comlinear CLC1603, CLC3603, CLC3613 Single and Triple, 1.1mA, 200MHz Amplifiers Normalized Gain (dB) Non-Inverting Frequency Response at +Vs = 5V, -VS=GND Data Sheet Typical Performance Characteristics - Continued TA = 25°C, +Vs = 5V, -VS = -5V, Rf = Rg =1.2kΩ, RL = 100Ω to GND, G = 2; unless otherwise noted. Gain Flatness at +Vs = 5V, -VS = GND 0.1 0 0 -0.1 Rf = 1.1kΩ -0.2 Rf = 1.2kΩ Normalized Gain (dB) 0.1 -0.3 -0.4 -0.1 Rf = 1.1kΩ -0.2 Rf = 1.2kΩ -0.3 -0.4 VOUT = 2Vpp RL = 150Ω -0.5 VOUT = 2Vpp RL = 150Ω -0.5 0.1 1 10 100 1000 0.1 1 Frequency (MHz) CMRR vs. Frequency PSRR vs. Frequency -20 -25 100 1000 0 VS = ±5.0V -10 -30 -20 -35 PSRR (dB) CMRR (dB) 10 Frequency (MHz) -40 -45 -50 -30 -40 -50 -55 -60 -60 -65 10k 100k 1M 10M -70 0.01 100M 0.1 1 10 100 Frequency (MHz) Frequency (Hz) Closed Loop Output Impedance vs Frequency Input Voltage Noise 100 7 Input Voltage Noise (nV/√Hz) Output Resistance (Ω) VS = ±5.0V 10 1 0.1 5 4 3 2 0.1 1 Frequency (MHz) ©2007-2008 CADEKA Microcircuits LLC 10 100 0.0001 0.001 0.01 0.1 1001 Frequency (MHz) www.cadeka.com 11 Rev 1A 0.01 0.01 6 Comlinear CLC1603, CLC3603, CLC3613 Single and Triple, 1.1mA, 200MHz Amplifiers Normalized Gain (dB) Gain Flatness Data Sheet Typical Performance Characteristics - Continued TA = 25°C, +Vs = 5V, -VS = -5V, Rf = Rg =1.2kΩ, RL = 100Ω to GND, G = 2; unless otherwise noted. 2nd Harmonic Distortion vs. RL -40 -45 -45 -50 -50 RL = 100Ω RL = 100Ω Distortion (dBc) -55 -60 -65 -70 -75 RL = 1kΩ -80 -60 -65 -70 RL = 1kΩ -75 -80 -85 -85 VOUT = 2Vpp -90 VOUT = 2Vpp -90 -95 -95 0 5 10 15 20 0 5 Frequency (MHz) 2nd Harmonic Distortion vs. VOUT 15 20 3rd Harmonic Distortion vs. VOUT -45 -45 -50 -55 -55 -60 -60 -65 5MHz -70 -75 -80 10MHz -50 10MHz Distortion (dBc) Distortion (dBc) 10 Frequency (MHz) 5MHz -65 -70 1MHz -75 -80 1MHz -85 -85 RL = 100Ω -90 0.5 0.75 RL = 100Ω -90 1 1.25 1.5 1.75 2 2.25 2.5 Output Amplitude (Vpp) 0.5 0.75 1 1.25 1.5 1.75 2 2.25 2.5 Output Amplitude (Vpp) Crosstalk vs. Frequency -30 -35 -40 -45 Crosstalk (dB) -50 -55 -60 -65 -70 -75 -80 -85 VOUT = 2Vpp -90 0.1 1 10 Rev 1A -95 100 Frequency (MHz) ©2007-2008 CADEKA Microcircuits LLC Comlinear CLC1603, CLC3603, CLC3613 Single and Triple, 1.1mA, 200MHz Amplifiers -40 -55 Distortion (dBc) 3rd Harmonic Distortion vs. RL www.cadeka.com 12 Data Sheet Typical Performance Characteristics - Continued TA = 25°C, +Vs = 5V, -VS = -5V, Rf = Rg =1.2kΩ, RL = 100Ω to GND, G = 2; unless otherwise noted. Small Signal Pulse Response Large Signal Pulse Response 2.5 0.1 2 0.075 1.5 1 Voltage (V) 0.05 Voltage (V) VOUT = 4Vpp 0.025 0 -0.025 0 -0.5 -0.05 -1 -0.075 -1.5 -0.1 -2 -0.125 VOUT = 2Vpp 0.5 -2.5 0 10 20 30 40 50 60 70 80 90 100 0 10 20 30 40 Time (ns) 50 60 70 80 90 100 Time (ns) Small Signal Pulse Response at +Vs = 5V, -VS = GND Large Signal Pulse Response at +Vs = 5V, -VS = GND 2.625 4 2.6 3.5 2.575 VOUT = 2Vpp 3 2.525 Voltage (V) Voltage (V) 2.55 2.5 2.475 VOUT = 1Vpp 2.5 2 2.45 2.425 1.5 2.4 2.375 1 0 10 20 30 40 50 60 70 80 90 100 0 10 20 30 Time (ns) 0.03 Diff Gain (%) / Diff Phase (°) Diff Gain (%) / Diff Phase (°) 0.3 0.25 0.02 0.01 DG -0.01 DP RL = 150Ω AC coupled into 220 F -0.03 60 70 80 90 100 Differential Gain & Phase DC Coupled Output 0.04 -0.02 50 Time (ns) Differential Gain & Phase AC Coupled Output 0 40 DP 0.2 0.15 0.1 DG 0.05 0 -0.05 RL = 150Ω DC coupled -0.1 -0.7 -0.5 -0.3 -0.1 0.1 Input Voltage (V) ©2007-2008 CADEKA Microcircuits LLC 0.3 0.5 0.7 -0.7 -0.5 -0.3 -0.1 0.1 0.3 0.5 0.7 Input Voltage (V) www.cadeka.com 13 Rev 1A -0.15 -0.04 Comlinear CLC1603, CLC3603, CLC3613 Single and Triple, 1.1mA, 200MHz Amplifiers 0.125 Data Sheet General Information - Current Feedback Technology Advantages of CFB Technology CFB also alleviates the traditional trade-off between closed loop gain and usable bandwidth that is seen with a VFB amplifier. With CFB, the bandwidth is primarily determined by the value of the feedback resistor, Rf. By using optimum feedback resistor values, the bandwidth of a CFB amplifier remains nearly constant with different gain configurations. When designing with CFB amplifiers always abide by these basic rules: • Use the recommended feedback resistor value • Do not use reactive (capacitors, diodes, inductors, etc.) elements in the direct feedback path • Avoid stray or parasitic capacitance across feedback resistors • Follow general high-speed amplifier layout guidelines • Ensure proper precautions have been made for driving capacitive loads VIN Ierr x1 Zo*Ierr VOUT Rf RL Rg VOUT = 1+ Rf Rg + 1+ 1 Rf Eq. 1 Zo(jω) Figure 1. Non-Inverting Gain Configuration with First Order Transfer Function ©2007-2008 CADEKA Microcircuits LLC VIN Rg VOUT VIN VOUT Rf = − Rf Rg + 1+ 1 Rf RL Eq. 2 Zo(jω) Figure 2. Inverting Gain Configuration with First Order Transfer Function CFB Technology - Theory of Operation Figure 1 shows a simple representation of a current feedback amplifier that is configured in the traditional noninverting gain configuration. Instead of having two high-impedance inputs similar to a VFB amplifier, the inputs of a CFB amplifier are connected across a unity gain buffer. This buffer has a high impedance input and a low impedance output. It can source or sink current (Ierr) as needed to force the non-inverting input to track the value of Vin. The CFB architecture employs a high gain trans-impedance stage that senses Ierr and drives the output to a value of (Zo(jω) * Ierr) volts. With the application of negative feedback, the amplifier will drive the output to a voltage in a manner which tries to drive Ierr to zero. In practice, primarily due to limitations on the value of Zo(jω), Ierr remains a small but finite value. A closer look at the closed loop transfer function (Eq.1) shows the effect of the trans-impedance, Zo(jω) on the gain of the circuit. At low frequencies where Zo(jω) is very large with respect to Rf, the second term of the equation approaches unity, allowing Rf and Rg to set the gain. At higher frequencies, the value of Zo(jω) will roll off, and the effect of the secondary term will begin to dominate. The -3dB small signal parameter specifies the frequency where the value Zo(jω) equals the value of Rf causing the gain to drop by 0.707 of the value at DC. For more information regarding current feedback amplifiers, visit www.cadeka.com for detailed application notes, such as AN-3: The Ins and Outs of Current Feedback Amplifiers. www.cadeka.com 14 Rev 1A VIN Ierr Zo*Ierr Comlinear CLC1603, CLC3603, CLC3613 Single and Triple, 1.1mA, 200MHz Amplifiers The CLCx603 Family of amplifiers utilize current feedback (CFB) technology to achieve superior performance. The primary advantage of CFB technology is higher slew rate performance when compared to voltage feedback (VFB) architecture. High slew rate contributes directly to better large signal pulse response, full power bandwidth, and distortion. x1 Data Sheet Application Information Basic Operation +Vs Input Feedback Resistor Selection 6.8μF 0.1μF + Output - RL 0.1μF Rg Rf 6.8μF G = 1 + (Rf/Rg) -Vs Figure 3. Typical Non-Inverting Gain Circuit +Vs R1 Input 0.1μF + Rg 6.8μF RL 0.1μF Rf 6.8μF G = - (Rf/Rg) -Vs For optimum input offset voltage set R1 = Rf || Rg Figure 4. Typical Inverting Gain Circuit Input 6.8μF 0.1μF + Output - 6.8μF RL Rf G=1 Rf is required for CFB amplifiers Figure 5. Typical Unity Gain (G=1) Circuit ©2007-2008 CADEKA Microcircuits LLC Gain (V/V Rf (Ω) Rg (Ω) ±0.1dB BW (MHz) -3dB BW (MHz) 1 2.5k -- 42 240 2 1.2k 1.2k 30 200 5 1.2k 300 8 70 Table 1: Recommended Rf vs. Gain In general, lowering the value of Rf from the recommended value will extend the bandwidth at the expense of additional high frequency gain peaking. This will cause increased overshoot and ringing in the pulse response characteristics. Reducing Rf too much will eventually cause oscillatory behavior. Increasing the value of Rf will lower the bandwidth. Lowering the bandwidth creates a flatter frequency response and improves 0.1dB bandwidth performance. This is important in applications such as video. Further increase in Rf will cause premature gain rolloff and adversely affect gain flatness. www.cadeka.com 15 Rev 1A 0.1μF -Vs Table 1, provides recommended Rf and associated Rg values for various gain settings. These values produce the optimum frequency response, maximum bandwidth with minimum peaking. Adjust these values to optimize performance for a specific application. The typical performance characteristics section includes plots that illustrate how the bandwidth is directly affected by the value of Rf at various gain settings. Output - +Vs One of the key design considerations when using a CFB amplifier is the selection of the feedback resistor, Rf. Rf is used in conjunction with Rg to set the gain in the traditional non-inverting and inverting circuit configurations. Refer to figures 3 and 4. As discussed in the Current Feedback Technology section, the value of the feedback resistor has a pronounced effect on the frequency response of the circuit. Comlinear CLC1603, CLC3603, CLC3613 Single and Triple, 1.1mA, 200MHz Amplifiers Figures 3, 4, and 5 illustrate typical circuit configurations for non-inverting, inverting, and unity gain topologies for dual supply applications. They show the recommended bypass capacitor values and overall closed loop gain equations. CFB amplifiers can be used in unity gain configurations. Do not use the traditional voltage follower circuit, where the output is tied directly to the inverting input. With a CFB amplifier, a feedback resistor of appropriate value must be used to prevent unstable behavior. Refer to figure 5 and Table 1. Although this seems cumbersome, it does allow a degree of freedom to adjust the passband characteristics. Data Sheet Driving Capacitive Loads Input + Rs - Output CL Rf RL Rg Overdrive Recovery An overdrive condition is defined as the point when either one of the inputs or the output exceed their specified voltage range. Overdrive recovery is the time needed for the amplifier to return to its normal or linear operating point. The recovery time varies, based on whether the input or output is overdriven and by how much the range is exceeded. The CLCx603 Family will typically recover in less than 30ns from an overdrive condition. Figure 7 shows the CLC1603 in an overdriven condition. Figure 6. Addition of RS for Driving Capacitive Loads CL (pF) 10 RS (Ω) 40 -3dB BW (MHz) 350 50 20 200 100 15 140 0.75 4 3 0.50 Input Voltage (V) 5 VIN = 1.5Vpp G=5 Input 2 0.25 1 Output 0.00 0 -1 -0.25 -2 -0.50 Output Voltage (V) Table 2 provides the recommended RS for various capacitive loads. The recommended RS values result in <=0.5dB peaking in the frequency response. The Frequency Response vs. CL plot, on pages 9 and 10, illustrate the response of the CLCx603 Family. 1.00 -3 -0.75 -4 -1.00 -5 0 20 40 60 80 100 120 140 160 180 200 Time (ns) Figure 7. Overdrive Recovery Table 1: Recommended RS vs. CL For a given load capacitance, adjust RS to optimize the tradeoff between settling time and bandwidth. In general, reducing RS will increase bandwidth at the expense of additional overshoot and ringing. Parasitic Capacitance on the Inverting Input Physical connections between components create unintentional or parasitic resistive, capacitive, and inductive elements. In general, avoid adding any additional parasitic capacitance at this node. In addition, stray capacitance across the Rf resistor can induce peaking and high frequency ©2007-2008 CADEKA Microcircuits LLC Power dissipation should not be a factor when operating under the stated 100 ohm load condition. However, applications with low impedance, DC coupled loads should be analyzed to ensure that maximum allowed junction temperature is not exceeded. Guidelines listed below can be used to verify that the particular application will not cause the device to operate beyond it’s intended operating range. Maximum power levels are set by the absolute maximum junction rating of 150°C. To calculate the junction temperature, the package thermal resistance value ThetaJA (ӨJA) is used along with the total die power dissipation. Rev 1A Parasitic capacitance at the inverting input can be especially troublesome with high frequency amplifiers. A parasitic capacitance on this node will be in parallel with the gain setting resistor Rg. At high frequencies, its impedance can begin to raise the system gain by making Rg appear smaller. Power Dissipation Comlinear CLC1603, CLC3603, CLC3613 Single and Triple, 1.1mA, 200MHz Amplifiers Increased phase delay at the output due to capacitive loading can cause ringing, peaking in the frequency response, and possible unstable behavior. Use a series resistance, RS, between the amplifier and the load to help improve stability and settling performance. Refer to Figure 6. ringing. Refer to the Layout Considerations section for additional information regarding high speed layout techniques. TJunction = TAmbient + (ӨJA × PD) Where TAmbient is the temperature of the working environment. www.cadeka.com 16 Data Sheet PD = Psupply - Pload Psupply = Vsupply × IRMS supply Vsupply = VS+ - VSPower delivered to a purely resistive load is: Pload = ((VLOAD)RMS2)/Rloadeff The effective load resistor (Rloadeff) will need to include the effect of the feedback network. For instance, SOIC-16 2 1.5 SOIC-14 1 0.5 SOT23-6 0 -40 -20 0 20 40 60 80 Ambient Temperature (°C) Figure 8. Maximum Power Derating Rloadeff in figure 3 would be calculated as: RL || (Rf + Rg) These measurements are basic and are relatively easy to perform with standard lab equipment. For design purposes however, prior knowledge of actual signal levels and load impedance is needed to determine the dissipated power. Here, PD can be found from PD = PQuiescent + PDynamic - PLoad Quiescent power can be derived from the specified IS values along with known supply voltage, VSupply. Load power can be calculated as above with the desired signal amplitudes using: (VLOAD)RMS = VPEAK / √2 ( ILOAD)RMS = ( VLOAD)RMS / Rloadeff The dynamic power is focused primarily within the output stage driving the load. This value can be calculated as: PDYNAMIC = (VS+ - VLOAD)RMS × ( ILOAD)RMS Better thermal ratings can be achieved by maximizing PC board metallization at the package pins. However, be careful of stray capacitance on the input pins. In addition, increased airflow across the package can also help to reduce the effective ӨJA of the package. In the event the outputs are momentarily shorted to a low impedance path, internal circuitry and output metallization are set to limit and handle up to 65mA of output current. However, extended duration under these conditions may not guarantee that the maximum junction temperature (+150°C) is not exceeded. Layout Considerations General layout and supply bypassing play major roles in high frequency performance. CADEKA has evaluation boards to use as a guide for high frequency layout and as aid in device testing and characterization. Follow the steps below as a basis for high frequency layout: Assuming the load is referenced in the middle of the power rails or Vsupply/2. • Include 6.8µF and 0.1µF ceramic capacitors for power supply decoupling Figure 8 shows the maximum safe power dissipation in the package vs. the ambient temperature for the 8 and 14 lead SOIC packages. • Place the 6.8µF capacitor within 0.75 inches of the power pin • Place the 0.1µF capacitor within 0.1 inches of the power pin • Minimize all trace lengths to reduce series inductances Refer to the evaluation board layouts below for more information. ©2007-2008 CADEKA Microcircuits LLC www.cadeka.com 17 Rev 1A • Remove the ground plane under and around the part, especially near the input and output pins to reduce parasitic capacitance Comlinear CLC1603, CLC3603, CLC3613 Single and Triple, 1.1mA, 200MHz Amplifiers Supply power is calculated by the standard power equation. 2.5 Maximum Power Dissipation (W) In order to determine PD, the power dissipated in the load needs to be subtracted from the total power delivered by the supplies. Data Sheet Evaluation Board Information The following evaluation boards are available to aid in the testing and layout of these devices: Products Comlinear CLC1603, CLC3603, CLC3613 Single and Triple, 1.1mA, 200MHz Amplifiers Evaluation Board # CEB002 CEB018 CEB013 CLC1603 CLC3613 CLC3603 Evaluation Board Schematics Evaluation board schematics and layouts are shown in Figures 9-14. These evaluation boards are built for dual- supply operation. Follow these steps to use the board in a single-supply application: Figure 10. CEB002 Top View 1. Short -Vs to ground. 2. Use C3 and C4, if the -VS pin of the amplifier is not directly connected to the ground plane. Figure 11. CEB002 Bottom View Figure 9. CEB002 Schematic Rev 1A ©2007-2008 CADEKA Microcircuits LLC www.cadeka.com 18 Data Sheet Comlinear CLC1603, CLC3603, CLC3613 Single and Triple, 1.1mA, 200MHz Amplifiers Figure 14. CEB018 Bottom View Figure 12. CEB018 Schematic Figure 16. CEB013 Schematic Figure 13. CEB018 Top View Rev 1A ©2007-2008 CADEKA Microcircuits LLC www.cadeka.com 19 Data Sheet Comlinear CLC1603, CLC3603, CLC3613 Single and Triple, 1.1mA, 200MHz Amplifiers Figure 17. CEB013 Top View Figure 18. CEB013 Bottom View Rev 1A ©2007-2008 CADEKA Microcircuits LLC www.cadeka.com 20 Data Sheet Mechanical Dimensions SOT23-6 Package Comlinear CLC1603, CLC3603, CLC3613 Single and Triple, 1.1mA, 200MHz Amplifiers SOIC-14 Rev 1A ©2007-2008 CADEKA Microcircuits LLC www.cadeka.com 21 Data Sheet Mechanical Dimensions SOIC-16 Package Comlinear CLC1603, CLC3603, CLC3613 Single and Triple, 1.1mA, 200MHz Amplifiers Rev 1A For additional information regarding our products, please visit CADEKA at: cadeka.com CADEKA Headquarters Loveland, Colorado T: 970.663.5452 T: 877.663.5452 (toll free) CADEKA, the CADEKA logo design, COMLINEAR, the COMLINEAR logo design, and ARCTIC are trademarks or registered trademarks of CADEKA Microcircuits LLC. All other brand and product names may be trademarks of their respective companies. CADEKA reserves the right to make changes to any products and services herein at any time without notice. CADEKA does not assume any responsibility or liability arising out of the application or use of any product or service described herein, except as expressly agreed to in writing by CADEKA; nor does the purchase, lease, or use of a product or service from CADEKA convey a license under any patent rights, copyrights, trademark rights, or any other of the intellectual property rights of CADEKA or of third parties. Copyright ©2007-2008 by CADEKA Microcircuits LLC. All rights reserved. A m p l i fy t h e H u m a n E x p e r i e n c e