Revised October 1999 MM74C192 • MM74C193 Synchronous 4-Bit Up/Down Decade Counter • Synchronous 4-Bit Up/Down Binary Counter General Description Features The MM74C192 and MM74C193 up/down counters are monolithic complementary MOS (CMOS) integrated circuits. The MM74C192 is a BCD counter, while the MM74C193 is a binary counter. ■ High noise margin: Counting up and counting down is performed by two count inputs, one being held high while the other is clocked. The outputs change on the positive-going transition of this clock. 1V guaranteed ■ Tenth power TTL compatible: Drive 2 LPTTL loads ■ Wide supply range: 3V to 15V ■ Carry and borrow outputs for N-bit cascading ■ Asynchronous clear ■ High noise immunity: 0.45 VCC (typ.) These counters feature preset inputs that are set when load is a logical “0” and a clear which forces all outputs to “0” when it is at a logical “1”. The counters also have carry and borrow outputs so that they can be cascaded using no external circuitry. Ordering Code: Order Number Package Number Package Description MM74C192N N16E 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide MM74C193M M16A 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150” Narrow MM74C193N N16E 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code. Connection Diagram Top View © 1999 Fairchild Semiconductor Corporation DS005901 www.fairchildsemi.com MM74C192 • MM74C193 Synchronous 4-Bit Up/Down Decade Counter • Synchronous 4-Bit Up/Down Binary Counter January 1991 MM74C192 • MM74C193 Absolute Maximum Ratings(Note 1) −0.3V to VCC + 0.3V Voltage at Any Pin Operating Temperature Range (TA) Storage Temperature Range (TS) −40°C to +85°C −65°C to +150°C Maximum VCC Voltage 18V Power Dissipation (PD) Dual-In-Line 700 mW Small Outline 500 mW Operating VCC Range Note 1: “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. Except for “Operating Temperature Range” they are not meant to imply that the devices should be operated at these limits. The Electrical Characteristics table provides conditions for actual device operation. 3V to 15V Lead Temperature (TA) (Soldering, 10 seconds) 260°C DC Electrical Characteristics Min/Max limits apply across temperature range unless otherwise noted Symbol Parameter Conditions Min Typ Max Units CMOS TO CMOS VIN(1) VIN(0) VOUT(1) VOUT(0) Logical “1” Input Voltage Logical “0” Input Voltage Logical “1” Output Voltage Logical “0” Output Voltage VCC = 5V 3.5 V VCC = 10V 8.0 V VCC = 5V 1.5 V VCC = 10V 2.0 V VCC = 5V, IO = −10 µA 4.5 VCC = 10V, IO = −10 µA 9.0 V V VCC = 5V, IO = 10 µA 0.5 V VCC = 10V, IO = 10 µA 1.0 V 1.0 µA 300 µA 0.8 V IIN(1) Logical “1” Input Current VCC = 15V, VIN = 15V IIN(0) Logical “0” Input Current VCC = 15V, VIN = 0V ICC Supply Current VCC = 15V 0.005 −1.0 −0.005 0.05 µA CMOS TO LPTTL INTERFACE VIN(1) Logical “1” Input Voltage VCC = 4.75V VIN(0) Logical “0” Input Voltage VCC = 4.75V VCC − 1.5 VOUT(1) Logical “1” Output Voltage VCC = 4.75V, IO = −100 µA VOUT(0) Logical “0” Output Voltage VCC = 4.75V, IO = 360 µA V 2.4 V 0.4 V OUTPUT DRIVE (See Family Characteristics Data Sheet) (Short Circuit Current) ISOURCE Output Source Current VCC = 5V, VIN(0) = 0V −1.75 mA −8 mA 1.75 mA 8 mA TA = 25°C, VOUT = 0V ISOURCE Output Source Current VCC = 10V, VIN(0) = 0V TA = 25°C, VOUT = 0V ISINK Output Sink Current VCC = 5V, VIN(1) = 5V TA = 25°C, VOUT = VCC ISINK Output Sink Current VCC = 10V, VIN(1) = 10V TA = 25°C, VOUT = VCC www.fairchildsemi.com 2 (Note 2) Symbol tpd tpd tpd tS tW tW Typ Max Units Propagation Delay Parameter VCC = 5V 250 400 ns Time to Q from Count Up or Down VCC = 10V 100 160 ns Propagation Delay VCC = 5V 120 200 ns Time to Q Borrow from Count Down VCC = 10V 50 80 ns Propagation Delay VCC = 5V 120 200 ns Time to Carry from Count Up VCC = 10V 50 80 ns Time Prior to Load VCC = 5V 100 160 ns that Data Must be Present VCC = 10V 30 50 ns Minimum Clear Pulse Width VCC = 5V 300 480 ns VCC = 10V 120 190 ns VCC = 5V 100 160 ns VCC = 10V 40 65 ns Minimum Load Pulse Width Conditions Min tpd0 Propagation Delay VCC = 5V 300 480 ns tpd1 Time to Q from Load VCC = 10V 120 190 ns tW Minimum Count Pulse Width VCC = 5V 120 200 ns VCC = 10V 35 80 fMAX Maximum Count Frequency VCC = 5V 2.5 4 VCC = 10V 6 10 tr Count Rise and Fall Time VCC = 5V 15 VCC = 10V 5 tf ns MHz MHz µs µs CIN Input Capacitance (Note 3) 5 pF CPD Power Dissipation Capacitance (Note 4) 100 pF Note 2: AC Parameters are guaranteed by DC correlated testing. Note 3: Capacitance is guaranteed by periodic testing. Note 4: CPD determines the no load AC power consumption of any CMOS device. For complete explanation, see Application Note AN-90. Cascading Packages Guaranteed Noise Margin as a Function of VCC 3 www.fairchildsemi.com MM74C192 • MM74C193 AC Electrical Characteristics TA = 25°C, CL = 50 pF, unless otherwise noted MM74C192 • MM74C193 Timing Diagrams MM74C192 Note A: Clear outputs to zero. Note B: Load (preset) to binary thirteen. Note C: Count up to fourteen, fifteen, carry, zero, one and two. Note D: Count down to one, zero, borrow, fifteen, fourteen, and thirteen. MM74C193 Note A: Clear outputs to zero. Note B: Load (preset) to BCD seven. Note C: Count up to eight, nine, carry, zero, one, and two. Note D: Count down to one, zero, borrow, nine, eight, and seven. Note E: Clear overrides load, data, and count inputs. Note F: When counting up, count down input must be HIGH; when counting down, count-up input must be HIGH. www.fairchildsemi.com 4 MM74C192 • MM74C193 Physical Dimensions inches (millimeters) unless otherwise noted 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150” Narrow Package Number M16A 5 www.fairchildsemi.com MM74C192 • MM74C193 Synchronous 4-Bit Up/Down Decade Counter • Synchronous 4-Bit Up/Down Binary Counter Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide Package Number N16E Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. www.fairchildsemi.com www.fairchildsemi.com 6