MC100LVEL12 3.3VECL Low Impedance Driver Description The MC100LVEL12 is a low impedance drive buffer. With two pairs of OR/NOR outputs the device is ideally suited for high drive applications such as memory addressing. The device is functionally equivalent to the EL12 device and operates from a 3.3 V power supply. With propagation delays equivalent to the EL12, the LVEL12 is ideally suited for those applications which require the ultimate in AC performance in a low voltage environment. http://onsemi.com MARKING DIAGRAMS* 8 1 Features • 445 ps Propagation Delay • Dual Outputs for 25 Drive Applications • ESD Protection: >4 kV Human Body Model, SOIC−8 D SUFFIX CASE 751 > 200 V Machine Model • • • • • • • 1 1 with VEE = 0 V NECL Mode Operating Range: VCC= 0 V with VEE = −3.0 V to −3.8 V Internal Input Pulldown Resistors Q Output will Default LOW with All Inputs Open or at VEE Meets or Exceeds JEDEC Spec EIA/JESD78 IC Latchup Test Moisture Sensitivity Level 1 For Additional Information, see Application Note AND8003/D Flammability Rating: UL−94 V−0 @ 0.125 in, Oxygen Index: 28 to 34 Transistor Count = 83 devices Pb−Free Packages are Available TSSOP−8 DT SUFFIX CASE 948R 1 KV12 ALYWG G 4A M G G • KVL12 ALYW G 8 8 • The 100 Series Contains Temperature Compensation • PECL Mode Operating Range:VCC = 3.0 V to 3.8 V 8 1 4 DFN8 MN SUFFIX CASE 506AA A = Assembly Location L = Wafer Lot Y = Year W = Work Week M = Date Code G = Pb−Free Package (Note: Microdot may be in either location) *For additional marking information, refer to Application Note AND8002/D. ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 4 of this data sheet. © Semiconductor Components Industries, LLC, 2006 December, 2006 − Rev. 3 1 Publication Order Number: MC100LVEL12/D MC100LVEL12 Table 1. PIN DESCRIPTION Qa 1 8 VCC PIN FUNCTION D0, D1 Qa, Qa; Qb, Qb VCC VEE ECL Data Inputs ECL Data Outputs Positive Supply Negative Supply EP Exposed pad must be connected to a sufficient thermal conduit. Electrically connect to the most negative supply or leave floating open. Qb 2 7 D0 Qa 3 6 D1 Qb 4 5 VEE Figure 1. Logic Diagram and Pinout Assignment Table 2. MAXIMUM RATINGS Symbol Parameter Condition 1 Condition 2 Rating Units VCC PECL Mode Power Supply VEE = 0 V 8 to 0 V VEE NECL Mode Power Supply VCC = 0 V −8 to 0 V VI PECL Mode Input Voltage NECL Mode Input Voltage VEE = 0 V VCC = 0 V 6 to 0 −6 to 0 V V Iout Output Current Continuous Surge 50 100 mA mA TA Operating Temperature Range −40 to +85 °C Tstg Storage Temperature Range −65 to +150 °C qJA Thermal Resistance (Junction−to−Ambient) 0 lfpm 500 lfpm 8 SOIC 8 SOIC 190 130 °C/W °C/W qJC Thermal Resistance (Junction−to−Case) Standard Board 8 SOIC 41 to 44 ± 5% °C/W qJA Thermal Resistance (Junction−to−Ambient) 0 lfpm 500 lfpm 8 TSSOP 8 TSSOP 185 140 °C/W °C/W qJC Thermal Resistance (Junction−to−Case) Standard Board 8 TSSOP 41 to 44 ± 5% °C/W JA Thermal Resistance (Junction−to−Ambient) 0 lfpm 500 lfpm DFN8 DFN8 129 84 °C/W °C/W Tsol Wave Solder <2 to 3 sec @ 248°C <2 to 3 sec @ 260°C 265 265 °C Pb Pb−Free VI VCC VI VEE Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. http://onsemi.com 2 MC100LVEL12 Table 3. LVPECL DC CHARACTERISTICS VCC = 3.3 V; VEE = 0.0 V (Note 1) −40°C Symbol Characteristic Min 25°C Typ Max 17 24 Min 85°C Typ Max 17 24 Min Typ Max Unit 18 25 mA IEE Power Supply Current VOH Output HIGH Voltage (Note 2) 2215 2295 2420 2275 2345 2420 2275 2345 2420 mV VOL Output LOW Voltage (Note 2) 1470 1605 1745 1490 1595 1680 1490 1595 1680 mV VIH Input HIGH Voltage 2135 2420 2135 2420 2135 2420 mV VIL Input LOW Voltage 1490 1825 1490 1825 1490 1825 mV IIH Input HIGH Current 150 mA IIL Input LOW Current 150 0.5 150 0.5 0.5 mA NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 1. Input and output parameters vary 1:1 with VCC. VEE can vary ±0.3 V. 2. Outputs are terminated through a 50 resistor to VCC − 2.0 V. Table 4. LVNECL DC CHARACTERISTICS VCC = 0.0 V; VEE = −3.3 V (Note 3) −40°C Symbol Characteristic Min Typ 25°C Max Min Typ 85°C Max Min Typ Max Unit IEE Power Supply Current 17 24 17 24 18 25 mA VOH Output HIGH Voltage (Note 4) −1085 −1005 −880 −1025 −955 −880 −1025 −955 −880 mV VOL Output LOW Voltage (Note 4) −1830 −1695 −1555 −1810 −1705 −1620 −1810 −1705 −1620 mV VIH Input HIGH Voltage −1165 −880 −1165 −880 −1165 −880 mV VIL Input LOW Voltage −1810 −1475 −1810 −1475 −1810 −1475 mV IIH Input HIGH Current 150 mA IIL Input LOW Current 150 0.5 150 0.5 0.5 mA NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 3. Input and output parameters vary 1:1 with VCC. VEE can vary ±0.3 V. 4. Outputs are terminated through a 50 resistor to VCC − 2.0 V. Table 5. AC CHARACTERISTICS VCC = 3.3 V; VEE = 0.0 V or VCC = 0.0 V; VEE = −3.3 V (Note 5) −40°C Symbol Characteristic fmax Maximum Toggle Frequency tPLH tPHL Propagation Delay to Output tJITTER Cycle−to−Cycle Jitter tr tf Output Rise/Fall Times Q (20% − 80%) Min Typ 25°C Max Min TBD 310 580 400 Max Min TBD 310 TBD 230 Typ 85°C 445 580 320 TBD 550 230 400 Typ Max TBD 590 TBD 550 230 400 Unit GHz ps ps 550 ps NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 5. VEE can vary ±0.3 V. http://onsemi.com 3 MC100LVEL12 Zo = 50 Q D Receiver Device Driver Device Q D Zo = 50 50 50 VTT VTT = VCC − 3.0 V Figure 2. Typical Termination for Output Driver and Device Evaluation (See Application Note AND8020/D − Termination of ECL Logic Devices.) ORDERING INFORMATION Package Shipping† SOIC−8 98 Units / Rail MC100LVEL12DG SOIC−8 (Pb−Free) 98 Units / Rail MC100LVEL12DR2 SOIC−8 2500 / Tape & Reel MC100LVEL12DR2G SOIC−8 (Pb−Free) 2500 / Tape & Reel MC100LVEL12DT TSSOP−8 100 Units / Rail MC100LVEL12DTG TSSOP−8 (Pb−Free) 100 Units / Rail MC100LVEL12DTR2 TSSOP−8 2500 / Tape & Reel MC100LVEL12DTR2G TSSOP−8 (Pb−Free) 2500 / Tape & Reel MC100LVEL12MNR4 DFN8 1000 / Tape & Reel DFN8 (Pb−Free) 1000 / Tape & Reel Device MC100LVEL12D MC100LVEL12MNR4G †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. Resource Reference of Application Notes AN1405/D − ECL Clock Distribution Techniques AN1406/D − Designing with PECL (ECL at +5.0 V) AN1503/D − ECLinPSt I/O SPiCE Modeling Kit AN1504/D − Metastability and the ECLinPS Family AN1568/D − Interfacing Between LVDS and ECL AN1672/D − The ECL Translator Guide AND8001/D − Odd Number Counters Design AND8002/D − Marking and Date Codes AND8020/D − Termination of ECL Logic Devices AND8066/D − Interfacing with ECLinPS AND8090/D − AC Characteristics of ECL Devices http://onsemi.com 4 MC100LVEL12 PACKAGE DIMENSIONS SOIC−8 NB CASE 751−07 ISSUE AH −X− NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. 751−01 THRU 751−06 ARE OBSOLETE. NEW STANDARD IS 751−07. A 8 5 S B 1 0.25 (0.010) M Y M 4 −Y− K G C N DIM A B C D G H J K M N S X 45 _ SEATING PLANE −Z− H 0.10 (0.004) D 0.25 (0.010) M Z Y S X M J S SOLDERING FOOTPRINT* 1.52 0.060 7.0 0.275 4.0 0.155 0.6 0.024 1.270 0.050 SCALE 6:1 mm Ǔ ǒinches *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. http://onsemi.com 5 MILLIMETERS MIN MAX 4.80 5.00 3.80 4.00 1.35 1.75 0.33 0.51 1.27 BSC 0.10 0.25 0.19 0.25 0.40 1.27 0_ 8_ 0.25 0.50 5.80 6.20 INCHES MIN MAX 0.189 0.197 0.150 0.157 0.053 0.069 0.013 0.020 0.050 BSC 0.004 0.010 0.007 0.010 0.016 0.050 0 _ 8 _ 0.010 0.020 0.228 0.244 MC100LVEL12 PACKAGE DIMENSIONS TSSOP−8 DT SUFFIX PLASTIC TSSOP PACKAGE CASE 948R−02 ISSUE A 8x 0.15 (0.006) T U 0.10 (0.004) S 2X L/2 L 8 5 1 PIN 1 IDENT 0.15 (0.006) T U K REF S M T U V S 0.25 (0.010) B −U− 4 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A DOES NOT INCLUDE MOLD FLASH. PROTRUSIONS OR GATE BURRS. MOLD FLASH OR GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25 (0.010) PER SIDE. 5. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 6. DIMENSION A AND B ARE TO BE DETERMINED AT DATUM PLANE −W−. S M A −V− F DETAIL E C 0.10 (0.004) −T− SEATING PLANE D −W− G DETAIL E http://onsemi.com 6 DIM A B C D F G K L M MILLIMETERS MIN MAX 2.90 3.10 2.90 3.10 0.80 1.10 0.05 0.15 0.40 0.70 0.65 BSC 0.25 0.40 4.90 BSC 0_ 6_ INCHES MIN MAX 0.114 0.122 0.114 0.122 0.031 0.043 0.002 0.006 0.016 0.028 0.026 BSC 0.010 0.016 0.193 BSC 0_ 6_ MC100LVEL12 PACKAGE DIMENSIONS DFN8 CASE 506AA−01 ISSUE D D NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994 . 2. CONTROLLING DIMENSION: MILLIMETERS. 3. DIMENSION b APPLIES TO PLATED TERMINAL AND IS MEASURED BETWEEN 0.25 AND 0.30 MM FROM TERMINAL. 4. COPLANARITY APPLIES TO THE EXPOSED PAD AS WELL AS THE TERMINALS. A B PIN ONE REFERENCE 2X 0.10 C 2X ÇÇÇÇ ÇÇÇÇ ÇÇÇÇ ÇÇÇÇ 0.10 C TOP VIEW 0.08 C SEATING PLANE MILLIMETERS MIN MAX 0.80 1.00 0.00 0.05 0.20 REF 0.20 0.30 2.00 BSC 1.10 1.30 2.00 BSC 0.70 0.90 0.50 BSC 0.20 −−− 0.25 0.35 A 0.10 C 8X DIM A A1 A3 b D D2 E E2 e K L E (A3) SIDE VIEW A1 C D2 e e/2 4 1 8X L E2 K 8 5 8X b 0.10 C A B 0.05 C NOTE 3 BOTTOM VIEW ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. 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