MB88155 Spread Spectrum Clock Generator MB88155 is a clock generator for EMI (Electro Magnetic Interference) reduction. The peak of unnecessary radiation noise (EMI) can be attenuated by making the oscillation frequency slightly modulate periodically with the internal modulator. For modulation, the MB88155 supports both center-spreading and down-spreading. It has a non-modulated clock output pin (REFOUT) as well as a modulated clock output pin (CKOUT) . Features ■ Input frequency : 12.5 MHz to 50 MHz (Multiplied by 1) 12.5 MHz to 20 MHz (Multiplied by 4) ■ Output frequency : CKOUT REFOUT ■ Modulation rate : ■ Equipped with oscillation circuit : range of oscillation 12.5 MHz to 40 MHz (Fundamental oscillation) 40 MHz to 48 MHz (3rd overtone) ■ Modulation clock output Duty : 40 to 60 ■ 0.5, 12.5 MHz to 80 MHz The same as input frequency (not multiplied) 1.0 (center spread) , 1.0, 2.0 (Down spread) Modulation clock cycle cycle jitter : MB88155-1xx MB88155-1xx MB88155-4xx 12.5 MHz to 20 MHz 20 MHz to 50 MHz less than 150 ps less than 100 ps less than 200 ps ■ Low current consumption by CMOS process : 5 mA (24 MHz : Typ-sample, no load) ■ Power supply voltage : 3.3 V 0.3 V ■ Operating temperature : ■ Package : 8-pin plastic TSSOP 40 °C to 85 °C Cypress Semiconductor Corporation Document Number: 002-08298 Rev. *A • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Revised December 21, 2016 MB88155 Contents Product Lineup ................................................................. 3 Pin Assignment ................................................................ 4 Pin Description ................................................................. 4 I/O Circuit Type ................................................................. 5 Handling Devices .............................................................. 7 Preventing Latch-up .................................................... 7 Handling unused pins .................................................. 7 The attention when the external clock is used ............ 7 Power supply pins ....................................................... 7 Oscillation circuit ......................................................... 7 Block Diagram .................................................................. 8 Pin Setting ......................................................................... 9 Absolute Maximum Ratings .......................................... 11 Recommended Operating Conditions .......................... 12 Electrical Characteristics ............................................... 13 Document Number: 002-08298 Rev. *A Output Clock Duty Cycle (tdcc, tdcr tb/ta) ............... 15 Input Frequency (fin 1/tin) ......................................... 15 Output Slew Rate (SRc, SRr) ........................................ 15 Cycle-Cycle Jitter (tjc |tn tn 1| ) ......................... 16 Modulation Waveform .................................................... 17 Lock-Up Time .................................................................. 18 Oscillation Circuit ........................................................... 20 Interconnection Circuit Example .................................. 21 Spectrum Example Characteristics .............................. 22 Ordering Information ...................................................... 23 Package Dimensions ...................................................... 25 Document History ........................................................... 26 Sales, Solutions, and Legal Information .......................27 Page 2 of 27 MB88155 1. Product Lineup The MB88155 is available in different models : 2 models different in multiplier (× 1 and × 4) , 2 in modulation type (center-spreading and down-spreading) , 2 in input frequency range at a multiplier of 1 (12.5 MHz to 25 MHz and 25 MHz to 50 MHz) , and 1 in input frequency range at a multiplier of 4 (12.5 MHz to 20 MHz) . The MB88155 is also available in two versions : modulation-on/off selectable version (with ENS pin) and power-down function builtin version (with XPD pin) . MB88155-M T F Input frequency range, With/without ENS/XPD Spread type Multiplication rate setting Multiplied 0 : 12.5 MHz to 25.0 MHz, With ENS, Without XPD by 1 1 : 25.0 MHz to 50.0 MHz, With ENS, Without XPD 2 : 12.5 MHz to 25.0 MHz, Without ENS, With XPD 3 : 25.0 MHz to 50.0 MHz, Without ENS, With XPD Multiplied 0 : 12.5 MHz to 20.0 MHz, With ENS, Without XPD by 4 2 : 12.5 MHz to 20.0 MHz, Without ENS, With XPD → 0 : Down spread, 1 : Center spread → 1 : Multiplied by 1, 4 : Multiplied by 4 → Line-up of MB88155 Product Input frequency MB88155-100 12.5 MHz to 25 MHz MB88155-101 25 MHz to 50 MHz MB88155-102 12.5 MHz to 25 MHz MB88155-103 25 MHz to 50 MHz MB88155-110 12.5 MHz to 25 MHz MB88155-111 25 MHz to 50 MHz MB88155-112 12.5 MHz to 25 MHz MB88155-113 25 MHz to 50 MHz MB88155-400 12.5 MHz to 20 MHz MB88155-402 MB88155-410 MB88155-412 Document Number: 002-08298 Rev. *A Multiplication rate Output frequency Modulation type Modulation enable pin Power down pin Yes No No Yes Yes No No Yes Down spread Yes No No Yes Center spread Yes No No Yes Down spread Multiplied by 1 The same as input frequency Center spread Multiplied by 4 50 MHz to 80 MHz Page 3 of 27 MB88155 2. Pin Assignment XIN 1 8 VDD MB88155 -xx0 -xx1 XOUT 2 ENS 3 SEL 4 XIN 1 7 CKOUT XOUT 2 6 VSS XPD 3 5 REFOUT SEL 4 8 VDD MB88155 -xx2 -xx3 7 CKOUT 6 VSS 5 REFOUT FPT-8P-M07 3. Pin Description Pin name I/O Pin no. XIN I 1 Connection pin of resonator/clock input pin XOUT O 2 Connection pin of resonator ENS/XPD I 3 Modulation enable pin/power down pin SEL I 4 Modulation rate setting pin Down spread, SEL “L” : Modulation rate 1.0 Down spread, SEL “H” : Modulation rate 2.0 Down spread, SEL “L” : Modulation rate 0.5 Down spread, SEL “H” : Modulation rate 1.0 REFOUT O 5 Non-modulated clock output pin This pin becomes to“L” at power-down. VSS 6 GND Pin CKOUT O 7 Modulated clock output pin This pin becomes to“L” at power-down. VDD 8 Power supply voltage pin Document Number: 002-08298 Rev. *A Description Page 4 of 27 MB88155 4. I/O Circuit Type Pin Circuit type Remarks CMOS hysteresis input SEL, XPD ENS CMOS hysteresis input with pull-up resistor of 50 k (Typ) 50 kΩ REFOUT ■ CMOS output ■ IOL 3 mA ■ “L” output at power-down (Continued) Document Number: 002-08298 Rev. *A Page 5 of 27 MB88155 (Continued) Pin Circuit type Remarks ■ CMOS output ■ IOL 4 mA ■ “L” output at power-down CKOUT Note : For XIN pin and XOUT pin, refer to “Oscillation Circuit”. Document Number: 002-08298 Rev. *A Page 6 of 27 MB88155 5. Handling Devices 5.1 Preventing Latch-up A latch-up can occur if, on this device, (a) a voltage higher than VDD or a voltage lower than VSS is applied to an input or output pin or (b) a voltage higher than the rating is applied between VDD and VSS. The latch-up, if it occurs, significantly increases the power supply current and may cause thermal destruction of an element. When you use this device, be very careful not to exceed the maximum rating. 5.2 Handling unused pins Do not leave an unused input pin open, since it may cause a malfunction. Handle by, using a pull-up or pull-down resistor. Unused output pin should be opened. 5.3 The attention when the external clock is used Input the clock to XIN pin, and XOUT pin should be opened when you use the external clock. Please pay attention so that an overshoot and an undershoot do not occur to an input clock of XIN pin. 5.4 Power supply pins Please design connecting the power supply pin of this device by as low impedance as possible from the current supply source. We recommend connecting electrolytic capacitor (about 10 F) and the ceramic capacitor (about 0.01 F) in parallel between VSS and VDD near the device, as a bypass capacitor. 5.5 Oscillation circuit Noise near the XIN and XOUT pins may cause the device to malfunction. Design printed circuit boards so that electric wiring of XIN or XOUT pin and the resonator do not intersect other wiring. Design the printed circuit board that surrounds the XIN and XOUT pins with ground. Document Number: 002-08298 Rev. *A Page 7 of 27 MB88155 6. Block Diagram VDD Modulation enable/ power down setting ENS/XPD SEL Modulation rate setting PLL block Clock output CKOUT Reference clock XOUT Reference clock output Rf = 1 MΩ XIN REFOUT Power down signal VSS 1 − M Phase compare Reference clock 1 − N Charge pump V/I conversion IDAC Loop filter 1 − L Modulation logic MB88155 PLL block ICO Modulation clock output Modulation rate setting/ Modulation enable setting A glitchless IDAC (current output D/A converter) provides precise modulation, thereby dramatically reducing EMI. Document Number: 002-08298 Rev. *A Page 8 of 27 MB88155 7. Pin Setting The modulation clock requires stabilization wait time after the PIN setting is changed. For the modulation clock stabilization wait time, assure the maximum value for “Lock-up time” in the AC Characteristics list in “ Electrical Characteristics”. ENS modulation enable setting ENS Modulation L No modulation H Modulation MB88155-xx0, xx1 Note : Spectrum does not diffuse when “L” is set to ENS pin. MB88155-xx2, xx3 do not have ENS pin. XPD power down XPD Status L Power down status H Operating status MB88155-xx2, xx3 Note : When setting “L” to XPD pin, it becomes power down mode (low power consumption mode) . Both CKOUT and REFOUT of output pins are fixed to “L” output during power down. MB88155-xx0, xx1 do not have XPD pin. SEL modulation rate setting SEL L H Frequency 0.5 MB88155-x1x 1.0 MB88155-x0x 1.0 MB88155-x1x 2.0 MB88155-x0x Note : The modulation rate can be changed at the level of the pin. Document Number: 002-08298 Rev. *A Page 9 of 27 MB88155 ■ Center spread Spectrum is spread (modulated) by centering on the non-spread frequency. Modulation width 2.0 Radiation level −1.0% +1.0% Frequency Non-spread frequency Example of center spread at modulation rate 1.0 ■ Down spread Spectrum is spread (modulated) below the non-spread frequency. Radiation level Modulation width 2.0 −2.0% Frequency Non-spread frequency Example of down spread at modulation rate 2.0 Document Number: 002-08298 Rev. *A Page 10 of 27 MB88155 8. Absolute Maximum Ratings Parameter Rating Symbol Power supply voltage* VDD Input voltage* VI Output voltage* VO Storage temperature TST Operation junction temperature TJ Output current IO Unit Min Max 0.5 VSS 0.5 VSS 0.5 55 40 4.0 VDD 0.5 VDD 0.5 125 125 14 mA VDD 1.0 (tOVER 50 ns) V V Overshoot VIOVER 14 Undershoot VIUNDER VSS 1.0 (tUNDER 50 ns) V V V °C °C * : The parameter is based on VSS 0.0 V. WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings. Overshoot/Undershoot tUNDER 50 ns VIOVER VDD 1.0 V VDD Input pin VSS tOVER 50 ns Document Number: 002-08298 Rev. *A VIUNDER VSS 1.0 V Page 11 of 27 MB88155 9. Recommended Operating Conditions (VSS 0.0 V) Parameter Symbol Pin Conditions Power supply voltage VDD VDD “H” level input voltage VIH “L” level input voltage Value Unit Min Typ Max 3.0 3.3 3.6 V XIN, SEL, ENS, XPD VDD × 0.8 VDD 0.3 V VIL XIN, SEL, ENS, XPD VSS VDD × 0.2 V Input clock duty cycle tDCI XIN 12.5 MHz to 50 MHz 40 50 60 Operating temperature Ta 40 85 °C WARNING: The recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. All of the device’s electrical characteristics are warranted when the device is operated within these ranges. Always use semiconductor devices within their recommended operating condition ranges. Operation outside these ranges may adversely affect reliability and could result in device failure. No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. Users considering application outside the listed conditions are advised to contact their Cypress representatives beforehand. Input clock duty cycle (tDCI tb/ta) ta tb XIN Document Number: 002-08298 Rev. *A 1.5 V Page 12 of 27 MB88155 10. Electrical Characteristics ■ DC Characteristics Parameter Power supply current (Ta 40 °C to 85 °C, VDD 3.3 V 0.3 V, VSS 0.0 V) Symbol ICC Pin VDD Conditions Value Unit Min Typ Max 24 MHz output No load capacitance 5.0 7.0 mA At power-down 10 A VDD 0.5 VDD V VSS 0.4 V VOHC CKOUT “H” level output IOH 4 mA VOHR REFOUT “H” level output IOH 3 mA VOLC CKOUT “L” level output IOL 4 mA VOLR REFOUT “L” level output IOL 3 mA ZOC CKOUT 12.5 MHz to 80 MHz 45 ZOR REFOUT 12.5 MHz to 50 MHz 70 Ta 25 C VDD VI 0.0 V f 1 MHz 16 pF CIN XIN, SEL, ENS/XPD Input capacitance Input pull-up resistor RPU ENS VIL 0.0 V 25 50 200 k 12.5 MHz to 50 MHz 15 pF 12.5 MHz to 50 MHz 15 50 MHz to 80 MHz 7 Output voltage Output impedance REFOUT Load capacitance CL Document Number: 002-08298 Rev. *A CKOUT Page 13 of 27 MB88155 ■ AC Characteristics Parameter Oscillation frequency (Ta 40 °C to 85 °C, VDD 3.3 V 0.3 V, VSS 0.0 V) Symbol Pin fx XIN, XOUT Conditions Fundamental oscillation 3rd overtone MB88155 1x0, 1x2 Input frequency fin XIN REFOUT Output frequency fOUT CKOUT Modulation frequency Lock-up time*2 Cycle-cycle jitter Min Typ Unit Max 12.5 40 40 48 12.5 25 25 50 MB88155 4xx 12.5 20 MB88155 1x0, 1x2 12.5 25 MB88155 1x1, 1x3 25 50 MB88155 4xx 12.5 20 MB88155 1x0, 1x2 12.5 25 MB88155 1x1, 1x3 25 50 MB88155 4xx 50 80 MHz MHz MHz SRc CKOUT Load capacitance 15 pF, 0.4 V to 2.4 V 0.4 4.0 SRR REFOUT Load capacitance 15 pF, 0.4 V to 2.4 V 0.3 2.0 tDCC CKOUT 1.5 V reference level 40 60 tDCR REFOUT 1.5 V reference level tDCI 10* tDCI 10* fMOD CKOUT 32.4 kHz tLK CKOUT 2 5 ms MB88155 1xx Input frequency 12.5 MHz to 20 MHz, No load capacitance, Ta 25 °C, VDD 3.3 V, Standard deviation 150 ps MB88155 1xx Input frequency 20 MHz to 50 MHz, No load capacitance, Ta 25 °C, VDD 3.3 V, Standard deviation 100 ps MB88155 4xx No load capacitance, Ta 25 °C, VDD 3.3 V, Standard deviation 200 ps Output slew rate Output clock duty cycle MB88155 1x1, 1x3 Value tJC CKOUT Input frequency at 24 MHz 1 V/ns 1 *1 : Duty of the REFOUT output is guaranteed only for the following A and B because it depends on tDCI of input clock duty. A. Resonator input : When resonator is connected with XIN pin and XOUT pin, and oscillates normally. B. External clock input : The input level is Full-swing (VSS VDD). *2 : The modulation clock requires stabilization wait time after the IC is turned on or released from power-down mode, or after SEL (modulation factor) or ENS (modulation enable) setting is changed. For the modulation clock stabilization wait time, assure the maximum value for the lock-up time. Document Number: 002-08298 Rev. *A Page 14 of 27 MB88155 11. Output Clock Duty Cycle (tDCC, tDCR tb/ta) ta tb 1.5 V CKOUT, REFOUT 12. Input Frequency (fin 1/tin) tin 0.8 VDD XIN 13. Output Slew Rate (SRC, SRR) 2.4 V CKOUT, REFOUT 0.4 V tr tf Note : SRC (2.4 0.4) /tr, SRC (2.4 0.4) /tf SRR (2.4 0.4) /tr, SRR (2.4 0.4) /tf Document Number: 002-08298 Rev. *A Page 15 of 27 MB88155 14. Cycle-Cycle Jitter (tJC |tn tn 1| ) CKOUT tn tn+1 Note : Cycle-cycle jitter indicates the difference between a certain cycle and the immediately succeeding (or preceding) cycle. Document Number: 002-08298 Rev. *A Page 16 of 27 MB88155 15. Modulation Waveform ■ Modulation rate 1.0, example of center spread CKOUT output frequency + 1.0 % Frequency at modulation off Time − 1.0 % fMOD (Typ) = 32.4 kHz (fin = 24 MHz) ■ Modulation rate 1.0, example of down spread CKOUT output frequency Frequency at modulation off Time − 0.5 % − 1.0 % fMOD (Typ) = 32.4 kHz (fin = 24 MHz) Document Number: 002-08298 Rev. *A Page 17 of 27 MB88155 16. Lock-Up Time VDD 3.0 V External clock stabilization waiting time XIN XPD SEL ENS VIH VIH tLK (Lock-up time) CKOUT If the XPD pin is fixed at the “H” level, the maximum time after the power is turned on until the set clock signal is output from CKOUT pin is (the stabilization wait time of input clock to XIN pin) (the lock-up time “tLK”). For the input clock stabilization time, check the characteristics of the resonator or oscillator used. VDD 3.0 V External clock stabilization waiting time XIN VIH XPD SEL ENS VIH tLK (Lock-up time) CKOUT If the XPD pin is used for power-down control, the set clock signal is output from the CKOUT pin at most the lock-up time “tLK” after the XPD pin goes “H” level. (Continued) Document Number: 002-08298 Rev. *A Page 18 of 27 MB88155 (Continued) XIN ENS VIH VIL tLK (Lock-up time) tLK (Lock-up time) CKOUT If the ENS pin is used for modulation enable control during normal operation, the set clock signal is output from the CKOUT pin at most the lock-up time “tLK” after the level at the ENS pin is determined. Note : The wait time for the clock signal output from the CKOUT pin to become stable is required after the IC is released from powerdown mode by the XPD pin or after another pin’s setting is changed. During the period until the output clock signal becomes stable, neither of the output frequency, output clock duty cycle, modulation period, and cycle-cycle jitter characteristic cannot be guaranteed. It is therefore advisable to take action, such as cancelling a device reset at the stage after the lock-up time has passed. Document Number: 002-08298 Rev. *A Page 19 of 27 MB88155 17. Oscillation Circuit The following schematic on the left-hand side shows a sample connection of a general resonator. The oscillation circuit contains a feedback resistor (1 M) . The values of capacitors (C1 and C2) must be adjusted to the optimum constant of the resonator used. The following schematic on the right-hand side shows a sample connection of a 3rd overtone resonator. The values of capacitors (C1, C2, and C3) and inductor (L1) must be adjusted to the optimum constant of the resonator used. The most suitable value is different by individual resonator. Please refer to the resonator manufacturer which you use for the most suitable value. To use an external clock signal (without using the resonator) , input the clock signal to the XIN pin with the XOUT pin connected to nothing. ■ When using the resonator LSI internal Rf (1 MΩ) Rf (1 MΩ) XIN pin XOUT pin XOUT pin XIN pin LSI external L1 C2 C1 C2 C1 C3 Fundamental resonator ■ 3rd overtone resonator When using the external clock LSI internal Rf (1 MΩ) XOUT pin XIN pin External clock LSI external OPEN Note : Note that the jitter characteristic of the input clock signal may affect the cycle-cycle jitter characteristic. Document Number: 002-08298 Rev. *A Page 20 of 27 MB88155 18. Interconnection Circuit Example 1 8 2 7 R1 MB88155 C1 3 6 4 5 C2 R2 C4 C3 C1, C2 : Oscillation stabilization capacitance (refer to “ Oscillation Circuit”) C3 : Capacitor of 10 F or higher C4 : Capacitor of about 0.01 F (connect a capacitor of good high frequency property (ex. laminated ceramic capacitor) to close to this device) R1, R2 : Impedance matching resistor for board pattern Document Number: 002-08298 Rev. *A Page 21 of 27 MB88155 19. Spectrum Example Characteristics The condition of the examples of the characteristic is shown as follows : Input frequency 16 MHz (Output frequency 64 MHz : Using MB88155-410 (Multiplied by 4) ) Power-supply voltage 3.3 V, None load capacity. Modulation rate 1.0 (center spread). Spectrum analyzer HP4396B is connected with CKOUT. The result of the measurement with RBW 1 kHz (ATT use for 6 dB) . CH B Spectrum 10 dB /REF 0 dBm No modulation 5.64 dBm Avg 4 1.0 modulation 26.93 dBm RBW# 1 kHZ VBW 1 kHZ CENTER 64 MHZ Document Number: 002-08298 Rev. *A ATT 6 dB SWP 8.005 s SPAN 12.8 MHZ Page 22 of 27 MB88155 20. Ordering Information Part number Input frequency MB88155PFT-G100-JNE1 12.5 MHz to 25 MHz MB88155PFT-G101-JNE1 25 MHz to 50 MHz MB88155PFT-G102-JNE1 12.5 MHz to 25 MHz MB88155PFT-G103-JNE1 25 MHz to 50 MHz MB88155PFT-G110-JNE1 12.5 MHz to 25 MHz MB88155PFT-G111-JNE1 25 MHz to 50 MHz MB88155PFT-G112-JNE1 12.5 MHz to 25 MHz MB88155PFT-G113-JNE1 25 MHz to 50 MHz MB88155PFT-G400-JNE1 12.5 MHz to 20 MHz MB88155PFT-G402-JNE1 MultiplicaOutput Modulation Modulation enable tion rate frequency type pin Multiplied by 1 MB88155PFT-G101-JN-EFE1 25 MHz to 50 MHz MB88155PFT-G102-JN-EFE1 12.5 MHz to 25 MHz MB88155PFT-G103-JN-EFE1 25 MHz to 50 MHz No Yes Yes No 8-pin plastic TSSOP (FPT-8P-M07) Center spread Down spread 50 MHz to 80 MHz MB88155PFT-G412-JNE1 12.5 MHz to 25 MHz No Remarks The same as input frequency Center spread MB88155PFT-G100-JN-EFE1 Yes Package Down spread Multiplied by 4 MB88155PFT-G410-JNE1 Power down pin Multiplied by 1 Document Number: 002-08298 Rev. *A The same as input frequency No Yes Yes No No Yes Yes No No Yes Yes No 8-pin plastic TSSOP (FPT-8P-M07) Down spread No Emboss taping (EF type) Yes Page 23 of 27 MB88155 Part number Input frequency MB88155PFT-G110-JN-EFE1 12.5 MHz to 25 MHz MB88155PFT-G111-JN-EFE1 25 MHz to 50 MHz MB88155PFT-G112-JN-EFE1 12.5 MHz to 25 MHz MB88155PFT-G113-JN-EFE1 25 MHz to 50 MHz MB88155PFT-G400-JN-EFE1 12.5 MHz to 20 MHz MB88155PFT-G402-JN-EFE1 MultiplicaOutput Modulation Modulation enable tion rate frequency type pin Yes Multiplied by 1 50 MHz to 80 MHz Center spread MB88155PFT-G412-JN-EFE1 MB88155PFT-G100-JN-ERE1 12.5 MHz to 25 MHz MB88155PFT-G101-JN-ERE1 25 MHz to 50 MHz MB88155PFT-G102-JN-ERE1 12.5 MHz to 25 MHz MB88155PFT-G103-JN-ERE1 25 MHz to 50 MHz MB88155PFT-G110-JN-ERE1 12.5 MHz to 25 MHz MB88155PFT-G111-JN-ERE1 25 MHz to 50 MHz MB88155PFT-G112-JN-ERE1 12.5 MHz to 25 MHz MB88155PFT-G113-JN-ERE1 25 MHz to 50 MHz MB88155PFT-G400-JN-ERE1 12.5 MHz to 20 MHz MB88155PFT-G402-JN-ERE1 MB88155PFT-G410-JN-ERE1 Package Remarks 8-pin plastic TSSOP (FPT-8P-M07) Emboss taping (EF type) 8-pin plastic TSSOP (FPT-8P-M07) Emboss taping (EF type) 8-pin plastic TSSOP (FPT-8P-M07) Emboss taping (ER type) No Center spread Down spread Multiplied by 4 MB88155PFT-G410-JN-EFE1 The same as input frequency Power down pin No Yes Yes No No Yes Yes No No Yes Yes No No Yes Yes No Down spread Multiplied by 1 The same as input frequency Center spread Down spread Multiplied by 4 MB88155PFT-G412-JN-ERE1 Document Number: 002-08298 Rev. *A 50 MHz to 80 MHz Center spread No Yes Yes No No Yes Yes No No Yes Page 24 of 27 MB88155 21. Package Dimensions 8-pin plastic TSSOP Lead pitch 0.65 mm Package width × package length 4.40 mm × 3.10 mm Lead shape Gullwing Sealing method Plastic mold Mounting height 1.20 mm Max (FPT-8P-M07) 8-pin plastic TSSOP (FPT-8P-M07) Note) Pins width and pins thickness include plating thickness. 0.127±0.08 (.0050±.003) 3.10±0.10(.122±.004) 8 5 4.40±0.10 6.40±0.20 (.173±.004) (.252±.008) INDEX Details of "A" part 1.20(.047)MAX 4 1 "A" 0.65(.026) 0.22±0.10 (.009±.004) TYP 0~8˚ 0.50(.020) NOM 0.60±0.10 (.024±.004) 0.10±0.05 (Stand off) (.004±.002) 0.25(.010) 0.10(.004) 1.95(.077) REF C 2006 FUJITSU LIMITED F08015Sc-1-1 Document Number: 002-08298 Rev. *A Dimensions in mm (inches). Note: The values in parentheses are reference values Page 25 of 27 MB88155 Document History Spansion Publication Number: DS04-29119-2Ea Document Title: MB88155 Spread Spectrum Clock Generator Document Number: 002-08298 ECN Orig. of Change ** – TAOA 11/09/2006 Initial Release *A 5568597 TAOA 12/29/2016 Updated to Cypress Template Revision Submission Date Document Number: 002-08298 Rev. *A Description of Change Page 26 of 27 MB88155 Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at Cypress Locations. PSoC®Solutions Products ARM® Cortex® Microcontrollers Automotive cypress.com/arm cypress.com/automotive Clocks & Buffers Interface cypress.com/clocks cypress.com/interface Internet of Things Lighting & Power Control Memory cypress.com/iot cypress.com/powerpsoc cypress.com/memory PSoC Cypress Developer Community Forums | WICED IoT Forums | Projects | Video | Blogs | Training | Components Technical Support cypress.com/support cypress.com/psoc Touch Sensing cypress.com/touch USB Controllers Wireless/RF PSoC 1 | PSoC 3 | PSoC 4 | PSoC 5LP cypress.com/usb cypress.com/wireless 27 © Cypress Semiconductor Corporation, 2005-2016. This document is the property of Cypress Semiconductor Corporation and its subsidiaries, including Spansion LLC (“Cypress”). This document, including any software or firmware included or referenced in this document (“Software”), is owned by Cypress under the intellectual property laws and treaties of the United States and other countries worldwide. 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Cypress products are not designed, intended, or authorized for use as critical components in systems designed or intended for the operation of weapons, weapons systems, nuclear installations, life-support devices or systems, other medical devices or systems (including resuscitation equipment and surgical implants), pollution control or hazardous substances management, or other uses where the failure of the device or system could cause personal injury, death, or property damage (“Unintended Uses”). A critical component is any component of a device or system whose failure to perform can be reasonably expected to cause the failure of the device or system, or to affect its safety or effectiveness. Cypress is not liable, in whole or in part, and you shall and hereby do release Cypress from any claim, damage, or other liability arising from or related to all Unintended Uses of Cypress products. You shall indemnify and hold Cypress harmless from and against all claims, costs, damages, and other liabilities, including claims for personal injury or death, arising from or related to any Unintended Uses of Cypress products. Cypress, the Cypress logo, Spansion, the Spansion logo, and combinations thereof, WICED, PSoC, CapSense, EZ-USB, F-RAM, and Traveo are trademarks or registered trademarks of Cypress in the United States and other countries. For a more complete list of Cypress trademarks, visit cypress.com. Other names and brands may be claimed as property of their respective owners. Document Number: 002-08298 Rev. *A Revised December 29, 2016 Page 27 of 27