TI1 ISO721 1007 3.3-v / 5-v high-speed digital isolator Datasheet

ISO721, ISO721M
ISO722, ISO722M
www.ti.com
SLLS629J – JANUARY 2006 – REVISED JULY 2010
3.3-V / 5-V HIGH-SPEED DIGITAL ISOLATORS
Check for Samples: ISO721, ISO721M, ISO722, ISO722M
FEATURES
1
•
23
•
•
•
•
•
•
DESCRIPTION
4000-V(peak) Isolation, 560-Vpeak VIORM
– UL 1577, IEC 60747-5-2 (VDE 0884, Rev. 2)
IEC 61010-1, IEC 60950-1 and CSA
Approved
– 50 kV/µs Transient Immunity, Typical
Signaling Rate 0 Mbps to 150 Mbps
– Low Propagation Delay
– Low Pulse Skew (Pulse-Width Distortion)
Low-Power Sleep Mode
High Electromagnetic Immunity
Low Input-Current Requirement
Failsafe Output
Drop-In Replacement for Most Opto and
Magnetic Isolators
The ISO721, ISO721M, ISO722, and ISO722M are
digital isolators with a logic input and output buffer
separated by a silicon dioxide (SiO2) insulation
barrier. This barrier provides galvanic isolation of up
to 4000 V. Used in conjunction with isolated power
supplies, these devices prevent noise currents on a
data bus or other circuits from entering the local
ground, and interfering with or damaging sensitive
circuitry.
A binary input signal is conditioned, translated to a
balanced signal, then differentiated by the capacitive
isolation barrier. Across the isolation barrier, a
differential comparator receives the logic transition
information, then sets or resets a flip-flop and the
output circuit accordingly. A periodic update pulse is
sent across the barrier to ensure the proper dc level
of the output. If this dc-refresh pulse is not received
for more than 4 ms, the input is assumed to be
unpowered or not being actively driven, and the
failsafe circuit drives the output to a logic-high state.
APPLICATIONS
•
•
•
•
Industrial Fieldbus
– Modbus
– Profibus
– DeviceNet™ Data Buses
– Smart Distributed Systems ( SDS™)
Computer Peripheral Interface
Servo Control Interface
Data Acquisition
FUNCTION DIAGRAM
DC Channel
Isolation Barrier
+
_
OSC
+
PWM
Vref
_
+
POR
BIAS
Filter
Pulse Width
Demodulation
Carrier Detect
POR
ISO722
Only
IN
Input
+
Filter
+
_
Vref
_
Data MUX
AC Detect
3-State
Output Buffer
EN
OUT
+
AC Channel
1
2
3
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
SDS is a trademark of Honeywell.
DeviceNet is a trademark of Open Devicenet Vendors Association, Inc.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2006–2010, Texas Instruments Incorporated
ISO721, ISO721M
ISO722, ISO722M
SLLS629J – JANUARY 2006 – REVISED JULY 2010
www.ti.com
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
DESCRIPTION (CONTINUED)
The symmetry of the dielectric and capacitor within the integrated circuitry provides for close capacitive matching,
and allows fast transient voltage changes between the input and output grounds without corrupting the output.
The small capacitance and resulting time constant provide for fast operation with signaling rates(1) from 0 Mbps
(dc) to 100 Mbps for the ISO721/ISO722, and 0 Mbps to 150 Mbps with the ISO721M/ISO722M.
These devices require two supply voltages of 3.3-V, 5-V, or any combination. All inputs are 5-V tolerant when
supplied from a 3.3-V supply and all outputs are 4-mA CMOS.
The ISO722 and ISO722M devices include an active-low output enable that when driven to a high logic level,
places the output in a high-impedance state and turns off internal bias circuitry to conserve power.
Both the ISO721 and ISO722 have TTL input thresholds and a noise filter at the input that prevent transient
pulses of up to 2 ns in duration from being passed to the output of the device.
The ISO721M and ISO722M have CMOS VCC/2 input thresholds, but do not have the noise-filter and the
additional propagation delay. These features of the ISO721M also provide for reduced-jitter operation.
The ISO721, ISO721M, ISO722, and ISO722M are characterized for operation over the ambient temperature
range of –40°C to 125°C.
(1) The signaling rate of a line is the number of voltage transitions that are made per second expressed in
the units bps (bits per second).
IN
2
VCC1
3
GND1
4
8
VCC2
7
GND2
6
OUT
5
GND2
VCC1
1
IN
2
VCC1
3
GND1
8
VCC2
7
EN
6
OUT
5
4
P0066-09
GND2
VCC1
1
IN
2
VCC1
3
GND1
4
Isolation
1
ISO721
DUB Package
(Top View)
ISO722, ISO722M
D Package
(Top View)
Isolation
VCC1
Isolation
ISO721, ISO721M
D Package
(Top View)
8
VCC2
7
GND2
6
OUT
5
GND2
P0106-01
P0066-10
AVAILABLE OPTIONS
PRODUCT
OUTPUT
ENABLED
INPUT
THRESHOLDS
NOISE
FILTER
PACKAGE (1)
MARKED
AS
ISO721D (rail)
D-8
ISO721
NO
TTL
YES
ISO721
DUB-8
(1)
2
ORDERING NUMBER
ISO721DR (reel)
ISO721DUB (rail)
ISO721DUBR (reel)
ISO721M
NO
CMOS
NO
D-8
IS721M
ISO722
YES
TTL
YES
D-8
ISO722
ISO722M
YES
CMOS
NO
D-8
IS722M
ISO721MD (rail)
ISO721MDR (reel)
ISO722D (rail)
ISO722DR (reel)
ISO722MD (rail)
ISO722MDR (reel)
For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
Web site at www.ti.com.
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Copyright © 2006–2010, Texas Instruments Incorporated
Product Folder Link(s): ISO721 ISO721M ISO722 ISO722M
ISO721, ISO721M
ISO722, ISO722M
www.ti.com
SLLS629J – JANUARY 2006 – REVISED JULY 2010
Table 1. REGULATORY INFORMATION
VDE
CSA
UL
Certified according to IEC 60747-5-2
Approved under CSA Component
Acceptance notice: CA-5A
Recognized under 1577
Component Recognition Program (1)
File number: 40016131
File number: 1698195
File number: E181974
(1)
Production tested ≥ 3000 VRMS for 1 second in accordance with UL 1577.
ABSOLUTE MAXIMUM RATINGS (1)
UNIT
VCC
Supply voltage (2), VCC1, VCC2
–0.5 V to 6 V
VI
Voltage at IN, OUT, or EN terminal
–0.5 V to 6 V
IO
Output current
±15 mA
Human-body model
JEDEC Standard 22, Test Method A114-C.01
Charged-device model
JEDEC Standard 22, Test Method C101
ESD
Electrostatic
discharge
TJ
Maximum junction temperature
(1)
(2)
All pins
±2 kV
±1 kV
170°C
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltage values except differential I/O bus voltages are with respect to network ground terminal and are peak voltage values. Vrms
values are not listed in this publication.
RECOMMENDED OPERATING CONDITIONS
MIN
VCC
IOH
IOL
Supply voltage (1), VCC1, VCC2
3
MAX
UNIT
5.5
V
4
Output current
mA
–4
ISO72x
tui
Input pulse duration
VIH
High-level input voltage (IN, EN)
VIL
Low-level input voltage (IN, EN)
VIH
High-level input voltage (IN, EN)
VIL
Low-level input voltage (IN, EN)
TJ
Junction temperature
H
External magnetic field intensity per IEC 61000-4-8 and IEC 61000-4-9
certification
(1)
TYP
10
ISO72xM
2
VCC
0
0.8
0.7 VCC
VCC
0
0.3 VCC
ISO72x
IOS72xM
ns
6.67
See the Thermal Characteristics table
V
V
150
°C
1000
A/m
For the 5-V operation, VCC1 or VCC2 is specified from 4.5 V to 5.5 V. For the 3-V operation, VCC1 or VCC2 is specified from 3 V to 3.6 V.
Copyright © 2006–2010, Texas Instruments Incorporated
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3
ISO721, ISO721M
ISO722, ISO722M
SLLS629J – JANUARY 2006 – REVISED JULY 2010
www.ti.com
INSULATION CHARACTERISTICS (1)
over recommended operating conditions (unless otherwise noted)
PARAMETER
VIORM
VPR
TEST CONDITIONS
Maximum working insulation voltage
Input to output test voltage
VIOTM
Transient overvoltage
VISO
Isolation voltage per UL
RS
Insulation resistance
4
UNIT
560
Vpeak
After Input/Output Safety Test Subgroup 2/3
VPR = VIORM × 1.2, t = 10 s,
Partial discharge < 5 pC
672
Vpeak
Method a, VPR = VIORM × 1.6,
Type and sample test with t = 10 s,
Partial discharge < 5 pC
896
Vpeak
Method b1, VPR = VIORM × 1.875,
100% production test with t = 1 s,
Partial discharge < 5 pC
1050
Vpeak
t = 60 s
4000
Vpeak
VTEST = VISO, t = 60 s (qualification)
3535 / 2500
VTEST = 1.2 × VISO, t = 1 s (100% production) (2)
4242 / 3000
>109
VIO = 500 V at TS
Pollution degree
(1)
(2)
SPECIFICATIONS
Vpeak/Vrms
Ω
2
Climatic classification 40/125/21
Based on lifetime curve (see the High-Voltage Lifetime of the ISO72x Family of Digital Isolators application report, SLLA197); these
devices can withstand 4242 Vpeak / 3000 Vrms for > 10,000 s at 150oC.
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Product Folder Link(s): ISO721 ISO721M ISO722 ISO722M
ISO721, ISO721M
ISO722, ISO722M
www.ti.com
SLLS629J – JANUARY 2006 – REVISED JULY 2010
ELECTRICAL CHARACTERISTICS: VCC1 and VCC2 5-V (1) OPERATION
over recommended operating conditions (unless otherwise noted)
PARAMETER
ICC1
TEST CONDITIONS
Quiescent
VCC1 supply current
VI = VCC or 0 V, no load
25 Mbps
ISO722/722M Sleep Mode
ICC2
VCC2 supply current
VOH
High-level output voltage
VOL
Low-level output voltage
MIN
MAX
0.5
1
2
4
EN at VCC
Quiescent
VI = VCC or 0 V,
No load
25 Mbps
VI = VCC or 0 V, no load
UNIT
mA
200
EN at 0 V or
ISO721/721M
8
12
10
14
IOH = -4 mA, See Figure 1
VCC – 0.8
4.6
IOH = –20 mA, See Figure 1
VCC – 0.1
5
mA
mA
V
IOL = 4 mA, See Figure 1
0.2
0.4
IOL = 20 mA, See Figure 1
0
0.1
VI(HYS) Input voltage hysteresis
V
150
IIH
High-level input current
EN, IN at 2 V
IIL
Low-level input current
EN, IN at 0.8 V
IOZ
High-impedance output
current
CI
Input capacitance to ground
IN at VCC, VI = 0.4 sin (4E6pt)
CMTI
Common-mode transient immunity
VI = VCC or 0 V, See Figure 5
(1)
TYP
ISO722, ISO722M
mV
10
mA
–10
EN, IN at VCC
1
25
mA
1
pF
50
kV/ms
For 5-V operation, VCC1 and VCC2 are specified from 4.5 V to 5.5 V.
SWITCHING CHARACTERISTICS: VCC1 and VCC2 5-V OPERATION
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
tPLH
Propagation delay, low-to-high-level output
tPHL
Propagation delay, high-to-low-level output
tsk(p)
Pulse skew |tPHL – tPLH|
tPLH
Propagation delay, low-to-high-level output
tPHL
Propagation delay, high-to-low-level output
tsk(p)
Pulse skew |tPHL – tPLH|
ISO72x
MIN
TYP
MAX
13
17
24
ns
13
EN at 0 V,
See Figure 1
8
24
ns
2
ns
10
16
ns
10
16
ns
1
ns
Part-to-part skew
0
3
ns
tr
Output signal rise time
1
tf
Output signal fall time
tpHZ
Sleep-mode propagation delay,
high-level-to-high-mpedance output
(1)
EN at 0 V,
See Figure 1
tpZH
Sleep-mode propagation delay,
high-impedance-to-high-level output
tpLZ
Sleep-mode propagation delay,
low-level-to-high-impedance output
ISO722
ISO722M
tfs
Failsafe output delay time from input power loss
ISO72x
See Figure 4
8
15
ns
3.5
4
8
ms
5.5
8
15
ns
4
5
8
ms
3
100-Mbps NRZ data input, See Figure 6
2
100-Mbps unrestricted bit run length data
input, See Figure 6
3
150-Mbps NRZ data input, See Figure 6
1
ISO72xM 150-Mbps unrestricted bit run length data
input, See Figure 6
(1)
6
See Figure 3
Sleep-mode propagation delay,
high-impedance-to-low-level output
Peak-to-peak eye-pattern jitter
ns
1
See Figure 2
tpZL
tjit(PP)
8
17
0.5
0.5
tsk(pp)
ISO72xM
UNIT
ms
ns
2
tsk(PP) is the magnitude of the difference in propagation delay times between any specified terminals of two devices when both devices
operate with the same supply voltages, at the same temperature, and have identical packages and test circuits.
Copyright © 2006–2010, Texas Instruments Incorporated
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Product Folder Link(s): ISO721 ISO721M ISO722 ISO722M
5
ISO721, ISO721M
ISO722, ISO722M
SLLS629J – JANUARY 2006 – REVISED JULY 2010
www.ti.com
ELECTRICAL CHARACTERISTICS: VCC1 at 5-V, VCC2 at 3.3-V (1) OPERATION
over recommended operating conditions (unless otherwise noted)
PARAMETER
ICC1
TEST CONDITIONS
Quiescent
VCC1 supply current
VI = VCC or 0 V, no load
25 Mbps
ISO722/722M
Sleep mode
ICC2
VCC2 supply current
VI = VCC or 0 V,
No load
Quiescent
25 Mbps
VOH
High-level output voltage
VOL
Low-level output voltage
MIN
MAX
0.5
1
2
4
EN at VCC
UNIT
mA
150
EN at 0 V or
ISO721/721M
VI = VCC or 0 V, no load
4
6.5
5
7.5
IOH = –4 mA, See Figure 1
VCC – 0.4
3
IOH = –20 mA, See Figure 1
VCC – 0.1
3.3
mA
mA
V
IOL = 4 mA, See Figure 1
0.2
0.4
IOL = 20 mA, See Figure 1
0
0.1
VI(HYS) Input voltage hysteresis
V
150
IIH
High-level input current
EN, IN at 2 V
IIL
Low-level input current
EN, IN at 0.8 V
IOZ
High-impedance output
current
CI
Input capacitance to ground
IN at VCC, VI = 0.4 sin (4E6pt)
CMTI
Common-mode transient immunity
VI = VCC or 0 V, See Figure 5
(1)
TYP
ISO722, ISO722M
mV
10
mA
–10
mA
EN, IN at VCC
1
25
mA
1
pF
40
kV/ms
For 5-V operation, VCC1 is specified from 4.5 V to 5.5 V. For 3.3-V operation, VCC2 is specified from 3 V to 3.6 V.
SWITCHING CHARACTERISTICS: VCC1 at 5-V, VCC2 at 3.3-V OPERATION
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
tPLH
Propagation delay, low-to-high-level output
tPHL
Propagation delay , high-to-low-level output
tsk(p)
Pulse skew |tPHL – tPLH|
tPLH
Propagation delay, low-to-high-level output
tPHL
Propagation delay, high-to-low-level output
tsk(p)
Pulse skew |tPHL – tPLH|
tsk(pp)
(1)
EN at 0 V,
See Figure 1
ISO72xM
Output signal rise time
tf
Output signal fall time
tpHZ
Sleep-mode propagation delay,
high-level-to-high-mpedance output
Sleep-mode propagation delay,
high-impedance-to-high-level output
tpLZ
Sleep-mode propagation delay,
low-level-to-high-impedance output
ISO722
ISO722M
15
19
30
ns
15
19
30
ns
0.5
3
ns
10
12
20
ns
10
12
20
ns
0.5
1
ns
0
5
ns
2
ns
2
ns
7
11
25
ns
4.5
6
8
ms
7
13
25
ns
4.5
6
8
ms
See Figure 3
Sleep-mode propagation delay,
high-impedance-to-low-level output
tfs
Failsafe output delay time from input power loss
ISO72x
Peak-to-peak eye-pattern jitter
UNIT
See Figure 2
tpZL
See Figure 4
3
100-Mbps NRZ data input, See Figure 6
2
100-Mbps unrestricted bit run length data
input, See Figure 6
3
150-Mbps NRZ data input, See Figure 6
1
ISO72xM 150-Mbps unrestricted bit run length data
input, See Figure 6
6
MAX
EN at 0 V,
See Figure 1
tpZH
(1)
TYP
Part-to-part skew
tr
tjit(PP)
ISO72x
MIN
ms
ns
2
tsk(PP) is the magnitude of the difference in propagation delay times between any specified terminals of two devices when both devices
operate with the same supply voltages, at the same temperature, and have identical packages and test circuits.
Submit Documentation Feedback
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Product Folder Link(s): ISO721 ISO721M ISO722 ISO722M
ISO721, ISO721M
ISO722, ISO722M
www.ti.com
SLLS629J – JANUARY 2006 – REVISED JULY 2010
ELECTRICAL CHARACTERISTICS: VCC1 at 3.3-V, VCC2 at 5-V (1) OPERATION
over recommended operating conditions (unless otherwise noted)
PARAMETER
ICC1
TEST CONDITIONS
Quiescent
VCC1 supply current
VCC2 supply current
VI = VCC or 0 V,
No load
Quiescent
25 Mbps
VOH
High-level output voltage
VOL
Low-level output voltage
MAX
0.3
0.5
1
2
EN at VCC
UNIT
mA
200
EN at 0 V or
ISO721/721M
VI = VCC or 0 V, No load
8
12
10
14
IOH = –4 mA, See Figure 1
VCC – 0.8
4.6
IOH = –20 mA, See Figure 1
VCC – 0.1
5
mA
mA
V
IOL = 4 mA, See Figure 1
0.2
0.4
IOL = 20 mA, See Figure 1
0
0.1
VI(HYS) Input voltage hysteresis
V
150
IIH
High-level input current
EN, IN at 2 V
IIL
Low-level input current
EN, IN at 0.8 V
IOZ
High-impedance output
current
CI
Input capacitance to ground
IN at VCC, VI = 0.4 sin (4E6pt)
CMTI
Common-mode transient immunity
VI = VCC or 0 V, See Figure 5
(1)
TYP
VI = VCC or 0 V, no load
25 Mbps
ISO722/722M
Sleep mode
ICC2
MIN
ISO722, ISO722M
mV
10
mA
–10
mA
EN, IN at VCC
1
25
mA
1
pF
40
kV/ms
For 5-V operation, VCC2 is specified from 4.5 V to 5.5 V. For 3.3-V operation, VCC1 is specified from 3 V to 3.6 V.
SWITCHING CHARACTERISTICS: VCC1 at 3.3-V, VCC2 at 5-V OPERATION
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
tPLH
Propagation delay, low-to-high-level output
tPHL
Propagation delay , high-to-low-level output
tsk(p)
Pulse skew |tPHL – tPLH|
tPLH
Propagation delay, low-to-high-level output
tPHL
Propagation delay, high-to-low-level output
tsk(p)
Pulse skew |tPHL – tPLH|
tsk(pp)
(1)
EN at 0 V,
See Figure 1
ISO72xM
Output signal rise time
tf
Output signal fall time
tpHZ
Sleep-mode propagation delay,
high-level-to-high-mpedance output
MAX
15
17
30
ns
15
17
30
ns
0.5
2
ns
10
12
21
ns
10
12
21
ns
0.5
1
ns
0
5
ns
EN at 0 V,
See Figure 1
tpZH
Sleep-mode propagation delay,
high-impedance-to-high-level output
tpLZ
Sleep-mode propagation delay,
low-level-to-high-impedance output
ISO722
ISO722M
1
ns
1
ns
7
9
15
ns
4.5
5
8
ms
7
9
15
ns
4.5
5
8
ms
See Figure 3
Sleep-mode propagation delay,
high-impedance-to-low-level output
tfs
Failsafe output delay time from input power loss
ISO72x
Peak-to-peak eye-pattern jitter
UNIT
See Figure 2
tpZL
See Figure 4
3
100-Mbps NRZ data input, See Figure 6
2
100-Mbps unrestricted bit run length data
input, See Figure 6
3
150-Mbps NRZ data input, See Figure 6
1
ISO72xM 150-Mbps unrestricted bit run length data
input, See Figure 6
(1)
TYP
Part-to-part skew
tr
tjit(PP)
ISO72x
MIN
ms
ns
2
tsk(PP) is the magnitude of the difference in propagation delay times between any specified terminals of two devices when both devices
operate with the same supply voltages, at the same temperature, and have identical packages and test circuits.
Copyright © 2006–2010, Texas Instruments Incorporated
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ISO722, ISO722M
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www.ti.com
ELECTRICAL CHARACTERISTICS: VCC1 and VCC2 at 3.3-V (1) OPERATION
over recommended operating conditions (unless otherwise noted)
PARAMETER
ICC1
TEST CONDITIONS
Quiescent
VCC1 supply current
VI = VCC or 0 V, no load
25 Mbps
ISO722/722M
Sleep Mode
ICC2
VCC2 supply current
VI = VCC or 0 V,
No load
Quiescent
25 Mbps
VOH
High-level output voltage
VOL
Low-level output voltage
MIN
MAX
0.3
0.5
1
2
EN at VCC
UNIT
mA
150
EN at 0 V or
ISO721/721M
VI = VCC or 0 V, no load
4
6.5
5
7.5
IOH = –4 mA, See Figure 1
VCC – 0.4
3
IOH = –20 mA, See Figure 1
VCC – 0.1
3.3
mA
mA
V
IOL = 4 mA, See Figure 1
0.2
0.4
IOL = 20 mA, See Figure 1
0
0.1
VI(HYS) Input voltage hysteresis
V
150
IIH
High-level input current
EN, IN at 2 V
IIL
Low-level input current
EN, IN at 0.8 V
IOZ
High-impedance output
ISO722, ISO722M
current
EN, IN at VCC
CI
Input capacitance to ground
IN at VCC, VI = 0.4 sin (4E6pt)
CMTI
Common-mode transient immunity
VI = VCC or 0 V, See Figure 5
(1)
TYP
mV
10
mA
–10
mA
1
25
mA
1
pF
40
kV/ms
For the 3.3-V operation, VCC1 and VCC2 are specified from 3 V to 3.6 V.
SWITCHING CHARACTERISTICS: VCC1 and VCC2 at 3.3-V OPERATION
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
tPLH
Propagation delay, low-to-high-level output
tPHL
Propagation delay , high-to-low-level output
tsk(p)
Pulse skew |tPHL – tPLH|
tPLH
Propagation delay, low-to-high-level output
tPHL
Propagation delay, high-to-low-level output
tsk(p)
Pulse skew |tPHL – tPLH|
tsk(pp)
(1)
EN at 0 V,
See Figure 1
ISO72xM
Output signal rise time
tf
Output signal fall time
tpHZ
Sleep-mode propagation delay,
high-level-to-high-mpedance output
Sleep-mode propagation delay,
high-impedance-to-high-level output
tpLZ
Sleep-mode propagation delay,
low-level-to-high-impedance output
17
20
34
ns
17
20
34
ns
0.5
3
ns
10
12
25
ns
10
12
25
ns
0.5
1
ns
0
5
ns
2
ns
2
ISO722
ISO722M
7
13
25
ns
5
6
8
µs
7
13
25
ns
5
6
8
ms
See Figure 3
Sleep-mode propagation delay,
high-impedance-to-low-level output
tfs
Failsafe output delay time from input power loss
ISO72x
Peak-to-peak eye-pattern jitter
UNIT
See Figure 2
tpZL
See Figure 4
3
100-Mbps NRZ data input, See Figure 6
2
100-Mbps unrestricted bit run length data
input, See Figure 6
3
150-Mbps NRZ data input, See Figure 6
1
ISO72xM 150-Mbps unrestricted bit run length data
input, See Figure 6
8
MAX
EN at 0 V,
See Figure 1
tpZH
(1)
TYP
Part-to-part skew
tr
tjit(PP)
ISO72x
MIN
ms
ns
2
tsk(PP) is the magnitude of the difference in propagation delay times between any specified terminals of two devices when both devices
operate with the same supply voltages, at the same temperature, and have identical packages and test circuits.
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ISOLATION BARRIER
PARAMETER MEASUREMENT INFORMATION
IN
Input
Generator
NOTE A
+
VI
50 W
-
VCC1
IO
OUT
VCC1/2
VI
0V
EN
tPHL
VOH
tPLH
+
ISO722
and
ISO722M
VCC1/2
CL
Note B
VO
-
90%
50%
VO
50%
10%
tr
VOL
tf
3V
ISOLATION BARRIER
Figure 1. Switching Characteristic Test Circuit and Voltage Waveforms
IN
Input
Generator
NOTE A
VO
OUT
VCC2
VI
VCC2/2
0V
EN
RL = 1 kW ±1 %
CL
NOTE B
+
tPZH
VOH
50%
VO
VI
VCC2/2
50 W
0.5 V
0V
tPHZ
-
Figure 2. ISO722 Sleep-Mode High-Level Output Test Circuit and Voltage Waveforms
0V
ISOLATION BARRIER
VCC2
IN
Input
Generator
NOTE A
RL = 1 kW ±1%
OUT
EN
CL
NOTE B
+
VI
VCC2
VI
VO
VCC2/2
0V
tPZL
VO
VCC2/2
tPLZ
VCC2
0.5 V
50%
VOL
50 W
-
Figure 3. ISO722 Sleep-Mode Low-Level Output Test Circuit and Voltage Waveforms
NOTE
A: The input pulse is supplied by a generator having the following characteristics:
PRR ≤ 50 kHz, 50% duty cycle, tr ≤ 3 ns, tf ≤ 3 ns, ZO = 50 Ω.
B: CL = 15 pF ± 20% and includes instrumentation and fixture capacitance.
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PARAMETER MEASUREMENT INFORMATION (continued)
VCC1
0V
IN
ISOLATION BARRIER
VI
VCC1
VI
OUT
VO
0V
tfs
VO
CL
15 pF
±20%
EN
ISO722
and
ISO722M
2.7 V
VOH
50%
VOL
NOTE: VI transition time is 100 ns.
VCC1
IN
VCC
or
0V
CI = 0.1 mF,
GND1
ISOLATION BARRIER
Figure 4. Failsafe Delay Time Test Circuit and Voltage Waveforms
±1%
VCC2
OUT
GND2
CL
15 pF
±20%
VO
VCM
NOTE: Pass/fail criterion is no change in VO.
Figure 5. Common-Mode Transient-Immunity Test Circuit and Voltage Waveform
10
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PARAMETER MEASUREMENT INFORMATION (continued)
Tektronix
HFS9009
Tektronix
784D
PATTERN
GENERATOR
VCC1
In p u t
0V
O u tp u t
VCC2/2
J itte r
NOTE: Bit pattern run length is 216 – 1. Transition time is 800 ps. NRZ data input has no more than five consecutive
1s or 0s.
Figure 6. Peak-to-Peak Eye-Pattern Jitter Test Circuit and Voltage Waveform
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DEVICE INFORMATION
PACKAGE INSULATION CHARACTERISTICS
PARAMETER
DESCRIPTIONS / TEST CONDITIONS
(1)
4.8
DUB-8
6.1
D-8
4.3
DUB-8
6.8
TYP
MAX UNIT
L(101)
Minimum air gap (clearance)
L(102)
Minimum external tracking
(creepage)
CTI
Tracking resistance (comparative
DIN IEC 60112/VDE 0303 Part 1
tracking index)
≥ 175
V
Minimum internal gap (internal
clearance)
0.008
mm
RIO
Shortest terminal-to-terminal distance through air
MIN
D-8
Shortest terminal-to-terminal distance across the
package surface
Isolation resistance
Distance through insulation
mm
mm
Input to output, VIO = 500 V; all pins on each side of the
barrier tied together, creating a two-terminal device; TA <
100°C
>1012
Ω
Input to output, VIO = 500 V,
100°C ≤ TA< TA max.
>1011
Ω
CIO
Barrier capacitance
Input-to-output
VI = 0.4 sin (4E6pt)
1
pF
CI
Input capacitance to ground
VI = 0.4 sin (4E6pt)
1
pF
(1)
Creepage and clearance requirements are applied according to the specific equipment isolation standards of an application. Care should
be taken to maintain the creepage and clearance distance of a board design to ensure that the mounting pads of the isolator on the
printed circuit board do not reduce this distance.
Creepage and clearance on a printed circuit board become equal according to the measurement techniques shown in the Isolation
Glossary. Techniques such as inserting grooves and/or ribs on a printed circuit board are used to help increase these specifications.
IEC 60664-1 RATINGS TABLE
PARAMETER
TEST CONDITIONS
Basic isolation group
Installation classification
SPECIFICATION
Material group
IIIa
Rated mains voltage ≤150 VRMS
I-IV
Rated mains voltage ≤300 VRMS
I-III
DEVICE I/O SCHEMATIC
Equivalent Input and Output Schematic Diagrams
Enable
Output
Input
VCC2
VCC2
VCC1
VCC2
VCC1
VCC1
750 kW
500 W
OUT
500 W
EN
IN
13 W
1 MW
12
8W
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IEC SAFETY LIMITING VALUES
Safety limiting intends to prevent potential damage to the isolation barrier upon failure of input or output circuitry.
A failure of the I/O can allow low resistance to ground or the supply, and without current limiting, dissipate
sufficient power to overheat the die and damage the isolation barrier, potentially leading to secondary system
failures.
PARAMETER
TEST CONDITIONS
IS
Safety input, output, or supply current
TS
Maximum case temperature
MIN
TYP
MAX
qJA = 263°C/W, VI = 5.5 V, TJ = 170°C, TA = 25°C
100
qJA = 263°C/W, VI = 3.6 V, TJ = 170°C, TA = 25°C
153
UNIT
mA
150
°C
The safety-limiting constraint is the absolute maximum junction temperature specified in the absolute maximum
ratings table. The power dissipation and junction-to-air thermal impedance of the device installed in the
application hardware determines the junction temperature. The junction-to-air thermal resistance in the Thermal
Characteristics table is that of a device installed in the JESD51-3, Low Effective Thermal Conductivity Test Board
for Leaded Surface Mount Packages and is conservative. The power is the recommended maximum input
voltage times the current. The junction temperature is then the ambient temperature plus the power times the
junction-to-air thermal resistance.
Table 2. THERMAL CHARACTERISTICS for D-8 PACKAGE
(over recommended operating conditions unless otherwise noted)
PARAMETER
TEST CONDITIONS
Junction-to-air
RqJB
Junction-to-board thermal resistance
RqJC
Junction-to-case thermal resistance
(1)
UNIT
263
°C/W
High-K thermal resistance (1)
125
°C/W
44
°C/W
75
°C/W
Low-K thermal resistance
RqJA
PD
TYP MAX
(1)
MIN
ISO72x
VCC1 = VCC2 = 5.5 V, TJ = 150°C, CL = 15 pF,
Input a 100-Mbps 50% duty-cycle square wave
159
ISO72xM
VCC1 = VCC2 = 5.5 V, TJ = 150°C, CL = 15 pF,
Input a 150-Mbps 50% duty-cycle square wave
195
Device power dissipation
mW
Tested in accordance with the low-K or high-K thermal metric definition of EIA/JESD51-3 for leaded surface-mount packages.
Table 3. THERMAL CHARACTERISTICS for DUB-8 PACKAGE
(over recommended operating conditions unless otherwise noted)
PARAMETER
TEST CONDITIONS
RqJA
Junction-to-air
RqJB
Junction-to-board thermal resistance
RqJC
Junction-to-case thermal resistance
PD
(1)
Device power dissipation
ISO721
TYP MAX
UNIT
Low-K thermal resistance (1)
MIN
188
°C/W
High-K thermal resistance (1)
117
°C/W
82.1
°C/W
60
°C/W
VCC1 = VCC2 = 5.5 V, TJ = 150°C, CL = 15 pF,
Input a 100 Mbps 50% duty cycle square wave
159
mW
Tested in accordance with the low-K or high-K thermal metric definition of EIA/JESD51-3 for leaded surface-mount packages.
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200
Safety Limiting Current − mA
175
VCC1, VCC2 = 3.6 V
150
125
100
75
VCC1, VCC2 = 5.5 V
50
25
0
0
50
100
150
200
o
Case Temperature − C
Figure 7. qJC Thermal Derating Curve per IEC 60747-5-2
FUNCTION TABLE
Table 4. ISO721 (1)
(1)
VCC1
VCC2
PU
PU
PD
PU
INPUT
(IN)
OUTPUT
(OUT)
H
H
L
L
Open
H
X
H
PU = Powered up (VCC ≥ 3 V); PD = Powered down (VCC ≤ 2.5 V); X = Irrelevant; H = High level;
L = Low level
Table 5. ISO722 (1)
VCC1
(1)
14
VCC2
INPUT
(IN)
ISO722/ISO722M
OUTPUT ENABLE (EN)
OUTPUT
(OUT)
H
L or open
H
L
L or open
L
X
H
Z
PU
PU
Open
L or open
H
PD
PU
X
L or open
H
PD
PU
X
H
Z
PU = Powered up (VCC ≥ 3 V); PD = Powered down (VCC ≤ 2.5 V); X = Irrelevant; Z = High impedance; H = High level; L = Low level
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SLLS629J – JANUARY 2006 – REVISED JULY 2010
TYPICAL CHARACTERISTICS
RMS SUPPLY CURRENT vs
SIGNALING RATE
RMS SUPPLY CURRENT vs
SIGNALING RATE
15
10
VCC1 = 3.3 V,
VCC2 = 3.3 V,
o
TA = 25 C,
CL = 15 pF
8
VCC1 = 5 V,
VCC2 = 5 V,
o
TA = 25 C,
CL = 15 pF
13
ICC − Supply Current − (mARMS)
ICC − Supply Current − (mARMS)
9
14
7
6
ICC2
5
4
3
ICC1
2
12
11
10
9
8
7
ICC1
6
5
4
3
2
1
1
0
0
0
25
50
75
0
100
Figure 9.
PROPAGATION DELAY vs
FREE-AIR TEMPERATURE
PROPAGATION DELAY vs
FREE-AIR TEMPERATURE
100
20
16
tPLH
15
tPHL
ISO72xM
10
VCC1 = 3.3 V,
VCC2 = 3.3 V,
CL = 15 pF,
Air Flow at 7 cf/m
5
-10
5
20
35
50
80
65
95
Propagation Delay − ns
20
-25
tPLH
18
ISO72x
tPHL
tPHL
ISO72x
Propagation Delay − ns
75
Figure 8.
tPLH
14
tPLH
12
tPHL
10
8
ISO72xM
6
VCC1 = 5 V,
VCC2 = 5 V,
CL = 15 pF,
Air Flow at 7 cf/m
4
2
0
-40
110 125
-25
-10
o
5
20
35
50
80
65
95
110 125
o
TA − Free-Air Temperature − C
TA − Free-Air Temperature − C
Figure 10.
Figure 11.
ISO72x INPUT THRESHOLD VOLTAGE vs
FREE-AIR TEMPERATURE
ISO72xM INPUT THRESHOLD VOLTAGE vs
FREE-AIR TEMPERATURE
1.4
2.5
5-V (VIT+)
2.4
1.3
3.3-V (VIT+)
1.25
1.2
Air Flow at 7 cf/m
1.15
5-V (VIT- )
1.1
VIT − Input Voltage Threshold − V
1.35
5-V (VIT+)
2.3
2.2
5-V (VIT-)
2.1
2
Air Flow at 7 cf/m
1.9
1.8
3.3-V (VIT+)
1.7
1.6
1.05
3.3-V (VIT- )
1
-40
50
Signaling Rate (Mbps)
25
0
-40
25
Signaling Rate (Mbps)
30
VIT − Input Voltage Threshold − V
ICC2
-25
-10
5
20
35
50
3.3-V (VIT-)
1.5
80
65
o
TA − Free-Air Temperature − C
95
110 125
1.4
-40
-25
-10
5
20
50
80
65
95
110 125
o
Figure 12.
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35
TA − Free-Air Temperature − C
Figure 13.
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TYPICAL CHARACTERISTICS (continued)
HIGH-LEVEL OUTPUT CURRENT vs
HIGH-LEVEL OUTPUT VOLTAGE
2.92
-80
2.9
-70
IOH − High-Level Output Current − mA
VCC1 Failsafe Voltage − V
VCC1 FAILSAFE THRESHOLD VOLTAGE vs
FREE-AIR TEMPERATURE
Vfs+
2.88
VCC = 5 V or 3.3 V,
CL = 15 pF,
Air Flow at 7 cf/m
2.86
2.84
2.82
Vfs-
2.8
2.78
-40
o
TA = 25 C
VCC = 5 V
-60
-50
-40
VCC = 3.3 V
-30
-20
-10
0
-25
-10
5
20
35
50
80
65
95
0
110 125
1
2
3
4
5
6
VOH − High-Level Output Voltage − V
o
TA − Free-Air Temperature − C
Figure 14.
Figure 15.
LOW-LEVEL OUTPUT CURRENT vs
LOW-LEVEL OUTPUT VOLTAGE
70
o
IOL − Low-Level Output Current − mA
TA = 25 C
60
VCC = 5 V
50
40
30
VCC = 3.3 V
20
10
0
0
1
2
3
4
5
VOL − Low-Level Output Voltage − V
Figure 16.
16
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APPLICATION INFORMATION
MANUFACTURER CROSS-REFERENCE DATA
The ISO72xx isolators have the same functional pinout as those of most other vendors, and they are often
pin-for-pin drop-in replacements. The notable differences in the products are propagation delay, signaling rate,
power consumption, and transient protection rating. Table 6 is used as a guide for replacing other isolators with
the ISO72x family of single channel isolators.
IN 2
VCC1 3
6 OUT
GND1 4
5 GND2
GND1 4
8 VCC2
7 GND2
6 OUT
5 GND2
VDD1 1
VI 2
VDD1 3
GND1 4
8 VDD2
7 GND2
6 VO
5 GND2
VDD1 1
VI 2
*
3
GND1 4
IL710
8 VDD2
7 NC
VDD1 1
VI 2
6 VO
5 GND2
NC 3
GND1 4
8 VDD2
7 VOE
Isolation
VCC1 1
HCPL-xxxx
ADuM1100
Isolation
VCC1 3
8 VCC2
7 EN
Isolation
IN 2
Isolation
VCC1 1
ISO721
or
ISO721M
Isolation
ISO722
or
ISO722M
6 VO
5 GND2
Figure 17. Pin Cross Reference
Table 6. CROSS REFERENCE
PIN 7
ISOLATOR
ISO721 (1)
(2)
ADuM1100 (1)
HCPL-xxxx
IL710
(1)
(2)
(3)
(4)
(5)
(2)
PIN 1
PIN 2
PIN 3
PIN 4
PIN 5
PIN 6
ISO721
OR
ISO721M
VCC1
IN
VCC1
GND1
GND2
OUT
GND2
VDD1
VI
VDD1
GND1
GND2
VO
GND2
VDD2
VDD1
VI
*Leave
Open (3)
GND1
GND2
VO
NC (4)
VDD2
GND1
GND2
VO
V OE
VDD2
VDD1
VI
NC
(5)
ISO722
OR
ISO722M
PIN 8
EN
VCC2
Pin 1 should be used as VCC1. Pin 3 may also be used as VCC1 or left open, as long as pin 1 is connected to VCC1.
Pin 5 should be used as GND2. Pin 7 may also be used as GND2 or left open, as long as pin 5 is connected to GND2.
Pin 3 of the HCPL devices must be left open. This is not a problem when substituting an ISO72xx device, because the extra VCC1 on pin
3 may be left an open circuit as well.
An HCPL device pin 7 must be left floating (open) or grounded when an ISO722 or ISO722M device is to be used as a drop-in
replacement. If pin 7 of the ISO722 or ISO722M device is placed in a high logic state, the output of the device is disabled.
Pin 3 of the IL710 must not be tied to ground on the circuit board because this shorts the ISO72xx's VCC1 to ground. The IL710 pin 3
may only be tied to VCC or left open to drop in an ISO72xx.
VCC1
VCC2
2 mm
max.
from
VCC1
0.1mF
ISO721
or ISO 721M
1
8
2 mm
max.
from
VCC2
0.1mF
2 IN
7
6
3
OUT
4
5
INPUT
OUTPUT
GND1
GND2
Figure 18. Basic Application Circuit
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ISOLATION GLOSSARY
Creepage Distance — The shortest path between two conductive input to output leads measured along the
surface of the insulation. The shortest distance path is found around the end of the package body.
Clearance — The shortest distance between two conductive input to output leads measured through air (line of
sight).
Input-to Output Barrier Capacitance — The total capacitance between all input terminals connected together,
and all output terminals connected together.
Input-to Output Barrier Resistance — The total resistance between all input terminals connected together, and
all output terminals connected together.
Primary Circuit — An internal circuit directly connected to an external supply main or other equivalent source
which supplies the primary circuit electric power.
Secondary Circuit — A circuit with no direct connection to primary power, which derives its power from a
separate isolated source.
Comparative Tracking Index (CTI) — CTI is an index used for electrical insulating materials that is defined as
the numerical value of the voltage which causes failure by tracking during standard testing. Tracking is the
process that produces a partially conducting path of localized deterioration on or through the surface of an
insulating material as a result of the action of electric discharges on or close to an insulation surface -- the higher
the CTI value of the insulating material, the smaller the minimum creepage distance.
Generally, insulation breakdown occurs either through the material, over its surface, or both. Surface failure may
arise from flashover or from the progressive degradation of the insulation surface by small localized sparks. Such
sparks are the result of the breaking of a surface film of conducting contaminant on the insulation. The resulting
break in the leakage current produces an overvoltage at the site of the discontinuity, and an electric spark is
generated. These sparks often cause carbonization on insulation material and lead to a carbon track between
points of different potential. This process is known as tracking.
18
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Insulation:
Operational insulation — Insulation needed for the correct operation of the equipment.
Basic insulation — Insulation to provide basic protection against electric shock.
Supplementary insulation — Independent insulation applied in addition to basic insulation in order to ensure
protection against electric shock in the event of a failure of the basic insulation.
Double insulation — Insulation comprising both basic and supplementary insulation.
Reinforced insulation — A single insulation system which provides a degree of protection against electric shock
equivalent to double insulation.
Pollution Degree:
Pollution Degree 1 — No pollution, or only dry, nonconductive pollution occurs. The pollution has no influence.
Pollution Degree 2 — Normally, only nonconductive pollution occurs. However, a temporary conductivity caused
by condensation must be expected.
Pollution Degree 3 — Conductive pollution occurs or dry nonconductive pollution occurs which becomes
conductive due to condensation which is to be expected.
Pollution Degree 4 – Continuous conductivity occurs due to conductive dust, rain, or other wet conditions.
Installation Category:
Overvoltage Category — This section is directed at insulation co-ordination by identifying the transient
overvoltages which may occur, and by assigning four different levels as indicated in IEC 60664.
I: Signal level — Special equipment or parts of equipment.
II: Local level — Portable equipment, etc.
III: Distribution level — Fixed installation
IV: Primary supply level — Overhead lines, cable systems
Each category should be subject to smaller transients than the category above.
A
A
A
REVISION HISTORY
Changes from Revision I (February 2010) to Revision J
Page
•
Changed V to Vpeak in UNIT column of IEC Insulation Characteristics table ..................................................................... 4
•
Added row for VISO to IEC Insulation Characteristics table .................................................................................................. 4
•
Changed note from " ............................................................................................................................................................. 5
•
Removed VCC2 from 5-V operation, changed 3-V operation to 3.3-V operation, and removed VCC1 from 3.3-V
operation in note. .................................................................................................................................................................. 6
•
Removed VCC1 from 5-V operation, changed 3-V operation to 3.3-V operation, and removed VCC2 from 3.3-V
operation in note. .................................................................................................................................................................. 7
•
Removed 5-V operation, changed 3-V operation to 3.3-V operation, and changed " .......................................................... 8
•
Added "INSULATION" to the title of "PACKAGE CHARACTERISTICS" table ................................................................... 12
•
Added "Descriptions" to header of PACKAGE INSULATION CHARACTERISTICS table ................................................. 12
Changes from Revision H (June 2009) to Revision I
•
Page
Changed 50 kV/s to 50 kV/µs ............................................................................................................................................... 1
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Product Folder Link(s): ISO721 ISO721M ISO722 ISO722M
19
PACKAGE OPTION ADDENDUM
www.ti.com
10-Jul-2010
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package
Drawing
Pins
Package Qty
Eco Plan
(2)
Lead/
Ball Finish
MSL Peak Temp
(3)
Samples
(Requires Login)
ISO721D
ACTIVE
SOIC
D
8
75
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM
Request Free Samples
ISO721DG4
ACTIVE
SOIC
D
8
75
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM
Request Free Samples
ISO721DR
ACTIVE
SOIC
D
8
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM
Purchase Samples
ISO721DRG4
ACTIVE
SOIC
D
8
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM
Purchase Samples
ISO721DUB
ACTIVE
SOP
DUB
8
50
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-4-260C-72 HR
Purchase Samples
ISO721DUBR
ACTIVE
SOP
DUB
8
350
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-4-260C-72 HR
Request Free Samples
ISO721MD
ACTIVE
SOIC
D
8
75
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM
Contact TI Distributor
or Sales Office
ISO721MDG4
ACTIVE
SOIC
D
8
75
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM
Contact TI Distributor
or Sales Office
ISO721MDR
ACTIVE
SOIC
D
8
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM
Purchase Samples
ISO721MDRG4
ACTIVE
SOIC
D
8
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM
Purchase Samples
ISO722D
ACTIVE
SOIC
D
8
75
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM
Contact TI Distributor
or Sales Office
ISO722DG4
ACTIVE
SOIC
D
8
75
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM
Contact TI Distributor
or Sales Office
ISO722DR
ACTIVE
SOIC
D
8
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM
Request Free Samples
ISO722DRG4
ACTIVE
SOIC
D
8
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM
Request Free Samples
ISO722MD
ACTIVE
SOIC
D
8
75
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM
Contact TI Distributor
or Sales Office
ISO722MDG4
ACTIVE
SOIC
D
8
75
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM
Contact TI Distributor
or Sales Office
ISO722MDR
ACTIVE
SOIC
D
8
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM
Request Free Samples
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
Orderable Device
ISO722MDRG4
10-Jul-2010
Status
(1)
ACTIVE
Package Type Package
Drawing
SOIC
D
Pins
8
Package Qty
2500
Eco Plan
(2)
Green (RoHS
& no Sb/Br)
Lead/
Ball Finish
MSL Peak Temp
CU NIPDAU Level-1-260C-UNLIM
(3)
Samples
(Requires Login)
Request Free Samples
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF ISO721, ISO721M :
• Automotive: ISO721-Q1
• Enhanced Product: ISO721M-EP
NOTE: Qualified Version Definitions:
• Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects
Addendum-Page 2
PACKAGE OPTION ADDENDUM
www.ti.com
10-Jul-2010
• Enhanced Product - Supports Defense, Aerospace and Medical Applications
Addendum-Page 3
PACKAGE MATERIALS INFORMATION
www.ti.com
27-Oct-2010
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
ISO721DUBR
SOP
DUB
8
350
330.0
24.4
10.9
10.01
5.85
16.0
24.0
Q1
ISO722DR
SOIC
D
8
2500
330.0
12.4
6.4
5.2
2.1
8.0
12.0
Q1
ISO722MDR
SOIC
D
8
2500
330.0
12.4
6.4
5.2
2.1
8.0
12.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
27-Oct-2010
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
ISO721DUBR
SOP
DUB
ISO722DR
SOIC
D
8
350
358.0
335.0
35.0
8
2500
358.0
335.0
35.0
ISO722MDR
SOIC
D
8
2500
358.0
335.0
35.0
Pack Materials-Page 2
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Applications
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amplifier.ti.com
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www.ti.com/audio
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dataconverter.ti.com
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www.ti.com/automotive
DLP® Products
www.dlp.com
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Telecom
www.ti.com/communications
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dsp.ti.com
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www.ti.com/computers
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www.ti.com/clocks
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www.ti.com/consumer-apps
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interface.ti.com
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www.ti.com/energy
Logic
logic.ti.com
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www.ti.com/industrial
Power Mgmt
power.ti.com
Medical
www.ti.com/medical
Microcontrollers
microcontroller.ti.com
Security
www.ti.com/security
RFID
www.ti-rfid.com
Space, Avionics &
Defense
www.ti.com/space-avionics-defense
RF/IF and ZigBee® Solutions www.ti.com/lprf
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www.ti.com/video
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www.ti.com/wireless-apps
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