NCP360 USB Positive Overvoltage Protection Controller with Internal PMOS FET and Status FLAG NCP360 is able to disconnect the systems from its output pin in case wrong VBUS operating conditions is detected. The system is positive over-voltage protected up to +20V. Thanks to this device using internal PMOS FET, no external device is necessary, reducing the system cost and the PCB area of the application board. NCP360 is able to instantaneously disconnect the output from the input if the input voltage exceeds the overvoltage threshold (OVLO). NCP360 provides a negative going flag (FLAG) output, which alerts the system that a fault has occurred. In addition, the device has ESD-protected input (15kV Air) when bypassed with a 1mF or larger capacitor. http://onsemi.com MARKING DIAGRAMS UDFN6 TBD SUFFIX CASE 517AB TSOP-5 TBD SUFFIX CASE 483 5 1 8kV (Contact) 15kV (Air) •ESD Ratings: Machine Model = B ESD Ratings: Human Body Model = 3 •6 Lead UDFN 2x2 mm Package •5 Lead TSOP 3x3 mm Package •These are Pb-Free Devices ZD M G M = Date Code SYAAYWG G 1 Features •Very Fast Protection, Up to 20V, with 25 mA Current Consumption •On-chip PMOS Transistor •Overvoltage Lockout (OVLO) •Undervoltage Lockout (UVLO) •Alert FLAG Output •EN Enable Pin •Thermal Shutdown •Compliance to IEC61000-4-2 (Level 4) 1 A = Assembly Location Y = Year W = Work Week G = Pb-Free Package (Note: Microdot may be in either location) ORDERING INFORMATION Package Shipping† NCP360MUTBG UDFN6 (Pb-Free) 3000/Tape & Reel NCP360MUTXG UDFN6 (Pb-Free) 10000/Tape & Reel NCP360SNT1G TSOP-5 (Pb-Free) 3000/Tape & Reel NCP360SNT3G TSOP-5 (Pb-Free) 10000/Tape & Reel Device Applications †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specification Brochure, BRD8011/D. •USB Devices •Mobile Phones •Peripheral •Personal Digital Applications •MP3 Players Q © Semiconductor Components Industries, LLC, 2007 May, 2007 - Rev. 1 1 Publication Order Number: NCP360/D NCP360 PIN CONNECTIONS EN 1 GND 2 IN 1 5 OUT GND 2 4 OUT EN 3 6 FLAG PAD1 IN 3 5 OUT 4 FLAG TSOP-5 UDFN6 (Top Views) PIN FUNCTION DESCRIPTION (UDFN6 Package) Pin No. Name Type Description 1 EN INPUT 2 GND POWER Ground 3 IN POWER Input Voltage Pin. This pin is connected to the VBUS. A 1 mF low ESR ceramic capacitor, or larger, must be connected between this pin and GND. 4, 5 OUT OUTPUT Output Voltage Pin. The output is disconnected from the VBUS power supply when the input voltage is above OVLO threshold or below UVLO threshold. A 1 mF capacitor must be connected to these pins. The two OUT pins must be hardwired to common supply. 6 FLAG OUTPUT Fault Indication Pin. This pin allows an external system to detect a fault on VBUS pin. The FLAG pin goes low when input voltage exceeds OVLO threshold. Since the FLAG pin is open drain functionality, an external pull up resistor to VCC must be added. - PAD1 POWER Exposed Pad. Can be connected to GND or isolated plane. Must be used to thermal dissipation. Enable Pin. The device enters in shutdown mode when this pin is tied to a high level. In this case the output is disconnected from the input. To allow normal functionality, the EN pin shall be connected to GND to a pull down or to a I/O pin. This pin does not have an impact on the fault detection. PIN FUNCTION DESCRIPTION (TSOP-5 Package) Pin No. Name Type Description 1 IN POWER Input Voltage Pin. This pin is connected to the VBUS. A 1 mF low ESR ceramic capacitor, or larger, must be connected between this pin and GND. 2 GND POWER Ground 3 EN INPUT 4 FLAG OUTPUT Fault Indication Pin. This pin allows an external system to detect a fault on VBUS pin. The FLAG pin goes low when input voltage exceeds OVLO threshold. Since the FLAG pin is open drain functionality, an external pull up resistor to VCC must be added. 5 OUT OUTPUT Output Voltage Pin. The output is disconnected from the VBUS power supply when the input voltage is above OVLO threshold or below UVLO threshold. A 1 mF capacitor must be connected to this pin. Enable Pin. The device enters in shutdown mode when this pin is tied to a high level. In this case the output is disconnected from the input. To allow normal functionality, the EN pin shall be connected to GND to a pull down or to a I/O pin. This pin does not have an impact on the fault detection. http://onsemi.com 2 NCP360 INPUT OUTPUT 3 1 mF 25 V X5R 0603 C1 4 OUT 5 OUT IN C2 NCP360 1 EN FLAG GND FLAG Power 1 mF 25 V X5R 0603 6 FLAG 2 R1 1M J2 2 1 FLAG_State Figure 1. Typical Application Circuit (UDFN Pinout) OUTPUT INPUT (2 out pins in UDFN package) Thermal Shutdown Soft Start EN LDO UVLO OVLO VREF Figure 2. Functional Block Diagram http://onsemi.com 3 FLAGV NCP360 MAXIMUM RATINGS Rating Symbol Value Unit Vminin -0.3 V Vmin -0.3 V Vmaxin 21 V Maximum Voltage (All others to GND) Vmax 7.0 V Maximum Current from Vin to Vout (PMOS) Imax 600 mA RqJA 305 260 °C/W Operating Ambient Temperature Range TA -40 to +85 °C Storage Temperature Range Tstg -65 to +150 °C Junction Operating Temperature TJ 150 °C ESD Withstand Voltage (IEC 61000-4-2) Human Body Model (HBM), Model = 2 (Note 2) Machine Model (MM) Model = B (Note 3) Vesd 15 Air, 8.0 Contact 2000 200 kV V V Moisture Sensitivity MSL Level 1 - Minimum Voltage (IN to GND) Minimum Voltage (All others to GND) Maximum Voltage (IN to GND) Thermal Resistance, Junction-to-Air (Note 1) TSOP-5 UDFN Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. 1. RqJA is highly dependent on the PCB heat sink area (connected to PAD1, UDFN). See PCB Recommendations. 2. Human Body Model, 100 pF discharged through a 1.5 kW resistor following specification JESD22/A114. 3. Machine Model, 200 pF discharged through all pins following specification JESD22/A115. 4. Compliant with JEDEC Latch-up Test, up to maximum voltage range. ELECTRICAL CHARACTERISTICS (Min/Max limits values (-40°C < TA < +85°C) and Vin = +5.0 V. Typical values are TA = +25°C, unless otherwise noted.) Characteristic Input Voltage Range Symbol Undervoltage Lockout Threshold UVLO Uvervoltage Lockout Hysteresis UVLOhyst Overvoltage Lockout Threshold OVLO Overvoltage Lockout Hysteresis OVLOhyst Vin versus Vout Dopout Conditions Vin Min Typ 1.2 Vin falls down UVLO threshold Vin rises up OVLO threshold Max Unit 20 V 2.85 3.0 3.15 V 50 70 90 mV 5.43 5.675 5.9 V 50 100 125 mV Vdrop Vin = 5 V, I charge = 500 mA 105 200 mV Idd No Load, Vin = 5.25 V 24 35 mA Idduvlo Vin = 7 V 50 85 mA Output Off State Current Istd Vin = 5.25 V, EN = 1.2 V 26 37 mA FLAG Output Low Voltage Volflag Vin > OVLO, Sink 1 mA on FLAG pin 400 mV Supply Quiescent Current OVLO Supply Current FLAG Leakage Current FLAGleak FLAG level = 5 V EN Voltage High Vih Vin from 3.3 V to 5.25 V 5.0 EN Voltage Low Vol Vin from 3.3 V to 5.25 V EN Leakage Current ENleak EN = 5.5 V or GND 170 nA 1.2 V 0.4 V nA TIMINGS Start Up Delay ton From Vin > UVLO to Vout = 0.8xVin, See Fig 3 4.0 tstart From Vin > UVLO to FLAG = 1.2 V, See Fig 3 3.0 toff From Vin > OVLO to Vout ≤ 0.3 V, See Fig 4 Vin increasing from 5 V to 8 V at 1V/ms. No output capacitor. 0.8 1.5 ms Alert Delay tstop From Vin > OVLO to FLAG ≤ 0.4 V, See Fig 4 Vin increasing from 5 V to 8 V at 3V/ms 1.0 2.0 ms Disable Time tdis From EN 0.4 to 1.2V to Vout ≤ 0.3 V, See Fig 5 Vin = 4.75 V. No output capacitor. 2.0 ms Tsd 150 °C Tsdhyst 30 °C FLAG going up Delay Output Turn Off Time Thermal Shutdown Temperature Thermal Shutdown Hysteresis NOTE: Thermal Shutdown parameter has been fully characterized and guaranteed by design. http://onsemi.com 4 15 ms ms NCP360 <OVLO UVLO Vin OVLO Vin ton 0.8 Vin Vout toff Vout Vin - RDS(on) x I Vin - (RDS(on) I) 0.3 V tstart FLAG FLAG tstop 1.2 V 0.4 V Figure 3. Start Up Sequence Figure 4. Shutdown on Over Voltage Detection EN 1.2 V EN tdis Vout Vin - RDS(on) x I 1.2 V OVLO Vin 0.3 V UVLO 3 ms FLAG FLAG Figure 5. Disable on EN = 1 Figure 6. FLAG Response with EN = 1 CONDITIONS IN OUT VIN > OVLO or VIN < UVLO Voltage Detection Figure 7. CONDITIONS IN OUT Voltage Detection Figure 8. http://onsemi.com 5 UVLO < VIN < OVLO NCP360 TYPICAL OPERATING CHARACTERISTICS Figure 10. FLAG Going Up Delay Vout = Ch3, FLAG = Ch2 Figure 9. Startup Vin = Ch1, Vout = Ch3 Figure 12. Alert Delay Vout = Ch1, FLAG = Ch3 Figure 11. Output Turn Off Time Vin = Ch1, Vout = Ch2 Figure 14. Thermal Shutdown Vin = Ch1, Vout = Ch2, FLAG = Ch3 Figure 13. Disable Time EN = Ch1, Vout = Ch2, FLAG = Ch3 http://onsemi.com 6 NCP360 TYPICAL OPERATING CHARACTERISTICS 450 400 Vin = 3.6 V RDS(on) (mW) 350 300 250 Vin = 5 V 200 150 100 50 0 -50 0 50 100 TEMPERATURE (°C) IQ, SUPPLY QUIESCENT CURRENT (mA) Figure 15. Direct Output Short Circuit Figure 16. RDS(on) vs. Temperature (Load = 500 mA) 180 160 140 120 100 125°C 80 25°C 60 40 -40 °C 20 0 1 3 5 7 9 11 13 15 17 19 21 Vin, INPUT VOLTAGE (V) Figure 17. Supply Quiescent Current vs. Vin http://onsemi.com 7 150 NCP360 In Operation EN Input NCP360 provides overvoltage protection for positive voltage, up to 20V. A PMOS FET protects the systems (i.e.: VBUS) connected on the Vout pin, against positive over-voltage. The Output follows the VBUS level until OVLO threshold is overtaken. To enable normal operation, the EN pin shall be forced to low or connected to ground. A high level on the pin disconnects OUT pin from IN pin. EN does not overdrive an OVLO or UVLO fault. Undervoltage Lockout (UVLO) NCP360 includes an internal PMOS FET to protect the systems, connected on OUT pin, from positive overvoltage. Regarding electrical characteristics, the RDSon, during normal operation, will create low losses on Vout pin, characterized by Vin versus Vout dropout. (See Figure 16). Internal PMOS FET To ensure proper operation under any conditions, the device has a built-in undervoltage lock out (UVLO) circuit. During Vin positive going slope, the output remains disconnected from input until Vin voltage is above 3.2V nominal. The FLAGV output is pulled to low as long as Vin does not reach UVLO threshold. This circuit has a 50mV hysteresis to provide noise immunity to transient condition. ESD Tests NCP360 fully support the IEC61000-4-2, level 4 (Input pin, 1 mF mounted on board). That means, in Air condition, Vin has a ±15kV ESD protected input. In Contact condition, Vin has ±8kV ESD protected input. Please refer to Fig 19 to see the IEC 61000-4-2 electrostatic discharge waveform. Vin (V) 20 V OVLO UVLO 0 Vout OVLO UVLO 0 Figure 18. Output Characteristic vs. Vin Overvoltage Lockout (OVLO) To protect connected systems on Vout pin from overvoltage, the device has a built-in overvoltage lock out (OVLO) circuit. During overvoltage condition, the output remains disabled until the input voltage exceeds OVLO Hysteresis. FLAG output is tied to low until Vin is higher than OVLO. This circuit has a 100mV hysteresis to provide noise immunity to transient conditions. Figure 19. PCB Recommendations FLAG Output The NCP360 integrates a 500 mA rated PMOS FET, and the PCB rules must be respected to properly evacuate the heat out of the silicon. The UDFN PAD1 must be connected to ground plane to increase the heat transfer if necessary from an application standpoint. Of course, in any case, this pad shall be not connected to any other potential. NCP360 provides a FLAG output, which alerts external systems that a fault has occurred. This pin is tied to low as soon the OVLO threshold is exceeded When Vin level recovers normal condition, FLAG is held high. The pin is an open drain output, thus a pull up resistor (typically 1 MW- Minimum 10 kW) must be provided to Vbattery. FLAG pin is an open drain output. http://onsemi.com 8 NCP360 PACKAGE DIMENSIONS UDFN6 2x2, 0.65P CASE 517AB-01 ISSUE B D NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: MILLIMETERS. 3. COPLANARITY APPLIES TO THE EXPOSED PAD AS WELL AS THE TERMINALS. A B ÍÍÍ ÍÍÍ ÍÍÍ DIM A A1 A3 b D D2 E E2 e K L E PIN ONE REFERENCE 0.10 C 2X 0.10 C 2X MILLIMETERS MIN MAX 0.45 0.55 0.00 0.05 0.127 REF 0.25 0.35 2.00 BSC 1.50 1.70 2.00 BSC 0.80 1.00 0.65 BSC 0.20 --0.25 0.35 A3 SOLDERING FOOTPRINT* 0.10 C 6X A 6X 0.08 C 0.47 0.95 6X A1 C 0.40 1 SEATING PLANE D2 6X e L 4X 1.70 3 1 E2 0.65 PITCH 2.30 6X K 6 4 6X BOTTOM VIEW DIMENSIONS: MILLIMETERS b 0.10 C A B *For additional information on our Pb-Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. 0.05 C http://onsemi.com 9 NCP360 PACKAGE DIMENSIONS TSOP-5 CASE 483-02 ISSUE G NOTE 5 2X 0.10 T 2X 0.20 T NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: MILLIMETERS. 3. MAXIMUM LEAD THICKNESS INCLUDES LEAD FINISH THICKNESS. MINIMUM LEAD THICKNESS IS THE MINIMUM THICKNESS OF BASE MATERIAL. 4. DIMENSIONS A AND B DO NOT INCLUDE MOLD FLASH, PROTRUSIONS, OR GATE BURRS. 5. OPTIONAL CONSTRUCTION: AN ADDITIONAL TRIMMED LEAD IS ALLOWED IN THIS LOCATION. TRIMMED LEAD NOT TO EXTEND MORE THAN 0.2 FROM BODY. D 5X 0.20 C A B M 5 1 4 2 3 B S K L DETAIL Z G A DIM A B C D G H J K L M S DETAIL Z J C 0.05 SEATING PLANE H T MILLIMETERS MIN MAX 3.00 BSC 1.50 BSC 0.90 1.10 0.25 0.50 0.95 BSC 0.01 0.10 0.10 0.26 0.20 0.60 1.25 1.55 0_ 10 _ 2.50 3.00 SOLDERING FOOTPRINT* 0.95 0.037 1.9 0.074 2.4 0.094 1.0 0.039 0.7 0.028 SCALE 10:1 mm Ǔ ǒinches *For additional information on our Pb-Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. 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