ICST ICS843011AG Femtoclocks-tm crystal-to- 3.3v lvpecl clock generator Datasheet

ICS843011
Integrated
Circuit
Systems, Inc.
FEMTOCLOCKS™ CRYSTAL-TO3.3V LVPECL CLOCK GENERATOR
GENERAL DESCRIPTION
FEATURES
The ICS843011 is a Fibre Channel Clock Generator
and a member of the HiPerClocksTM family of high
HiPerClockS™
performance devices from ICS. The ICS843011
uses a 26.5625MHz crystal to synthesize
106.25MHz or a 25MHz crystal to synthesize
100MHz. The ICS843011 has excellent <1ps phase jitter
performance, over the 637KHz – 10MHz integration range. The
ICS843011 is packaged in a small 8-pin TSSOP, making it ideal
for use in systems with limited board space.
• 1 differential 3.3V LVPECL output
ICS
• Crystal oscillator interface designed for 26.5625MHz
18pF parallel resonant crystal
• Output frequency: 106.25MHz or 100MHz
• VCO range: 560MHz - 680MHz
• RMS phase jitter @ 100MHz, using a 25MHz crystal
(637KHz - 10MHz): 0.80ps (typical)
• RMS phase noise at 106.25MHz
Phase noise:
Offset
Noise Power
100Hz ............... -92.8 dBc/Hz
1KHz .............. -119.6 dBc/Hz
10KHz .............. -129.5 dBc/Hz
100KHz .............. -130.5 dBc/Hz
• 3.3V operating supply
• Lead-Free package fully RoHS compliant
• -40°C to 85°C ambient operating temperature
FREQUENCY TABLE
Crystal (MHz)
Output Frequency (MHz)
26.5625
106.25
25
100
BLOCK DIAGRAM
XTAL_IN
OSC
XTAL_OUT
PIN ASSIGNMENT
Phase
Detector
VCO
637.5MHz w/
26.5625MHz Ref.
÷6
nQ0
Q0
1
2
3
4
8
7
6
5
VCC
Q0
nQ0
nc
ICS843011
M = ÷24 (fixed)
843011AG
VCCA
VEE
XTAL_OUT
XTAL_IN
8-Lead TSSOP
4.40mm x 3.0mm x 0.925mm package body
G Package
Top View
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1
REV. B DECEMBER 10, 2004
ICS843011
Integrated
Circuit
Systems, Inc.
FEMTOCLOCKS™ CRYSTAL-TO3.3V LVPECL CLOCK GENERATOR
TABLE 1. PIN DESCRIPTIONS
Number
Name
Type
1
VCCA
Power
Analog supply pin.
2
3,
4
5
V EE
XTAL_OUT,
XTAL_IN
nc
Power
Unused
Negative supply pin.
Crystal oscillator interface. XTAL_IN is the input,
XTAL_OUT is the output.
No connect.
6, 7
nQ0, Q0
Output
Differential clock outputs. LVPECL interface levels.
8
VCC
Power
Core supply pin.
Input
Description
TABLE 2. PIN CHARACTERISTICS
Symbol
Parameter
CIN
Input Capacitance
843011AG
Test Conditions
Minimum
Typical
4
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2
Maximum
Units
pF
REV. B DECEMBER 10, 2004
ICS843011
Integrated
Circuit
Systems, Inc.
FEMTOCLOCKS™ CRYSTAL-TO3.3V LVPECL CLOCK GENERATOR
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, VCC
4.6V
Inputs, VI
-0.5V to VCC + 0.5V
Outputs, IO
Continuous Current
Surge Current
50mA
100mA
Package Thermal Impedance, θJA
101.7°C/W (0 mps)
Storage Temperature, TSTG
-65°C to 150°C
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device. These ratings are stress specifications only. Functional
operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect product reliability.
TABLE 3A. POWER SUPPLY DC CHARACTERISTICS, VCC = 3.3V±5%, TA = -40°C TO 85°C
Symbol
Parameter
VCC
Core Supply Voltage
VCCA
Analog Supply Voltage
ICCA
Analog Supply Current
IEE
Power Supply Current
Test Conditions
Minimum
Typical
Maximum
Units
3.135
3.3
3.465
V
3.135
3.3
3.465
V
12
mA
93
mA
Maximum
Units
included in IEE
TABLE 3B. LVPECL DC CHARACTERISTICS, VCC = 3.3V±5%, TA = -40°C TO 85°C
Symbol
Parameter
Test Conditions
Minimum
Typical
VOH
Output High Voltage; NOTE 1
VCC - 1.4
VCC - 0.9
V
VOL
Output Low Voltage; NOTE 1
VCC - 2.0
VCC - 1.7
V
VSWING
Peak-to-Peak Output Voltage Swing
0.6
1.0
V
Maximum
Units
NOTE 1: Outputs terminated with 50Ω to VCC - 2V.
TABLE 4. CRYSTAL CHARACTERISTICS
Parameter
Test Conditions
Minimum
Mode of Oscillation
Typical
Fundamental
26.5625
MHz
Equivalent Series Resistance (ESR)
Frequency
25
50
Ω
Shunt Capacitance
7
pF
TABLE 5. AC CHARACTERISTICS, VCC = 3.3V±5%, TA = -40°C TO 85°C
Symbol Parameter
FOUT
tjit(Ø)
Test Conditions
Output Frequency
RMS Phase Jitter (Random);
NOTE 1
tR / tF
Output Rise/Fall Time
odc
Output Duty Cycle
Minimum
Typical
93.33
106.25MHz;
Integration Range: 637KHz - 10MHz
100MHz;
Integration Range: 637KHz - 10MHz
20% to 80%
Maximum
Units
113.33
MHz
0.80
ps
0.80
ps
300
600
ps
48
52
%
NOTE 1: Please refer to the Phase Noise Plot.
843011AG
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3
REV. B DECEMBER 10, 2004
ICS843011
Integrated
Circuit
Systems, Inc.
FEMTOCLOCKS™ CRYSTAL-TO3.3V LVPECL CLOCK GENERATOR
TYPICAL PHASE NOISE AT 100MHZ
➤
0
-10
Filter
-20
-30
-40
100MHz
-50
RMS Phase Noise Jitter
637K to 10MHz = 0.80ps (typical)
-70
-80
-90
Raw Phase Noise Data
-100
-110
➤
NOISE POWER dBc
Hz
-60
-120
-130
-140
-150
➤
-160
-170
Phase Noise Result by adding
a Filter to raw data
-180
-190
100
1k
10k
100k
1M
10M
100M
OFFSET FREQUENCY (HZ)
TYPICAL PHASE NOISE AT 106.25MHZ
➤
0
-10
-20
Fibre Channel Filter
-30
-40
106.25MHz
-50
RMS Phase Noise Jitter
637K to 10MHz = 0.80ps (typical)
-70
-80
-90
Raw Phase Noise Data
-100
-110
➤
NOISE POWER dBc
Hz
-60
-120
-130
-140
-150
➤
-160
-170
Phase Noise Result by adding
Fibre Channel Filter to raw data
-180
-190
100
1k
10k
100k
1M
10M
100M
OFFSET FREQUENCY (HZ)
843011AG
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4
REV. B DECEMBER 10, 2004
ICS843011
Integrated
Circuit
Systems, Inc.
FEMTOCLOCKS™ CRYSTAL-TO3.3V LVPECL CLOCK GENERATOR
PARAMETER MEASUREMENT INFORMATION
2V
Phase Noise Plot
Qx
SCOPE
Noise Power
V CC
LVPECL
Phase Noise Mask
nQx
VEE
f1
-1.3V ± 0.165V
Offset Frequency
f2
RMS Jitter = Area Under the Masked Phase Noise Plot
3.3V OUTPUT LOAD AC TEST CIRCUIT
RMS PHASE JITTER
nQ0
80%
Q0
80%
VSW I N G
Pulse Width
t
odc =
Clock
Outputs
PERIOD
20%
20%
t PW
tR
tF
t PERIOD
OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD
843011AG
OUTPUT RISE/FALL TIME
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5
REV. B DECEMBER 10, 2004
ICS843011
Integrated
Circuit
Systems, Inc.
FEMTOCLOCKS™ CRYSTAL-TO3.3V LVPECL CLOCK GENERATOR
APPLICATION INFORMATION
POWER SUPPLY FILTERING TECHNIQUES
As in any high speed analog circuitry, the power supply pins
are vulnerable to random noise. The ICS843011 provides separate power supplies to isolate any high switching
noise from the outputs to the internal PLL. VCC, and VCCA should
be individually connected to the power supply
plane through vias, and bypass capacitors should be
used for each pin. To achieve optimum jitter performance,
power supply isolation is required. Figure 1 illustrates how
a 10Ω resistor along with a 10µF and a .01µF bypass
capacitor should be connected to each VCCA pin.
3.3V
VCC
.01µF
10Ω
V CCA
.01µF
10µF
FIGURE 1. POWER SUPPLY FILTERING
CRYSTAL INPUT INTERFACE
allel resonant crystal and were chosen to minimize the ppm error. The optimum C1 and C2 values can be slightly adjusted for
different board layouts.
The ICS843011 has been characterized with 18pF parallel
resonant crystals. The capacitor values, C1 and C2, shown in
Figure 2 below were determined using a 26.5625MHz, 18pF par-
XTAL_OUT
C1
33p
X1
18pF Parallel Crystal
XTAL_IN
C2
22p
Figure 2. CRYSTAL INPUt INTERFACE
843011AG
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6
REV. B DECEMBER 10, 2004
ICS843011
Integrated
Circuit
Systems, Inc.
FEMTOCLOCKS™ CRYSTAL-TO3.3V LVPECL CLOCK GENERATOR
APPLICATION SCHEMATIC
Figure 3A shows a schematic example of the ICS843011. An
example of LVEPCL termination is shown in this schematic.
Additional LVPECL termination approaches are shown in the
LVPECL Termination Application Note. In this example, an 18 pF
parallel resonant 26.5625MHz crystal is used for generating
VCC
106.25MHz output frequency. The C1 = 27pF and C2 = 33pF
are recommended for frequency accuracy. For different board
layout, the C1 and C2 values may be slightly adjusted for optimizing frequency accuracy.
VCCA
VCC
R2
10
C3
10uF
C4
0.01u
R3
133
R5
133
Zo = 50 Ohm
U1
Q
1
2
3
4
C2
33pF
18pF
VCCA
VEE
XTAL_OUT
XTAL_IN
VCC
Q0
nQ0
NC
8
7
6
5
VCC
+
Zo = 50 Ohm
nQ
X1
-
ICS843011
R4
82.5
C5
0.1u
C1
22pF
R6
82.5
VCC=3.3V
FIGURE 3A. ICS843011 SCHEMATIC EXAMPLE
PC BOARD LAYOUT EXAMPLE
Figure 3B shows an example of ICS843011 P.C. board layout.
The crystal X1 footprint shown in this example allows installation of either surface mount HC49S or through-hole HC49 package. The footprints of other components in this example are listed
in the Table 6. There should be at least one decoupling capacitor
per power pin. The decoupling capacitors should be located as
close as possible to the power pins. The layout assumes that
the board has clean analog power ground plane.
TABLE 6. FOOTPRINT TABLE
Reference
Size
C1, C2
0402
C3
0805
C4, C5
0603
R2
0603
NOTE: Table 6, lists component
sizes shown in this layout example.
FIGURE 3B. ICS843011 PC BOARD LAYOUT EXAMPLE
843011AG
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REV. B DECEMBER 10, 2004
ICS843011
Integrated
Circuit
Systems, Inc.
FEMTOCLOCKS™ CRYSTAL-TO3.3V LVPECL CLOCK GENERATOR
POWER CONSIDERATIONS
This section provides information on power dissipation and junction temperature for the ICS843011.
Equations and example calculations are also provided.
1. Power Dissipation.
The total power dissipation for the ICS843011 is the sum of the core power plus the power dissipated in the load(s).
The following is the power dissipation for VCC = 3.3V + 5% = 3.465V, which gives worst case results.
NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.
•
•
Power (core)MAX = VCC_MAX * IEE_MAX = 3.465V * 93mA = 322.2mW
Power (outputs)MAX = 30mW/Loaded Output pair
Total Power_MAX (3.465V, with all outputs switching) = 322.2mW + 30mW = 352.2mW
2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the
device. The maximum recommended junction temperature for HiPerClockSTM devices is 125°C.
The equation for Tj is as follows: Tj = θJA * Pd_total + TA
Tj = Junction Temperature
θJA = Junction-to-Ambient Thermal Resistance
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)
TA = Ambient Temperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA must be used. Assuming a
moderate air flow of 1 meter per second and a multi-layer board, the appropriate value is 90.5°C/W per Table 6 below.
Therefore, Tj for an ambient temperature of 85°C with all outputs switching is:
85°C + 0.352W * 90.5°C/W = 116.9°C. This is below the limit of 125°C.
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow,
and the type of board (single layer or multi-layer).
TABLE 6. THERMAL RESISTANCE θJA
FOR
8-PIN TSSOP, FORCED CONVECTION
θJA by Velocity (Meters per Second)
Multi-Layer PCB, JEDEC Standard Test Boards
843011AG
0
1
2.5
101.7°C/W
90.5°C/W
89.8°C/W
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8
REV. B DECEMBER 10, 2004
ICS843011
Integrated
Circuit
Systems, Inc.
FEMTOCLOCKS™ CRYSTAL-TO3.3V LVPECL CLOCK GENERATOR
3. Calculations and Equations.
The purpose of this section is to derive the power dissipated into the load.
LVPECL output driver circuit and termination are shown in Figure 4.
VCC
Q1
VOUT
RL
50
VCC - 2V
FIGURE 4. LVPECL DRIVER CIRCUIT
AND
TERMINATION
To calculate worst case power dissipation into the load, use the following equations which assume a 50Ω load, and a termination
voltage of V - 2V.
CC
•
For logic high, VOUT = V
OH_MAX
(V
CCO_MAX
•
-V
OH_MAX
OL_MAX
CCO_MAX
-V
CC_MAX
– 0.9V
) = 0.9V
For logic low, VOUT = V
(V
=V
=V
CC_MAX
– 1.7V
) = 1.7V
OL_MAX
Pd_H is power dissipation when the output drives high.
Pd_L is the power dissipation when the output drives low.
Pd_H = [(V
OH_MAX
– (V
CC_MAX
- 2V))/R ] * (V
CC_MAX
L
-V
OH_MAX
) = [(2V - (V
CC_MAX
-V
OH_MAX
))/R ] * (V
CC_MAX
L
-V
OH_MAX
)=
[(2V - 0.9V)/50Ω] * 0.9V = 19.8mW
Pd_L = [(V
OL_MAX
– (V
CC_MAX
- 2V))/R ] * (V
L
CC_MAX
-V
OL_MAX
) = [(2V - (V
CC_MAX
-V
OL_MAX
))/R ] * (V
L
CC_MAX
-V
OL_MAX
)=
[(2V - 1.7V)/50Ω] * 1.7V = 10.2mW
Total Power Dissipation per output pair = Pd_H + Pd_L = 30mW
843011AG
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9
REV. B DECEMBER 10, 2004
ICS843011
Integrated
Circuit
Systems, Inc.
FEMTOCLOCKS™ CRYSTAL-TO3.3V LVPECL CLOCK GENERATOR
RELIABILITY INFORMATION
TABLE 7. θJAVS. AIR FLOW TABLE
FOR
8 LEAD TSSOP
θJA by Velocity (Meters per Second)
Multi-Layer PCB, JEDEC Standard Test Boards
0
1
2.5
101.7°C/W
90.5°C/W
89.8°C/W
TRANSISTOR COUNT
The transistor count for ICS843011 is: 2436
843011AG
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10
REV. B DECEMBER 10, 2004
ICS843011
Integrated
Circuit
Systems, Inc.
PACKAGE OUTLINE - G SUFFIX
FOR
FEMTOCLOCKS™ CRYSTAL-TO3.3V LVPECL CLOCK GENERATOR
8 LEAD TSSOP
TABLE 8. PACKAGE DIMENSIONS
SYMBOL
Millimeters
Minimum
N
A
Maximum
8
--
1.20
A1
0.05
0.15
A2
0.80
1.05
b
0.19
0.30
c
0.09
0.20
D
2.90
3.10
E
E1
6.40 BASIC
4.30
e
4.50
0.65 BASIC
L
0.45
0.75
α
0°
8°
aaa
--
0.10
Reference Document: JEDEC Publication 95, MO-153
843011AG
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11
REV. B DECEMBER 10, 2004
ICS843011
Integrated
Circuit
Systems, Inc.
FEMTOCLOCKS™ CRYSTAL-TO3.3V LVPECL CLOCK GENERATOR
TABLE 9. ORDERING INFORMATION
Part/Order Number
Marking
Package
Count
Temperature
ICS843011AG
3011A
8 lead TSSOP
100 per tube
-40°C to 85°C
ICS843011AGT
3011A
8 lead TSSOP on Tape and Reel
2500
-40°C to 85°C
ICS843011AGLF
011AL
8 lead "Lead-Free" TSSOP
100 per tube
-40°C to 85°C
ICS843011AGLFT
011AL
8 lead "Lead-Free" TSSOP on Tape and Reel
2500
-40°C to 85°C
The aforementioned trademarks, HiPerClockS™ and FemtoClocks™ are a trademark of Integrated Circuit Systems, Inc. or its subsidiaries in the United States and/or other countries.
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use
or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use
in normal commercial and industrial applications. Any other applications such as those requiring ehigh reliability or other extraordinary environmental requirements are not
recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product
for use in life support devices or critical medical instruments.
843011AG
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12
REV. B DECEMBER 10, 2004
ICS843011
Integrated
Circuit
Systems, Inc.
FEMTOCLOCKS™ CRYSTAL-TO3.3V LVPECL CLOCK GENERATOR
REVISION HISTORY SHEET
Rev
Table
Page
Description of Change
Date
B
3A
3
Power Supply DC Characteristics Table - added ICCA spec.
8/23/04
B
T9
12
10/13/04
B
T9
12
Ordering Information Table - corrected count from 154 to 100.
Ordering Information Table - corrected Lead-Free marking from 3011AL to
011AL.
Changed ambient operating temperature bullet from -30°C to 85°C to
-40°C to 85°C and throughout data sheet.
Cr ystal Input Interface - changed capacitor C2 value from 27p to 22p.
Application Schematic - corrected schematic to reflect Cr ystal Input Interface
change.
1
B
843011AG
6
7
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13
10/20/04
12/10/04
REV. B DECEMBER 10, 2004
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