LINER LT5527 Dual 12-bit 310msps adc Datasheet

LTC2158-12
Dual 12-Bit 310Msps ADC
FEATURES
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DESCRIPTION
The LTC®2158-12 is a 2-channel simultaneous sampling
310Msps 12-bit A/D converter designed for digitizing high
frequency, wide dynamic range signals. It is perfect for
demanding communications applications with AC performance that includes 67.6dB SNR and 88dB spurious
free dynamic range (SFDR). The 1.25GHz input bandwidth
allows the ADC to undersample high frequencies with
good performance. The latency is only six clock cycles.
67.6dBFS SNR
88dB SFDR
Low Power: 688mW Total
Single 1.8V Supply
DDR LVDS Outputs
1.32VP-P Input Range
1.25GHz Full Power Bandwidth S/H
Optional Clock Duty Cycle Stabilizer
Low Power Sleep and Nap Modes
Serial SPI Port for Configuration
Pin-Compatible 14-Bit Versions
64-Lead (9mm × 9mm) QFN Package
DC specs include ±0.6LSB INL (typ), ±0.1LSB DNL (typ)
and no missing codes over temperature. The transition
noise is 0.6LSBRMS.
The digital outputs are double data rate (DDR) LVDS.
APPLICATIONS
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The ENC+ and ENC– inputs can be driven differentially with
a sine wave, PECL, LVDS, TTL, or CMOS inputs. An optional
clock duty cycle stabilizer allows high performance at full
speed for a wide range of clock duty cycles.
Communications
Cellular Basestations
Software Defined Radios
Medical Imaging
High Definition Video
Testing and Measurement Instruments
L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear
Technology Corporation. All other trademarks are the property of their respective owners.
TYPICAL APPLICATION
LTC2158-12 32K Point 2-Tone FFT,
fIN = 71MHz and 69MHz, 310Msps
VDD
OVDD
ANALOG
INPUT
CLOCK
S/H
CLOCK/DUTY
CYCLE
CONTROL
12-BIT
PIPELINED
ADC CORE
CORRECTION
LOGIC
DA10_11
•
•
•
DA0_1
OUTPUT
DRIVERS
0
OGND
OVDD
CHANNEL B
–20
DDR
LVDS
AMPLITUDE (dBFS)
CHANNEL A
–40
–60
–80
–100
ANALOG
INPUT
S/H
12-BIT
PIPELINED
ADC CORE
CORRECTION
LOGIC
DB10_11
•
•
•
DB0_1
OUTPUT
DRIVERS
DDR
LVDS
–120
0
20
40
60 80 100 120 140
FREQUENCY (MHz)
215812 TA10b
GND
215812 TA01
OGND
215812fa
For more information www.linear.com/LTC2158-12
1
LTC2158-12
ABSOLUTE MAXIMUM RATINGS
PIN CONFIGURATION
(Notes 1, 2)
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
VDD
PAR/SER
CS
SCK
SDI
SDO
GND
DA10_11+
DA10_11–
DA8_9+
DA8_9–
DA6_7+
DA6_7–
DA4_5+
DA4_5 –
OVDD
TOP VIEW
VDD 1
VDD 2
GND 3
AINA+ 4
AINA– 5
GND 6
SENSE 7
VREF 8
GND 9
VCM 10
GND 11
AINB– 12
AINB+ 13
GND 14
VDD 15
VDD 16
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
65
GND
OGND
DA2_3+
DA2_3–
DA0_1+
DA0_1–
NC
NC
CLKOUT+
CLKOUT–
DB10_11+
DB10_11–
DB8_9+
DB8_9–
DB6_7+
DB6_7–
OGND
VDD
GND
ENC+
ENC–
GND
OF –
OF +
NC
NC
DB0_1–
DB0_1+
DB2_3–
DB2_3+
DB4_5 –
DB4_5+
OVDD
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
Supply Voltage
VDD, OVDD................................................. –0.3V to 2V
Analog Input Voltage
AINA/B+, AINA/B –, PAR/SER,
SENSE (Note 3)......................... –0.3V to (VDD + 0.2V)
Digital Input Voltage
ENC+, ENC– (Note 3)................. –0.3V to (VDD + 0.3V)
CS, SDI, SCK (Note 4)............................ –0.3V to 3.9V
SDO (Note 4).............................................. –0.3V to 3.9V
Digital Output Voltage................. –0.3V to (OVDD + 0.3V)
Operating Temperature Range
LTC2158C................................................. 0°C to 70°C
LTC2158I..............................................–40°C to 85°C
Storage Temperature Range................... –65°C to 150°C
UP PACKAGE
64-LEAD (9mm × 9mm) PLASTIC QFN
TJMAX = 150°C, θJA = 29°C/W
EXPOSED PAD (PIN 65) IS GND, MUST BE SOLDERED TO PCB
ORDER INFORMATION
LEAD FREE FINISH
TAPE AND REEL
PART MARKING*
PACKAGE DESCRIPTION
TEMPERATURE RANGE
LTC2158CUP-12#PBF
LTC2158CUP-12#TRPBF
LTC2158UP-12
64-Lead (9mm × 9mm) Plastic QFN
0°C to 70°C
LTC2158IUP-12#PBF
LTC2158IUP-12#TRPBF
LTC2158UP-12
64-Lead (9mm × 9mm) Plastic QFN
–40°C to 85°C
Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/
2
215812fa
For more information www.linear.com/LTC2158-12
LTC2158-12
CONVERTER CHARACTERISTICS The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. (Note 5)
PARAMETER
CONDITIONS
MIN
Resolution (No Missing Codes)
l
TYP
MAX
UNITS
12
Bits
Integral Linearity Error
Differential Analog Input (Note 6)
l
–2.2
±0.6
2.2
LSB
Differential Linearity Error
Differential Analog Input
l
–0.67
±0.1
0.67
LSB
Offset Error
(Note 7)
l
–12
±5
12
mV
Gain Error
Internal Reference
External Reference
l
–4.7
±1.5
±1
4.2
%FS
%FS
Offset Drift
Full-Scale Drift
Internal Reference
External Reference
Transition Noise
±20
µV/°C
±30
±10
ppm/°C
ppm/°C
0.6
LSBRMS
ANALOG INPUT
The l denotes the specifications which apply over the full operating temperature range, otherwise
specifications are at TA = 25°C. (Note 5)
SYMBOL PARAMETER
CONDITIONS
VIN
Analog Input Range (AIN+ – AIN–)
1.74V < VDD < 1.9V
VIN(CM)
Analog Input Common Mode (AIN+ + AIN–)/2
Differential Analog Input (Note 8)
VSENSE
External Voltage Reference Applied to SENSE External Reference Mode
MIN
TYP
MAX
UNITS
1.32
VP-P
l
VCM – 20mV
VCM
VCM + 20mV
V
l
1.230
1.250
1.270
V
l
–1
1
µA
IIN1
Analog Input Leakage Current
0 < AIN+, AIN– < VDD, No Encode
IIN2
PAR/SER Input Leakage Current
0 < PAR/SER < VDD
l
–1
1
µA
IIN3
SENSE Input Leakage Current
1.23V < SENSE < 1.27V
l
–1
1
µA
tAP
Sample-and-Hold Acquisition Delay Time
1
tJITTER
Sample-and-Hold Acquisition Delay Jitter
0.15
CMRR
Analog Input Common Mode Rejection Ratio
BW-3B
Full-Power Bandwidth
ns
psRMS
75
dB
1250
MHz
DYNAMIC ACCURACY
The l denotes the specifications which apply over the full operating temperature range,
otherwise specifications are at TA = 25°C. AIN = –1dBFS. (Note 5)
SYMBOL
PARAMETER
CONDITIONS
SNR
Signal-to-Noise Ratio
15MHz Input
70MHz Input
140MHz Input
SFDR
S/(N+D)
Spurious Free Dynamic Range 2nd or 3rd
Harmonic
15MHz Input
70MHz Input
140MHz Input
Spurious Free Dynamic Range 4th Harmonic
or Higher
15MHz Input
70MHz Input
140MHz Input
Signal-to-Noise Plus Distortion Ratio
Crosstalk Crosstalk Between Channels
15MHz Input
70MHz Input
140MHz Input
Up to 315MHz Input
l
l
l
l
MIN
TYP
64.4
67.6
67.1
67.0
MAX
UNITS
dBFS
dBFS
dBFS
70
88
85
80
dBFS
dBFS
dBFS
80
98
95
90
dBFS
dBFS
dBFS
64.3
67.1
67.0
66.9
dBFS
dBFS
dBFS
–95
dB
215812fa
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3
LTC2158-12
INTERNAL REFERENCE CHARACTERISTICS
The l denotes the specifications which apply over the
full operating temperature range, otherwise specifications are at TA = 25°C. (Note 5)
PARAMETER
CONDITIONS
VCM Output Voltage
IOUT = 0
MIN
TYP
MAX
0.435 •
VDD – 18mV
0.435 •
VDD
0.435 •
VDD + 18mV
VCM Output Temperature Drift
UNITS
±37
VCM Output Resistance
–1mA < IOUT < 1mA
VREF Output Voltage
IOUT = 0
V
ppm/°C
4
1.225
Ω
1.250
VREF Output Temperature Drift
1.275
V
±30
VREF Output Resistance
–400µA < IOUT < 1mA
7
VREF Line Regulation
1.71V < VDD < 1.89V
0.6
ppm/°C
Ω
mV/V
POWER REQUIREMENTS
The l denotes the specifications which apply over the full operating temperature
range, otherwise specifications are at TA = 25°C. (Note 5)
SYMBOL PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
VDD
Analog Supply Voltage
(Note 9)
l
1.74
1.8
1.9
V
OVDD
Output Supply Voltage
(Note 9)
l
1.74
1.8
1.9
V
IVDD
Analog Supply Current
l
340
370
mA
IOVDD
Digital Supply Current
1.75mA LVDS Mode
3.5mA LVDS Mode
l
l
42
70
50
81
mA
mA
PDISS
Power Dissipation
1.75mA LVDS Mode
3.5mA LVDS Mode
l
l
688
738
756
812
mW
mW
PSLEEP
Sleep Mode Power
Clock Disabled
Clocked at fS(MAX)
<5
<5
mW
mW
PNAP
Nap Mode Power
Clocked at fS(MAX)
190
mW
DIGITAL INPUTS AND OUTPUTS
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. (Note 5)
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
ENCODE INPUTS (ENC+, ENC– )
VID
Differential Input Voltage
(Note 8)
VICM
Common Mode Input Voltage
Internally Set
Externally Set (Note 8)
l
l
0.2
1.1
V
1.2
1.5
V
V
RIN
Input Resistance
(See Figure 2)
10
kΩ
CIN
Input Capacitance
(Note 8)
2
pF
DIGITAL INPUTS (CS, SDI, SCK)
VIH
High Level Input Voltage
VDD = 1.8V
l
VIL
Low Level Input Voltage
VDD = 1.8V
l
IIN
Input Current
VIN = 0V to 3.6V
l
CIN
Input Capacitance
(Note 8)
1.3
V
–10
0.6
V
10
µA
3
pF
200
Ω
SDO OUTPUT (Open-Drain Output. Requires 2k Pull-Up Resistor if SDO Is Used)
ROL
Logic Low Output Resistance to GND
VDD = 1.8V, SDO = 0V
IOH
Logic High Output Leakage Current
SDO = 0V to 3.6V
COUT
Output Capacitance
(Note 8)
4
l
–10
10
4
µA
pF
215812fa
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LTC2158-12
DIGITAL INPUTS AND OUTPUTS
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. (Note 5)
SYMBOL PARAMETER
DIGITAL DATA OUTPUTS
VOD
Differential Output Voltage
VOS
Common Mode Output Voltage
RTERM
On-Chip Termination Resistance
CONDITIONS
100Ω Differential Load, 3.5mA Mode
100Ω Differential Load, 1.75mA Mode
100Ω Differential Load, 3.5mA Mode
100Ω Differential Load, 1.75mA Mode
Termination Enabled, OVDD = 1.8V
l
l
l
l
MIN
TYP
MAX
UNITS
247
125
1.125
1.125
350
175
1.250
1.250
100
454
250
1.375
1.375
mV
mV
V
V
Ω
TIMING CHARACTERISTICS
The l denotes the specifications which apply over the full operating temperature
range, otherwise specifications are at TA = 25°C. (Note 5)
SYMBOL
PARAMETER
CONDITIONS
MIN
fS
Sampling Frequency
(Note 9)
l
10
tL
ENC Low Time (Note 8)
Duty Cycle Stabilizer Off
Duty Cycle Stabilizer On
l
l
1.5
1.2
tH
ENC High Time (Note 8)
Duty Cycle Stabilizer Off
Duty Cycle Stabilizer On
l
l
1.5
1.2
TYP
MAX
UNITS
310
MHz
1.6
1.6
50
50
ns
ns
1.6
1.6
50
50
ns
ns
DIGITAL DATA OUTPUTS
tD
ENC to Data Delay
CL = 5pF (Note 8)
l
1.7
2
2.3
ns
tC
ENC to CLKOUT Delay
CL = 5pF (Note 8)
l
1.3
1.6
2
ns
tSKEW
DATA to CLKOUT Skew
tD – tC (Note 8)
l
0.3
0.4
0.55
Pipeline Latency
6
6
ns
Cycles
SPI Port Timing (Note 8)
tSCK
SCK Period
tS
tH
Write Mode
Readback Mode CSDO= 20pF, RPULLUP = 2k
l
l
40
250
ns
ns
CS to SCK Set-Up Time
l
5
ns
SCK to CS Hold Time
l
5
ns
tDS
SDI Set-Up Time
l
5
ns
tDH
SDI Hold Time
l
5
tDO
SCK Falling to SDO Valid
Readback Mode, CSDO = 20pF, RPULLUP = 2k
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: All voltage values are with respect to GND with GND and OGND
shorted (unless otherwise noted).
Note 3: When these pin voltages are taken below GND or above VDD, they
will be clamped by internal diodes. This product can handle input currents
of greater than 100mA below GND or above VDD without latchup.
Note 4: When these pin voltages are taken below GND they will be
clamped by internal diodes. When these pin voltages are taken above VDD
they will not be clamped by internal diodes. This product can handle input
currents of greater than 100mA below GND without latchup.
l
ns
125
ns
Note 5: VDD = OVDD = 1.8V, fSAMPLE = 310MHz, differential ENC+/ENC– =
2VP-P sine wave, input range = 1.32VP-P with differential drive, unless
otherwise noted.
Note 6: Integral nonlinearity is defined as the deviation of a code from a
best fit straight line to the transfer curve. The deviation is measured from
the center of the quantization band.
Note 7: Offset error is the offset voltage measured from –0.5LSB when the
output code flickers between 0000 0000 0000 and 1111 1111 1111 in 2’s
complement output mode.
Note 8: Guaranteed by design, not subject to test.
Note 9: Recommended operating conditions.
215812fa
For more information www.linear.com/LTC2158-12
5
LTC2158-12
TYPICAL PERFORMANCE CHARACTERISTICS
LTC2158-12: Integral Nonlinearity
(INL)
LTC2158-12: Differential
Nonlinearity (DNL)
LTC2158-12: 32K Point FFT,
fIN = 15MHz, –1dBFS, 310Msps
0.50
2.0
0
1.5
–20
DNL ERROR (LSB)
INL ERROR (LSB)
0.5
0
–0.5
AMPLITUDE (dBFS)
0.25
1.0
0
0
4095
OUTPUT CODE
–0.50
4095
0
OUTPUT CODE
215812 G01
–120
–20
–20
–40
–60
–80
–100
–100
–120
AMPLITUDE (dBFS)
–20
AMPLITUDE (dBFS)
0
–80
0
20
40
60 80 100 120 140
FREQUENCY (MHz)
–120
0
20
40
–20
–20
–80
0
20
40
60 80 100 120 140
FREQUENCY (MHz)
215812 G07
6
–60
–80
–120
0
20
40
LTC2158-12: 32K Point FFT,
fIN = 421MHz, –1dBFS, 310Msps
0
–20
–40
–60
–80
–120
60 80 100 120 140
FREQUENCY (MHz)
215812 G06
LTC2158-12: 32K Point FFT,
fIN = 383MHz, –1dBFS, 310Msps
–100
–100
–120
60 80 100 120 140
FREQUENCY (MHz)
AMPLITUDE (dBFS)
0
AMPLITUDE (dBFS)
0
–60
–40
215812 G05
LTC2158-12: 32K Point FFT,
fIN = 223MHz, –1dBFS, 310Msps
60 80 100 120 140
FREQUENCY (MHz)
–100
215812 G04
–40
40
LTC2158-12: 32K Point FFT,
fIN = 185MHz, –1dBFS, 310Msps
0
–60
20
215812 G03
0
–40
0
215812 G02
LTC2158-12: 32K Point FFT,
fIN = 150MHz, –1dBFS, 310Msps
LTC2158-12: 32K Point FFT,
fIN = 70MHz, –1dBFS, 310Msps
AMPLITUDE (dBFS)
–80
–100
–1.5
AMPLITUDE (dBFS)
–60
–0.25
–1.0
–2.0
–40
–40
–60
–80
–100
0
20
40
60 80 100 120 140
FREQUENCY (MHz)
215812 G08
–120
0
20
40
60 80 100 120 140
FREQUENCY (MHz)
215812 G09
215812fa
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LTC2158-12
TYPICAL PERFORMANCE CHARACTERISTICS
0
–60
–80
–100
–40
–60
–80
–100
0
20
40
–120
60 80 100 120 140
FREQUENCY (MHz)
0
20
40
SFDR (dBFS)
2056
2060
OUTPUT CODE
60
dBc
2064
215812 G13
0
–90 –80 –70 –60 –50 –40 –30 –20 –10
AMPLITUDE (dBFS)
0
215812 G14
75
90
80
70
70
65
SNR (dBFS)
60
50
40
30
40
60 80 100 120 140
FREQUENCY (MHz)
215812 G12
LTC2158-12: SNR vs Input Level,
fIN = 70MHz, 1.32V Range,
310Msps
dBFS
50
40
dBc
30
20
10
LTC2158-12: SFDR vs Input
Frequency, –1dBFS, 1.32V Range,
310Msps
SFDR (dBFS)
COUNT
80
20
2000
20
60
dBFS
40
4000
0
70
100
14000
0
2052
–120
60 80 100 120 140
FREQUENCY (MHz)
120
16000
6000
–80
LTC2158-12: SFDR vs Input Level,
fIN = 70MHz, 1.32V Range, 310Msps
LTC2158-12: Shorted Input Histogram
8000
–60
215812 G11
18000
10000
–40
–100
215812 G10
12000
LTC2158-12: 32K Point 2-Tone FFT,
fIN = 71MHz and 69MHz, 310Msps
–20
AMPLITUDE (dBFS)
–40
–120
0
–20
AMPLITUDE (dBFS)
AMPLITUDE (dBFS)
–20
LTC2158-12: 32K Point FFT,
fIN = 907MHz, –1dBFS, 310Msps
SNR (dBc AND dBFS)
0
LTC2158-12: 32K Point FFT,
fIN = 567MHz, –1dBFS, 310Msps
0
–70
–60
–50 –40 –30 –20
INPUT LEVEL (dBFS)
–10
0
215812 G15
LTC2158-12: SNR vs Input
Frequency, –1dBFS, 1.32V Range,
310Msps
60
55
50
20
45
10
0
0 100 200 300 400 500 600 700 800 900 1000
INPUT FREQUENCY (MHz)
215812 G16
40
0 100 200 300 400 500 600 700 800 900 1000
INPUT FREQUENCY (MHz)
215812 G17
215812fa
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7
LTC2158-12
TYPICAL PERFORMANCE CHARACTERISTICS
–0.5
–1.0
340
LVDS CURRENT
3.5mA
320
60
IVDD (mA)
IOVDD (mA)
70
50
300
280
LVDS CURRENT
1.75mA
40
260
50
100 150 200 250
SAMPLE RATE (Msps)
300
215812 G18
240
–1.5
–2.0
–2.5
–3.0
–3.5
–4.0
30
0
LTC2158-12: Frequency Response
360
INPUT AMPLITUDE (dBFS)
80
LTC2158-12: IVDD vs Sample Rate,
15MHz Sine Wave Input, –1dBFS
LTC2158-12: IVDD vs Sample Rate,
15MHz Sine Wave Input, –1dBFS
0
62
186
124
248
SAMPLE RATE (Msps)
310
215812 G19
–4.5
100
1000
INPUT FREQUENCY (MHz)
215812 G20
PIN FUNCTIONS
VDD (Pins 1, 2, 15, 16, 17, 64): 1.8V Analog Power Supply.
Bypass to ground with 0.1µF ceramic capacitors. Pins 1,
2, 64 can share a bypass capacitor. Pins 15, 16, 17 can
share a bypass capacitor.
GND (Pins 3, 6, 9, 11, 14, 18, 21, 58, Exposed Pad
Pin 65): ADC Power Ground. The exposed pad must be
soldered to the PCB ground.
+
AINA (Pin 4): Positive Differential Analog Input for
Channel A.
AINA– (Pin 5): Negative Differential Analog Input for
Channel A.
SENSE (Pin 7): Reference Programming Pin. Connecting SENSE to VDD selects the internal reference and a
±0.66V input range. An external reference between 1.230V
and 1.270V applied to SENSE selects an input range of
±0.528 • VSENSE.
VREF (Pin 8): Reference Voltage Output. Bypass to ground
with a 2.2µF ceramic capacitor. Nominally 1.25V.
VCM (Pin 10): Common Mode Bias Output; nominally
equal to 0.435 • VDD. VCM should be used to bias the
common mode of the analog inputs. Bypass to ground
with a 0.1µF ceramic capacitor.
8
AINB– (Pin 12): Negative Differential Analog Input for
Channel B.
AINB+ (Pin 13): Positive Differential Analog Input for
Channel B.
ENC+ (Pin 19): Encode Input. Conversion starts on the
rising edge.
ENC– (Pin 20): Encode Complement Input. Conversion
starts on the falling edge.
NC (Pins 24, 25, 42, 43): Not Connected.
OGND (Pins 33, 48): Output Driver Ground.
OVDD (Pins 32, 49): 1.8V Output Driver Supply. Bypass
each pin to ground with separate 0.1µF ceramic capacitors.
SDO (Pin 59): Serial Interface Data Output. In serial
programming mode, (PAR/SER = 0V), SDO is the optional
serial interface data output. Data on SDO is read back from
the mode control registers and can be latched on the falling
edge of SCK. SDO is an open-drain N-channel MOSFET
output that requires an external 2k pull-up resistor from
1.8V to 3.3V. If readback from the mode control registers
is not needed, the pull-up resistor is not necessary and
SDO can be left unconnected.
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LTC2158-12
PIN FUNCTIONS
SDI (Pin 60): Serial Interface Data Input. In serial programming mode, (PAR/SER = 0V), SDI is the serial interface
data input. Data on SDI is clocked into the mode control
registers on the rising edge of SCK. In the parallel programming mode (PAR/SER = VDD), SDI selects 3.5mA or
1.75mA LVDS output current (see Table 2). SDI can be
driven with 1.8V to 3.3V logic.
SCK (Pin 61): Serial Interface Clock Input. In serial
programming mode, (PAR/SER = 0V), SCK is the serial
interface clock input. In the parallel programming mode
(PAR/SER = VDD), SCK can be used to place the part in the
low power sleep mode (see Table 2). SCK can be driven
with 1.8V to 3.3V logic.
CS (Pin 62): Serial Interface Chip Select Input. In serial
programming mode, (PAR/SER = 0V), CS is the serial interface chip select input. When CS is low, SCK is enabled
for shifting data on SDI into the mode control registers.
In the parallel programming mode (PAR/SER = VDD), CS
controls the clock duty cycle stabilizer (see Table 2). CS
can be driven with 1.8V to 3.3V logic.
PAR/SER (Pin 63): Programming Mode Selection Pin.
Connect to ground to enable the serial programming mode
where CS, SCK, SDI, SDO become a serial interface that
control the A/D operating modes. Connect to VDD to enable the parallel programming mode where CS, SCK, SDI
become parallel logic inputs that control a reduced set of
the A/D operating modes. PAR/SER should be connected
directly to ground or the VDD of the part and not be driven
by a logic signal.
LVDS Outputs
The following pins are differential LVDS outputs. The
output current level is programmable. There is an optional
internal 100Ω termination resistor between the pins of
each LVDS output pair.
OF–/OF+ (Pins 22/23): Over/Underflow Digital Output.
OF+ is high when an overflow or underflow has occurred.
The overflows for channel A and channel B are multiplexed
together.
DB0_1–/DB0_1+ to DB10_11–/DB10_11+ (Pins 26/27, 28/29,
30/31, 34/35, 36/37, 38/39): Channel B Double Data Rate
Digital Outputs. Two data bits are multiplexed onto each
differential output pair. The even data bits (DB0, DB2, DB4,
DB6, DB8, DB10) appear when CLKOUT+ is low. The odd
data bits (DB1, DB3, DB5, DB7, DB9, DB11) appear when
CLKOUT+ is high.
CLKOUT –/CLKOUT+ (Pins 40/41): Data Output Clock.
The digital outputs normally transition at the same time
as the falling and rising edges of CLKOUT+. The phase of
CLKOUT+ can also be delayed relative to the digital outputs
by programming the mode control registers.
DA0_1–/DA0_1+ to DA10_11–/DA10_11+ (Pins 44/45, 46/47,
50/51, 52/53, 54/55, 56/57): Channel A Double Data Rate
Digital Outputs. Two data bits are multiplexed onto each
differential output pair. The even data bits (DA0, DA2, DA4,
DA6, DA8, DA10) appear when CLKOUT+ is low. The odd
data bits (DA1, DA3, DA5, DA7, DA9, DA11) appear when
CLKOUT+ is high.
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9
LTC2158-12
FUNCTIONAL BLOCK DIAGRAM
VDD
OVDD
CHANNEL A
ANALOG
INPUT
12-BIT
PIPELINED
ADC CORE
S/H
VCM
0.1µF
CORRECTION
LOGIC
DA10_11
•
•
•
DA0_1
OUTPUT
DRIVERS
VCM
BUFFER
DDR
LVDS
OGND
BUFFER
GND
CLOCK
CLOCK/DUTY
CYCLE CONTROL
CS
SCK
SDI
PAR/SER
SPI
VREF
2.2µF
1.25V
REFERENCE
GND
RANGE
SELECT
SENSE
ANALOG
INPUT
BUFFER
S/H
OVDD
12-BIT
PIPELINED
ADC CORE
CORRECTION
LOGIC
DB10_11
•
•
•
DB0_1
OUTPUT
DRIVERS
DDR
LVDS
CHANNEL B
215812 F01
OGND
GND
Figure 1. Functional Block Diagram
10
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LTC2158-12
TIMING DIAGRAMS
Double Data Rate Output Timing, All Outputs Are Differential LVDS
N
tAP
N+3
N+2
N+1
tL
tH
ENC–
ENC+
CLKOUT+
CLKOUT –
DA0_1–
DA0_1+
DA10_11–
DA10_11+
DB0_1–
DB0_1+
tC
DA0N-6
DA1N-6
DA0N-5
DA1N-5
DA0N-4
DA1N-4
tD
DA10N-6 DA11N-6 DA10N-5 DA11N-5 DA10N-4 DA11N-4
DB0N-6
DB1N-6
DB0N-5
DB1N-5
DB0N-4
DB1N-4
DB10_11–
DB10_11+
DB10N-6 DB11N-6 DB10N-5 DB11N-5 DB10N-4 DB11N-4
OF–
OF+
OF_A N-6 OF_B N-6 OF_A N-5 OF_B N-5 OF_A N-4 OF_B N-4
tSKEW
215812 TD01
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11
LTC2158-12
TIMING DIAGRAMS
SPI Port Timing (Readback Mode)
tDS
tS
tDH
tSCK
tH
CS
SCK
tDO
SDI
SDO
R/W
A6
A5
A4
A3
A2
A1
A0
XX
D7
HIGH IMPEDANCE
XX
D6
XX
D5
XX
D4
XX
D3
XX
D2
XX
XX
D1
D0
SPI Port Timing (Write Mode)
CS
SCK
SDI
SDO
12
R/W
A6
A5
A4
A3
A2
A1
A0
D7
D6
D5
D4
D3
D2
D1
D0
215812 TD02
HIGH IMPEDANCE
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LTC2158-12
APPLICATIONS INFORMATION
CONVERTER OPERATION
INPUT DRIVE CIRCUITS
The LTC2158-12 is a two-channel, 12-bit 310Msps
A/D converter powered by a single 1.8V supply. The
analog inputs must be driven differentially. The encode inputs should be driven differentially for optimal
performance. The digital outputs are double data rate
LVDS. Additional features can be chosen by programming
the mode control registers through a serial SPI port.
Input Filtering
ANALOG INPUT
The analog inputs are differential CMOS sample-andhold circuits (Figure 2). The inputs must be driven differentially around a common mode voltage set by the VCM
output pin, which is nominally 0.435 • VDD. For the 1.32V
input range, the inputs should swing from VCM – 0.33V to
VCM + 0.33V. There should be 180° phase difference
between the inputs.
The two channels are simultaneously sampled by a
shared encode circuit.
If possible, there should be an RC lowpass filter right at
the analog inputs. This lowpass filter isolates the drive
circuitry from the A/D sample-and-hold switching, and also
limits wide band noise from the drive circuitry. Figure 3
shows an example of an input RC filter. The RC component values should be chosen based on the application’s
specific input frequency.
Transformer-Coupled Circuits
Figure 3 shows the analog input being driven by an RF
transformer with the common mode supplied through a
pair of resistors via the VCM pin.
At higher input frequencies a transmission line balun
transformer (Figures 4 and 5) has better balance, resulting
in lower A/D distortion.
10Ω
VCM
0.1µF
0.1µF
LTC2158-12
VDD
IN
RON
20Ω
AIN+
T1
1:1
4.7Ω
25Ω
10pF
0.1µF
4.7Ω
2pF
VDD
AIN–
AIN+
2pF
25Ω
RON
20Ω
LTC2158-12
AIN–
T1: MACOM ETC1-1T
2pF
215812 F03
Figure 3. Analog Input Circuit Using a Transformer.
Recommended for Input Frequencies from 5MHz to 70MHz
2pF
VDD
10Ω
1.2V
VCM
0.1µF
0.1µF
IN
10k
ENC+
LTC2158-12
4.7Ω
AIN+
45Ω
ENC–
0.1µF
0.1µF
215812 F02
Figure 2. Equivalent Input Circuit. Only One
of Two Analog Channels Is Shown
100Ω
45Ω
T2: MABA
T1: WBC1-1L
007159-000000
4.7Ω
AIN–
215812 F04
Figure 4. Recommended Front-End Circuit for
Input Frequencies from 15MHz to 150MHz
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13
LTC2158-12
APPLICATIONS INFORMATION
Amplifier Circuits
VCM
AIN+
AIN–
At very high frequencies an RF gain block will often have
lower distortion than a differential amplifier. If the gain
block is single-ended, then a transformer circuit (Figures
3 and 5) should convert the signal to differential before
driving the A/D. The A/D cannot be driven single-ended.
LTC2158-12
4.7Ω
IN
Figure 6 shows the analog input being driven by a high
speed differential amplifier. The output of the amplifier is
AC coupled to the A/D so the amplifier’s output common
mode voltage can be optimally set to minimize distortion.
0.1µF
10Ω
0.1µF
45Ω
100Ω
0.1µF
45Ω
0.1µF
4.7Ω
T1: MABA
007159-000000
215812 F05
Figure 5. Recommended Front-End Circuit for
Input Frequencies from 150MHz to 900MHz
Reference
The LTC2158-12 has an internal 1.25V voltage reference.
For a 1.32V input range with internal reference, connect
SENSE to VDD. For a 1.32V input range with an external
reference, apply a 1.25V reference voltage to SENSE
(Figure 7).
50Ω
VCM
0.1µF
50Ω
Encode Input
LTC2158-12
3pF
0.1µF
4.7Ω
INPUT
0.1µF
4.7Ω
3pF
AIN+
AIN–
3pF
215812 F06
Figure 6. Front-End Circuit Using a High
Speed Differential Amplifier
The signal quality of the encode inputs strongly affects
the A/D noise performance. The encode inputs should
be treated as analog signals—do not route them next to
digital traces on the circuit board.
The encode inputs are internally biased to 1.2V through
10k equivalent resistance (Figure 8). If the common mode
of the driver is within 1.1V to 1.5V, it is possible to drive
the encode inputs directly. Otherwise a transformer or
coupling capacitors are needed (Figures 9 and 10). The
maximum (peak) voltage of the input signal should never
exceed VDD +0.1V or go below –0.1V.
LTC2158-12
VREF
5Ω
VDD
LTC2158-12
1.25V
1.2V
2.2µF
SCALER/
BUFFER
SENSE
ADC
REFERENCE
SENSE
DETECTOR
ENC+
ENC–
215812 F07
Figure 7. Reference Circuit
14
10k
215812 F08
Figure 8. Equivalent Encode Input Circuit
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LTC2158-12
APPLICATIONS INFORMATION
Clock Duty Cycle Stabilizer
DIGITAL OUTPUTS
For good performance the encode signal should have a
50% (±5%) duty cycle. If the optional clock duty cycle
stabilizer circuit is enabled, the encode duty cycle can
vary from 30% to 70% and the duty cycle stabilizer will
maintain a constant 50% internal duty cycle. The duty cycle
stabilizer is enabled via SPI Register A2 (see Table 3) or
by CS in parallel programming mode.
The digital outputs are double data rate LVDS signals. T wo
data bits are multiplexed and output on each differential
output pair. There are six LVDS output pairs for channel A
(DA0_1+/DA0_1– through DA10_11–/DA10_11+) and six
pairs for channel B (DB0_1+/DB0_1– through DB10_11–/
DB10_11+). Overflow (OF+/OF –) and the data output clock
(CLKOUT+/CLKOUT–) each have an LVDS output pair. Note
that overflow for both channels is multiplexed onto the
OF+/OF – output pair.
For applications where the sample rate needs to be changed
quickly, the clock duty cycle stabilizer can be disabled. In
this case, care should be taken to make the clock a 50%
(±5%) duty cycle.
LTC2158-12
VDD
1.2V
0.1µF
10k
50Ω
100Ω
0.1µF
50Ω
T1: MACOM
ETC1-1-13
215812 F09
Figure 9. Sinusoidal Encode Drive
LTC2158-12
VDD
1.2V
0.1µF
PECL OR
LVDS INPUT
ENC+
10k
100Ω
0.1µF
ENC–
215812 F10
Figure 10. PECL or LVDS Encode Drive
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15
LTC2158-12
APPLICATIONS INFORMATION
Programmable LVDS Output Current
The default output driver current is 3.5mA. This current
can be adjusted by serially programming mode control
register A3 (see Table 3). Available current levels are
1.75mA, 2.1mA, 2.5mA, 3mA, 3.5mA, 4mA and 4.5mA.
Optional LVDS Driver Internal Termination
In most cases, using just an external 100Ω termination
resistor will give excellent LVDS signal integrity. In addition, an optional internal 100Ω termination resistor can
be enabled by serially programming mode control register
A3. The internal termination helps absorb any reflections
caused by imperfect termination at the receiver. When the
internal termination is enabled, the output driver current
is doubled to maintain the same output voltage swing.
Overflow Bit
The overflow output bit (OF) outputs a logic high when
the analog input is either overranged or underranged. The
overflow bit has the same pipeline latency as the data bits.
The OF output is double data rate; when CLKOUT+ is low,
channel A’s overflow is available; when CLKOUT+ is high,
channel B’s overflow is available.
Phase Shifting the Output Clock
To allow adequate set-up and hold time when latching the
output data, the CLKOUT+ signal may need to be phase
shifted relative to the data output bits. Most FPGAs have
this feature; this is generally the best place to adjust the
timing.
Alternatively, the ADC can also phase shift the CLKOUT+/
CLKOUT– signals by serially programming mode control
register A2. The output clock can be shifted by 0°, 45°,
90°, or 135°. To use the phase shifting feature the clock
duty cycle stabilizer must be turned on. Another control register bit can invert the polarity of CLKOUT+ and
CLKOUT–, independently of the phase shift. The combination of these two features enables phase shifts of 45° up
to 315° (Figure 11).
ENC+
D0-D11, OF
CLKOUT+
MODE CONTROL BITS
PHASE
SHIFT
CLKINV
CLKPHASE1
CLKPHASE0
0°
0
0
0
45°
0
0
1
90°
0
1
0
135°
0
1
1
180°
1
0
0
225°
1
0
1
270°
1
1
0
315°
1
1
1
215812 F11
Figure 11. Phase Shifting CLKOUT
16
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LTC2158-12
APPLICATIONS INFORMATION
DATA FORMAT
CLKOUT
Table 1 shows the relationship between the analog input
voltage, the digital data output bits and the overflow bit.
By default the output data format is offset binary. The 2’s
complement format can be selected by serially programming mode control register A4.
(1.32V Range)
OF
D11-D0
(OFFSET BINARY)
OF
OF
D11
Table 1. Output Codes vs Input Voltage
AIN+ – AIN–
CLKOUT
D11/D0
D10
D11-D0
(2’s COMPLEMENT)
>0.66V
1
1111 1111 1111
0111 1111 1111
+0.66V
0
1111 1111 1111
0111 1111 1111
+0.6596777V
0
1111 1111 1110
0111 1111 1110
+0.0003222V
0
1000 0000 0001
0000 0000 0001
+0.000000V
0
1000 0000 0000
0000 0000 0000
–0.0003222V
0
0111 1111 1111
1111 1111 1111
–0.0006445V
0
0111 1111 1110
1111 1111 1110
–0.6596777V
0
0000 0000 0001
1000 0000 0001
–0.66V
0
0000 0000 0000
1000 0000 0000
< –0.66V
1
0000 0000 0000
1000 0000 0000
Digital Output Randomizer
D10/D0
•
•
•
RANDOMIZER
ON
D1
D1/D0
D0
D0
215812 F12
Figure 12. Functional Equivalent of Digital Output Randomizer
PC BOARD
Interference from the A/D digital outputs is sometimes
unavoidable. Digital interference may be from capacitive or
inductive coupling or coupling through the ground plane.
Even a tiny coupling factor can cause unwanted tones
in the ADC output spectrum. By randomizing the digital
output before it is transmitted off chip, these unwanted
tones can be randomized which reduces the unwanted
tone amplitude.
The digital output is randomized by applying an exclusive‑OR logic operation between the LSB and all other
data output bits. To decode, the reverse operation is
applied—an exclusive-OR operation is applied between
the LSB and all other bits. The LSB, OF and CLKOUT outputs are not affected. The output randomizer is enabled
by serially programming mode control register A4.
CLKOUT FPGA
OF
D11/D0
LTC2158-12
D11
D10/D0
D1/D0
D0
•
•
•
D10
D1
D0
215812 F13
Figure 13. Decoding a Randomized Digital
Output Signal
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17
LTC2158-12
APPLICATIONS INFORMATION
Alternate Bit Polarity
Sleep Mode
Another feature that may reduce digital feedback on the
circuit board is the alternate bit polarity mode. When this
mode is enabled, all of the odd bits (D1, D3, D5, D7, D9,
D11) are inverted before the output buffers. The even
bits (D0, D2, D4, D6, D8, D10), OF and CLKOUT are not
affected. This can reduce digital currents in the circuit
board ground plane and reduce digital noise, particularly
for very small analog input signals.
The A/D may be placed in sleep mode to conserve power.
In sleep mode the entire A/D converter is powered down,
resulting in < 5mW power consumption. If the encode
input signal is not disabled the power consumption will be
higher (up to 5mW at 310Msps). Sleep mode is enabled
by mode control register A1 (serial programming mode),
or by SCK (parallel programming mode).
The digital output is decoded at the receiver by inverting
the odd bits (D1, D3, D5, D7, D9, D11). The alternate bit
polarity mode is independent of the digital output randomizer—either both or neither function can be on at the same
time. The alternate bit polarity mode is enabled by serially
programming mode control register A4.
In the serial programming mode it is also possible to disable channel B while leaving channel A in normal operation.
The amount of time required to recover from sleep mode
depends on the size of the bypass capacitor on VREF . For
the suggested value in Figure 1, the A/D will stabilize after
0.1ms + 2500 • tp where tp is the period of the sampling
clock.
Digital Output Test Patterns
Nap Mode
To allow in-circuit testing of the digital interface to the
A/D, there are several test modes that force the A/D data
outputs (OF, D11 to D0) to known values:
In nap mode the A/D core is powered down while the
internal reference circuits stay active, allowing faster
wake-up. Recovering from nap mode requires at least
100 clock cycles.
All 1s: All outputs are 1
All 0s: All outputs are 0
Alternating: Outputs change from all 1s to all 0s on
alternating samples
Checkerboard: Outputs change from 1010101010101
to 0101010101010 on alternating samples.
The digital output test patterns are enabled by serially
programming mode control register A4. When enabled,
the test patterns override all other formatting modes:
2’s complement, randomizer, alternate-bit polarity.
Output Disable
The digital outputs may be disabled by serially programming mode control register A3. All digital outputs including OF and CLKOUT are disabled. The high impedance
disabled state is intended for long periods of inactivity,
it is not designed for multiplexing the data bus between
multiple converters.
18
Wake-up time from nap mode is guaranteed only if the
clock is kept running, otherwise sleep mode wake-up
conditions apply.
Nap mode is enabled by setting register A1 in the serial
programming mode.
DEVICE PROGRAMMING MODES
The operating modes of the LTC2158-12 can be programmed by either a parallel interface or a simple serial
interface. The serial interface has more flexibility and
can program all available modes. The parallel interface
is more limited and can only program some of the more
commonly used modes.
Parallel Programming Mode
To use the parallel programming mode, PAR/SER should
be tied to VDD. The CS, SCK and SDI pins are binary logic
inputs that set certain operating modes. These pins can
be tied to VDD or ground, or driven by 1.8V, 2.5V, or 3.3V
CMOS logic. Table 2 shows the modes set by CS, SCK
and SDI.
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APPLICATIONS INFORMATION
Table 2. Parallel Programming Mode Control Bits (PAR/SER = VDD)
PIN
DESCRIPTION
CS
Clock Duty Cycle Stabilizer Control Bit
0 = Clock Duty Cycle Stabilizer Off
1 = Clock Duty Cycle Stabilizer On
SCK
Power Down Control Bit
0 = Normal Operation
1 = Sleep Mode (entire ADC is powered down)
SDI
LVDS Current Selection Bit
0 = 3.5mA LVDS Current Mode
1 = 1.75mA LVDS Current Mode
Software Reset
If serial programming is used, the mode control registers
should be programmed as soon as possible after the power
supplies turn on and are stable. The first serial command
must be a software reset which will reset all register data
bits to logic 0. To perform a software reset it is necessary to write 1 in register A0 (Bit D7). After the reset is
complete, Bit D7 is automatically set back to zero. This
register is write-only.
GROUNDING AND BYPASSING
Serial Programming Mode
To use the serial programming mode, PAR/SER should be
tied to ground. The CS, SCK, SDI and SDO pins become
a serial interface that program the A/D control registers.
Data is written to a register with a 16-bit serial word. Data
can also be read back from a register to verify its contents.
Serial data transfer starts when CS is taken low. The data
on the SDI pin is latched at the first sixteen rising edges
of SCK. Any SCK rising edges after the first sixteen are
ignored. The data transfer ends when CS is taken high again.
The first bit of the 16-bit input word is the R/W bit. The
next seven bits are the address of the register (A6:A0).
The final eight bits are the register data (D7:D0).
If the R/W bit is low, the serial data (D7:D0) will be written to the register set by the address bits (A6:A0). If the
R/W bit is high, data in the register set by the address bits
(A6:A0) will be read back on the SDO pin (see the Timing
Diagrams). During a readback command the register is
not updated and data on SDI is ignored.
The SDO pin is an open-drain output that pulls to ground
with a 200Ω impedance. If register data is read back
through SDO, an external 2k pull-up resistor is required.
If serial data is only written and readback is not needed,
then SDO can be left floating and no pull-up resistor is
needed. Table 3 shows a map of the mode control registers.
The LTC2158-12 requires a printed circuit board with a
clean unbroken ground plane in the first layer beneath the
ADC. A multilayer board with an internal ground plane is
recommended. Layout for the printed circuit board should
ensure that digital and analog signal lines are separated as
much as possible. In particular, care should be taken not
to run any digital track alongside an analog signal track
or underneath the ADC.
High quality ceramic bypass capacitors should be used at
the VDD, OVDD, VCM, VREF pins. Bypass capacitors must be
located as close to the pins as possible. Size 0402 ceramic
capacitors are recommended. The traces connecting the
pins and bypass capacitors must be kept short and should
be made as wide as possible.
The analog inputs, encode signals, and digital outputs
should not be routed next to each other. Ground fill and
grounded vias should be used as barriers to isolate these
signals from each other.
HEAT TRANSFER
Most of the heat generated by the LTC2158-12 is transferred from the die through the bottom-side exposed pad
and package leads onto the printed circuit board. For good
electrical and thermal performance, the exposed pad must
be soldered to a large grounded pad on the PC board. This
pad should be connected to the internal ground planes by
an array of vias.
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19
LTC2158-12
APPLICATIONS INFORMATION
Table 3. Serial Programming Mode Register Map (PAR/SER = GND). X indicates an unused bit that is read back as 0
REGISTER A0: RESET REGISTER (ADDRESS 00h) Write Only
D7
D6
D5
D4
D3
D2
D1
D0
RESET
X
X
X
X
X
X
X
RESET
Bit 7
Software Reset Bit
0 = Reset Disabled
1 = Software Reset. All mode control registers are reset to 00h. This bit is automatically set back to zero after the reset is complete.
Unused Bits
Bits 6-0
REGISTER A1: POWER-DOWN REGISTER (ADDRESS 01h)
D7
D6
D5
D4
D3
D2
D1
D0
X
X
X
X
SLEEP
NAP
PDB
0
Bits 7-4
Unused Bit
Bit 3
SLEEP
0 = Normal Operation
1 = Power Down Entire ADC
Bit 2
NAP
0 = Normal Mode
1 = Low Power Mode for Both Channels
PDB
Bit 1
0 = Normal Operation
1 = Power Down Channel B. Channel A operates normally.
Bit 0
Must be set to 0
REGISTER A2: TIMING REGISTER (ADDRESS 02h)
D7
D6
D5
D4
D3
D2
D1
D0
X
X
X
X
CLKINV
CLKPHASE1
CLKPHASE0
DCS
Bits 7-4
Unused Bit
Bit 3
CLKINV
Output Clock Invert Bit
0 = Normal CLKOUT Polarity (as shown in the Timing Diagrams)
1 = Inverted CLKOUT Polarity
Bits 2-1
Output Clock Phase Delay Bits
CLKPHASE1:CLKPHASE0
00 = No CLKOUT Delay (as shown in the Timing Diagrams)
01 = CLKOUT+/CLKOUT– delayed by 45° (Clock Period • 1/8)
10 = CLKOUT+/CLKOUT– delayed by 90° (Clock Period • 1/4)
11 = CLKOUT+/CLKOUT– delayed by 135° (Clock Period • 3/8)
Note: If the CLKOUT phase delay feature is used, the clock duty cycle stabilizer must also be turned on.
Bit 0
DCS
Clock Duty Cycle Stabilizer Bit
0 = Clock Duty Cycle Stabilizer Off
1 = Clock Duty Cycle Stabilizer On
20
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LTC2158-12
APPLICATIONS INFORMATION
REGISTER A3: OUTPUT MODE REGISTER (ADDRESS 03h)
D7
X
D6
D5
D4
D3
D2
D1
D0
X
X
ILVDS2
ILVDS1
ILVDS0
TERMON
OUTOFF
Bits 7-5
Unused Bit
Bits 4-2
ILVDS2:ILVDS0 LVDS Output Current Bits
000 = 3.5mA LVDS Output Driver Current
001 = 4.0mA LVDS Output Driver Current
010 = 4.5mA LVDS Output Driver Current
011 = Not Used
100 = 3.0mA LVDS Output Driver Current
101 = 2.5mA LVDS Output Driver Current
110 = 2.1mA LVDS Output Driver Current
111 = 1.75mA LVDS Output Driver Current
Bit 1
TERMON
LVDS Internal Termination Bit
0 = Internal Termination Off
1 = Internal Termination On. LVDS output driver current is 2× the current set by ILVDS2:ILVDS0
Bit 0
OUTOFF
Digital Output Mode Control Bits
0 = Digital Outputs Are Enabled
1 = Digital Outputs Are Disabled (High Impedance)
REGISTER A4: DATA FORMAT REGISTER (ADDRESS 04h)
D7
OUTTEST2
Bits 7-5
D6
D5
D4
D3
D2
D1
D0
OUTTEST1
OUTTEST0
ABP
0
DTESTON
RAND
TWOSCOMP
OUTTEST2:OUTTEST0
Digital Output Test Pattern Bits
000 = All Digital Outputs = 0
001 = All Digital Outputs = 1
010 = Alternating Output Pattern. OF, D11-D0 alternate between 0 0000 0000 0000 and 1 1111 1111 1111
100 = Checkerboard Output Pattern. OF, D11-D0 alternate between 1 0101 0101 0101 and 0 1010 1010 1010
Note 1: Other bit combinations are not used.
Note 2: Patterns from channel A and channel B may not be synchronous.
Bit 4
ABP
Alternate Bit Polarity Mode Control Bit
0 = Alternate Bit Polarity Mode Off
1 = Alternate Bit Polarity Mode On
Bit 3
Must Be Set to 0
Bit 2
DTESTON
Enable the digital output test patterns (set by Bits 7-5)
0 = Normal Mode
1 = Enable the Digital Output Test Patterns
Bit 1
Data Output Randomizer Mode Control Bit
RAND
0 = Data Output Randomizer Mode Off
1 = Data Output Randomizer Mode On
Bit 0
TWOSCOMP Two’s Complement Mode Control Bit
0 = Offset Binary Data Format
1 = Two’s Complement Data Format
215812fa
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21
LTC2158-12
TYPICAL APPLICATIONS
Silkscreen Top
Top Side
22
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LTC2158-12
TYPICAL APPLICATIONS
Inner Layer 2 GND
Inner Layer 3
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23
LTC2158-12
TYPICAL APPLICATIONS
Inner Layer 4
Inner Layer 5
Bottom Side
24
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LTC2158-12
TYPICAL APPLICATIONS
2158-12 Schematic
SDO
SDI
SCK
CD
VDD
C7
0.1µF
C5
0.1µF
C13, 0.1µF
PAR/SER
C12
0.1µF VDD
OVDD
AINA–
+
AINB
AINB
–
R33
10Ω
R8
100Ω
C24, 2.2µF
C29
0.1µF
R7
10Ω
R6
10Ω
R12
100Ω
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
65
VDD
VDD
GND
AINA+
AINA–
GND
SENSE
VREF
GND
VCM
GND
AINB–
AINB+
GND
VDD
VDD
GND
LTC2158-12
OGND
DA2_3+
DA2_3–
DA0_1+
DA0_1–
NC
NC
CLKOUT+
CLKOUT–
DB10_11+
DB10_11–
DB8_9+
DB8_9–
DB6_7+
DB6_7–
OGND
VDD
GND
ENC+
ENC–
GND
OF –
OF +
NC
NC
DB0_1–
DB0_1+
DB2_3–
DB2_3+
DB4_5 –
DB4_5+
OVDD
AINA
R34
10Ω
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
DA2_3+
DA2_3–
DA0_1+
DA0_1–
CLKOUT+
CLKOUT–
DB10_11+
DB10_11–
DB8_9+
DB8_9–
DB6_7+
DB6_7–
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
+
VDD
PAR/SER
CS
SCK
SDI
SDO
GND
DA10_11+
DA10_11–
DA8_9+
DA8_9–
DA6_7+
DA6_7 –
DA4_5+
DA4_5 –
OVDD
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
C11
0.1µF
DA10_11+
DA10_11–
DA8_9+
DA8_9–
DA6_7+
DA6_7–
DA4_5+
DA4_5–
VDD
OVDD
C15
0.1µF
R56
10Ω
C14
0.1µF
C78
0.1µF
ENC+
C798
0.1µF
ENC–
DB4_5+
DB2_5–
DB2_3+
DB2_3–
DB4_1+
DB4_1–
OF+
OF–
215812 TA09
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25
LTC2158-12
PACKAGE DESCRIPTION
Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings.
UP Package
64-Lead Plastic QFN (9mm × 9mm)
(Reference LTC DWG # 05-08-1705 Rev C)
0.70 ±0.05
7.15 ±0.05
7.50 REF
8.10 ±0.05 9.50 ±0.05
(4 SIDES)
7.15 ±0.05
PACKAGE OUTLINE
0.25 ±0.05
0.50 BSC
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED
9 .00 ±0.10
(4 SIDES)
0.75 ±0.05
R = 0.115
TYP
R = 0.10
TYP
63 64
0.40 ±0.10
PIN 1 TOP MARK
(SEE NOTE 5)
1
2
PIN 1
CHAMFER
C = 0.35
7.50 REF
(4-SIDES)
7.15 ±0.10
7.15 ±0.10
0.200 REF
0.00 – 0.05
NOTE:
1. DRAWING CONFORMS TO JEDEC PACKAGE OUTLINE MO-220 VARIATION WNJR-5
2. ALL DIMENSIONS ARE IN MILLIMETERS
3. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.20mm ON ANY SIDE, IF PRESENT
4. EXPOSED PAD SHALL BE SOLDER PLATED
5. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE
6. DRAWING NOT TO SCALE
26
(UP64) QFN 0406 REV C
0.25 ±0.05
0.50 BSC
BOTTOM VIEW—EXPOSED PAD
215812fa
For more information www.linear.com/LTC2158-12
LTC2158-12
REVISION HISTORY
REV
DATE
DESCRIPTION
A
12/14
Changed the pipeline latency to 6
PAGE NUMBER
Updated G15
5 and 10
7
215812fa
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection
of itsinformation
circuits as described
herein will not infringe on existing patent rights.
For more
www.linear.com/LTC2158-12
27
LTC2158-12
TYPICAL APPLICATION
LTC2158-12: 32K Point 2-Tone FFT,
fIN = 71MHz and 69MHz, 310Msps
VDD
OVDD
ANALOG
INPUT
CLOCK
S/H
12-BIT
PIPELINED
ADC CORE
S/H
DA10_11
•
•
•
DA0_1
OUTPUT
DRIVERS
DDR
LVDS
OGND
CLOCK/DUTY
CYCLE
CONTROL
ANALOG
INPUT
CORRECTION
LOGIC
0
–40
–60
–80
OVDD
CHANNEL B
12-BIT
PIPELINED
ADC CORE
–20
AMPLITUDE (dBFS)
CHANNEL A
–100
CORRECTION
LOGIC
DB10_11
•
•
•
DB0_1
OUTPUT
DRIVERS
DDR
LVDS
–120
0
20
40
60 80 100 120 140
FREQUENCY (MHz)
215812 TA10b
GND
215812 TA10a
OGND
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10GHz GBW, 1.1nV/√Hz Differential Amplifier/ADC Driver 88dB SFDR at 100MHz, Input Range Includes Ground 52mA
Supply Current, 3mm × 2mm QFN Package
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Continuously Adjustable Gain Control, 35dBm OIP3 at 240MHz,
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1.8GHz Dual Low Noise, Low Distortion Differential ADC
Drivers for 300MHz IF
Fixed Gain 10V/V, 1nV/√Hz Total Input Noise, 80mA Supply
Current per Amplifier, 3mm × 4mm QFN-20 Package
LTM9002
14-Bit Dual Channel IF/Baseband Receiver Subsystem
Integrated High Speed ADC, Passive Filters and Fixed Gain
Differential Amplifiers
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12-Bit Digital Pre-Distortion Receiver
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3.8GHz Input Frequency Range
Receiver Subsystems
28 Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
For more information www.linear.com/LTC2158-12
(408) 432-1900 ● FAX: (408) 434-0507
●
www.linear.com/LTC2158-12
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LT 1214 REV A• PRINTED IN USA
 LINEAR TECHNOLOGY CORPORATION 2012