AD AD9787 Dual 12-/14-/16-bit 800 msps dac with low power 32-bit complex nco Datasheet

Dual 12-/14-/16-Bit 800 MSPS DAC
with Low Power 32-Bit Complex NCO
AD9785/AD9787/AD9788
FEATURES
GENERAL DESCRIPTION
Analog output: adjustable 8.7 mA to 31.7 mA,
RL = 25 Ω to 50 Ω
Low power, fine complex NCO allows carrier placement
anywhere in DAC bandwidth while adding <300 mW power
Auxiliary DACs allow I and Q gain matching and offset control
Includes programmable I and Q phase compensation
Internal digital upconversion capability
Multiple chip synchronization interface
High performance, low noise PLL clock multiplier
Digital inverse sinc filter
100-lead, exposed paddle TQFP package
The AD9785/AD9787/AD9788 are 12-bit, 14-bit, and 16-bit,
high dynamic range TxDAC® devices, respectively, that provide
a sample rate of 800 MSPS, permitting multicarrier generation
up to the Nyquist frequency. Features are included for optimizing
direct conversion transmit applications, including complex
digital modulation, as well as gain, phase, and offset compensation. The DAC outputs are optimized to interface seamlessly
with analog quadrature modulators, such as the ADL537x
family from Analog Devices, Inc. A serial peripheral interface
(SPI) provides for programming and readback of many internal
parameters. Full-scale output current can be programmed over
a range of 10 mA to 30 mA. The AD978x family is manufactured
on a 0.18 μm CMOS process and operates from 1.8 V and 3.3 V
supplies. It is enclosed in a 100-lead TQFP package.
APPLICATIONS
Wireless infrastructure
WCDMA, CDMA2000, TD-SCDMA, WiMAX, GSM
Digital high or low IF synthesis
Transmit diversity
Wideband communications
LMDS/MMDS, point-to-point
PRODUCT HIGHLIGHTS
1.
Low noise and intermodulation distortion (IMD) enable
high quality synthesis of wideband signals from baseband
to high intermediate frequencies.
2.
Proprietary DAC output switching technique enhances
dynamic performance.
3.
CMOS data input interface with adjustable setup and hold.
4.
Low power complex 32-bit numerically controlled
oscillators (NCOs).
TYPICAL SIGNAL CHAIN
QUADRATURE
MODULATOR/
MIXER/
AMPLIFIER
COMPLEX I AND Q
DC
LO
DC
DIGITAL INTERPOLATION FILTERS
I DAC
POST DAC
ANALOG FILTER
FPGA/ASIC/DSP
A
07098-001
Q DAC
Figure 1.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
©2008 Analog Devices, Inc. All rights reserved.
AD9785/AD9787/AD9788
TABLE OF CONTENTS
Features .............................................................................................. 1
Input Data RAM......................................................................... 37
Applications....................................................................................... 1
Digital Datapath ............................................................................. 38
General Description ......................................................................... 1
Interpolation Filters ................................................................... 38
Product Highlights ........................................................................... 1
Quadrature Modulator .............................................................. 40
Typical Signal Chain......................................................................... 1
Numerically Controlled Oscillator .......................................... 40
Revision History ............................................................................... 2
Inverse Sinc Filter ....................................................................... 40
Specifications..................................................................................... 3
Digital Amplitude and Offset Control .................................... 41
DC Specifications ......................................................................... 3
Digital Phase Correction........................................................... 41
Digital Specifications ................................................................... 4
Device Synchronization................................................................. 42
AC Specifications.......................................................................... 5
Synchronization Logic Overview............................................. 42
Absolute Maximum Ratings............................................................ 6
Synchronizing Devices to a System Clock .............................. 44
Thermal Resistance ...................................................................... 6
Synchronizing Multiple Devices to Each Other..................... 45
ESD Caution.................................................................................. 6
Interrupt Request Operation .................................................... 46
Pin Configurations and Function Descriptions ........................... 7
Driving the REFCLK Input ........................................................... 47
Typical Performance Characteristics ........................................... 13
DAC REFCLK Configuration................................................... 47
Terminology .................................................................................... 20
Analog Outputs............................................................................... 50
Theory of Operation ...................................................................... 21
Digital Amplitude Scaling......................................................... 50
Serial Port Interface.................................................................... 21
Power Dissipation........................................................................... 52
SPI Register Map............................................................................. 24
AD9785/AD9787/AD9788 Evaluation Boards........................... 54
SPI Register Descriptions .......................................................... 25
Output Configuration................................................................ 54
Input Data Ports.............................................................................. 33
Digital Picture of Evaluation Board......................................... 54
Single-Port Mode........................................................................ 33
Evaluation Board Software........................................................ 55
Dual-Port Mode.......................................................................... 33
Evaluation Board Schematics ................................................... 56
Input Data Referenced to DATACLK ...................................... 33
Outline Dimensions ....................................................................... 62
Input Data Referenced to REFCLK.......................................... 35
Ordering Guide .......................................................................... 62
Optimizing the Data Input Timing.......................................... 36
REVISION HISTORY
1/08—Revision 0: Initial Version
Rev. 0 | Page 2 of 64
AD9785/AD9787/AD9788
SPECIFICATIONS
DC SPECIFICATIONS
TMIN to TMAX, AVDD33 = 3.3 V, DVDD33 = 3.3 V, DVDD18 = 1.8 V, CVDD18 = 1.8 V, IOUTFS = 20 mA, maximum sample rate, unless
otherwise noted. LVDS driver and receiver are compliant to the IEEE 1596 reduced range link, unless otherwise noted.
Table 1.
Parameter
RESOLUTION
ACCURACY
Differential Nonlinearity (DNL)
Integral Nonlinearity (INL)
MAIN DAC OUTPUTS
Offset Error
Gain Error (with Internal Reference)
Full-Scale Output Current
Output Compliance Range
Output Resistance
Gain DAC Monotonicity
Guaranteed
MAIN DAC TEMPERATURE DRIFT
Offset
Gain
Reference Voltage
AUX DAC OUTPUTS
Resolution
Full-Scale Output Current 1
Output Compliance Range (Source)
Output Compliance Range (Sink)
Output Resistance
Aux DAC Monotonicity Guaranteed
REFERENCE
Internal Reference Voltage
Output Resistance
ANALOG SUPPLY VOLTAGES
AVDD33
CVDD18
DIGITAL SUPPLY VOLTAGES
DVDD33
DVDD18
POWER CONSUMPTION
1× Mode, fDATA = 100 MSPS,
PLL Off, IF = 2 MHz
2× Mode, fDATA = 100 MSPS,
Inverse Sinc Off, PLL Off
4× Mode, fDATA = 100 MSPS,
Inverse Sinc Off, PLL Off
8× Mode, fDATA = 100 MSPS,
Inverse Sinc Off, PLL Off
Power-Down Mode
OPERATING RANGE
1
Min
AD9785
Typ
Max
12
Min
±0.2
±0.3
–0.001
8.66
–1.0
0
±2
20.2
AD9787
Typ
Max
14
Min
±0.5
±1.0
+0.001
−0.001
31.66
+1.0
8.66
–1.0
+0.001
−0.001
31.66
+1.0
8.66
–1.0
Unit
Bits
±2.1
±3.7
LSB
LSB
10
10
10
10
10
10
% FSR
% FSR
mA
V
MΩ
Bits
0.04
100
30
0.04
100
30
0.04
100
30
ppm/°C
ppm/°C
ppm/°C
10
0
±2
20.2
AD9788
Typ
Max
16
+0.001
31.66
+1.0
1
10
1
10
1
10
Bits
mA
V
V
MΩ
Bits
1.2
5
1.2
5
1.2
5
V
kΩ
–1.998
0
0.8
10
0
±2
20.2
+1.998
1.6
1.6
–1.998
0
0.8
10
+1.998
1.6
1.6
–1.998
0
0.8
+1.998
1.6
1.6
3.13
1.70
3.3
1.8
3.47
1.90
3.13
1.70
3.3
1.8
3.47
1.90
3.13
1.70
3.3
1.8
3.47
1.90
V
V
3.13
1.70
3.3
1.8
3.47
1.90
3.13
1.70
3.3
1.8
3.47
1.90
3.13
1.70
3.3
1.8
3.47
1.90
V
V
375
450
375
450
375
450
mW
–40
533
533
533
mW
754
754
754
mW
1054
1054
1054
mW
2.5
+25
9.0
+85
–40
Based on a 10 Ω external resistor.
Rev. 0 | Page 3 of 64
2.5
+25
9.0
+85
–40
2.5
+25
9.0
+85
mW
°C
AD9785/AD9787/AD9788
DIGITAL SPECIFICATIONS
TMIN to TMAX, AVDD33 = 3.3 V, DVDD33 = 3.3 V, DVDD18 = 1.8 V, CVDD18 = 1.8 V, IOUTFS = 20 mA, maximum sample rate, unless
otherwise noted.
Table 2.
Parameter
CMOS INPUT LOGIC LEVEL
Input VIN Logic High
Input VIN Logic Low
LVDS INPUT (SYNC_I+, SYNC_I−)
Input Voltage Range, VIA or VIB
Input Differential Threshold, VIDTH
Input Differential Hysteresis, VIDTHH − VIDTHL
Receiver Differential Input Impedance, RIN
LVDS Input Rate (fSYNC_I = fDATA)
Setup Time, SYNC_I to DAC Clock
Hold Time, SYNC _I to DAC Clock
LVDS DRIVER OUTPUTS (SYNC_O+, SYNC_O−)
Output Voltage High, VOA or VOB
Output Voltage Low, VOA or VOB
Output Differential Voltage, |VOD|
Output Offset Voltage, VOS
Output Impedance, Single-Ended, RO
DAC CLOCK INPUT (REFCLK+, REFCLK–)
Differential Peak-to-Peak Voltage
Common-Mode Voltage
Maximum Clock Rate
DVDD18 = 1.8 V ± 5%
DVDD18 = 1.9 V ± 5%
MAXIMUM INPUT DATA RATE
1× Interpolation
2× Interpolation
4× Interpolation
DVDD18 = 1.8 V ± 5%
DVDD18 = 1.9 V ± 5%
8× Interpolation
DVDD18 = 1.8 V ±5%
DVDD18 = 1.9 V ± 5%
SERIAL PERIPHERAL INTERFACE
Maximum Clock Rate (SCLK)
Minimum Pulse Width High
Minimum Pulse Width Low
Setup Time, SPI_SDIO to SCLK
Hold Time, SPI_SDIO to SCLK
Setup Time, SPI_CSB to SCLK
Data Valid, SPI_SDO to SCLK
INPUT DATA
Setup Time, Input Data to DATACLK
Hold Time, Input Data to DATACLK
Setup Time, Input Data to REFCLK
Hold Time, Input Data to REFCLK
Test Conditions/Comments
Min
Typ
Max
Unit
0.8
V
V
2.0
SYNC_I+ = V1A, SYNC_I− = V1B
825
–100
1575
+100
20
80
30
0.45
0.25
120
825
1025
150
1150
80
1575
200
400
300
mV
mV
mV
Ω
MHz
ns
ns
SYNC_O+ = VOA, SYNC_O− = VOB, 100 Ω termination
100
250
1250
120
mV
mV
mV
mV
Ω
800
400
1600
500
mV
mV
800
900
MHz
MHz
250
250
MSPS
MSPS
200
225
MSPS
MSPS
100
112.5
MSPS
MSPS
40
12.5
12.5
2.8
0.0
3.0
10.0
MHz
ns
ns
ns
ns
ns
ns
460
−1.5
−0.25
2.4
ns
ns
ns
ns
All modes, −40°C to +85°C 1
Rev. 0 | Page 4 of 64
AD9785/AD9787/AD9788
Parameter
LATENCY (DACCLK CYCLES)
1× Interpolation
2× Interpolation
4× Interpolation
8× Interpolation
Inverse Sinc
POWER-UP TIME 2
DAC Wake-Up Time 3
DAC Sleep Time 4
Test Conditions/Comments
Min
With or without modulation
With or without modulation
With or without modulation
With or without modulation
Typ
Max
40
83
155
294
18
260
22
22
IOUT current settling to 1%
IOUT current to less than 1% of full scale
Unit
Cycles
Cycles
Cycles
Cycles
Cycles
ms
ms
ms
1
Timing vs. temperature and data valid windows are delineated in Table 25.
Measured from SPI_CSB rising edge on Register 0x00; toggle Bit 4 from 0 to 1. VREF decoupling capacitor = 0.1 μF.
3
Measured from SPI_CSB rising edge on Register 0x05 or Register 0x07; toggle Bit 15 or Bit 14 from 0 to 1.
4
Measured from SPI_CSB rising edge on Register 0x05 or Register 0x07; toggle Bit 15 or Bit 14 from 1 to 0.
2
AC SPECIFICATIONS
TMIN to TMAX, AVDD33 = 3.3 V, DVDD33 = 3.3 V, DVDD18 = 1.8 V, CVDD18 = 1.8 V, IOUTFS = 20 mA, maximum sample rate, unless
otherwise noted.
Table 3.
Parameter
SPURIOUS-FREE DYNAMIC RANGE (IN-BAND SFDR)
fDACCLK = 200 MSPS, fOUT = 70 MHz 1× Interpolation
fDACCLK = 200 MSPS, fOUT = 70 MHz 2× Interpolation
fDACCLK = 200 MSPS, fOUT = 70 MHz 4× Interpolation
fDACCLK = 800 MSPS, fOUT = 40 MHz 8× Interpolation
TWO-TONE INTERMODULATION DISTORTION (IMD)
fDATA = 200 MSPS, fOUT = 50 MHz 1× Interpolation
fDATA = 200 MSPS, fOUT = 50 MHz 2× Interpolation
fDATA = 200 MSPS, fOUT = 100 MHz 4× Interpolation
fDATA = 100 MSPS, fOUT = 100 MHz 8× Interpolation
NOISE SPECTRAL DENSITY (NSD), EIGHT TONE, 500 kHz TONE
SPACING
fDACCLK = 200 MSPS, fOUT = 80 MHz
fDACCLK = 400 MSPS, fOUT = 80 MHz
fDACCLK = 800 MSPS, fOUT = 80 MHz
WCDMA ADJACENT CHANNEL LEAKAGE RATIO (ACLR),
SINGLE CARRIER
fDACCLK = 491.52 MSPS, fOUT = 100 MHz 4× Interpolation
fDACCLK = 491.52 MSPS, fOUT = 200 MHz 4× Interpolation
WCDMA SECOND ADJACENT CHANNEL LEAKAGE RATIO
(ACLR), SINGLE CARRIER
fDACCLK = 491.52 MSPS, fOUT = 100 MHz 4× Interpolation
fDACCLK = 491.52 MSPS, fOUT = 200 MHz 4× Interpolation
AD9785
Min Typ Max
AD9787
Min Typ Max
AD9788
Min Typ Max
Unit
80
80
78
85
82
82
80
87
83
83
81
90
dBc
dBc
dBc
dBc
80
78
78
70
82
79
79
70
83
80
80
70
dBc
dBc
dBc
dBc
−154
−154
−154
−157
−158
−159
−158
−161
−162
dBm/Hz
dBm/Hz
dBm/Hz
78
72
80
74
82
76
dBc
dBc
80
78
82
80
88
82
dBc
dBc
Rev. 0 | Page 5 of 64
AD9785/AD9787/AD9788
ABSOLUTE MAXIMUM RATINGS
Table 4.
Parameter
AVDD33 to AGND, DGND, CGND
DVDD33, DVDD18, CVDD18
to AGND, DGND, CGND
AGND to DGND, CGND
DGND to AGND, CGND
CGND to AGND, DGND
I120, VREF, IPTAT to AGND
OUT1_P, OUT1_N, OUT2_P, OUT2_N,
AUX1_P, AUX1_N, AUX2_P,
AUX2_N to AGND
P1D[15] to P1D[0], P2D[15] to P2D[0]
to DGND
DATACLK, TXENABLE to DGND
REFCLK+, REFCLK−, RESET, IRQ,
PLL_LOCK, SYNC_O+, SYNC_O−,
SYNC_I+, SYNC_I− to CGND
RESET, IRQ, PLL_LOCK, SYNC_O+,
SYNC_O−, SYNC_I+, SYNC_I−,
SPI_CSB, SCLK, SPI_SDIO, SPI_SDO
to DGND
Junction Temperature
Storage Temperature Range
THERMAL RESISTANCE
Rating
−0.3 V to +3.6 V
−0.3 V to +2.1 V
−0.3 V to +0.3 V
−0.3 V to +0.3 V
−0.3 V to +0.3 V
−0.3 V to AVDD33 + 0.3 V
−1.0 V to AVDD33 + 0.3 V
For this 100-lead, thermally enhanced TQFP, the exposed paddle
(EPAD) must be soldered to the ground plane. Note that these
specifications are valid with no airflow movement.
Table 5. Thermal Resistance
Resistance
θJA
θJB
θJC
Unit
19.1°C/W
12.4°C/W
7.1°C/W
−0.3 V to DVDD33 + 0.3 V
−0.3 V to DVDD33 + 0.3 V
−0.3 V to CVDD18 + 0.3 V
ESD CAUTION
−0.3 V to DVDD33 + 0.3 V
125°C
−65°C to +150°C
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Rev. 0 | Page 6 of 64
Conditions
EPAD soldered. No airflow.
EPAD soldered. No airflow.
EPAD soldered. No airflow.
AD9785/AD9787/AD9788
AVDD33
AGND
AVDD33
AGND
AVDD33
AGND
AGND
OUT2_P
OUT2_N
AGND
AUX2_P
AUX2_N
AGND
AUX1_N
AUX1_P
AGND
OUT1_N
OUT1_P
AGND
AGND
AVDD33
AGND
AVDD33
AGND
AVDD33
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76
75
I120
74
VREF
73
IPTAT
4
72
AGND
REFCLK+
5
71
IRQ
REFCLK–
6
70
RESET
CGND
7
69
SPI_CSB
CGND
8
68
SCLK
CVDD18
9
67
SPI_SDIO
66
SPI_SDO
65
PLL_LOCK
AGND 12
64
DGND
SYNC_I+ 13
63
SYNC_O+
SYNC_I– 14
62
SYNC_O–
DGND 15
61
DVDD33
DVDD18 16
60
DVDD18
P1D[11] 17
59
NC
P1D[10] 18
58
NC
P1D[9] 19
57
NC
P1D[8] 20
56
NC
P1D[7] 21
55
P2D[0]
DGND 22
54
DGND
DVDD18 23
53
DVDD18
P1D[6] 24
52
P2D[1]
P1D[5] 25
51
P2D[2]
DIGITAL DOMAIN
AD9785
CVDD18 10
TOP VIEW
(Not to Scale)
CGND 11
Figure 2. AD9785 Pin Configuration
Table 6. AD9785 Pin Function Descriptions
Pin No.
1, 2, 9, 10
3, 4, 7, 8, 11
5
6
12, 72, 77, 79, 81, 82, 85,
88, 91, 94, 95, 97, 99
13
14
15, 22, 32, 44, 54, 64
16, 23, 33, 43, 53, 60
17
18
19
20
21
24
25
26
27
28
Mnemonic
CVDD18
CGND
REFCLK+
REFCLK−
AGND
Description
1.8 V Clock Supply.
Clock Common.
Differential Clock Input, Positive.
Differential Clock Input, Negative.
Analog Common.
SYNC_I+
SYNC_I−
DGND
DVDD18
P1D[11]
P1D[10]
P1D[9]
P1D[8]
P1D[7]
P1D[6]
P1D[5]
P1D[4]
P1D[3]
P1D[2]
Differential Synchronization Input, Positive.
Differential Synchronization Input, Negative.
Digital Common.
1.8 V Digital Supply.
Port 1, Data Input D11 (MSB).
Port 1, Data Input D10.
Port 1, Data Input D9.
Port 1, Data Input D8.
Port 1, Data Input D7.
Port 1, Data Input D6.
Port 1, Data Input D5.
Port 1, Data Input D4.
Port 1, Data Input D3.
Port 1, Data Input D2.
Rev. 0 | Page 7 of 64
07098-005
P2D[3]
P2D[4]
P2D[5]
P2D[6]
P2D[7]
P2D[8]
DGND
DVDD18
P2D[9]
NC
NC
DVDD18
DGND
NC
P1D[0]
P1D[1]
P1D[2]
P1D[3]
26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
P1D[4]
NC = NO CONNECT
P2D[10]
CGND
ANALOG DOMAIN
P2D[11]
3
TXENABLE
CGND
PIN 1 INDICATOR
DVDD33
2
DATACLK
1
CVDD18
NC
CVDD18
AD9785/AD9787/AD9788
Pin No.
29
30
31, 34 to 36, 56 to 59
37
38, 61
39
40
41
42
45
46
47
48
49
50
51
52
55
62
63
65
66
67
68
69
70
71
73
Mnemonic
P1D[1]
P1D[0]
NC
DATACLK
DVDD33
TXENABLE
P2D[11]
P2D[10]
P2D[9]
P2D[8]
P2D[7]
P2D[6]
P2D[5]
P2D[4]
P2D[3]
P2D[2]
P2D[1]
P2D[0]
SYNC_O−
SYNC_O+
PLL_LOCK
SPI_SDO
SPI_SDIO
SCLK
SPI_CSB
RESET
IRQ
IPTAT
74
75
76, 78, 80, 96, 98, 100
83
84
86
87
89
90
92
93
Exposed Paddle
VREF
I120
AVDD33
OUT2_P
OUT2_N
AUX2_P
AUX2_N
AUX1_N
AUX1_P
OUT1_N
OUT1_P
EPAD
Description
Port 1, Data Input D1.
Port 1, Data Input D0 (LSB).
No Connection Necessary.
Data Clock Output.
3.3 V Digital Supply.
Transmit Enable.
Port 2, Data Input D11 (MSB).
Port 2, Data Input D10.
Port 2, Data Input D9.
Port 2, Data Input D8.
Port 2, Data Input D7.
Port 2, Data Input D6.
Port 2, Data Input D5.
Port 2, Data Input D4.
Port 2, Data Input D3.
Port 2, Data Input D2.
Port 2, Data Input D1.
Port 2, Data Input D0 (LSB).
Differential Synchronization Output, Negative.
Differential Synchronization Output, Positive.
PLL Lock Indicator.
SPI Port Data Output.
SPI Port Data Input/Output.
SPI Port Clock.
SPI Port Chip Select Bar.
Reset, Active High.
Interrupt Request.
Factory Test Pin. Output current is proportional to absolute temperature, approximately 10 μA at
25°C with approximately 20 nA/°C slope. This pin should remain floating.
Voltage Reference Output.
120 μA Reference Current.
3.3 V Analog Supply.
Differential DAC Current Output, Positive, Channel 2.
Differential DAC Current Output, Negative, Channel 2.
Auxiliary DAC Current Output, Positive, Channel 2.
Auxiliary DAC Current Output, Negative, Channel 2.
Auxiliary DAC Current Output, Negative, Channel 1.
Auxiliary DAC Current Output, Positive, Channel 1.
Differential DAC Current Output, Negative, Channel 1.
Differential DAC Current Output, Positive, Channel 1.
Conductive Heat Sink. Connect to analog common (AGND).
Rev. 0 | Page 8 of 64
AVDD33
AGND
AVDD33
AGND
AVDD33
AGND
AGND
OUT2_P
OUT2_N
AGND
AUX2_P
AUX2_N
AGND
AUX1_N
AUX1_P
AGND
OUT1_N
OUT1_P
AGND
AGND
AVDD33
AGND
AVDD33
AGND
AVDD33
AD9785/AD9787/AD9788
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76
75
I120
74
VREF
73
IPTAT
4
72
AGND
REFCLK+
5
71
IRQ
REFCLK–
6
70
RESET
CGND
7
69
SPI_CSB
CGND
8
68
SCLK
CVDD18
9
AD9787
67
SPI_SDIO
TOP VIEW
(Not to Scale)
66
SPI_SDO
65
PLL_LOCK
AGND 12
64
DGND
SYNC_I+ 13
63
SYNC_O+
SYNC_I– 14
62
SYNC_O–
DGND 15
61
DVDD33
DVDD18 16
60
DVDD18
P1D[13] 17
59
NC
P1D[12] 18
58
NC
P1D[11] 19
57
P2D[0]
P1D[10] 20
56
P2D[1]
P1D[9] 21
55
P2D[2]
DGND 22
54
DGND
DVDD18 23
53
DVDD18
P1D[8] 24
52
P2D[3]
P1D[7] 25
51
P2D[4]
DIGITAL DOMAIN
CVDD18 10
CGND 11
Figure 3. AD9787 Pin Configuration
Table 7. AD9787 Pin Function Descriptions
Pin No.
1, 2, 9, 10
3, 4, 7, 8, 11
5
6
12, 72, 77, 79, 81, 82, 85,
88, 91, 94, 95, 97, 99
13
14
15, 22, 32, 44, 54, 64
16, 23, 33, 43, 53, 60
17
18
19
20
21
24
25
26
27
28
29
30
Mnemonic
CVDD18
CGND
REFCLK+
REFCLK−
AGND
Description
1.8 V Clock Supply.
Clock Common.
Differential Clock Input, Positive.
Differential Clock Input, Negative.
Analog Common.
SYNC_I+
SYNC_I−
DGND
DVDD18
P1D[13]
P1D[12]
P1D[11]
P1D[10]
P1D[9]
P1D[8]
P1D[7]
P1D[6]
P1D[5]
P1D[4]
P1D[3]
P1D[2]
Differential Synchronization Input, Positive.
Differential Synchronization Input, Negative.
Digital Common.
1.8 V Digital Supply.
Port 1, Data Input D13 (MSB).
Port 1, Data Input D12.
Port 1, Data Input D11.
Port 1, Data Input D10.
Port 1, Data Input D9.
Port 1, Data Input D8.
Port 1, Data Input D7.
Port 1, Data Input D6.
Port 1, Data Input D5.
Port 1, Data Input D4.
Port 1, Data Input D3.
Port 1, Data Input D2.
Rev. 0 | Page 9 of 64
07098-004
P2D[5]
P2D[6]
P2D[7]
P2D[8]
P2D[9]
P2D[10]
DGND
DVDD18
P2D[11]
NC
P1D[0]
DVDD18
DGND
P1D[1]
P1D[2]
P1D[3]
P1D[4]
P1D[5]
26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
P1D[6]
NC = NO CONNECT
P2D[12]
CGND
ANALOG DOMAIN
P2D[13]
3
TXENABLE
CGND
PIN 1 INDICATOR
DVDD33
2
DATACLK
1
CVDD18
NC
CVDD18
AD9785/AD9787/AD9788
Pin No.
31
34
35, 36, 58, 59
37
38, 61
39
40
41
42
45
46
47
48
49
50
51
52
55
56
57
62
63
65
66
67
68
69
70
71
73
Mnemonic
P1D[1]
P1D[0]
NC
DATACLK
DVDD33
TXENABLE
P2D[13]
P2D[12]
P2D[11]
P2D[10]
P2D[9]
P2D[8]
P2D[7]
P2D[6]
P2D[5]
P2D[4]
P2D[3]
P2D[2]
P2D[1]
P2D[0]
SYNC_O−
SYNC_O+
PLL_LOCK
SPI_SDO
SPI_SDIO
SCLK
SPI_CSB
RESET
IRQ
IPTAT
74
75
76, 78, 80, 96, 98, 100
83
84
86
87
89
90
92
93
Exposed Paddle
VREF
I120
AVDD33
OUT2_P
OUT2_N
AUX2_P
AUX2_N
AUX1_N
AUX1_P
OUT1_N
OUT1_P
EPAD
Description
Port 1, Data Input D1.
Port 1, Data Input D0 (LSB).
No Connection Necessary.
Data Clock Output.
3.3 V Digital Supply.
Transmit Enable.
Port 2, Data Input D13 (MSB).
Port 2, Data Input D12.
Port 2, Data Input D11.
Port 2, Data Input D10.
Port 2, Data Input D9.
Port 2, Data Input D8.
Port 2, Data Input D7.
Port 2, Data Input D6.
Port 2, Data Input D5.
Port 2, Data Input D4.
Port 2, Data Input D3.
Port 2, Data Input D2.
Port 2, Data Input D1.
Port 2, Data Input D0 (LSB).
Differential Synchronization Output, Negative.
Differential Synchronization Output, Positive.
PLL Lock Indicator.
SPI Port Data Output.
SPI Port Data Input/Output.
SPI Port Clock.
SPI Port Chip Select Bar.
Reset, Active High.
Interrupt Request.
Factory Test Pin. Output current is proportional to absolute temperature, approximately 10 μA
at 25°C with approximately 20 nA/°C slope. This pin should remain floating.
Voltage Reference Output.
120 μA Reference Current.
3.3 V Analog Supply.
Differential DAC Current Output, Positive, Channel 2.
Differential DAC Current Output, Negative, Channel 2.
Auxiliary DAC Current Output, Positive, Channel 2.
Auxiliary DAC Current Output, Negative, Channel 2.
Auxiliary DAC Current Output, Negative, Channel 1.
Auxiliary DAC Current Output, Positive, Channel 1.
Differential DAC Current Output, Negative, Channel 1.
Differential DAC Current Output, Positive, Channel 1.
Conductive Heat Sink. Connect to analog common (AGND).
Rev. 0 | Page 10 of 64
AVDD33
AGND
AVDD33
AGND
AVDD33
AGND
AGND
OUT2_P
OUT2_N
AGND
AUX2_P
AUX2_N
AGND
AUX1_N
AUX1_P
AGND
OUT1_N
OUT1_P
AGND
AGND
AVDD33
AGND
AVDD33
AGND
AVDD33
AD9785/AD9787/AD9788
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76
CVDD18
1
CVDD18
2
75
I120
74
CGND
3
VREF
73
CGND
IPTAT
4
72
AGND
REFCLK+
5
71
IRQ
REFCLK–
6
70
RESET
CGND
7
69
SPI_CSB
CGND
8
68
SCLK
CVDD18
9
AD9788
67
SPI_SDIO
TOP VIEW
(Not to Scale)
66
SPI_SDO
65
PLL_LOCK
AGND 12
64
DGND
SYNC_I+ 13
63
SYNC_O+
SYNC_I– 14
62
SYNC_O–
DGND 15
61
DVDD33
DVDD18 16
60
DVDD18
P1D[15] 17
59
P2D[0]
P1D[14] 18
58
P2D[1]
P1D[13] 19
57
P2D[2]
P1D[12] 20
56
P2D[3]
P1D[11] 21
55
P2D[4]
DGND 22
54
DGND
DVDD18 23
53
DVDD18
P1D[10] 24
52
P2D[5]
P1D[9] 25
51
P2D[6]
PIN 1 INDICATOR
ANALOG DOMAIN
DIGITAL DOMAIN
CVDD18 10
CGND 11
Figure 4. AD9788 Pin Configuration
Table 8. AD9788 Pin Function Descriptions
Pin No.
1, 2, 9, 10
3, 4, 7, 8, 11
5
6
12, 72, 77, 79, 81, 82, 85,
88, 91, 94, 95, 97, 99
13
14
15, 22, 32, 44, 54, 64
16, 23, 33, 43, 53, 60
17
18
19
20
21
24
25
26
27
28
29
30
Mnemonic
CVDD18
CGND
REFCLK+
REFCLK−
AGND
Description
1.8 V Clock Supply.
Clock Common.
Differential Clock Input, Positive.
Differential Clock Input, Negative.
Analog Common.
SYNC_I+
SYNC_I−
DGND
DVDD18
P1D[15]
P1D[14]
P1D[13]
P1D[12]
P1D[11]
P1D[10]
P1D[9]
P1D[8]
P1D[7]
P1D[6]
P1D[5]
P1D[4]
Differential Synchronization Input, Positive.
Differential Synchronization Input, Negative.
Digital Common.
1.8 V Digital Supply.
Port 1, Data Input D15 (MSB).
Port 1, Data Input D14.
Port 1, Data Input D13.
Port 1, Data Input D12.
Port 1, Data Input D11.
Port 1, Data Input D10.
Port 1, Data Input D9.
Port 1, Data Input D8.
Port 1, Data Input D7.
Port 1, Data Input D6.
Port 1, Data Input D5.
Port 1, Data Input D4.
Rev. 0 | Page 11 of 64
07098-003
P2D[7]
P2D[8]
P2D[9]
P2D[10]
P2D[11]
P2D[12]
DGND
DVDD18
P2D[13]
P2D[14]
P2D[15]
TXENABLE
DVDD33
DATACLK
P1D[0]
P1D[1]
P1D[2]
DVDD18
DGND
P1D[3]
P1D[4]
P1D[5]
P1D[6]
P1D[7]
P1D[8]
26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
AD9785/AD9787/AD9788
Pin No.
31
34
35
36
37
38, 61
39
40
41
42
45
46
47
48
49
50
51
52
55
56
57
58
59
62
63
65
66
67
68
69
70
71
73
Mnemonic
P1D[3]
P1D[2]
P1D[1]
P1D[0]
DATACLK
DVDD33
TXENABLE
P2D[15]
P2D[14]
P2D[13]
P2D[12]
P2D[11]
P2D[10]
P2D[9]
P2D[8]
P2D[7]
P2D[6]
P2D[5]
P2D[4]
P2D[3]
P2D[2]
P2D[1]
P2D[0]
SYNC_O−
SYNC_O+
PLL_LOCK
SPI_SDO
SPI_SDIO
SCLK
SPI_CSB
RESET
IRQ
IPTAT
74
75
76, 78, 80, 96, 98, 100
83
84
86
87
89
90
92
93
Exposed Paddle
VREF
I120
AVDD33
OUT2_P
OUT2_N
AUX2_P
AUX2_N
AUX1_N
AUX1_P
OUT1_N
OUT1_P
EPAD
Description
Port 1, Data Input D3.
Port 1, Data Input D2.
Port 1, Data Input D1.
Port 1, Data Input D0 (LSB).
Data Clock Output.
3.3 V Digital Supply.
Transmit Enable.
Port 2, Data Input D15 (MSB).
Port 2, Data Input D14.
Port 2, Data Input D13.
Port 2, Data Input D12.
Port 2, Data Input D11.
Port 2, Data Input D10.
Port 2, Data Input D9.
Port 2, Data Input D8.
Port 2, Data Input D7.
Port 2, Data Input D6.
Port 2, Data Input D5.
Port 2, Data Input D4.
Port 2, Data Input D3.
Port 2, Data Input D2.
Port 2, Data Input D1.
Port 2, Data Input D0 (LSB).
Differential Synchronization Output, Negative.
Differential Synchronization Output, Positive.
PLL Lock Indicator.
SPI Port Data Output.
SPI Port Data Input/Output.
SPI Port Clock.
SPI Port Chip Select Bar.
Reset, Active High.
Interrupt Request.
Factory Test Pin. Output current is proportional to absolute temperature, approximately 10 μA
at 25°C with approximately 20 nA/°C slope. This pin should remain floating.
Voltage Reference Output.
120 μA Reference Current.
3.3 V Analog Supply.
Differential DAC Current Output, Positive, Channel 2.
Differential DAC Current Output, Negative, Channel 2.
Auxiliary DAC Current Output, Positive, Channel 2.
Auxiliary DAC Current Output, Negative, Channel 2.
Auxiliary DAC Current Output, Negative, Channel 1.
Auxiliary DAC Current Output, Positive, Channel 1.
Differential DAC Current Output, Negative, Channel 1.
Differential DAC Current Output, Positive, Channel 1.
Conductive Heat Sink. Connect to analog common (AGND).
Rev. 0 | Page 12 of 64
AD9785/AD9787/AD9788
TYPICAL PERFORMANCE CHARACTERISTICS
–142
100
95
–146
250 MSPS
85
2×
SFDR (dB)
NSD (dBm/Hz)
–150
–154
1×
–158
200 MSPS
90
4×
160 MSPS
80
75
70
65
–162
60
–166
0
20
40
60
80
100
fOUT (MHz)
50
0
20
40
60
100
80
fOUT (MHz)
Figure 5. AD9785 Noise Spectral Density vs. fOUT, Multitone Input,
fDATA = 200 MSPS
07098-067
55
07098-064
–170
Figure 8. AD9785 In-Band SFDR vs. fOUT, 2× Interpolation
–142
100
–146
90
2×
150 MSPS
4×
IMD (dBc)
NSD (dBm/Hz)
–150
–154
–158
1×
80
70
–162
100 MSPS
60
200 MSPS
20
40
60
80
100
fOUT (MHz)
50
0
80
400
80 100 120 140 160 180 200 220 240 260
120
160
200
240
280
320
360
fOUT (MHz)
Figure 6. AD9785 Noise Spectral Density vs. fOUT, Single-Tone Input,
fDATA = 200 MSPS
Figure 9. AD9785 IMD vs. fOUT, 4× Interpolation
–55
–55
–60
–60
–65
–65
ACLR (dBc)
FIRST ADJ CHAN
–70
–75
–70
FIRST ADJ CHAN
–75
SECOND ADJ CHAN
–85
–90
SECOND ADJ CHAN
–80
–80
–85
THIRD ADJ CHAN
0
20
40
60
80 100 120 140 160 180 200 220 240 260
fOUT (MHz)
–90
07098-066
ACLR (dBc)
40
07098-068
0
07098-065
–170
07098-069
–166
THIRD ADJ CHAN
0
20
40
60
fOUT (MHz)
Figure 10. AD9787 ACLR, 4× Interpolation, fDATA = 122.88 MSPS
Figure 7. AD9785 ACLR, 4× Interpolation, fDATA = 122.88 MSPS
Rev. 0 | Page 13 of 64
–142
–60
–146
–65
–150
NSD (dBm/Hz)
–55
–70
FIRST ADJ CHAN
–75
SECOND ADJ CHAN
–85
–90
20
40
60
–158
1×
2×
4×
–162
–166
THIRD ADJ CHAN
0
–154
80 100 120 140 160 180 200 220 240 260
fOUT (MHz)
–170
0
20
40
60
80
100
07098-073
–80
07098-070
ACLR (dBc)
AD9785/AD9787/AD9788
fOUT (MHz)
Figure 14. AD9787 Noise Spectral Density vs. fOUT over Output Frequency of
Multitone Input, fDATA = 200 MSPS
Figure 11. AD9787 ACLR, 4× Interpolation, fDATA = 122.88 MSPS,
Amplitude = −3 dB
–142
100
–146
90
NSD (dBm/Hz)
IMD (dBc)
–150
80
200MSPS
100MSPS
70
–154
1×
–158
2×
4×
–162
150MSPS
60
0
40
80
120
160
200
240
280
320
360
400
fOUT (MHz)
–170
07098-071
50
20
40
60
80
100
fOUT (MHz)
Figure 15. AD9787 Noise Spectral Density vs. fOUT, Single-Tone Input,
fDATA = 200 MSPS
Figure 12. AD9787 IMD vs. fOUT, 4× Interpolation
–55
100
95
–60
90
0 dBFS PLL ON
160MSPS
–65
85
ACLR (dBc)
250MSPS
80
200MSPS
75
70
65
–70
0 dBFS PLL OFF
–3 dBFS PLL OFF
–75
–80
60
–85
50
0
20
40
60
80
fOUT (MHz)
Figure 13. AD9787 In-Band SFDR vs. fOUT, 2× Interpolation
100
–90
–6 dBFS PLL OFF
0
20
40
60
80 100 120 140 160 180 200 220 240 260
fOUT (MHz)
07098-076
55
07098-072
SFDR (dB)
0
07098-074
–166
Figure 16. AD9788 ACLR for First Adjacent Band WCDMA, 4× Interpolation,
fDATA = 122.88 MSPS, NCO Translates Baseband Signal to IF
Rev. 0 | Page 14 of 64
AD9785/AD9787/AD9788
–55
100
–60
200MSPS
90
0 dBFS PLL ON
–70
IMD (dBc)
ACLR (dBc)
–65
–6 dBFS PLL OFF
–75
80
160MSPS
250MSPS
70
–80
60
–85
–3 dBFS PLL OFF
20
40
60
80 100 120 140 160 180 200 220 240 260
fOUT (MHz)
50
0
50
100
150
200
07098-080
0
0 dBFS PLL OFF
07098-077
–90
fOUT (MHz)
Figure 17. AD9788 ACLR for Second Adjacent Band WCDMA,
4× Interpolation, fDATA = 122.88 MSPS, NCO Translates Baseband Signal to IF
Figure 20. AD9788 IMD vs. fOUT, 2× Interpolation
–70
100
90
–75
40
60
70
200MSPS
60
0 dBFS PLL OFF
80 100 120 140 160 180 200 220 240 260
fOUT (MHz)
50
0
120
160
200
240
280
320
360
400
200
Figure 21. AD9788 IMD vs. fOUT, 4× Interpolation
100
100
160MSPS
90
90
250MSPS
IMD (dBc)
80
200MSPS
70
80
PLL ON
70
PLL OFF
60
60
0
20
40
60
80
100
fOUT (MHz)
120
07098-079
IMD (dBc)
80
fOUT (MHz)
Figure 18. AD9788 ACLR for Third Adjacent Band WCDMA, 4× Interpolation,
fDATA = 122.88 MSPS, NCO Translates Baseband Signal to IF
50
40
07098-081
20
150MSPS
100MSPS
–3 dBFS PLL OFF
0
80
07098-082
–85
–90
IMD (dBc)
–6 dBFS PLL OFF
–80
07098-078
ACLR (dBc)
0 dBFS PLL ON
50
0
20
40
60
80
100
120
140
160
180
fOUT (MHz)
Figure 22. AD9788 IMD vs. fOUT, 8× Interpolation, fDATA = 100 MSPS,
PLL On/PLL Off
Figure 19. AD9788 IMD vs. fOUT, 1× Interpolation
Rev. 0 | Page 15 of 64
AD9785/AD9787/AD9788
100
100
95
90
90
80
80
IMD (dBc)
IMD (dBc)
85
75MSPS
70
50MSPS
75
70
100MSPS
65
60
60
55
50
100
150
200
250
300
350
400
450
fOUT (MHz)
50
0
40
80
120
160
200
240
280
320
360
400
07098-086
0
07098-083
50
fOUT (MHz)
Figure 23. AD9788 IMD vs. fOUT, 8× Interpolation
Figure 26. AD9788 IMD vs. fOUT, over 50 Parts, 4× Interpolation,
fDATA = 200 MSPS
–142
100
–146
90
80
NSD (dBm/Hz)
IMD (dBc)
–150
–6dBFS
0dBFS
–3dBFS
70
–154
–3dBFS
–158
0dBFS
–162
–6dBFS
60
0
40
80
120
160
200
240
280
320
360
400
fOUT (MHz)
–170
07098-084
50
0
20
40
60
80
100
fOUT (MHz)
07098-087
–166
Figure 27. AD9788 Noise Spectral Density vs. Digital Full-Scale Single-Tone
Input, fDATA = 200 MSPS, 2× Interpolation
Figure 24. AD9788 IMD Performance vs. Digital Full-Scale Input,
4× Interpolation, fDATA = 200 MSPS
–142
100
–146
90
–150
NSD (dBm/Hz)
IMD (dBc)
20mA
80
30mA
70
–154
–158
2×
–162
10mA
4×
8×
60
0
40
80
120
160
200
240
280
320
360
400
fOUT (MHz)
–170
0
10
20
30
40
50
fOUT (MHz)
Figure 28. AD9788 Noise Spectral Density vs. fOUT, Multitone Input,
fDATA = 100 MSPS
Figure 25. AD9788 IMD Performance vs. Full-Scale Output Current,
4× Interpolation, fDATA = 200 MSPS
Rev. 0 | Page 16 of 64
07098-088
50
07098-085
–166
AD9785/AD9787/AD9788
–142
90
–146
85
160MSPS
75
SFDR (dB)
–154
–158
2×
250MSPS
65
4×
–162
60
8×
–166
55
0
10
20
30
40
50
07098-089
–170
70
50
fOUT (MHz)
0
20
40
60
80
100
fOUT (MHz)
Figure 29. AD9788 Noise Spectral Density vs. fOUT, Single-Tone Input,
fDATA = 100 MSPS
07098-092
NSD (dBm/Hz)
–150
Figure 32. AD9788 In-Band SFDR vs. fOUT, 1× Interpolation
80
–142
–146
75
–150
250MSPS
200MSPS
70
SFDR (dB)
NSD (dBm/Hz)
200MSPS
80
–154
–158
1×
2×
160MSPS
65
60
–162
4×
0
20
40
60
80
50
07098-090
–170
100
fOUT (MHz)
0
10
20
30
40
50
60
70
80
90
100
fOUT (MHz)
Figure 30. AD9788 Noise Spectral Density vs. fDAC, Eight-Tone Input
with 500 kHz Spacing, fDATA = 200 MSPS
07098-093
55
–166
Figure 33. AD9788 Out-of-Band SFDR vs. fOUT, 2× Interpolation
–142
95
90
–146
10mA
85
20mA
–150
SFDR (dB)
NSD (dBm/Hz)
80
–154
1×
–158
2×
75
30mA
70
65
–162
4×
60
–166
20
40
60
fOUT (MHz)
80
100
Figure 31. AD9788 Noise Spectral Density vs. fDAC, Full-Scale Single-Tone
Input at −6 dB, fDATA = 200 MSPS
Rev. 0 | Page 17 of 64
50
0
10
20
30
40
50
60
70
80
fOUT (MHz)
Figure 34. AD9788 In-Band SFDR vs. Full-Scale Output Current,
2× Interpolation, fDATA = 200 MSPS
07098-094
0
07098-091
–170
55
AD9785/AD9787/AD9788
110
100
100MSPS
95
100
150MSPS
250MSPS
85
90
200MSPS
SFDR (dB)
SFDR (dB)
160MSPS
90
80
70
200MSPS
80
75
70
65
60
60
10
20
30
40
50
60
70
80
90
fOUT (MHz)
50
07098-095
0
100MSPS
80
100
50MSPS
150MSPS
90
80
60
70
55
60
20
30
40
50
60
70
80
90
fOUT (MHz)
50
07098-096
10
20
30
40
50
45
Figure 39. AD9788 In-Band SFDR vs. fOUT, 8× Interpolation
90
–3dBFS
0dBFS
10
fOUT (MHz)
Figure 36. AD9788 Out-of-Band SFDR vs. fOUT, 4× Interpolation
90
0
07098-099
65
07098-100
SFDR (dB)
200MSPS
0
100MSPS
100
70
SFDR (dB)
60
110
75
50MSPS
85
85
80
80
–6dBFS
75
100MSPS
SFDR (dB)
75
70
65
70
65
60
60
55
55
0
10
20
30
40
50
60
70
80
fOUT (MHz)
07098-097
SFDR (dB)
40
Figure 38. AD9788 In-Band SFDR vs. fOUT, 2× Interpolation
80
50
20
fOUT (MHz)
Figure 35. AD9788 In-Band SFDR vs. fOUT, 4× Interpolation
50
0
07098-098
55
50
50
0
5
10
15
20
25
30
35
40
fOUT (MHz)
Figure 40. AD9788 Out-of-Band SFDR vs. fOUT, 8× Interpolation
Figure 37. AD9788 In-Band SFDR vs. Digital Full-Scale Input,
2× Interpolation, fDATA = 200 MSPS
Rev. 0 | Page 18 of 64
AD9785/AD9787/AD9788
110
PLL OFF
100
PLL ON
SFDR (dB)
90
80
70
50
0
10
20
30
fOUT (MHz)
40
50
07098-101
60
Figure 41. AD9788 In-Band SFDR vs. fOUT, 4× Interpolation, fDATA = 100 MSPS,
PLL On/PLL Off
Rev. 0 | Page 19 of 64
AD9785/AD9787/AD9788
TERMINOLOGY
Integral Nonlinearity (INL)
INL is defined as the maximum deviation of the actual analog
output from the ideal output, determined by a straight line
drawn from zero scale to full scale.
Differential Nonlinearity (DNL)
DNL is the measure of the variation in analog value, normalized
to full scale, associated with a 1 LSB change in digital input code.
Monotonicity
A DAC is monotonic if the output either increases or remains
constant as the digital input increases.
Offset Error
The deviation of the output current from the ideal of zero is
called offset error. For IOUTA, 0 mA output is expected when the
inputs are all 0s. For IOUTB, 0 mA output is expected when all
inputs are set to 1.
Gain Error
The difference between the actual and ideal output span is
called gain error. The actual span is determined by the difference between the output when all inputs are set to 1 and the
output when all inputs are set to 0.
Output Compliance Range
The output compliance range is the range of allowable voltage
at the output of a current output DAC. Operation beyond the
maximum compliance limits can cause either output stage
saturation or breakdown, resulting in nonlinear performance.
Temperature Drift
Temperature drift is specified as the maximum change from the
ambient (25°C) value to the value at either TMIN or TMAX. For
offset and gain drift, the drift is reported in ppm of full-scale
range (FSR) per degree Celsius. For reference drift, the drift is
reported in ppm per degree Celsius.
Power Supply Rejection (PSR)
PSR is the maximum change in the full-scale output as the
supplies are varied from minimum to maximum specified
voltages.
Spurious-Free Dynamic Range (SFDR)
Spurious-free dynamic range is the difference, in decibels,
between the peak amplitude of the output signal and the peak
amplitude of the largest spurious signal in a given frequency
band from the signal. For out-of-band SFDR, the frequency
band is 0 to one half the DAC sample rate. For in-band SFDR,
the frequency band is 0 to one half the input data rate.
Total Harmonic Distortion (THD)
THD is the ratio of the rms sum of the first six harmonic components to the rms value of the measured fundamental. It is
expressed as a percentage or in decibels.
Noise Spectral Density (NSD)
NSD is the noise power at the analog output measured in a 1 Hz
bandwidth.
Interpolation Filter
If the digital inputs to the DAC are sampled at a multiple rate of
fDATA (interpolation rate), a digital filter can be constructed that
has a sharp transition band near fDATA/2. Images that typically
appear around fDAC (output data rate) can be greatly suppressed.
Adjacent Channel Leakage Ratio (ACLR)
ACLR is the ratio in dBc between the measured power within a
channel relative to its adjacent channel.
Complex Image Rejection
In a traditional two-part upconversion, two images are created
around the second intermediate frequency (IF). These images
have the effect of wasting transmitter power and system bandwidth. By placing the real part of a second complex modulator
in series with the first complex modulator, either the upper or
lower frequency image near the second IF can be rejected.
Sinc
Sinc is shorthand for the mathematical function
sinc(x) = sin(x)/x
This function is a useful tool for digital signal processing. The
normalized sinc function is used here and is defined as follows:
sinc(x) = sin(π × x)/(π × x)
Settling Time
Settling time is the time required for the output to reach and
remain within a specified error band around its final value,
measured from the start of the output transition.
Rev. 0 | Page 20 of 64
AD9785/AD9787/AD9788
THEORY OF OPERATION
The AD9785/AD9787/AD9788 devices combine many features
that make them very attractive DACs for wired and wireless
communications systems. The dual digital signal path and dual
DAC structure allow an easy interface to common quadrature
modulators when designing single sideband transmitters. The
speed and performance of the AD9785/AD9787/AD9788 allow
wider bandwidths and more carriers to be synthesized than in
previously available DACs. In addition, these devices include
an innovative low power, 32-bit complex NCO that greatly
increases the ease of frequency placement.
SERIAL PORT INTERFACE
The AD9785/AD9787/AD9788 serial port is a flexible,
synchronous serial communications port allowing easy
interface to many industry-standard microcontrollers and
microprocessors. The serial I/O is compatible with most
synchronous transfer formats, including both the Motorola®
6905/11 SPI and the Intel® 8051 SSR protocols.
The serial interface allows read/write access to all registers that
configure the AD9785/AD9787/AD9788. MSB first and LSB
first transfer formats are supported. In addition, the serial
interface port can be configured as a single-pin I/O (SDIO),
which allows a 3-wire interface, or two unidirectional pins for
input/output (SDIO/SDO), which enables a 4-wire interface.
One optional pin, SPI_CSB (chip select), allows enabling of
multiple devices on a single bus.
The AD9785/AD9787/AD9788 offer features that allow
simplified synchronization with incoming data and between
multiple parts, as well as the capability to phase synchronize
NCOs on multiple devices. Auxiliary DACs are also provided
on chip for output dc offset compensation (for LO compensation in SSB transmitters) and for gain matching (for image
rejection optimization in SSB transmitters). Another innovative
feature in the devices is the digitally programmable output
phase compensation, which increases the amount of image
cancellation capability in SSB (single sideband) transmitters.
With the AD9785/AD9787/AD9788, the instruction byte
specifies read/write operation and the register address. Serial
operations on the AD9785/AD9787/AD9788 occur only at the
register level, not at the byte level, due to the lack of byte
address space in the instruction byte.
+
×
SIN(×)
+
FREQUENCY
16-BIT
DAC2
OUT2_P
16
1
PHASE
CORRECTION
10
AUX1
INTERNAL CLOCK TIMING AND CONTROL LOGIC
1
0
LVDS
DELAY
LINE
DELAY
LINE
MULTICHIP
SYNCHRONIZATION
PROGRAMMING
REGISTERS
SERIAL
I/O
PORT
POWER-ON
RESET
Figure 42. Functional Block Diagram
Rev. 0 | Page 21 of 64
DAC_CLK
AUX2
OUT2_N
VREF
RESET
AUX1_P
AUX1_N
AUX2_P
AUX2_N
0
1
CLOCK
MULTIPLIER
(2× – 16×)
PLL_LOCK
SYNC_I
LVDS
IRQ
RESET
SYNC_O
10
PLL CONTROL
DELAY
LINE
SPI_SDO
SPI_SDIO
SCLK
SPI_CSB
DATACLK
OUT1_N
CLK
RCVR
REFCLK+
REFCLK–
07098-002
0
Q-OFFSET
REFERENCE
AND BIAS
Q-SCALE
GAIN2
2
1
0
OUT1_P
10
32
GAIN1
3
16
θ
NCO
ω
10
16 SIN
10
16 COS
3
16-BIT
DAC1
I-OFFSET
I-SCALE
INV_SINC_EN
QUAD
HB
FILTER
(2×)
16
0
1
PHASE
QUAD
HB
FILTER
(2×)
×
SIN(×)
+
INTERPOLATION
FACTOR
16
HB1_CLK
P2D[15:0]
QUAD
HB
FILTER
(2×)
HB3_CLK
16
P1D[15:0]
HB2_CLK
TXENABLE
DATA ASSEMBLER
+
0
1
2
AD9785/AD9787/AD9788
For example, when accessing the frequency tuning word (FTW)
register, which is four bytes wide, Phase 2 requires that four
bytes be transferred. If accessing the amplitude scale factor (ASF)
register, which is three bytes wide, Phase 2 requires that three
bytes be transferred. After transferring all data bytes per the
instruction byte, the communication cycle is completed.
At the completion of any communication cycle, the AD9785/
AD9787/AD9788 serial port controller expects the next eight
rising SCLK edges to be the instruction byte of the next
communication cycle.
All data input is registered on the rising edge of SCLK. All data
is driven out of the AD9785/AD9787/AD9788 on the falling
edge of SCLK.
INSTRUCTION CYCLE
DATA TRANSFER CYCLE
SPI_CSB
SPI_SDIO
R/W N1
N0
A4 A3
A2 A1
A0
SPI_SDO
D7 D6N D5N
D3 0 D20 D10 D00
D7 D6N D5 N
D3 0 D20 D10 D00
07098-006
SCLK
Figure 43. Serial Register Interface Timing, MSB First
INSTRUCTION CYCLE
DATA TRANSFER CYCLE
SPI_CSB
SCLK
SPI_SDIO
A0
A1
A2
A3 A4
N0 N1 R/W D00 D10 D20
D4N D5N D6N D7 N
D00 D10 D20
D4N D5 N D6N D7N
SPI_SDO
07098-007
The first eight SCLK rising edges of each communication cycle
are used to write the instruction byte into the AD9785/AD9787/
AD9788. The remaining SCLK edges are for Phase 2 of the
communication cycle. Phase 2 is the actual data transfer
between the AD9785/AD9787/AD9788 and the system
controller. The number of bytes transferred during Phase 2 of
the communication cycle is a function of the register being
accessed.
Figure 43 through Figure 46 are useful in understanding the
general operation of the AD9785/AD9787/AD9788 serial port.
Figure 44. Serial Register Interface Timing, LSB First
tDS
tSCLK
SPI_CSB
tPWH
tPWL
SCLK
tDS
SPI_SDIO
tDH
INSTRUCTION BIT 7
INSTRUCTION BIT 6
07098-008
There are two phases to a communication cycle with the
AD9785/AD9787/AD9788. Phase 1 is the instruction cycle,
which is the writing of an instruction byte into the AD9785/
AD9787/AD9788, coincident with the first eight SCLK rising
edges. The instruction byte provides the AD9785/AD9787/
AD9788 serial port controller with information regarding the
data transfer cycle, which is Phase 2 of the communication
cycle. The instruction byte defines whether the upcoming data
transfer is read or write and the serial address of the register
being accessed.
Figure 45. SPI Register Write Timing
SPI_CSB
tDV
SPI_SDIO
SPI_SDO
DATA BIT n
DATA BIT n–1
Figure 46. SPI Register Read Timing Instruction Byte
Rev. 0 | Page 22 of 64
07098-009
SCLK
AD9785/AD9787/AD9788
Instruction Byte
SPI_SDO—Serial Data Output
The instruction byte contains the following information as
shown in the instruction byte bit map.
Instruction Byte Information Bit Map
MSB
LSB
D7
D6
D5
D4
D3
D2
D1
D0
R/W
X
X
A4
A3
A2
A1
A0
R/W—Bit 7 of the instruction byte determines whether a read
or write data transfer occurs after the instruction byte write.
Logic 1 indicates a read operation. Logic 0 indicates a write
operation.
X, X —Bit 6 and Bit 5 of the instruction byte are don’t care. In
previous TxDACs, such as the AD9779, these bits define the
number of registers written to or read from in an SPI read/write
operation. In the AD9785/AD9787/AD9788, the register itself
now defines how many bytes are written to or read from.
A4, A3, A2, A1, A0—Bit 4, Bit 3, Bit 2, Bit 1, and Bit 0 of the
instruction byte determine which register is accessed during the
data transfer portion of the communication cycle.
Serial Interface Port Pin Description
SCLK—Serial Clock
The serial clock pin is used to synchronize data to and from the
AD9785/AD9787/AD9788 and to run the internal state machines.
SCLK maximum frequency is 40 MHz.
SPI_CSB—Chip Select
Active low input that allows more than one device on the same
serial communications line. The SPI_SDO and SPI_SDIO pins
go to a high impedance state when this input is high. If driven
high during any communication cycle, that cycle is suspended
until SPI_CSB is reactivated low. Chip select can be tied low in
systems that maintain control of SCLK.
Data is read from this pin for protocols that use separate lines
for transmitting and receiving data. In the case where the
AD9785/AD9787/AD9788 operate in a single bidirectional
I/O mode, this pin does not output data and is set to a high
impedance state.
MSB/LSB Transfers
The AD9785/AD9787/AD9788 serial port can support both
most significant bit (MSB) first or least significant bit (LSB)
first data formats. This functionality is controlled by Bit 6 of the
communication (COMM) register. The default value of COMM
Register Bit 6 is low (MSB first). When COMM Register Bit 6 is
set high, the serial port is in LSB first format. The instruction byte
must be written in the format indicated by COMM Register Bit 6.
That is, if the device is in LSB first mode, the instruction byte
must be written from least significant bit to most significant bit.
For MSB first operation, the serial port controller generates the
most significant byte (of the specified register) address first,
followed by the next lesser significant byte addresses until the
I/O operation is complete. All data written to or read from the
AD9785/AD9787/AD9788 must be in MSB first order.
If the LSB mode is active, the serial port controller generates the
least significant byte address first, followed by the next greater
significant byte addresses until the I/O operation is complete.
All data written to or read from the AD9785/AD9787/AD9788
must be in LSB first order.
SPI Resynchronization Capability
If the SPI port becomes unsynchronized at any time, toggling
SCLK for eight or more cycles with SPI_CSB held high resets
the SPI port state machine. The device is then ready for the next
register read or write access.
SPI_SDIO—Serial Data I/O
Data is always written into the AD9785/AD9787/AD9788 on
this pin. However, this pin can be used as a bidirectional data
line. Bit 7 of Register 0x00 controls the configuration of this pin.
The default is Logic 0, which configures the SPI_SDIO pin as
bidirectional.
Rev. 0 | Page 23 of 64
AD9785/AD9787/AD9788
SPI REGISTER MAP
When reading Table 9, note that the AD9785/AD9787/AD9788 is a 32-bit part and, therefore, the 4th through the 11th columns (beginning
with the MSB and ending with the LSB) represent a set of eight bits. Refer to the Bit Range column for the actual bits being described.
Table 9.
Address
0x00
0x01
Register
Name
Comm.
(COMM)
Register
Bit
Range
[7:0]
Digital
Control
Register
0x02
Data Sync
Control
Register
0x03
Multichip
Sync
Control
Register
MSB − 2
Software
reset
MSB − 3
Powerdown
mode
[7:0]
MSB
MSB − 1
SPI_SDIO
LSB first
bidirectional
(active high,
3-wire)
Interpolation Factor [1:0]
Data
format
[15:8]
Reserved
Clear phase
accumulator
[7:0]
Data Timing
Margin [0]
LVDS data
clock enable
PN code
sync
enable
DATACLK
invert
Singleport
mode
Sync
mode
select
DATACLK
delay
enable
[15:8]
[7:0]
[15:8]
[23:16]
[31:24]
0x04
PLL
Control
Register
[7:0]
[15:8]
[23:16]
[7:0]
[15:8]
0x05
I DAC
Control
Register
0x06
Auxiliary
DAC 1
Control
Register
[7:0]
[15:8]
0x07
Q DAC
Control
Register
[7:0]
[15:8]
0x08
Auxiliary
DAC 2
Control
Register
[7:0]
[15:8]
0x09
Interrupt
Control
Register
[7:0]
[15:8]
0x0A
Frequency
Tuning
Word
Register
[31:0]
DATACLK Delay [4:0]
Clock State [3:0]
SYNC _O Delay [4:0]
MSB − 4
Auto
powerdown
enable
Real
mode
MSB − 5
I/O
transfer
(selfreset)
IQ select
invert
MSB − 6
Automatic
I/O
transfer
enable
Q first
Pulse
sync
enable
Data
timing
mode
Spectral
inversion
Inverse
sinc
enable
Data sync
polarity
Set low
LSB
Open
Default
0x02
Modulator
gain
control
DATACLK
output
enable
Reserved
0x00
Data Timing Margin [3:1]
Sync Timing Margin [3:0]
SYNC_O
Sync
Set high
polarity
loopback
enable
Set low
DATACLK
SYNC_I Delay [4:0]
Sync
input
error
check
mode
Correlate Threshold [4:0]
SYNC _I
SYNC _O
Set low
enable
enable
PLL Band Select [5:0]
PLL VCO Drive [1:0]
PLL enable
PLL VCO Divisor [1:0]
PLL Loop Divisor [1:0]
PLL Bias [2:0]
VCO Control Voltage [2:0]
PLL Loop Bandwidth [4:0]
I DAC Gain Adjustment [7:0]
I DAC sleep
I DAC
Reserved
I DAC Gain Adjustment
power-down
[9:8]
Auxiliary DAC 1 Data [7:0]
Reserved
Auxiliary DAC 1 Data
Auxiliary
Auxiliary
Auxiliary
[9:8]
DAC 1
DAC 1 sign
DAC 1
powercurrent
down
direction
Q DAC Gain Adjustment [7:0]
Q DAC sleep
Q DAC
Reserved
Q DAC Gain Adjustment
power-down
[9:8]
Auxiliary DAC 2 Data [7:0]
Reserved
Auxiliary DAC 2 Data
Auxiliary
Auxiliary
Auxiliary
[9:8]
DAC 2
DAC 2 sign
DAC 2
powercurrent
down
direction
PLL lock
Reserved Data port
Sync port
Sync
Data timing
Sync timing
Data
indicator
IRQ enable IRQ
timing
error IRQ
error IRQ
timing
enable
error
error
type
type
Sync lock
Reserved
Reserved
Clear lock Sync
status
lock
indicator
lost
(selfstatus
reset)
Frequency Tuning Word [31:0]
Rev. 0 | Page 24 of 64
0x31
0x00
0x00
0x00
0x00
0x00
0x80
0xCF
0x37
0x38
0xF9
0x01
0x00
0x00
0xF9
0x01
0x00
0x00
0x00
0x00
0x00
AD9785/AD9787/AD9788
Address
0x0B
Register
Name
Phase
Control
Register
Bit
Range
[15:0]
[23:16]
MSB
MSB − 1
[31:24]
0x0C
Amplitude
Scale
Factor
Register
Reserved
[7:0]
[15:8]
0x0E 1
0x1D1
0x1E
1
Output
Offset
Register
Version
Register
RAM
Test
Register
MSB − 5
MSB − 6
LSB
Phase Correction Word
[9:8]
I DAC Amplitude Scale Factor [7:0]
Q DAC Amplitude Scale Factor [6:0]
[23:16]
0x0D
MSB − 2
MSB − 3
MSB − 4
NCO Phase Offset Word [15:0]
Phase Correction Word [7:0]
Reserved
[15:0]
[31:16]
I DAC Offset [15:0]
Q DAC Offset [15:0]
[7:0]
[15:8]
[31:0]
[31:0]
Version ID
Reserved
RAM
Test
I DAC
Amplitude
Scale
Factor [8]
Q DAC Amplitude Scale
Factor [8:7]
Default
0x00
0x00
0x00
0x80
0x00
0x01
0x00
0x00
Address space between Address 0x0E and Address 0x1D is intentionally left open.
SPI REGISTER DESCRIPTIONS
The communication (COMM) register comprises one byte located at Address 0x00.
Table 10. Communication (COMM) Register
Address
0x00
Bit
[7]
Name
SPI_SDIO
bidirectional
[6]
LSB first
[5]
Software reset
[4]
Power-down mode
[3]
Auto power-down
enable
[2]
I/O transfer
(self-reset)
[1]
Automatic I/O
transfer enable
Description
0: Default. Use the SPI_SDIO pin for input data only, 4-wire serial mode.
1: Use SPI_SDIO as a read/write pin, 3-wire serial mode.
0: Default. MSB first format is active.
1: Serial interface accepts serial data in LSB first format.
0: Default. Bit is in the inactive state.
1: In the AD9785/AD9787/AD9788, all programmable bits return to their power-up state
except for the COMM register bits, which are unaffected by the software reset. The software
reset remains in effect until this bit is set to 0 (inactive state).
0: Default. The full chip power-down is not active.
1: The AD9785/AD9787/AD9788 enter a power-down mode in which all functions are
powered down. This power-down puts the part into its lowest possible power dissipation
state. The part remains in this low power state until the user sets this bit to a Logic 0. The
analog circuitry requires 250 ms to become operational.
0: Default. Inactive state, automatic power-down feature is not enabled.
1: The device automatically switches into its low power mode whenever TXENABLE is
deasserted for a sufficiently long period of time.
0: Default. Inactive state.
1: The contents of the frequency tuning word memory buffer, phase control memory buffer,
amplitude scale factor memory buffer, and the output offset memory buffer are moved to a
memory location that affects operation of the device. The one-word memory buffer is
employed to simultaneously update the NCO frequency, phase, amplitude, and offset control.
Note that this bit automatically clears itself after the I/O transfer occurs. For this reason,
unless the reference clock is stopped, it is difficult to read back a Logic 1 on this bit.
0: Automatic I/O transfer disabled. The I/O transfer bit (Bit 2) must be set to update the device
in the event that changes have been made to Register 0x0A, Register 0x0B, Register 0x0C, or
Register 0x0D. This allows the user to change important operating modes of the device all at
once, rather than one at a time with individual SPI writes.
1: Default. Automatic I/O transfer enabled. The device updates its operation immediately
when SPI writes are completed to Register 0x0A, Register 0x0B, Register 0x0C, or Register 0x0D.
Rev. 0 | Page 25 of 64
AD9785/AD9787/AD9788
The digital control (DCTL) register comprises two bytes located at Address 0x01.
Table 11. Digital Control (DCTL) Register
Address
0x01
Bit
[15]
[14]
Name
Reserved
Clear phase
accumulator
[13]
PN code sync
enable
[12]
Sync mode select
[11]
Pulse sync enable
[10]
Spectral inversion
[9]
Inverse sinc
enable
[8]
DATACLK
output enable
[7:6]
Interpolation
Factor [1:0]
[5]
Data format
[4]
Single-port mode
[3]
Real mode
[2]
IQ select invert
[1]
Q first (data
pairing)
[0]
Modulator gain
control
Description
Reserved for future use.
0: Default. The feature that clears the NCO phase accumulator is inactive. The phase
accumulator operates as normal.
1: The NCO phase accumulator is held in the reset state until this bit is cleared.
0: PN code synchronization mode is disabled.
1: PN code synchronization mode is enabled. See the Device Synchronization section for
details.
0: Selects pulse mode synchronization.
1: Selects PN code synchronization. See the Device Synchronization section for details.
0: Pulse mode synchronization is disabled.
1: Pulse mode synchronization is enabled. See the Device Synchronization section for details.
0: The modulator outputs high-side image.
1: The modulator outputs low-side image. The image is spectrally inverted compared to the
input data.
0: Default. The inverse sinc filter is bypassed.
1: The inverse sinc filter is enabled and operational.
0: Data clock pin is disabled.
1: Default. The output data clock pin is active (configured as an output).
Specifies the filter interpolation rate where:
00: 1× interpolation
01: 2× interpolation
10: 4× interpolation
11: 8× interpolation
0: Default. The incoming data is expected to be twos complement.
1: The incoming data is expected to be offset binary.
0: Default. When the single-port bit is cleared, I/Q data is sampled simultaneously on the P1D
and P2D input ports. Specifically, I data is registered from the P1D[15:0] pins and Q data is
registered from the P2D[15:0] pins.
1: When the single-port bit is set, I/Q data is sampled in a serial word fashion on the P1D input
port. In this mode, the I/Q data is sampled into the part at twice the I/Q sample rate.
0: Default. Logic 0 is the inactive state for this bit.
1: When the real mode bit is set, the Q path logic after modulation and phase compensation is
disabled.
0: Default. When the IQ Select Invert bit is cleared, a Logic 1 on the TXENABLE pin indicates
I data, and a Logic 0 on the TXENABLE pin indicates Q data, if the user is employing a
continuous timing style on the TXENABLE pin.
1: When the IQ Select Invert bit is set, a Logic 1 on the TXENABLE pin indicates Q data, and a
Logic 0 on the TXENABLE pin indicates I data, if the user is employing a continuous timing
style on the TXENABLE pin.
0: Default. When the Q first bit is cleared, the I/Q data pairing is nominal, that is, the I data
precedes the Q data in the assembly of the I/Q data pair. As such, data input to the device as
I0, Q0, I1, Q1 . . . In, Qn is paired as follows: (I0/Q0), (I1/Q1) … (In/Qn).
1: When the Q first bit is set, the I/Q data pairing is altered such that the I data is paired with
the previous Q data. As such, data input to the device as I0, Q0, I1, Q1, I2, Q2, I3, Q3 . . . In, Qn is
paired as follows: (I1/Q0), (I2/Q1), (I3/Q2) … (In + 1/Qn).
0: Default. No gain scaling is applied to the NCO input to the internal digital modulator.
1: Gain scaling of 0.5 is applied to the NCO input to the modulator. This can eliminate
saturation of the modulator output for some combinations of data inputs and NCO signals.
Rev. 0 | Page 26 of 64
AD9785/AD9787/AD9788
The data synchronization control register (DSCR) comprises two bytes located at Address 0x02.
Table 12. Data Synchronization Control Register (DSCR)
Address
0x02
Bit
[15:11]
Name
DATACLK Delay [4:0]
[10:7]
Data Timing Margin [3:0]
[6]
LVDS data clock enable
[5]
DATACLK invert
[4]
DATACLK delay enable
[3]
Data timing mode
[2]
[1]
Set low
Data sync polarity
[0]
Reserved
Description
Controls the amount of delay applied to the output data clock signal. The minimum delay
corresponds to the 00000 state, and the maximum delay corresponds to the 11111 state.
The minimum delay is 0.7 ns and the maximum delay is 6.5 ns. The incremental delay is
190 ps and corresponds to an incremental change in the data clock delay bits.
The data timing margin bits control the amount of delay applied to the data and clock
signals used for checking setup and hold times, respectively, on the input data ports, with
respect to the internal data assembler clock. The minimum delay corresponds to the 0000
state, and the maximum delay corresponds to the 1111 state. The delays are 190 ps.
0: Default. When the LVDS data clock enable bit is cleared, the SYNC_O+ and SYNC_O−
LVDS pad cells are driven by the multichip synchronization logic.
1: When the LVDS data clock enable bit is set, the SYNC_O+ and SYNC_O− LVDS pad cells
are driven by the signal that drives the CMOS DATACLK output pad.
0: Default. When the data clock invert bit is cleared, the DATACLK signal is in phase with
the clock that samples the data into the part.
1: When the DATACLK invert bit is set, the DATACLK signal is inverted from the clock that
samples the data into the part.
0: Default. When the DATACLK delay enable bit is cleared, the data port input
synchronization function is effectively inactive and the delay is bypassed.
1: When the DATACLK delay enable bit is set, the data port input synchronization function
is active and controlled by the data delay mode bits. The data output clock is routed
through the delay cell.
Determines the timing optimization mode. See the Optimizing the Data Input Timing
section for details.
0: Manual timing optimization mode
1: Automatic timing optimization mode
This bit should always be set low.
0: Default. The digital input data sampling edge is aligned with the falling edge of DCI.
1: The digital input data sampling edge is aligned with the rising edge of DCI.
Used only in slave mode (see the MSCR register, Address 0x03, Bit 16).
Reserved for future use.
Rev. 0 | Page 27 of 64
AD9785/AD9787/AD9788
The multichip synchronization register (MSCR) comprises four bytes located at Address 0x03.
Table 13. Multichip Synchronization Register (MSCR)
Address
0x03
Bit
[31:27]
Name
Correlate Threshold
[4:0]
[26]
SYNC_I enable
[25]
SYNC_O enable
[24]
[23:19]
Set low
SYNC_I Delay [4:0]
[18]
Sync error check mode
[17]
[16]
Set low
DATACLK input
[15:11]
SYNC_O Delay [4:0]
[10]
[9]
Set high
SYNC_O polarity
[8]
Sync loopback enable
[7:4]
Clock State [3:0]
[3:0]
Sync Timing Margin
[3:0]
Description
Sets the threshold for determining if the received synchronization data can be demodulated
accurately. A smaller threshold value makes the demodulator more noise immune; however,
the system becomes more susceptible to false locks (or demodulation errors).
0: Default. The synchronization receive logic is disabled.
1: The synchronization receive logic is enabled.
0: Default. The output synchronization pulse generation logic is disabled.
1: The output synchronization pulse generation logic is enabled.
This bit should always be set low.
These bits are the input synchronization pulse delay word. These bits are don’t care if the
synchronization driver enable bit is cleared.
Specifies the synchronization pulse error check mode.
0: Manual error check
1: Automatic continuous error check
This bit should always be set low.
0: Default. Slave mode is disabled.
1: Slave mode is enabled. Pin 37 functions as an input for the DATACLK signal, called DCI
(DATACLK input) in this mode. Depending on the state of Bit 1 in the DSCR register (Address
0x02), the sampling edge (where the data is latched into the AD9785/AD9787/AD9788) can
be programmed to be aligned with either the rising or falling edge of DCI. This mode can
only be used with 4× or 8× interpolation.
These bits are the output synchronization pulse delay word. These bits control the DAC
sample rate clock to output the delay time of the synchronization pulse. These bits are
don’t care if the synchronization driver enable bit is cleared.
This bit should always be set high.
0: Default. SYNC_O changes state on the rising edge of DACCLK.
1: SYNC_O is generated on the falling edge of DACCLK.
0: Default. The AD9785/AD9787/AD9788 are not operating in internal loopback mode.
1: If the SYNC_O enable and Sync loopback enable bits are set, the AD9785/AD9787/AD9788
are operating in a mode in which the internal synchronization pulse of the device is used at
the multichip receiver logic and the SYNC_I+ and SYNC_I− input pins are ignored. For proper
operation of the loopback synchronization mode, the synchronization driver enable and
sync enable bits must be set.
This value determines the state of the internal clock generation state machine upon
synchronization.
These bits are the synchronization window delay word. These bits are don’t care if the
synchronization driver enable bit is cleared.
Rev. 0 | Page 28 of 64
AD9785/AD9787/AD9788
The PLL control (PLLCTL) register comprises three bytes located at Address 0x04. These bits are routed directly to the periphery of the
digital logic. No digital functionality within the main digital block is required.
Table 14. PLL Control (PLLCTL) Register
Address
0x04
Bit
[23:21]
[15]
Name
VCO Control Voltage
[2:0]
PLL Loop Bandwidth
[4:0]
PLL enable
[14:13]
PLL VCO Divisor [1:0]
[12:11]
PLL Loop Divisor [1:0]
[10:8]
[7:2]
[1:0]
PLL Bias [2:0]
PLL Band Select [5:0]
PLL VCO Drive [1:0]
[20:16]
Description
000 to 111, proportional to voltage at VCO, control voltage input (readback only). A value of
011 indicates that the VCO control voltage is centered.
These bits control the bandwidth of the PLL filter. Increasing the value lowers the loop
bandwidth. Set to 01111 for optimal performance.
0: Default. With PLL off, the DAC sample clock is sourced directly by the REFCLK input.
1: With PLL on, the DAC clock is synthesized internally from the REFCLK input via the PLL
clock multiplier. See the Clock Multiplication section for details.
Sets the value of the VCO output divider, which determines the ratio of the VCO output
frequency to the DAC sample clock frequency, fVCO/fDACCLK.
00: fVCO/fDACCLK = 1
01: fVCO/fDACCLK = 2
10: fVCO/fDACCLK = 4
11: fVCO/fDACCLK = 8
Sets the value of the DACCLK divider, which determines the ratio of the DAC sample clock
frequency to the REFCLK frequency, fDACCLK/fREFCLK.
00: fDACCLK/fREFCLK = 2
01: fDACCLK/fREFCLK = 4
10: fDACCLK/fREFCLK = 8
11: fDACCLK/fREFCLK = 16
These bits control the VCO bias current. Set to 011 for optimal performance.
These bits set the operating frequency of the VCO. For further details, refer to Table 35.
These bits control the signal strength of the VCO output. Set to 11 for optimal performance.
The I DAC control register comprises two bytes located at Address 0x05. These bits are routed directly to the periphery of the digital
logic. No digital functionality within the main digital block is required.
Table 15. I DAC Control Register
Address
0x05
Bit
[15]
Name
I DAC sleep
[14]
I DAC power-down
[13:10]
[9:0]
Reserved
I DAC gain
adjustment
Description
0: Default. If the I DAC sleep bit is cleared, the I DAC is active.
1: If the I DAC sleep bit is set, the I DAC is inactive and enters a low power state.
0: Default. If the I DAC power-down bit is cleared, the I DAC is active.
1: If the I DAC power-down bit is set, the I DAC is inactive and enters a low power state.
Reserved for future use.
These bits are the I DAC gain adjustment bits.
Rev. 0 | Page 29 of 64
AD9785/AD9787/AD9788
The Auxiliary DAC 1 control register comprises two bytes located at Address 0x06. These bits are routed directly to the periphery of the
digital logic. No digital functionality within the main digital block is required.
Table 16. Auxiliary DAC 1 Control Register
Address
0x06
Bit
[15]
Name
Auxiliary DAC 1 sign
[14]
Auxiliary DAC 1
current direction
[13]
Auxiliary DAC 1
power-down
[12:10]
[9:0]
Reserved
Auxiliary DAC 1 data
Description
0: Default. If the Auxiliary DAC 1 sign bit is cleared, the Aux DAC 1 sign is positive.
Pin 90 is the active pin.
1: If the Auxiliary DAC 1 sign bit is set, the Aux DAC 1 sign is negative. Pin 89 is the
active pin.
0: Default. If the Auxiliary DAC 1 current direction bit is cleared, the Aux DAC 1 sources
current.
1: If the Auxiliary DAC 1 current direction bit is set, the Aux DAC 1 sinks current.
0: Default. If the Auxiliary DAC 1 power-down bit is cleared, the Aux DAC 1 is active.
1: If the Auxiliary DAC 1 power-down bit is set, the Aux DAC 1 is inactive and enters a
low power state.
Reserved for future use.
These bits are the Auxiliary DAC 1 gain adjustment bits.
The Q DAC control register comprises two bytes located at Address 0x07. These bits are routed directly to the periphery of the digital
logic. No digital functionality within the main digital block is required.
Table 17. Q DAC Control Register
Address
0x07
Bit
[15]
Name
Q DAC sleep
[14]
Q DAC power-down
[13:10]
[9:0]
Reserved
Q DAC gain adjustment
Description
0: Default. If the Q DAC sleep bit is cleared, the Q DAC is active.
1: If the Q DAC sleep bit is set, the Q DAC is inactive and enters a low power state.
0: Default. If the Q DAC power-down bit is cleared, the Q DAC is active.
1: If the Q DAC power-down bit is set, the Q DAC is inactive and enters a low power state.
Reserved for future use.
These bits are the Q DAC gain adjustment bits.
The Auxiliary DAC 2 control register comprises two bytes located at Address 0x08. These bits are routed directly to the periphery of the
digital logic. No digital functionality within the main digital block is required.
Table 18. Auxiliary DAC 2 Control Register
Address
0x08
Bit
[15]
Name
Auxiliary DAC 2 sign
[14]
Auxiliary DAC 2
current direction
[13]
Auxiliary DAC 2
power-down
[12:10]
[9:0]
Reserved
Auxiliary DAC 2 data
Description
0: Default. If the Auxiliary DAC 2 sign bit is cleared, the Aux DAC 2 sign is positive.
Pin 86 is the active pin.
1: If the Auxiliary DAC 2 sign bit is set, the Aux DAC 2 sign is negative. Pin 87 is the
active pin.
0: Default. If the Auxiliary DAC 2 current direction bit is cleared, the Aux DAC 2 sources
current.
1: If the Auxiliary DAC 2 current direction bit is set, the Aux DAC 2 sinks current.
0: Default. If the Auxiliary DAC 2 power-down bit is cleared, the Aux DAC 2 is active.
1: If the Auxiliary DAC 2 power-down bit is set, the Aux DAC 2 is inactive and enters
a low power state.
Reserved for future use.
These bits are the Auxiliary DAC 2 gain adjustment bits.
Rev. 0 | Page 30 of 64
AD9785/AD9787/AD9788
The interrupt control register comprises two bytes located at Address 0x09. Bits [11:10] and Bits [7:3] are read-only bits that indicate the
current status of a specific event that may cause an interrupt request (IRQ pin active low). These bits are controlled via the digital logic
and are read only via the serial port. Bits [1:0] are the IRQ mask (or enable) bits, which are writable by the user and can also be read back.
Table 19. Interrupt Control Register
Address
0x09
Bit
[15:13]
[12]
Name
Reserved
Clear lock indicator
[11]
Sync lock lost status
[10]
Sync lock status
[9:8]
[7]
Reserved
Data timing error IRQ
[6]
Sync timing error IRQ
[5]
Data timing error type
[4]
Sync timing error type
[3]
PLL lock indicator
[2]
[1]
Reserved
Data port IRQ enable
[0]
Sync port IRQ enable
Description
Reserved for future use.
Writing a 1 to this bit clears the sync lock lost status bit. This bit does not automatically
reset itself to 0 when the reset is complete.
When high, this bit indicates that the device has lost synchronization. This bit is latched
and does not reset automatically after the device regains synchronization. To reset this
bit to 0, a 1 must be written to the clear lock indicator bit.
When this bit is low, the device is not synchronized. When this bit is high, the device is
synchronized.
Reserved for future use.
0: Default. No setup or hold time error has been detected via the input data port
setup/hold error checking logic.
1: A setup or hold time error has been detected via the input data port setup/hold error
checking logic.
0: Default. No setup or hold time error has been detected via the multichip
synchronization receive pulse setup/hold error checking logic.
1: A setup or hold time error has been detected via the multichip synchronization
receive pulse setup/hold error checking logic.
0: Default. A hold error has been detected via the input data port setup/hold error
checking logic. This bit is valid only if the data timing error IRQ bit (Bit 7) is set.
1: A setup error has been detected via the input data port setup/hold error checking
logic. This bit is valid only if the data timing error IRQ bit (Bit 7) bit is set.
0: Default. A hold error has been detected via the multichip synchronization receive
pulse setup/hold error checking logic. This bit is valid only if the sync timing error IRQ
bit (Bit 6) is set.
1: A setup error has been detected via the multichip synchronization receive pulse
setup/hold error checking logic. This bit is valid only if the sync timing error IRQ bit
(Bit 6) is set.
0: Default. The PLL clock multiplier is not locked to the input reference clock.
1: The PLL clock multiplier is locked to the input reference clock.
Reserved for future use.
0: Default. The data IRQ bit (and the IRQ pin) are not enabled (masked) for any errors
that may be detected via the input data port setup/hold error checking logic.
1: The data IRQ bit (and the IRQ pin) are enabled and go active if a setup or hold error is
detected via the input data port setup/hold error checking logic.
0: Default. The sync IRQ bit (and the IRQ pin) are not enabled (masked) for any errors
that may be detected via the multichip synchronization receive pulse setup/hold error
checking logic.
1: The sync IRQ bit (and the IRQ pin) are enabled and go active if a setup or hold error
is detected via the multichip synchronization receive pulse setup/hold error checking
logic.
Rev. 0 | Page 31 of 64
AD9785/AD9787/AD9788
The frequency tuning word (FTW) register comprises four bytes located at Address 0x0A.
Table 20. Frequency Tuning Word (FTW) Register
Address
0x0A
Bit
[31:0]
Name
Frequency Tuning
Word [31:0]
Description
These bits make up the frequency tuning word applied to the NCO phase accumulator.
See the Numerically Controlled Oscillator section for details.
The phase control register (PCR) comprises four bytes located at Address 0x0B.
Table 21. Phase Control Register (PCR)
Address
0x0B
Bit
[31:26]
[25:16]
[15:0]
Name
Reserved
Phase Correction
Word [9:0]
NCO Phase Offset
Word [15:0]
Description
Reserved for future use.
These bits are the 10-bit phase correction word.
These bits are the 16-bit NCO phase offset word. See the Numerically Controlled Oscillator
section for details.
The amplitude scale factor (ASF) register comprises three bytes located at Address 0x0C.
Table 22. Amplitude Scale Factor (ASF) Register
Address
0x0C
Bit
[23:18]
[17:9]
[8:0]
Name
Reserved
Q DAC Amplitude
Scale Factor [8:0]
I DAC Amplitude
Scale Factor [8:0]
Description
Reserved for future use.
These bits are the 9-bit Q DAC amplitude scale factor. The bit weighting is MSB = 21,
LSB = 2−7, which yields a multiplier range of 0 to 3.9921875.
These bits are the 9-bit I DAC amplitude scale factor. The bit weighting is MSB = 21,
LSB = 2−7, which yields a multiplier range of 0 to 3.9921875.
The output offset (OOF) register comprises four bytes located at Address 0x0D.
Table 23. Output Offset (OOF) Register
Address
0x0D
Bit
[31:16]
[15:0]
Name
Q DAC Offset [15:0]
I DAC Offset [15:0]
Description
These bits are the 16-bit Q DAC offset factor. The LSB bit weight is 20.
These bits are the 16-bit I DAC offset factor. The LSB bit weight is 20.
The version register (VR) comprises two bytes located at Address 0x0E and is read only.
Table 24. Version Register (VR)
Address
0x0E
Bit
[15:8]
[7:0]
Name
Reserved
Version ID
Description
Reserved for future use.
These bits read back the current version of the product.
Rev. 0 | Page 32 of 64
AD9785/AD9787/AD9788
INPUT DATA PORTS
The AD9785/AD9787/AD9788 can operate in two data input
modes: dual-port mode and single-port mode. In the default
dual-port mode (single-port mode = 0), each DAC receives data
from a dedicated input port. In single-port mode (single-port
mode = 1), both DACs receive data from Port 1. In single-port
mode, DAC 1 and DAC 2 data is interleaved and the TXENABLE
input is used to steer data to the intended DAC. In dual-port
mode, the TXENABLE input is used to power down the digital
datapath.
In dual-port mode, the data must be delivered at the input data
rate. In single-port mode, data must be delivered at twice the
input data rate of each DAC. Because the data inputs function up
to a maximum of 300 MSPS, it is only practical to operate with
input data rates up to 150 MHz per DAC in single-port mode.
In both dual-port and single-port modes, a data clock output
(DATACLK) signal is available as a fixed-time base with which
to drive data from an FPGA (field programmable gate array) or
from another data source. This output signal operates at the
input data rate. The DATACLK pin can operate as either an
input or an output.
SINGLE-PORT MODE
In single-port mode, data for both DACs is received on the
Port 1 input bus (P1D[15:0]). I and Q data samples are interleaved and are latched on the rising edges of DATACLK.
Accompanying the data is the TXENABLE (Pin 39) input
signal, which steers incoming data to its respective DAC. When
TXENABLE is high, the corresponding data-word is sent to the
I DAC and, when TXENABLE is low, the corresponding data is
sent to the Q DAC. The timing of the digital interface in
interleaved mode is shown in Figure 48.
The Q first bit (Register 0x01, Bit 1) controls the pairing
order of the input data. With the Q first bit set to the default
of 0, the I/Q pairing sent to the DACs is the two input datawords corresponding to TXENABLE low followed by
TXENABLE high.
With the Q first bit set to 1, the I/Q pairing sent to the DACs is
the two input data-words corresponding to TXENABLE high
followed by TXENABLE low. Note that with Q first set, the
I data still corresponds to the TXENABLE high word and the
Q data corresponds to the TXENABLE low word and only the
pairing order changes.
DUAL-PORT MODE
In dual-port mode, data for each DAC is received on the
respective input bus (P1D[15:0] or P2D[15:0]). I and Q data
arrive simultaneously and are sampled on the rising edge of an
internal sampling clock (SMP_CLK) that is synchronous with
DATACLK.
INPUT DATA REFERENCED TO DATACLK
The simplest method of interfacing to the AD9785/AD9787/
AD9788 is when the input data is referenced to the DATACLK
output. The DATACLK output is phase-locked (with some
offset) to the internal clock that is used to latch the input data.
Therefore, if the setup and hold times of the input data with
respect to DATACLK are met, the interface timing latches in the
data correctly.
Table 25 shows the setup and hold time requirements for the
input data over the operating temperature range of the device.
Table 25 also shows the data valid window (DVW). The data
valid window is the sum of the setup and hold times of the
interface. This is the minimum amount of time valid data must
be presented to the device in order to ensure proper sampling.
Rev. 0 | Page 33 of 64
AD9785/AD9787/AD9788
DATACLK
tSDATACLK
07098-112
tHDATACLK
INPUT
DATA
Figure 47. DATACLK Timing
DATACLK
P1D[15:0]
P1D(1)
P1D(2)
P1D(3)
P1D(4)
P1D(5)
P1D(6)
P1D(7)
P1D(8)
TXENABLE
SMP_CLK
P1D_SMP[15:0]
P1D(1)
P1D(2)
P1D(3)
P1D(4)
P1D(5)
P1D(6)
P1D(7)
P1D(8)
QFIRST = 0
QFIRST = 1
I DAC[15:0]
P1D(1)
P1D(3)
P1D(5)
Q DAC[15:0]
P1D(2)
P1D(4)
P1D(6)
I DAC[15:0]
P1D(1)
Q DAC[15:0]
P1D(3)
P1D(5)
P1D(4)
P1D(6)
07098-110
IQSEL_SMP
Figure 48. Single-Port (Interleaved) Mode Digital Interface Timing
Table 25. Data Timing Specifications vs. Temperature
Timing Parameter
Data with respect to REFCLK
Data with respect to DATACLK
SYNC_I with respect to REFCLK
Temperature
−40°C
+25°C
+85°C
−40°C to +85°C
−40°C
+25°C
+85°C
−40°C to +85°C
−40°C
+25°C
+85°C
−40°C to +85°C
Min tS (ns)
−0.25
−0.45
−0.6
−0.25
3.7
4.2
4.6
4.6
0.45
0.3
0.2
0.45
Rev. 0 | Page 34 of 64
Min tH (ns)
1.7
2.1
2.4
2.4
−1.5
−1.8
−2.0
−1.5
−0.1
0.1
0.25
0.25
Min DVW (ns)
1.45
1.65
1.8
2.15
2.2
2.4
2.6
3.1
0.35
0.4
0.45
0.7
AD9785/AD9787/AD9788
Setting the Frequency of DATACLK
INPUT DATA REFERENCED TO REFCLK
The DATACLK signal is derived from the internal DAC sample
clock, DACCLK. The frequency of DATACLK output depends
on several programmable settings. The relationship between the
frequency of DACCLK and DATACLK is
In some systems, it may be more convenient to use the REFCLK
input instead of the DATACLK output as the input data timing
reference. If the frequency of DACCLK is equal to the frequency
of the data input (PLL is bypassed and no interpolation is used),
the timing parameter “Data with respect to REFCLK” shown in
Table 25 applies directly without further considerations. If the
frequency of DACCLK is greater than the frequency of the data
input, a divider is used to generate the internal data sampling clock
(DCLK_SMP). This divider creates a phase ambiguity between
REFCLK and DCLK_SMP, which, in turn, causes a sampling
time uncertainty. To establish fixed setup and hold times for the
data interface, this phase ambiguity must be eliminated.
f DATACLK =
f DACCLK
IF × P
where the variables have the values shown in Table 26.
Table 26. DACCLK to DATACLK Divisor Values
Value
Interpolation factor
0.5 (if single port is enabled)
1 (if dual port is selected)
Address
Register
Bits
0x01
[7:6]
0x01
[4]
To eliminate the phase ambiguity, the SYNC_I input pins
(Pin 13 and Pin 14) must be used to synchronize the data to
a specific DCLK_SMP phase. The specific steps for accomplishing this are detailed in the Device Synchronization section.
The timing relationships between SYNC_I, DACCLK, REFCLK,
and the input data are shown in Figure 49 through Figure 51.
SYNC_I
tH_SYNC
tS_SYNC
DACCLK
REFCLK
tHREFCLK
07098-113
tSREFCLK
INPUT
DATA
Figure 49. REFCLK 2×
SYNC_I
tH_SYNC
tS_SYNC
DACCLK
REFCLK
tSREFCLK
tHREFCLK
07098-114
Variable
IF
P
INPUT
DATA
Figure 50. REFCLK 4×
Rev. 0 | Page 35 of 64
AD9785/AD9787/AD9788
SYNC_I
tH_SYNC
tS_SYNC
DACCLK
REFCLK
tSREFCLK
07098-111
tHREFCLK
INPUT
DATA
Figure 51. REFCLK 8×
OPTIMIZING THE DATA INPUT TIMING
The AD9785/AD9787/AD9788 have on-chip circuitry that
enables the user to optimize the input data timing by adjusting
the relationship between the DATACLK output and DCLK_SMP,
the internal clock that samples the input data. This optimization
is made by a sequence of SPI register read and write operations.
The timing optimization can be done under strict control of the
user, or the device can be programmed to maintain a configurable
timing margin automatically.
Figure 52 shows the circuitry that detects sample timing errors
and adjusts the data interface timing. The DCLK_SMP signal is
the internal clock used to latch the input data. Ultimately, it is
the rising edge of this signal that must be centered in the valid
sampling period of the input data. This is accomplished by
adjusting the time delay, tD, which changes the DATACLK
timing and, as a result, the arrival time of the input data with
respect to DCLK_SMP.
ΔtM
DATA
TIMING MARGIN[3:0]
D
PD1[0]
D
Δ tM
In addition to setting the data timing error IRQ, the data timing
error type bit (Register 0x09, Bit 5) is set when an error occurs.
The data timing error bit is set low to indicate a hold error and
high to indicate a setup error. Figure 53 shows a timing diagram
of the data interface and the status of the data timing error type bit.
DATA
TIMING ERROR = 0
TIMING
ERROR
IRQ
Q
CLK
The Data Timing Margin [3:0] variable (Register 0x02, Bits [10:7])
determines the amount of time before and after the actual data
sampling point the margin test data are latched. That is, the
Data Timing Margin [3:0] variable determines how much setup
and hold margin the interface needs for the data timing error
IRQ to remain inactive (to show error-free operation). Therefore, the data timing error IRQ is set whenever the setup and
hold margins drop below the Data Timing Margin [3:0] value.
This does not necessarily indicate that the data latched into the
device is incorrect.
TIMING
ERROR
DETECTION
TIMING
ERROR
TYPE
DATA
TIMING ERROR = 1,
DATA TIMING ERROR TYPE = 1
Q
CLK
DATA
DATACLK DELAY[4:0]
Δ tM
DELAYED
DATA
SAMPLING
Figure 52. Timing Error Detection and Optimization Circuitry
The error detection circuitry works by creating two sets of
sampled data (referred to as the margin test data) in addition to
the actual sampled data used in the device datapath. One set of
sampled data is latched before the actual data sampling point.
The other set of sampled data is latched after the actual data
sampling point. If the margin test data matches the actual data,
the sampling is considered valid and no error is declared. If
there is a mismatch between the actual data and the margin test
data, an error is declared.
Δ tM
ACTUAL
SAMPLING
INSTANT
DATA TIMING ERROR = 1,
DATA TIMING ERROR TYPE = 0
DELAYED
CLOCK
SAMPLING
07098-062
ΔtD
DATACLK
07098-061
DCLK_SMP
Figure 53. Timing Diagram of Margin Test Data
Automatic Timing Optimization Mode
When the automatic timing optimization mode is enabled
(Register 0x02, Bit 3 = 1), the device continuously monitors the
timing error IRQ and timing error type bits. The DATACLK
Delay [4:0] value (Register 0x02, Bits [4:0]) increases if a setup
error is detected and decreases if a hold error is detected. The
value of the DATACLK Delay [4:0] setting currently in use can
be read back by the user.
Rev. 0 | Page 36 of 64
AD9785/AD9787/AD9788
Manual Timing Optimization Mode
When the device is operating in manual timing optimization
mode (Register 0x02, Bit 3 = 0), the device does not alter the
DATACLK Delay [4:0] value that is programmed by the user. By
default, the DATACLK delay enable is inactive. This bit must be
set high for the DATACLK Delay [4:0] value to be realized.
The delay (in absolute time) when programming the DATACLK
delay from 00000 to 11111 varies from about 700 ps to about
6.5 ns. Typical delays per increment over temperature are shown
in Table 27.
Table 27. Data Delay Line Typical Delays over Temperature
Delay
Zero code delay (delay upon
enabling delay line)
Average unit delay
−40°C
630
+25°C
700
+85°C
740
Unit
ps
175
190
210
ps
In manual mode, the error checking logic is activated and
generates an interrupt if a setup/hold violation is detected. One
error check operation is performed per device configuration.
Any change to the Data Timing Margin [3:0] or DATACLK
Delay [4:0] values triggers a new error check operation.
The data can be written to the RAM in either LSB first or MSB
first format.
To write to the RAM in MSB first format, complete the
following steps:
1.
2.
After the instruction byte (a write to Register 0x1D) is received,
the device automatically generates the addresses required to write
the RAM, starting at the most significant address. The 32 rising
SCLK edges following the instruction byte write the first RAM
word. At this time, the internal address generator decrements
and the next 32 rising edges of SCLK write the second RAM
word. This cycle of decrementing the RAM address and writing
32-bit words continues until the last word is written. After the
64th word is written, the communication cycle is complete.
To write to the RAM in LSB first format, complete the following
steps:
1.
2.
INPUT DATA RAM
The AD9785/AD9787/AD9788 feature on-chip RAM that can
be used as an alternative input data source to the input data pins.
The input data RAM is loaded through the SPI port. After the
input data is stored in memory, the device can be configured to
transmit the stored data instead of receiving data through the
input data pins. This can be a useful test mode for factory or
in-system testing.
The RAM is 64 words long and 32 bits wide. The 16 MSBs drive
the I datapath, and the 16 LSBs drive the Q datapath. The RAM
configuration is shown in Figure 54.
64 WORDS
To begin using the RAM as an internal data generator, set
Register 0x1E (test register) to a value of 0x0C0. After these
24 bits are written, the DAC starts to output the waveform
stored in memory.
Q-SIDE
16 BITS
32 BITS
07098-060
0x1D
16 BITS
Set Bit 6 of Register 0x00 to 1.
Apply an instruction byte of 0xEE followed by the data to
be stored.
All memory elements must be accessed to complete a communication cycle. Note that the RAM is not a dual-port memory
element; therefore, if an I/O operation is begun while the RAM
is being used to drive data into the signal processing path, the
I/O operation has priority.
RAM
I-SIDE
Set Bit 6 of Register 0x00 to 0.
Apply an instruction byte of 0xEE followed by the data to
be stored.
Figure 54. Input Data RAM Configuration
Rev. 0 | Page 37 of 64
AD9785/AD9787/AD9788
DIGITAL DATAPATH
10
The AD9785/AD9787/AD9788 digital datapath consists of
three 2× half-band interpolation filters, a quadrature modulator,
and an inverse sinc filter. A 32-bit NCO provides the sine and
cosine carrier signals required for the quadrature modulator.
0
–10
ATTENUATION (dB)
–20
INTERPOLATION FILTERS
The AD9785/AD9787/AD9788 contain three half-band filters
that can be bypassed. This allows the device to operate with 2×,
4×, or 8× interpolation rates, or without interpolation. The
interpolation filters have a linear phase response. The coefficients
of the low-pass filters are given in Table 28, Table 29, and
Table 30. Spectral plots for the filter responses are shown in
Figure 55, Figure 56, and Figure 57.
–60
–3
–2
–1
0
1
2
3
4
fOUT (× Input Data Rate)
07098-011
–90
–100
–4
Figure 56. 4× Interpolation, Low-Pass Response to ±4× Input Data Rate
(Dotted Lines Indicate 1 dB Roll-Off)
10
0
–10
–20
0
–10
–30
–40
–50
–60
–70
–20
–80
–30
–90
–40
–100
–4
–50
–3
–2
–1
0
1
fOUT (× Input Data Rate)
–60
2
3
4
07098-012
ATTENUATION (dB)
–50
–80
10
Figure 57. 8× Interpolation, Low-Pass Response to ±4× Input Data Rate
(Dotted Lines Indicate 1 dB Roll-Off)
–70
–80
–3
–2
–1
0
1
fOUT (× Input Data Rate)
2
3
4
07098-010
–90
–100
–4
–40
–70
ATTENUATION (dB)
In 2×, 4×, or 8× interpolation mode, the usable bandwidth of
the interpolation filter is 80% of the complex input data rate.
The usable bandwidth has a pass-band ripple of less than
0.0005 dB and a stop-band attenuation of greater than 85 dB.
The center frequency of the interpolation filter is set by the
NCO frequency tuning word (Register 0x0A, Bits [31:0]), so
baseband input signals are always centered in the interpolation
filter pass band.
–30
Figure 55. 2× Interpolation, Low-Pass Response to ±4× Input Data Rate
(Dotted Lines Indicate 1 dB Roll-Off)
Rev. 0 | Page 38 of 64
AD9785/AD9787/AD9788
Table 28. Half-Band Filter 1
Lower Coefficient
H(1)
H(2)
H(3)
H(4)
H(5)
H(6)
H(7)
H(8)
H(9)
H(10)
H(11)
H(12)
H(13)
H(14)
H(15)
H(16)
H(17)
H(18)
H(19)
H(20)
H(21)
H(22)
H(23)
H(24)
H(25)
H(26)
H(27)
H(28)
Upper Coefficient
H(55)
H(54)
H(53)
H(52)
H(51)
H(50)
H(49)
H(48)
H(47)
H(46)
H(45)
H(44)
H(43)
H(42)
H(41)
H(40)
H(39)
H(38)
H(37)
H(36)
H(35)
H(34)
H(33)
H(32)
H(31)
H(30)
H(29)
Table 29. Half-Band Filter 2
Integer Value
−4
0
+13
0
−34
0
+72
0
−138
0
+245
0
−408
0
+650
0
−1003
0
+1521
0
−2315
0
+3671
0
−6642
0
+20,755
+32,768
Lower Coefficient
H(1)
H(2)
H(3)
H(4)
H(5)
H(6)
H(7)
H(8)
H(9)
H(10)
H(11)
H(12)
Upper Coefficient
H(23)
H(22)
H(21)
H(20)
H(19)
H(18)
H(17)
H(16)
H(15)
H(14)
H(13)
Integer Value
−2
0
+17
0
−75
0
+238
0
−660
0
+2530
+4096
Table 30. Half-Band Filter 3
Lower Coefficient
H(1)
H(2)
H(3)
H(4)
H(5)
H(6)
H(7)
H(8)
Rev. 0 | Page 39 of 64
Upper Coefficient
H(15)
H(14)
H(13)
H(12)
H(11)
H(10)
H(9)
Integer Value
−39
0
+273
0
−1102
0
+4964
+8192
AD9785/AD9787/AD9788
results in an output signal that is offset by a constant angle
relative to the nominal signal. This allows the user to phase
align the NCO output with some external signal, if necessary.
This can be especially useful when NCOs of multiple AD9785/
AD9787/AD9788 devices are programmed for synchronization.
The phase offset allows for the adjustment of the output timing
between the devices. The static phase adjustment is sourced
from the NCO Phase Offset Word [15:0] value located in
Register 0x0B.
QUADRATURE MODULATOR
The quadrature modulator is used to mix the carrier signal
generated by the NCO with the upsampled I and Q data
provided by the user at the 16-bit parallel input port of the
device. Figure 58 shows a detailed block diagram of the
quadrature modulator.
The NCO provides a quadrature carrier signal with a frequency
determined by the 32-bit frequency tuning word (FTW) set in
Register 0x0A, Bits [31:0]. The NCO operates at the rate equal
to the upsampled I data and Q data. The generated carrier
signal is mixed via multipliers with the I data and Q data. The
quadrature products are then summed.
By default, when an SPI write is completed for the frequency
tuning word, phase control, DAC gain scaling, or DAC offset
registers (Register 0x0A through Register 0x0D), the operation
of the AD9785/AD9787/AD9788 is immediately updated to
reflect these changes. However, in many applications it may be
more useful to update these registers without changing the
device operation until all these functions can be updated at
once. With the automatic I/O transfer enable bit set low in the
COMM register (Register 0x00, Bit 1), the value of all these
functions is stored in a buffer after the initial SPI write. To
update all these functions simultaneously, Bit 2 of the COMM
register should be set. This bit is self-resetting and thus does not
require another reset in a later SPI write.
Note that the sine output of the NCO contains a mux that
allows negating of the data. The mux is controlled with a
spectral inversion bit that the user stores in an I/O register
(Register 0x01, Bit 10). The default condition is to select
negated sine data.
NUMERICALLY CONTROLLED OSCILLATOR
The NCO generates a complex carrier signal to translate the
input signal to a new center frequency. A complex carrier signal
is a pair of sinusoidal waveforms of the same frequency, offset
90° from each other. The frequency of the complex carrier
signal is set via the Frequency Tuning Word [31:0] value in
Register 0x0A. The frequency of the complex carrier signal is
calculated as follows:
INVERSE SINC FILTER
The inverse sinc filter is implemented as a nine-tap FIR filter. It
is designed to provide greater than ±0.05 dB pass-band ripple
up to a frequency of 0.4 × fDACCLK. To provide the necessary
peaking at the upper end of the pass band, the inverse sinc filter
has an intrinsic insertion loss of 3.4 dB. The tap coefficients are
given in Table 31.
If {0 ≤ FTW ≤ 231}, use fCENTER = (FTW) (fDACCLK)/232
If {231 < FTW < 232 − 1}, use fCENTER = fDACCLK × (1 − (FTW/232))
A 16-bit phase offset may be added to the output of the phase
accumulator via the serial port. This static phase adjustment
I
DATA
INTERPOLATION
COSINE
FTW [31:0]
NCO
NCO PHASE OFFSET
WORD [15:0]
OUT_I
SINE
–
OUT_Q
+
–1
SPECTRAL
INVERSION
1
INTERPOLATION
07098-107
Q
DATA
0
Figure 58. Quadrature Modulator Block Diagram
Rev. 0 | Page 40 of 64
AD9785/AD9787/AD9788
Upper Coefficient
H(9)
H(8)
H(7)
H(6)
–
Integer Value
+2
−4
+10
−35
+401
IOUTx_P (mA)
Lower Coefficient
H(1)
H(2)
H(3)
H(4)
H(5)
The inverse sinc filter is disabled by default. It can be enabled by
setting the inverse sinc enable bit (Bit 9) in Register 0x01.
20
0
15
5
10
10
5
15
IOUTx_N (mA)
Table 31. Inverse Sinc Filter
The gain of the I datapath and the Q datapath can be independently scaled by adjusting the I DAC Amplitude Scale Factor [8:0]
or Q DAC Amplitude Scale Factor [8:0] value in Register 0x0C.
These values control the input to a digital multiplier. The value
of the scale factor ranges from 0 to 3.9921875 and can be
calculated as follows:
Scale Factor Value =
Scale Factor [8 : 0]
128
The digital scale factor can be used to compensate for the
attenuation incurred by the digital modulator and the inverse
sinc filter, as well as other factors.
The dc value of the I datapath and the Q datapath can also be
independently controlled. This is accomplished by adjusting
the I DAC Offset [15:0] and Q DAC Offset [15:0] values in
Register 0x0D. These values are added directly to the datapath
values. Care should be taken not to overrange the transmitted
values.
Figure 59 shows how the DAC offset current varies as a function
of the I DAC Offset [15:0] and Q DAC Offset [15:0] values. With
the digital inputs fixed at midscale (0x0000, twos complement
data format), the figure shows the nominal IOUTx_P and IOUTx_N
currents as the DAC offset value is swept from 0 to 65535.
Because IOUTx_P and IOUTx_N are complementary current outputs,
the sum of IOUTx_P and IOUTx_N is always 20 mA.
0
0x0000
0x4000
0x8000
0xC000
20
0xFFFF
DAC OFFSET VALUE
07098-108
DIGITAL AMPLITUDE AND OFFSET CONTROL
Figure 59. DAC Output Currents vs. DAC Offset Value
The offset currents generated by the DAC offset parameter
increase from 0 mA to 10 mA as the offset is swept from 0 to
0x7FFF. The offset currents increase from −10 mA to 0 mA as
the offset is swept from 0x8000 to 0xFFFF.
DIGITAL PHASE CORRECTION
The purpose of the phase correction block is to enable compensation of the phase imbalance of the analog quadrature modulator
following the DAC. If the quadrature modulator has a phase
imbalance, the unwanted sideband appears with significant
energy. Adjusting the phase correction word can optimize image
rejection in single sideband radios.
Ordinarily the I and Q channels have an angle of precisely 90°
between them. The Phase Correction Word [9:0] (Register 0x0B)
is used to change the angle between the I and Q channels. When
the Phase Correction Word [9:0] is set to 1000000000b, the
Q DAC output moves approximately 14° away from the I DAC
output, creating an angle of 104° between the channels. When
the Phase Correction Word [9:0] is set to 0111111111b, the
Q DAC output moves approximately 14° towards the I DAC
output, creating an angle of 76° between the channels. Based on
these two endpoints, the resolution of the phase compensation
register is approximately 28°/1024 or 0.027° per code.
Rev. 0 | Page 41 of 64
AD9785/AD9787/AD9788
DEVICE SYNCHRONIZATION
System demands may impose two different requirements for
synchronization. Some systems require multiple DACs to be
synchronized to each other, for example, a system that supports
transmit diversity or beamforming, where multiple antennas are
used to transmit a correlated signal. In this case, the DAC outputs
need to be phase aligned with each other, but there may not be a
requirement for the DAC outputs to be aligned with a systemlevel reference clock. In systems with a time division multiplexing
transmit chain, one or more DACs may be required to be
synchronized with a system-level reference clock.
Multiple devices are considered synchronized to each other
when the state of the clock generation state machines is
identical for all parts and the NCO phase accumulator is
identical for all parts. Devices are considered synchronized to a
system clock when there is a fixed and known relationship
between the clock generation state machine and the NCO phase
accumulator of the device to a particular clock edge of the
system clock. The AD9785/AD9787/AD9788 support two
modes of operation, pulse mode and PN code mode, for
synchronizing devices under these two conditions.
SYNCHRONIZATION LOGIC OVERVIEW
Figure 60 shows a block diagram of the on-chip synchronization
receive logic. There are two different modes of operation for the
multichip synchronization feature: pulse mode and pseudorandom
noise code (PN code) modulation/demodulation mode. The basic
function of these two modes is to initialize the internal clock
generation state machine and the NCO phase accumulator
upon the application of external signals to the device.
The receive logic responsible for initializing the clock generation state machine generates a single DACCLK cycle-wide
initialization pulse that sets the clock generation state machine
logic to a known state. In pulse mode, this pulse is generated at
every rising edge of the SYNC_I inputs. In PN code mode, the
pulse is generated every time the correct code sequence is
received on the SYNC_I inputs.
This initialization pulse loads the clock generation state machine
with the Clock State [3:0] value (Register 0x03, Bits [7:4]) as its
next state. If the initialization pulse from the synchronization
logic is generated properly, it is active for one DAC clock cycle,
every 32 (or multiple of 32) DAC clock cycles. Because the clock
generation state machine has 32 states operating at the DACCLK
rate, every initialization pulse received after the first pulse loads
the current state (the state to which the state machine is already
set), maintaining the proper clock operation of the device.
The Clock State [3:0] value is the state to which the clock
generation state machine resets upon initialization. By varying
this value, the timing of the internal clocks, with respect to
the SYNC_I signal, can be adjusted. Every increment of the
Clock State [3:0] value advances the internal clocks by one
DACCLK period.
The NCO phase accumulators can be initialized in pulse mode
or PN code mode. In pulse mode, a simultaneous strobe signal
must be sent to the TXENABLE pin of all devices that is
synchronous to the DATACLK signal. This signal resets the
phase accumulator of the NCOs across all devices, effectively
synchronizing the NCOs.
In PN code mode, the phase information of the master device is
sent to the slave devices by the SYNC_I signal. The slave devices
decode this phase information and automatically initialize their
NCO phase accumulators to match the master device.
Rev. 0 | Page 42 of 64
AD9785/AD9787/AD9788
DACCLK
CLOCK
GENERATION
NCO PHASE
ACCUMULATOR
STATE
RESET
•
•
•
INTERNAL
CLOCKS
LD-STATE
CLOCK
STATE [3:0]
NCO
RESET
GENERATOR
TXENABLE
(PIN 39)
TRANSMIT
PATH
PULSE MODE
ENABLE
0
1
SYNC MODE
SELECT
EDGE
DETECTOR
Δt
CODE
DEMODULATOR
SYNC_I
DELAY [4:0]
SYNC_I
ENABLE
SYNC ERROR
DETECTOR
PN CODE MODE ENABLE
CORRELATE
THRESHOLD [4:0]
SYNC TIMING
ERROR IRQ
07098-104
SYNC_I
(PIN 13, PIN 14)
Figure 60. Synchronization Receive Circuitry Block Diagram
MATCHED
LENGTH TRACES
REFCLK
TXENABLE
OUT
SYNC_I
SYSTEM CLOCK
LOW SKEW
CLOCK DRIVER
REFCLK
TXENABLE
PULSE
GENERATOR
OUT
LOW SKEW
CLOCK DRIVER
MATCHED
LENGTH TRACES
Figure 61. Multichip Synchronization in Pulse Mode
Rev. 0 | Page 43 of 64
07098-102
SYNC_I
AD9785/AD9787/AD9788
high logic level pin, the strobe signal should be a low logic level
pulse unless the TXENABLE invert bit is set in the SPI.
SYNCHRONIZING DEVICES TO A SYSTEM CLOCK
The AD9785/AD9787/AD9788 offer a pulse mode synchronization scheme (see Figure 61) to align the DAC outputs of
multiple devices within a system to the same DAC clock edge.
The pulse mode synchronization scheme is a two-part
operation. First, the internal clocks are synchronized by
providing either a one-time pulse or periodic signal to the
SYNC_I (SYNC_I+/SYNC_I−) inputs. The SYNC_I signal is
sampled by the internal DACCLK sample rate clock.
For this synchronization scheme, all devices are slave devices,
while the system clock generation/distribution chip serves as
the master. The external LVDS signal should be connected to the
SYNC_I inputs of all the slave devices following the constraints.
The DAC clock inputs and the SYNC_I inputs must be matched
in length across all devices.
It is vital that the SYNC_I signal be distributed between the
DACs with low skew. Likewise, the REFCLK signals must be
distributed with low skew. Any skew on these signals between
the DACs must be accounted for in the timing budget. The
SYNC_I signal is sampled at the DACCLK rate, thus the data
valid window of the SYNC_I pulse must be presented to all the
DACs within the same DACCLK period.
The SYNC_I input frequency has the following two constraints:
f SYNC _ IN ≤ f DATACLK
f SYNC _ IN =
f DAC
16 × N
where N is an integer.
Figure 62 shows the timing of the SYNC_I input with respect to
the REFCLK input. Note that although the timing is relative to
the REFCLK signal, SYNC_I is sampled at the DACCLK rate.
This means that the rising edge of the SYNC_I signal must
occur after the hold time of the preceding DACCLK rising edge
and not the preceding REFCLK rising edge. Figure 63 shows a
timing diagram of the TXENABLE input.
When the internal clocks are synchronized, the data sampling
clocks between all devices are phase aligned. The next step
requires a simultaneous strobe signal to the TXENABLE pin of
all devices that is synchronous to the DATACLK signal. This
resets the phase accumulator of the NCOs across all devices,
effectively synchronizing the NCOs. The strobe signal is
sampled by fDATACLK and must meet the same setup and hold
times as the input data. Because the TXENABLE pin is an active
SYNC_I
tH_SYNC
tS_SYNC
07098-106
REFCLK
DACCLK
Figure 62. Timing Diagram of SYNC_I with Respect to REFCLK
REFCLK
DATACLK
tSREFCLK
tSDATACLK
tHREFCLK
tHDATACLK
07098-105
TXENABLE
Figure 63. Timing Diagram of TXENABLE vs. DATACLK and REFCLK
Rev. 0 | Page 44 of 64
AD9785/AD9787/AD9788
Table 32 shows the register settings required to enable the pulse
mode synchronization feature.
6.
Table 32. Register Settings for Enabling Pulse Sync Mode
Register
0x01
0x03
Bit
[13]
[12]
[11]
[26]
[25]
[10]
Parameter
PN code sync enable
Sync mode select
Pulse sync enable
SYNC_I enable
SYNC_O enable
Set high
Value
0
0
1
1
0
1
7.
SYNCHRONIZING MULTIPLE DEVICES TO EACH
OTHER
Synchronization Timing Error Detection
The synchronization logic has error detection circuitry similar
to the input data timing. The Sync Timing Margin [3:0] variable
(Register 0x03) determines the setup and hold margin that the
synchronization interface needs for the SYNC timing error IRQ
to remain inactive (show error-free operation). Thus, the SYNC
timing error IRQ is set whenever the setup and hold margins
drop below the Sync Timing Margin [3:0] value and does not
necessarily indicate that the SYNC_I input was latched incorrectly.
When a SYNC timing error IRQ is set, corrective action can
restore the timing margin. The device can be configured for
manual mode sync error monitoring and error correction.
Follow these steps to monitor SYNC_I setup and hold timing
margins in manual mode:
2.
3.
4.
5.
Set sync error check mode (Register 0x03, Bit 18) = 0
(manual check mode).
Set Sync Timing Margin [3:0] (Register 0x03, Bits [3:0]) =
0000 (timing margin to minimum value).
Set SYNC_I Delay [4:0] (Register 0x03, Bits [23:19]) =
00000 (SYNC_I delay line to minimum value).
Set sync port IRQ enable (Register 0x09, Bit 0) = 1.
Write 1 to sync timing error IRQ (Register 0x09, Bit 6)
to clear.
The AD9785/AD9787/AD9788 synchronization engine uses
a PN code synchronization scheme to align multiple devices
within a system to the same DAC clock edge. The PN code
scheme synchronizes all the internal clocks, as well as the phase
accumulator of the NCO for all devices. With this scheme, one
device functions as the master, and the remainder of the devices
are configured as slaves.
The master device generates the PN encoded signal and drives
the signal out on the SYNC_O (SYNC_O+/SYNC_O−) output
pins. This signal is then sent to the SYNC_I (SYNC_I+/
SYNC_I−) inputs of all the slave devices and to itself. The slave
devices receive the code from the master and demodulate the
signal to produce a synchronization pulse every time a valid
code is received. The encoded signal of every device must be
sampled on the same DAC clock edge for the devices to be
properly synchronized. Therefore, it is extremely important that
the REFCLK signals arrive at all the devices with as little skew
between them as possible. In addition, the SYNC_I signals must
arrive at all the devices with as little skew as possible. At high
DACCLK frequencies, this requires using low skew clock
distribution devices to deliver the REFCLK and SYNC_I signals
and paying careful attention to printed circuit board signal
routing to equalize the trace lengths of these signals.
MATCHED
LENGTH TRACES
REFCLK
TXENABLE
OUT
SYNC_I
SYSTEM CLOCK
LOW SKEW
CLOCK DRIVER
REFCLK
TXENABLE
SYNC_I
LOW SKEW
CLOCK DRIVER
OUT
SYNC_O
MATCHED
LENGTH TRACES
07098-103
1.
Read back sync timing error IRQ and sync timing error
type (Register 0x09, Bit 4). If sync timing error IRQ is high,
a sampling error has occurred, and sync timing error type
indicates whether the sampling error is due to a setup time
violation or a hold time violation.
Adjust the SYNC_I Delay [4:0] value until the sync timing
error IRQ is no longer present.
Figure 64. Multichip Synchronization in PN Code Mode
Rev. 0 | Page 45 of 64
AD9785/AD9787/AD9788
Table 33 lists the register settings required to enable the PN
code mode synchronization feature.
The Correlate Threshold [4:0] value (Register 0x03,
Bits [31:27]) indicates how closely the code of the received
SYNC_I signal is to the expected code. A high threshold
requires a closer match of the encoded signal to set the
sync lock status bit; a lower value reduces the matching
requirements to set the sync lock status bit.
Table 33. Register Settings for Enabling PN Code Mode
Register
0x01
0x03
Bit
[13]
[12]
[11]
[31:27]
[26]
[25]
Parameter
PN code sync enable
Sync mode select
Pulse sync enable
Correlate Threshold
[4:0]
SYNC_I enable
SYNC_O enable
[10]
Set high
Value
1
1
0
10000
1
0 (slave devices)
1 (master device)
1
To verify that the devices have successfully synchronized, read
back the sync lock status bit on all devices (Register 0x09,
Bit 10). The sync lock status bit should read back as 1 on all
devices. Next, read back the sync lock lost status bit on all
devices (Register 0x09, Bit 11). The sync lock lost status bit
should read back as 0 on all devices. To clear the sync lock lost
status bit, set the clear lock indicator bit to 1, followed by a 0
(Register 0x09, Bit 12).
Because the SYNC_O signal generated by the master is spread
over many bits, this method of synchronization is very robust.
Any individual bits that may become corrupted or somehow
misread by the slave device usually have no effect on the
synchronization of the device. If the devices do not reliably
synchronize, there are several options for correcting the situation.
The SYNC_O Delay [4:0] value (Register 0x03, Bits [15:11]) on
the master device can be used to adjust the timing in 80 ps steps
effective across all devices. In addition, the SYNC_O polarity bit
(Register 0x03, Bit 9) on the master device can be set to provide
a delay of one half the DACCLK period. The SYNC_I Delay [4:0]
bits (Register 0x03, Bits [23:19]) can be used to adjust the
timing on a single slave device in 80 ps steps.
Increasing the Correlate Threshold [4:0] value makes the part
more resistant to false synchronization locks but requires a
lower bit error rate on the SYNC_I input to maintain locked
status. Decreasing the Correlate Threshold [4:0] value makes
the part more susceptible to false synchronization locks, but
maintains a locked status in the face of a higher bit error rate
on the SYNC_I input (that is, it is more noise resistant). The
recommended value for Correlate Threshold [4:0] is the default
value of 16.
INTERRUPT REQUEST OPERATION
The IRQ pin (Pin 71) acts as an alert that the device has
experienced a timing error and that it should be queried (by
reading Register 0x09) to determine the exact fault condition.
The IRQ pin is an open-drain, active low output. The IRQ pin
should be pulled high external to the device. This pin may be
tied to the IRQ pins of other devices with open-drain outputs to
wire-OR these pins together.
There are two different error flags that can trigger an interrupt
request: a data timing error or a sync timing error. By default,
when either or both of these error flags are set, the IRQ pin is
active low. Either or both of these error flags can be masked to
prevent them from activating an interrupt on the IRQ pin.
The error flags are latched and remain active until the flag bits
are overwritten.
Rev. 0 | Page 46 of 64
AD9785/AD9787/AD9788
DRIVING THE REFCLK INPUT
The REFCLK input requires a low jitter differential drive signal.
REFCLK is a PMOS input differential pair powered from the 1.8 V
supply; therefore, it is important to maintain the specified 400 mV
input common-mode voltage. Each input pin can safely swing
from 200 mV p-p to 1 V p-p about the 400 mV common-mode
voltage. Although these input levels are not directly LVDScompatible, REFCLK can be driven by an offset ac-coupled
LVDS signal, as shown in Figure 65.
0.1µF
LVDS_P_IN
REFCLK+
VCM = 400mV
REFCLK–
07098-024
50Ω
0.1µF
Direct Clocking
Figure 65. LVDS REFCLK Drive Circuit
If a clean sine clock is available, it can be transformer-coupled
to REFCLK, as shown in Figure 66. Use of a CMOS or TTL
clock is also acceptable for lower sample rates. It can be routed
through a CMOS-to-LVDS translator, then ac-coupled.
TTL OR CMOS
CLK INPUT
0.1µF
50Ω
The second mode bypasses the clock multiplier circuitry and
allows DACCLK to be directly sourced through the REFCLK
pins. This mode enables the user to source a very high quality
clock directly to the DAC core. Sourcing the DACCLK directly
through the REFCLK pins may be necessary in demanding
applications that require the lowest possible DAC output noise
at higher output frequencies.
In either case, using the on-chip clock multiplier or sourcing
the DACCLK directly through the REFCLK pins, it is necessary
that the REFCLK signal have low jitter to maximize the DAC
noise performance.
50Ω
LVDS_N_IN
on-chip clock multiplier removes the burden of generating and
distributing the high speed DACCLK.
REFCLK+
When the PLL is disabled (Register 0x04, Bit 15 = 0), the
REFCLK input is used directly as the DAC sample clock
(DACCLK). The output frequency of the DATACLK output
pin is
fDATACLK = fDACCLK ÷ IF
where IF is the interpolation factor, set in Register 0x01, Bits [7:6].
Clock Multiplication
VCM = 400mV
When the PLL is enabled (Register 0x04, Bit 15 = 1), the clock
multiplication circuit generates the DAC sample clock from the
lower rate REFCLK input. The functional diagram of the clock
multiplier is shown in Figure 68.
07098-025
REFCLK–
50Ω BAV99ZXCT
HIGH SPEED
DUAL DIODE
Figure 66. TTL or CMOS REFCLK Drive Circuit
A simple bias network for generating VCM is shown in Figure 67.
It is important to use CVDD18 and CGND for the clock bias
circuit. Any noise or other signal that is coupled onto the clock
is multiplied by the DAC digital input signal and can degrade
DAC performance.
The clock multiplication circuit operates such that the VCO
outputs a frequency, fVCO, equal to the REFCLK input signal
frequency multiplied by N1 × N2.
fVCO = fREFCLK × (N1 × N2)
The DAC sample clock frequency, fDACCLK, is equal to
VCM = 400mV
fDACCLK = fREFCLK × N2
The values of N1 and N2 must be chosen to keep fVCO in the
optimal operating range of 1.0 GHz to 2.0 GHz. When the VCO
output frequency is known, the correct PLL band select value
(Register 0x04, Bits [7:2]) can be chosen.
CVDD18
1nF
287Ω
0.1µF
1nF
CGND
07098-026
1kΩ
Figure 67. REFCLK VCM Generator Circuit
PLL Bias Settings
DAC REFCLK CONFIGURATION
The AD9785/AD9787/AD9788 offer two modes of sourcing
the DAC sample clock (DACCLK). The first mode employs an
on-chip clock multiplier that accepts a reference clock operating
at the lower input frequency, most commonly the data input
frequency. The on-chip phase-locked loop (PLL) then multiplies
the reference clock up to a higher frequency, which can then be
used to generate all the internal clocks required by the DAC.
The clock multiplier provides a high quality clock that meets
the performance requirements of most applications. Using the
There are three bias settings for the PLL circuitry that should be
programmed to their nominal values. The PLL values shown in
Table 34 are the recommended settings for these parameters.
Table 34. PLL Settings
PLL SPI Control
PLL Loop Bandwidth
PLL VCO Drive
PLL Bias
Rev. 0 | Page 47 of 64
Address
Register
Bit
0x04
[20:16]
0x04
[1:0]
0x04
[10:8]
Optimal
Setting
01111
11
011
AD9785/AD9787/AD9788
REFCLK
(PIN 5 AND PIN 6)
PHASE
DETECTION
0x04 [23:21]
VCO CONTROL
VOLTAGE
ADC
PLL_LOCK (PIN 65)
0x09 [3]
LOOP
FILTER
VCO
÷N2
÷N1
0x04 [12:11]
PLL LOOP
DIVISOR
0x04 [14:13]
PLL VCO
DIVISOR
÷IF
DAC
INTERPOLATION
RATE
DATACLK (PIN 37)
0x04 [15]
PLL ENABLE
DAC CLOCK
07098-027
0x01 [7:6]
Figure 68. Clock Multiplication Circuit
Table 35. Typical VCO Freq Range vs. PLL Band Select Value
PLL Lock Ranges over Temperature, −40°C to +85°C
VCO Frequency Range in MHz 1
PLL Band Select
fLOW
fHIGH
111111 (63)
Auto mode
Auto mode
111110 (62)
1975
2026
111101 (61)
1956
2008
111100 (60)
1938
1992
111011 (59)
1923
1977
111010 (58)
1902
1961
111001 (57)
1883
1942
111000 (56)
1870
1931
110111 (55)
1848
1915
110110 (54)
1830
1897
110101 (53)
1822
1885
110100 (52)
1794
1869
110011 (51)
1779
1853
110010 (50)
1774
1840
110001 (49)
1748
1825
110000 (48)
1729
1810
101111 (47)
1730
1794
101110 (46)
1699
1780
101101 (45)
1685
1766
101100 (44)
1684
1748
101011 (43)
1651
1729
101010 (42)
1640
1702
101001 (41)
1604
1681
101000 (40)
1596
1658
100111 (39)
1564
1639
100110 (38)
1555
1606
100101 (37)
1521
1600
100100 (36)
1514
1575
100011 (35)
1480
1553
100010 (34)
1475
1529
100001 (33)
1439
1505
100000 (32)
1435
1489
PLL Lock Ranges over Temperature, −40°C to +85°C
VCO Frequency Range in MHz 1
PLL Band Select
fLOW
fHIGH
011111 (31)
1402
1468
011110 (30)
1397
1451
011101 (29)
1361
1427
011100 (28)
1356
1412
011011 (27)
1324
1389
011010 (26)
1317
1375
011001 (25)
1287
1352
011000 (24)
1282
1336
010111 (23)
1250
1313
010110 (22)
1245
1299
010101 (21)
1215
1277
010100 (20)
1210
1264
010011 (19)
1182
1242
010010 (18)
1174
1231
010001 (17)
1149
1210
010000 (16)
1141
1198
001111 (15)
1115
1178
001110 (14)
1109
1166
001101 (13)
1086
1145
001100 (12)
1078
1135
001011 (11)
1055
1106
001010 (10)
1047
1103
001001 (9)
1026
1067
001000 (8)
1019
1072
000111 (7)
998
1049
000110 (6)
991
1041
000101 (5)
976
1026
000100 (4)
963
1011
000011 (3)
950
996
000010 (2)
935
981
000001 (1)
922
966
000000 (0)
911
951
1
The lock ranges in this table are typical values. Actual lock ranges will vary
from device to device.
Rev. 0 | Page 48 of 64
AD9785/AD9787/AD9788
4.
Configuring the PLL Band Select Value
The PLL VCO has a valid operating range from approximately
1.0 GHz to 2.0 GHz covered in 63 overlapping frequency bands
as shown in Table 35. For any desired VCO output frequency,
there are multiple valid PLL band select values. Note that the
data shown in Table 35 is for a typical device. Device-to-device
variations can shift the actual VCO output frequency range by
30 MHz to 40 MHz. Also, the VCO output frequency varies as
a function of temperature. Therefore, it is required that the
optimal PLL band select value be determined for each
individual device at the particular operating temperature.
The device has an automatic PLL band select feature on chip.
When enabled, the device determines the optimal PLL band
setting for the device at the given temperature. This setting holds
for a ±60°C temperature swing in ambient temperature. If the
device operates in an environment that experiences a larger
temperature swing, an offset should be applied to the automatically selected PLL band. The following procedure outlines a
method for setting the PLL band select value for a device
operating at a particular temperature that holds for a change in
ambient temperature over the total −40°C to +85°C operating
range of the device without further user intervention. (Note that
REFCLK must be applied to the device during this procedure.)
Configuring PLL Band Select with Temperature Sensing
The values of N1 (Register 0x04, Bits [14:13]) and N2
(Register 0x04, Bits [12:11]) should be programmed along
with the PLL settings shown in Table 34.
1.
2.
3.
Set the PLL Band Select [5:0] value (Register 0x04,
Bits [7:2]) to 63 to enable PLL auto mode.
Wait for the PLL_LOCK pin or the PLL lock indicator
(Register 0x09, Bit 3) to go high. This should occur
within 5 ms.
Read back the 6-bit PLL band select value (Register 0x04,
Bits [7:2]).
Based on the temperature when the PLL auto mode is
enabled, set the PLL band indicated in Table 36 or Table 37
by rewriting the readback values into the PLL Band Select
[5:0] parameter (Register 0x04, Bits [7:2]).
Table 36. Setting Optimal PLL Band for Lower Range
(0 to 31) Bands
System Start-Up Temperature
−40°C to −10°C
−10°C to +15°C
15°C to 55°C
55°C to 85°C
Set PLL Band to
Readback Band + 2
Readback Band + 1
Readback Band
Readback Band − 1
Table 37. Setting Optimal PLL Band for Higher Range
(32 to 62) Bands
System Start-Up Temperature
−40°C to −30°C
−30°C to −10°C
−10°C to +15°C
15°C to 55°C
55°C to 85°C
Set PLL Band to
Readback Band + 3
Readback Band + 2
Readback Band + 1
Readback Band
Readback Band − 1
Known Temperature Calibration with Memory
The procedure in the Configuring PLL Band Select with
Temperature Sensing section requires temperature sensing
upon start-up or reset of the device to choose the optimal PLL
band select value to hold over the entire operating temperature
range. If temperature sensing is not available in the system,
another option is to use the automatic PLL band select to
determine the optimal setting for the device when the device is
in a factory environment where the temperature is known. The
optimal band can then be stored in nonvolatile memory.
Whenever the system is powered up or restarted, the optimal
value can be loaded back into the device.
Rev. 0 | Page 49 of 64
AD9785/AD9787/AD9788
ANALOG OUTPUTS
Full-scale current on the I DAC and Q DAC can be set from
8.66 mA to 31.66 mA. Initially, the 1.2 V band gap reference is
used to set up a current in an external resistor connected to
I120 (Pin 75). A simplified block diagram of the reference
circuitry is shown in Figure 69.
AD9788
I DAC GAIN
1.2V BAND GAP
REFERENCE
5kΩ
I DAC
CURRENT
SCALING
I120
0.1µF
Gain scaling of the analog DAC output can be achieved by
changing the values in Register 0x05 and Register 0x07.
However, if this is done, the output common-mode voltage at
the analog output also decreases proportionally. This poses a
problem when the AD9785/AD9787/AD9788 are dc-coupled to
a quadrature modulator. Typical quadrature modulators have
tight restrictions on input common-mode variation.
10kΩ
DAC FULL-SCALE
REFERENCE
CURRENT
Q DAC
07098-030
VREF
DIGITAL AMPLITUDE SCALING
Q DAC GAIN
Figure 69. Full-Scale Current Generation Circuitry
The recommended value for the external resistor is 10 kΩ,
which sets up an IREFERENCE in the resistor of 120 μA, which in
turn provides a DAC output full-scale current of 20 mA. Because
the gain error is a linear function of this resistor, a high precision
resistor improves gain matching to the internal matching
specification of the devices. Internal current mirrors provide
a current-gain scaling, where DAC gain is a 10-bit word in the
SPI port register (Register 0x05 and Register 0x07). The default
value for the DAC gain registers gives an IFS of approximately
20 mA, where IFS for either I DAC or Q DAC is equal to
1.2 V ⎛ 27 ⎛ 6
⎞
×⎜ +⎜
× DAC gain⎞⎟ ⎟ × 32
R
⎠⎠
⎝ 12 ⎝ 1024
Auxiliary DAC Operation
Two auxiliary DACs are provided on the AD9785/AD9787/
AD9788. The full-scale output current on these DACs is derived
from the 1.2 V band gap reference and external resistor. The
gain scale from the reference amplifier current, IREFERENCE, to the
auxiliary DAC reference current is 16.67 with the auxiliary DAC
gain set to full scale (10-bit values, Register 0x06, Bits [9:0] and
Register 0x08, Bits [9:0]). This gives a full-scale current of approximately 2 mA for Auxiliary DAC 1 and Auxiliary DAC 2.
The auxiliary DAC outputs are not differential. Only one side of
the auxiliary DAC (P or N) is active at one time. The inactive side
goes into a high impedance state (100 kΩ). In addition, the P or N
output can act as a current source or a current sink. Control of
the P and N sides for both auxiliary DACs is via Register 0x06 and
Register 0x08, Bits [15:14]. When sourcing current, the output
compliance voltage is 0 V to 1.6 V. When sinking current, the
output compliance voltage is 0.8 V to 1.6 V.
35
30
25
20
15
10
5
0
0
200
400
600
800
DAC GAIN CODE
1000
07098-031
IFS (mA)
The AD9785/AD9787/AD9788 use a digital gain scaling block
to get around this problem. Because the gain scaling is done in
the digital processing of the AD9785/AD9787/AD9788, there is
no effect on the output full-scale current. This digital gain
scaling is done in such a way that the midscale value of the
signal is unaffected; the swing of the signal around midscale is
the value that is adjusted with the register settings. Digital gain
scaling is done using the amplitude scale factor (ASF) register
(Register 0x0C).
Figure 70. DAC Full-Scale Current vs. DAC Gain Code
Rev. 0 | Page 50 of 64
AD9785/AD9787/AD9788
There are two output signals on each auxiliary DAC. One signal
is designated P, the other N. The sign bit in each auxiliary DAC
control register (Bit 15) controls whether the P side or the N side
of the auxiliary DAC is turned on. Only one side of the auxiliary
DAC is active at a time. The auxiliary DAC structure is shown
in Figure 71.
0 TO 2mA
(SOURCE)
The choice of sinking or sourcing should be made at circuit
design time. There is no advantage to switching between
sourcing and sinking current after the circuit is in place.
The auxiliary DACs can be used for local oscillator (LO) cancellation when the DAC output is followed by a quadrature modulator. This LO feedthrough is caused by the input referred dc
offset voltage of the quadrature modulator (and the DAC output
offset voltage mismatch) and can degrade system performance.
Typical DAC-to-quadrature modulator interfaces are shown in
Figure 72 and Figure 73. Often, the input common-mode
voltage for the modulator is much higher than the output
compliance range of the DAC, so that ac coupling or a dc level
shift is necessary. If the required common-mode input voltage
on the quadrature modulator matches that of the DAC, then the
dc blocking capacitors in Figure 72 can be removed.
AUX_P
VBIAS
0 TO 2mA
(SINK)
AUX_N
07098-032
P/N
SOURCE/
SINK
Figure 71. Auxiliary DAC Structure
The magnitude of the auxiliary DAC 1 current is controlled by
the auxiliary DAC 1 control register (Register 0x06), and the
magnitude of the auxiliary DAC 2 current is controlled by the
auxiliary DAC 2 control register (Register 0x08). These auxiliary
DACs have the ability to source or sink current. This selection is
programmable via Bit 14 in either auxiliary DAC control register.
A low-pass or band-pass passive filter is recommended when
spurious signals from the DAC (distortion and DAC images) at
the quadrature modulator inputs can affect system performance.
Placing the filter at the location shown in Figure 72 and Figure 73
allows easy design of the filter, as the source and load impedances
can easily be designed close to 50 Ω.
QUADRATURE
MODULATOR V+
AUX
DAC1
QUADRATURE
MODULATOR V+
0.1µF
OPTIONAL
PASSIVE
FILTERING
I DAC
QUAD MOD
I INPUTS
AUX
DAC2
0.1µF
25Ω TO 50Ω
0.1µF
OPTIONAL
PASSIVE
FILTERING
Q DAC
QUAD MOD
Q INPUTS
07098-033
0.1µF
25Ω TO 50Ω
Figure 72. Typical Use of Auxiliary DACs AC Coupling to Quadrature Modulator
AUX
DAC1 OR
DAC2
25Ω TO 50Ω
OPTIONAL
PASSIVE
FILTERING
QUAD MOD
I AND Q INPUTS
25Ω TO 50Ω
07098-115
I OR Q DAC
Figure 73. Typical Use of Auxiliary DACs DC Coupling to Quadrature Modulator with DC Shift
Rev. 0 | Page 51 of 64
AD9785/AD9787/AD9788
POWER DISSIPATION
Figure 74 through Figure 78 detail the power dissipation of the
AD9785/AD9787/AD9788 under a variety of operating conditions.
All of the graphs are taken with data being supplied to both the
I and Q channels. The power consumption of the device does
not vary significantly with changes in the modulation mode or
analog output frequency. Graphs of the total power dissipation
are shown along with the power dissipation of the DVDD18,
DVDD33, and CVDD18 supplies.
The power dissipation of the AVDD33 supply rail is independent
of the digital operating mode and sample rate. The current drawn
from the AVDD33 supply rail is typically 51 mA (182 mW) when
the full-scale current of the I and Q DACs is set to the nominal
value of 20 mA. Changing the full-scale current directly impacts
the supply current drawn from the AVDD33 rail. For example,
if the full-scale current of the I DAC and the Q DAC is changed
to 10 mA each, the AVDD33 supply current drops to 31 mA.
70
1800
1600
60
4× NCO
8× NCO
4×
2× NCO
POWER (mW)
1000
2×
800
600
1× NCO
400
1×
50
100
150
200
250
300
fDATA (MSPS)
0
0
50
100
150
200
250
300
fDATA (MSPS)
Figure 76. Power Dissipation, Digital 3.3 V Supply, I and Q Data,
Dual DAC Mode
Figure 74. Power Dissipation, I and Q Data, Dual DAC Mode
120
1400
4× NCO
1200
100
8× NCO
1000
4×
POWER (mW)
80
8×
800
2× NCO
600
2×
60
40
400
1× NCO
200
2× NCO
2×
1× NCO
1×
20
1×
0
0
0
50
100
150
200
250
300
fDATA (MSPS)
07098-036
POWER (mW)
8× NCO
8×
4× NCO
4×
2× NCO
2×
1× NCO
1×
10
07098-035
0
30
20
200
0
40
0
50
100
150
200
8× NCO
8×
4× NCO
4×
250
300
fDATA (MSPS)
Figure 77. Power Dissipation, Clock 1.8 V Supply, I and Q Data,
Dual DAC Mode
Figure 75. Power Dissipation, Digital 1.8 V Supply, I and Q Data,
Dual DAC Mode
Rev. 0 | Page 52 of 64
07098-038
POWER (mW)
50
8×
1200
07098-037
1400
AD9785/AD9787/AD9788
140
120
POWER (mW)
100
80
60
40
0
0
200
400
600
fDAC (MSPS)
800
1000
07098-039
20
Figure 78. Digital 1.8 V Supply, Power Dissipation of Inverse Sinc Filter
Rev. 0 | Page 53 of 64
AD9785/AD9787/AD9788
AD9785/AD9787/AD9788 EVALUATION BOARDS
The remainder of this data sheet describes the evaluation
boards for testing the AD9785, AD9787, and AD9788 devices.
The factory default jumper configuration is as follows:
•
Jumpers JP2, JP3, JP4, and JP8 are unsoldered.
OUTPUT CONFIGURATION
•
Jumpers JP14, JP15, JP16, and JP17 are soldered.
Each evaluation board contains an Analog Devices ADL5372
quadrature modulator. The AD9785/AD9787/AD9788 devices
and the ADL5372 provide an easy-to-interface DAC/modulator
combination that can be easily characterized on the evaluation
board.
Solderable jumpers can be configured to evaluate the singleended or differential outputs of the AD9785/AD9787/AD9788.
To evaluate the ADL5372 on the evaluation board, reverse the
jumper positions as follows:
•
Jumpers JP2, JP3, JP4, and JP8 are soldered.
•
Jumpers JP14, JP15, JP16, and JP17 are unsoldered.
Note that the ADL5372 also requires its own separate 5 V and
GND connection on the evaluation board.
DIGITAL PICTURE OF EVALUATION BOARD
5V POWER
SYNC
INPUTS
REFCLK
INPUT
JP4 JP15
S5
GND
+5V
DIGITAL DATA
INPUTS
JP8 JP14
ADL5372
OUTPUT
S8
AD9788
S9
ADL5372
JP3 JP16
DATACLK
OUTPUT
ADL5372
LO INPUT
JP2 JP17
S6
RESET
SPI
PORT
Figure 79. Evaluation Board
Rev. 0 | Page 54 of 64
07098-058
SYNC
OUTPUTS
AD9785/AD9787/AD9788
EVALUATION BOARD SOFTWARE
A GUI .exe file for Microsoft® Windows® is included on the CD
that ships with the evaluation board. This file allows the user to
easily program all the functions on the AD9785/AD9787/AD9788.
Figure 80 shows this user interface. The most important
features for configuring the AD9785/AD9787/AD9788 are
called out in the figure.
I/Q FULL SCALE OUTPUT
CURRENT CONTROL
I/Q CHANNEL
GAIN MATCHING
DIGITAL GAIN
SCALING
I/Q OFFSET
CONTROL
I/Q PHASE
COMPENSATION
Figure 80. AD9788 User Interface
Rev. 0 | Page 55 of 64
NCO FREQUENCY
AND PHASE OFFSET
07098-059
INTERPOLATION AND
FILTER MODE SETTINGS
Rev. 0 | Page 56 of 64
C20
C76
C77
Figure 81. Evaluation Board, Power Supply and Decoupling
16V
22UF
DVDD33_IN
C21
TP6
RED
22UF
16V
AVDD33_IN
TP5
RED
16V
22UF
DVDD18_IN
16V
22UF
CVDD18_IN
ACASE
ACASE
ACASE
RED
TP3
ACASE
TP20
RED
RED
TP19
RED
TP18
RED
TP17
.1UF
C45
CC0603
.1UF
LC1812
L4
EXC-CL4532U1
C28
CC0603
.1UF
LC1812
L3
EXC-CL4532U1
C71
CC0603
.1UF
LC1812
L2
EXC-CL4532U1
C68
CC0603
LC1812
L1
.1UF
C42
CC0603
.1UF
C26
CC0603
.1UF
TP9
C70
CC0603
.1UF
C69
CC0603
BLK
DVDD33
BLK
TP8
AVDD33
TP4
BLK
DVDD18
BLK
TP2
CVDD18
SPI_SDO
SPI_SDIO
SCLK
SPI_CSB
R55
10K
BLACK
TP15
C46
RED
TP14
RC080
5
EXC-CL4532U1
GND
VDDM_IN
ACASE
RC080
5
TP1
RED
R52
10K
1
2
5
3
1
74AC14
SO14
U6
SO14
U5
74AC14
6
SO14
U5
74AC14
4
CC0402
SO14
U5
74AC14
2
22UF
16V
13
12
9
11
13
CC0402
74AC14
SO14
U6
SO14
U5
74AC14
8
SO14
U5
74AC14
10
SO14
U5
74AC14
12
C67
.1UF
LC1812
L12
EXC-CL4532U1
R54
R53
R51
.1UF
C66
TP13
RC0805
9K
RC0805
9K
RC0805
9K
GND
RED
VDDM
RED
TP16
5
9
11
3
U6
4
10
8
6
P1
TJAK06RAP
FCI-68898
CLASS=IO
6
5
4
3
2
1
74AC14
SO14
U6
74AC14
SO14
U6
74AC14
SO14
U6
74AC14
SO14
AD9785/AD9787/AD9788
EVALUATION BOARD SCHEMATICS
07098-044
AD9785/AD9787/AD9788
IOUT_N
IOUT-IOUT_P
AUX1_P
AUX1_N
AUX2_P
AUX2_N
S8
2
R 12
RC 060 3
R3
RC 060 3
RC 060 3
RC 060 3
RC0603
50 0
RC0603
50 0
RC0603
50 0
RC0603
50 0
1
R 15
R 17
S5
2
250
1
R2
250
R4
250
R14
250
R16
R 20
RC 060 3
R 19
0
RC 060 3
DNP
JP1
JP5
JP6
JP11
6
4
1
3
T2B
ADTL1-12
P
TC1-1T
T2A
IP
IN
QP
QN
S
4
6
3
1
1
2
3
6
4
T1B
ADTL1-12
P
TC1-1T
T1A
C62
C61
.1UF
C59
C60
S
C58
6
CC 040 2
1
CC 040 2
2
3
CC 040 2
4
C57
1NF
C56
C55
1NF
.1UF
C31
.1UF
C14
1NF
.1UF
CVDD18
1NF
1NF
1
1
.1UF
2
S15
S12
2
C6
CC 040 2
AVDD33
CC 040 2
CC 040 2
CC 040 2
CC 040 2
CC 040 2
CC 040 2
ACA S E
RC 060 3
RC 060 3
50
50
ACASE
VAL
CR2
59
P2D0
58
P2D1
3
6
4
P 2 D6
TC1-1T
54
52
T4A
P2D4
3
P2D3
55
2
P2D2
56
1
57
1
P 2 D7
TC1-1T
GN D ;5
P
P 2 D5
T3A
10 K
T4B
P 2 D8
V O LT
ACA S E
6
5
P2D5
51
P2D6
P AD
P AD
Q
Q_
9779 T QF P
U1
R 21
5
6
RC 060 3
22
C2
CC 040 2
QOUT_N
C38
1NF
.1UF
C25
.1UF
C10
1NF
C29
C12
.1UF
CC 040 2
S9
DVDD33
2
S16
74LCX112
CC 040 2
2
DVDD33
1
V O LT
RC 060 3
0
1
QOUT-QOUT_P
RC0805
ACA S E
R 22
S6
DVDD18
2
1
C4
4.7UF
P2D15
R59
RC0805
22
R58
DVDD33
DNP
CC 040 2
ACA S E
CC 040 2
VOLT
CC 040 2
V O LT
C34
CC 040 2
1NF
11
13
12
J
CLK
K
U10
DVDD18
CC 040 2
ACA S E
4 .7U F
10
14
C5
C35
C3
9
7
C4 0
C3 6
C27
1NF
C30
.1UF
Q
Q_
4.7UF
C13
PRE
CLR
GND
CC 040 2
CC 040 2
CC 040 2
CC 040 2
CC 040 2
CC 040 2
ACA S E
.1UF
1NF
1NF
C39
C11
.1UF
.1UF
4 .7U F
1NF
VOLT
Figure 82. Evaluation Board, Analog and Digital Interfaces to TxDAC
Rev. 0 | Page 57 of 64
07098-045
V O LT
ACA S E
4
PRE
CLR
JP7
4
15
VDDD 18 _ 5 3
JP16
61
53
P 2 D9
0
1
ADTL1-12
V SS D _ 5 4
QN
R 63
S
P 2 D4
P2D10
2
3
6
62
60
P2D11
4
4
63
P 2 D3
R7
R 65
3
1K
2
RC 120 6
64
1
P 2 D2
R10
0
P 2 D1
V SS D _ 4 4
R8
P 2 D0
VDD 18 _ 4 3
RC0603
P2D13
RC0603
VDDD 18 _ 6 0
P2D12
R9
VDDD 33 _ 6 1
P2D14
SPI_SDO
65
S YN C _O N
P2D15
SW1
SPI_SDI
66
S YN C _O P
TX
RC0603
VDDD 33 _ 3 8
R6
67
V SS D _ 6 4
4
J
CLK
K
50
P2D7
P LL _ LO CK
DC L K
SPI_CLK
6
49
P2D8
SP I_ S DO
P 1 D0
VAL
SPI_CSB
68
SP I_S DI
P 1 D1
1K
R 64
69
3
48
P2D9
SP I_ C L K
RED
1
3
1
2
U10
6PINCONN
47
P2D10
SP I_ C S B
VDDD 18 _ 3 3
RC 120 6
70
R ESE T
V SS D _ 3 2
P 1 D2
TP 1 1
TP 1 2
CR1
71
DVDD33
1
2
3
74LCX112
46
P2D11
P 1 D3
RED
72
S11
P2D12
IRQ
73
2
45
V SS_ 7 2
P 1 D4
CC 060 3
74
1
44
P 1 D5
75
S14
JP18
43
IPT AT
1
42
P2D13
P 1 D6
2
41
P2D14
VR E F _ 7 4
P
40
P2D15
P 1 D7
T3B
39
I12 0
RC1206
38
76
VDDA 33 _ 7 6
P 1 D8
ADTL1-12
37
77
V SS A _ 7 7
P 1 D9
RC 060 3
S
36
P1D0
RC 080 5
4
C84
35
P1D1
78
VDDA 33 _ 7 8
P1D10
RC 060 3
79
V SS A _ 7 9
VDDD 18 _ 2 3
6
34
P1D2
CC 060 3
80
VDDA 33 _ 8 0
V SS D _ 2 2
0
.1UF
33
81
V SS A _ 8 1
P1D11
IOUT2_P
82
JP17
32
83
QP
31
P1D3
P1D12
IOUT2_N
84
50
R18
100
30
P1D4
V SS A _ 8 2
AUX2_P
85
D2P
29
P1D5
P1D13
AUX2_N
86
6.3V
28
P1D6
IOU T 2 _ P
87
C18
P1D7
IOU T 2 _ N
P1D14
AUX1_N
10UF
27
A U X 2_ N
A U X 2_ P
V SS A _ 8 5
P1D15
AUX1_P
89
88
V SS A _ 8 8
VDDD 33 _ 1 6
IOUT1_N
90
R56
DVDD33
R26
100
RC 060 3
26
P1D8
A U X 1_ N
10K
25
P1D9
A U X 1_ P
V SS_ 1 2
91
C8
24
P1D10
RC 060 3
92
V SS C _ 1 1
V SS D _ 1 5
IOUT1_P
93
1NF
23
94
R11
3
2
1
U11
22
V SS A _ 9 1
RC0603
21
P1D11
VDDC 18 _ 1 0
95
JP2
A
NC
GND
SN74LVC1G34
20
P1D12
IOU T 1 _ N
S Y N C _1N
JP15
VCC
19
P1D13
VDDC 18 _ 9
S Y N C _1P
0
Y
18
P1D14
IOU T 1 _ P
JP3
17
P1D15
V SS C _ 8
D1N
4
5
16
V SS A _ 9 4
50
15
V SS C _ 7
R1
14
V SS A _ 9 5
JP8
13
VDDA 33 _ 9 6
CLK_N
D2N
25
RC0603
12
R5
11
96
CLK_P
JP4
10
CC 040 2
D1P
R3 2
9
CC 040 2
4 .7U F
97
V SS A _ 9 7
V SS C _ 4
1NF
8
DVDD33
.1UF
C32
7
C37
6
CC 040 2
C33
1
5
C24
2
4
CC 040 2
CC 040 2
98
VDDA 33 _ 9 8
V SS C _ 3
VOLT
99
V SS A _ 9 9
VDDC 18 _ 2
ACA S E
10 0
VDDA 33 _ 10 0
VDDC 18 _ 1
.1UF
S7
3
C9
2
1NF
C1
C78
C7
CC 040 2
.1UF
CLK_P
CLK_N
4.7UF
4.7UF
1NF
C15
1
IN
IP
JP14
V O LT
4 .7U F
D2P
D2N
D1N
VAL
C65
CC0603
VAL
C7 4
CC0603
VAL
C80
CC0603
VAL
L9
VAL
LC0805
VAL
LC0805
L8
L11
VAL
LC0805
VAL
C64
CC0603
VAL
C7 5
CC0603
VAL
C79
CC0603
GND
10UF
10V
C43
VDDM
GND
ACASE
JP12
R24
100PF
CC0402
RC0603
R23
DNP
C50
RC0603
RC0603
C82
DNP
CC0402
.1UF
C47
10K
R25
MOD_QP
MOD_QN
VDDM
MOD_IN
J4
6
5
4
3
2
1
MOD_QP
MOD_QN
Figure 83. Evaluation Board, ADL5372 (FMOD2) Quadrature Modulator
CC0402
T4
ETC1-1-13
1
S
2
9
8
7
100PF
3
GND
100PF
L10
1
24
LC0805
PAD
C53
C81
22
2
23
D1P
21
10
MOD_IP
C54
CC0402
GND
20
VAL
19
12
11
CC0603
FMOD
13
14
15
16
17
18
U9
MOD_IP
MOD_IN
CC0402
100PF
Rev. 0 | Page 58 of 64
C73
VAL
1
2
GND
CC0402
CC0402
C72
J3
.1UF
L17
CC0402
C51
100PF
100PF
OUTPUT
MODULATED
C63
CC0402
L18
VAL
LC0805
VAL
LC0805
100PF
100PF
CC0402
CC0402
C87
C83
.1UF
C52
.1UF
ACASE
GND
CC0402
C90
GND
ACASE
VDDM
10UF
10V
C41
VDDM
VDDM
10UF
10V
C44
07098-046
CC0603
AD9785/AD9787/AD9788
P
4
5
J1
2
1
R13
VAL
5
P
1
2
ETC1-1-13
S
3
.1UF
CC040
2
C23
.1UF
CC040
2
4
T2
25
R29
25
R28
RC040
2
RC040
2
RC040
2
RC040
2
C19
300
R31
R30
1K
CC0402
CC0402
.1UF
C17
DNP
C16
CVDD18
CLK_N
CLK_P
AD9785/AD9787/AD9788
Figure 84. Evaluation Board, TxDAC Clock Interface
Rev. 0 | Page 59 of 64
07098-047
RC040
2
Rev. 0 | Page 60 of 64
B17
B18
B19
B20
B21
B22
B23
B24
B25
A17
A18
A19
A20
A21
A22
A23
A24
A25
PKG_TYPE=MOLEX110
VAL
B16
A16
PKG_TYPE=MOLEX110
VAL
B15
A15
B11
B8
A8
A11
C9
B7
A7
B9
B6
A6
B10
B5
A5
A9
B4
A4
A10
C8
B3
A3
Figure 85. Evaluation Board, Digital Input Data Lines
BLK
GND
PKG_TYPE=MOLEX110
VAL
C25
C24
C23
C22
C21
C20
C19
C18
C17
C16
C15
C11
C10
C7
C6
C5
C4
C3
C2
B2
P4
C1
A2
P4
B1
P4
TP7
BLK
P1D14
P1D12
P1D10
P1D8
P1D6
P1D4
P1D2
P1D0
P2D14
P2D12
P2D10
P2D8
P2D6
P2D4
P2D2
P2D0
P4
PKG_TYPE=MOLEX110
VAL
D25
D24
D23
D22
D21
D20
D19
D18
D17
D16
D15
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
P4
PKG_TYPE=MOLEX110
VAL
E25
E24
E23
E22
E21
E20
E19
E18
E17
E16
E15
E11
E10
E9
E8
E7
E6
E5
E4
E3
E2
E1
P1D15
P1D13
P1D11
P1D9
P1D7
P1D5
P1D3
P1D1
P2D1
P2D15
P2D13
P2D11
P2D9
P2D7
P2D5
P2D3
07098-048
A1
AD9785/AD9787/AD9788
Figure 86. Evaluation Board, On-Board Power Supply
Rev. 0 | Page 61 of 64
VAL
CNTERM_2P
2
1
P2
2
1
C93
C94
CC0603
1UF
1UF
CC0603
C91
CC0603
1UF
C88
CC0603
1UF
C85
CC0603
1UF
C92
CC0603
1UF
C89
CC0603
1UF
C86
CC0603
1UF
3
2
1
3
2
3
2
1
ADP3339-3-3
4
U4
4
U3
4
U2
ADP3339-3-3
ADP3339-1-8
ADP3339-1-8
1
3
2
1
4
U7
JP22
JP21
JP20
JP19
AVDD33_IN
DVDD33_IN
DVDD18_IN
CVDD18_IN
07098-049
J2
AD9785/AD9787/AD9788
AD9785/AD9787/AD9788
OUTLINE DIMENSIONS
0.75
0.60
0.45
16.00 BSC SQ
1.20
MAX
14.00 BSC SQ
100
1
SEATING
PLANE
76
76
75
100
1
75
PIN 1
BOTTOM VIEW
(PINS UP)
TOP VIEW
(PINS DOWN)
CONDUCTIVE
HEAT SINK
51
25
26
0.20
0.09
51
50
25
50
1.05
1.00
0.95
7°
3.5°
0°
0.50 BSC
0.27
0.22
0.17
0.15
0.05
26
6.50
NOM
COPLANARITY
0.08
121207-A
COMPLIANT TO JEDEC STANDARDS MS-026-AED-HDT
NOTES:
1. CENTER FIGURES ARE TYPICAL UNLESS OTHERWISE NOTED.
2. THE PACKAGE HAS A CONDUCTIVE HEAT SLUG TO HELP DISSIPATE HEAT AND ENSURE RELIABLE OPERATION
OF THE DEVICE OVER THE FULL INDUSTRIAL TEMPERATURE RANGE. THE SLUG IS EXPOSED ON THE BOTTOM OF
THE PACKAGE AND ELECTRICALLY CONNECTED TO CHIP GROUND. IT IS RECOMMENDED THAT NO PCB SIGNAL
TRACES OR VIAS BE LOCATED UNDER THE PACKAGE THAT COULD COME IN CONTACT WITH THE CONDUCTIVE
SLUG. ATTACHING THE SLUG TO A GROUND PLANE WILL REDUCE THE JUNCTION TEMPERATURE OF THE DEVICE,
WHICH MAY BE BENEFICIAL IN HIGH TEMPERATURE ENVIRONMENTS.
3. θJA: 27.4°C/W WITH THERMAL PAD UNSOLDERED, 19.1°C/W WITH THERMAL PAD SOLDERED TO PCB.
Figure 87. 100-Lead Thin Quad Flat Package, Exposed Pad [TQFP_EP]
(SV-100-1)
Dimensions shown in millimeters
ORDERING GUIDE
Model
AD9785BSVZ 1
AD9785BSVZRL1
−40°C to +85°C
−40°C to +85°C
Package Description
100-Lead TQFP_EP
100-Lead TQFP_EP
Package Option
SV-100-1
SV-100-1
AD9787BSVZ1
AD9787BSVZRL1
−40°C to +85°C
−40°C to +85°C
100-Lead TQFP_EP
100-Lead TQFP_EP
SV-100-1
SV-100-1
AD9788BSVZ1
AD9788BSVZRL1
−40°C to +85°C
−40°C to +85°C
100-Lead TQFP_EP
100-Lead TQFP_EP
SV-100-1
SV-100-1
AD9785-EBZ1
AD9787-EBZ1
AD9788-EBZ1
1
Temperature Range
Evaluation Board
Evaluation Board
Evaluation Board
RoHS Compliant Part.
Rev. 0 | Page 62 of 64
AD9785/AD9787/AD9788
NOTES
Rev. 0 | Page 63 of 64
AD9785/AD9787/AD9788
NOTES
©2008 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D07098-0-1/08(0)
Rev. 0 | Page 64 of 64