AVAGO AMMC-5618-W10 6 - 20 ghz amplifier Datasheet

AMMC - 5618
6 - 20 GHz Amplifier
Data Sheet
Chip Size: 920 x 920 µm (36.2 x 36.2 mils)
Chip Size Tolerance: ± 10µm (±0.4 mils)
Chip Thickness: 100 ± 10µm (4 ± 0.4 mils)
Pad Dimensions: 80 x 80 µm (3.1 x 3.1 mils or larger)
Description
Features
Avago Technologies’ AMMC-5618 6-20 GHz MMIC is an
efficient two-stage amplifier designed to be used as a
cascadable intermediate gain block for EW applications.
In communication systems, it can be used as a LO buffer,
or as a transmit driver amplifier. It is fabricated using a
PHEMT integrated circuit structure that provides exceptional efficiency and flat gain performance. During typical operation with a single 5-V supply, each gain stage is
biased for Class-A operation for optimal power output
with minimal distortion. The RF input and output have
matching circuitry for use in 50-W environments. The
backside of the chip is both RF and DC ground. This helps
simplify the assembly process and reduces assembly related performance variations and costs. For improved reliability and moisture protection, the die is passivated at
the active areas. The MMIC is a cost effective alternative
to hybrid (discrete FET) amplifiers that require complex
tuning and assembly processes.
• Frequency Range: 6 - 20 GHz
Applications
• Driver/Buffer in microwave communication systems
• Cascadable gain stage for EW systems
• Phased array radar and transmit amplifiers
• High Gain: 14.5 dB Typical
• Output Power: 19.5 dBm Typical
• Input and Output Return Loss: < -12 dB
• Flat Gain Response: ± 0.3 dB Typical
• Single Supply Bias: 5 V @ 107 mA
AMMC-5618 Absolute Maximum Ratings [1]
Symbol
Parameters/ Conditions
Units
Min.
Max.
VD1, VD2
Drain Supply Voltage
V
VG1
Optional Gate Voltage
V
-5
+1
VG2
Optional Gate Voltage
V
-5
+1
ID1
Drain Supply Current
mA
70
ID2
Drain Supply Current
mA
84
Pin
RF Input Power
dBm
20
Tch
Channel Temp.
°C
+150
Tb
Operating Backside Temp.
°C
-55
Tstg
Storage Temp.
°C
-65
Tmax
Maximum Assembly Temp.
(60 sec max)
°C
7
+165
+300
Note:
1. Operation in excess of any one of these conditions may result in
permanent damage to this device.
Note: These devices are ESD sensitive. The following precautions are strongly recommended:
Ensure that an ESD approved carrier is used when dice are transported from one destination to another.
Personal grounding is to be worn at all times when handling these devices.
1
AMMC-5618 DC Specifications / Physical Properties [1]
Symbol
Parameters and Test Conditions
Unit
Min.
Typical
Max.
VD1,VD2
Recommended Drain Supply Voltage
V
3
5
7
ID1
First stage Drain Supply Current
(V D1= 5V, VG1 = Open or Ground)
mA
48
ID2
Second stage Drain Supply Current
(V D2= 5V, VG2 = Open or Ground)
mA
59
ID1 + ID2
Total Drain Supply Current
(VG1 = VG2 = Open or Ground, VD1= VD2 = 5 V)
mA
107
θ ch-b
Thermal Resistance [2]
(Backside temperature (Tb) = 25°C
°C/W
22
140
Notes:
1. Backside temperature Tb = 25°C unless otherwise noted
2. Channel-to-backside Thermal Resistance (θch-b) = 32°C/W at Tchannel (Tc) = 150°C as measured using infrared microscopy.
Thermal Resistance at backside temperature (Tb) = 25°C calculated from measured data.
AMMC-5618 RF Specifications [3, 5]
(Tb = 25°C, VDD= 5 V, IDD = 107 mA, Z0 = 50 Ω)
Symbol
Parameters and Test Conditions
Unit
Min.
Typical
|S21|
Small-signal Gain
dB
12.5
14.5
D|S21|
Small-signal Gain Flatness
dB
RLin
Input Return Loss
dB
9
12
RLout
Output Return Loss
dB
9
12
|S12|2
Isolation
dB
40
45
P-1dB
Output Power at 1dB Gain Compression @ 20 GHz
dBm
17.5
19.5
Psat
Saturated Output Power (3dB Gain Compression) @ 20 GHz
dBm
20.5
OIP3
Output 3rd Order Intercept Point @ 20 GHz
dBm
26
DS21 / DT
Temperature Coefficient of Gain [4]
dB/°C
-0.023
NF
Noise Figure @ 20 GHz
dB
4.4
2
2
± 0.3
Notes:
3. 100% on-wafer RF test is done at frequency = 6, 13 and 20 GHz, except as noted.
4. Temperature Coefficient of Gain based on sample test
5. All tested parameters guaranteed with measurement accuracy ±1.5dB for S12, ±1dB for S11, S21, S22, P1dB and ±0.5dB for NF.
2
Max.
6.5
AMMC-5618 Typical Performance (Tchuck=25°C, VDD=5V, IDD = 107 mA, Zo=50Ω)
0
18
0
-10
15
-5
ISOLATION (dB)
GAIN (dB)
12
9
6
-30
-40
-70
4
7
10
13
16
19
22
4
7
10
13
16
19
-25
22
4
7
Figure 2. Isolation
0
13
16
19
22
19
22
Figure 3. Input Return Loss
24
10
-5
10
FREQUENCY (GHz)
FREQUENCY (GHz)
FREQUENCY (GHz)
20
8
-10
-15
P1dB (dBm)
16
NF (dB)
OUTPUT RL (dB)
-15
-20
-60
Figure 1. Gain
6
4
-20
4
7
10
13
16
19
0
22
12
8
2
-25
-30
-10
-50
3
0
INPUT RL (dB)
-20
4
4
7
FREQUENCY (GHz)
10
13
16
19
0
22
4
7
Figure 5. Noise Figure
Figure 4. Output Return Loss
10
13
16
FREQUENCY (GHz)
FREQUENCY (GHz)
Figure 6. output Power at 1 dB Gain
Compression
0
15
-10
12
-20
9
Vdd=4V
Vdd=5V
Vdd=6V
6
3
0
4
7
10
13
16
FREQUENCY (GHz)
Figure 7. Gain and Voltage
3
19
22
0
Vdd=4V
Vdd=5V
Vdd=6V
-5
INPUT RL (dB)
18
ISOLATION (dB)
GAIN (dB)
AMMC-5618 Typical Performance vs. Supply Voltage (Tb=25°C, Zo=50Ω)
-30
-10
-15
-40
-20
-50
-25
-60
4
7
10
13
16
FREQUENCY (GHz)
Figure 8. Isolation and Voltage
19
22
-30
Vdd=4V
Vdd=5V
Vdd=6V
4
7
10
13
16
19
FREQUENCY (GHz)
Figure 9. Input Return Loss and Voltage
22
AMMC-5618 Typical Performance vs. Supply Voltage (cont.) (Tb=25°C, Zo=50Ω)
25
0
Vdd=4V
Vdd=5V
Vdd=6V
-5
20
P1dB (dBm)
OUTPUT RL (dB)
-10
-15
-20
15
10
Vdd=4V
Vdd=5V
Vdd=6V
-25
5
-30
-35
4
7
10
13
16
19
0
22
4
7
10
13
16
19
22
FREQUENCY (GHz)
FREQUENCY (GHz)
Figure 10. Output Return Loss and Voltage
Figure 11. Output Power and Voltage
AMMC-5618 Typical Performance vs. Temperature (VDD=5V, Zo=50Ω)
0
-10
12
-20
9
-40 C
25 C
85 C
6
-30
-40
-20
-40 C
25 C
85 C
4
7
10
13
16
19
-60
22
4
7
13
16
-30
22
5
4
3
-40 C
25 C
85 C
1
13
16
FREQUENCY (GHz)
Figure 15. Output Return Loss and
Temperature
16
19
22
19
22
20
2
-20
10
13
25
P1dB (dBm)
NOISE FIGURE (dB)
-15
7
10
Figure 14. Input Return Loss and
Temperature
6
-10
4
7
7
-40 C
25 C
85 C
-5
4
FREQUENCY (GHz)
8
0
4
19
Figure 13. Isolation and Temperature
Figure 12. Gain and Temperature
OUTPUT RL (dB)
10
FREQUENCY (GHz)
FREQUENCY (GHz)
-25
-10
-50
3
0
0
-40 C
25 C
85 C
INPUT RL (dB)
15
ISOLATION (dB)
GAIN (dB)
18
19
22
0
4
7
10
13
16
FREQUENCY (GHz)
Figure 16. Noise Figure and Temperature
19
15
10
-40 C
25 C
85 C
5
22
0
4
7
10
13
16
FREQUENCY (GHz)
Figure 17. Output Power and Temperature
AMMC-5618 Typical Scattering Parameters [1] (Tb=25°C, VDD= 5 V, IDD = 107 mA)
S11
S21
S12
S22
Freq GHz
dB
Mag
Phase
dB
Mag
Phase
dB
Mag
Phase
dB
Mag
Phase
2.00
-2.4
0.76
-125
-52.0
0
74
-80.0
0
-134
-0.4
0.95
-77
2.50
-2.9
0.72
-147
-35.4
0.02
-119
-74.0
0
-57
-0.9
0.91
-97
3.00
-3.2
0.69
-166
-19.0
0.11
-102
-69.1
0
-65
-1.6
0.84
-118
3.50
-3.6
0.66
174
-7.4
0.43
-120
-59.1
0
-60
-2.6
0.75
-138
4.00
-4.0
0.63
152
0.8
1.09
-147
-57.7
0
-104
-3.8
0.64
-156
4.50
-4.9
0.57
126
7.7
2.43
178
-51.8
0
-113
-5.3
0.55
-173
5.00
-7.3
0.43
94
12.5
4.2
138
-48.8
0
-142
-6.9
0.45
172
5.50
-12.7
0.23
67
14.7
5.41
94
-45.7
0.01
-170
-8.6
0.37
160
6.00
-19.8
0.1
66
15.1
5.69
60
-44.5
0.01
161
-10.1
0.31
151
6.50
-23.6
0.07
85
15.1
5.69
34
-44.6
0.01
142
-11.3
0.27
141
7.00
-24.7
0.06
87
15.0
5.64
13
-44.3
0.01
127
-12.6
0.23
130
7.50
-26.4
0.05
68
15.0
5.61
-5
-44.0
0.01
115
-13.9
0.2
120
8.00
-28.2
0.04
28
14.9
5.59
-22
-43.9
0.01
103
-15.3
0.17
109
8.50
-26.3
0.05
-23
14.9
5.57
-37
-43.6
0.01
95
-16.7
0.15
98
9.00
-22.8
0.07
-55
14.9
5.55
-51
-43.3
0.01
86
-18.2
0.12
87
9.50
-19.9
0.1
-74
14.8
5.52
-65
-43.2
0.01
77
-19.7
0.1
74
10.00
-17.7
0.13
-88
14.8
5.49
-77
-43.1
0.01
70
-21.4
0.09
60
10.50
-16.1
0.16
-100
14.7
5.45
-90
-42.9
0.01
63
-22.8
0.07
43
11.00
-14.8
0.18
-110
14.7
5.43
-101
-42.8
0.01
57
-24.3
0.06
23
11.50
-13.9
0.2
-120
14.7
5.41
-113
-42.5
0.01
52
-25.1
0.06
1
12.00
-13.2
0.22
-128
14.6
5.38
-124
-42.5
0.01
45
-25.1
0.06
-22
12.50
-12.6
0.23
-136
14.6
5.37
-134
-42.3
0.01
40
-24.5
0.06
-44
13.00
-12.2
0.25
-143
14.6
5.37
-145
-42.1
0.01
34
-23.3
0.07
-60
13.50
-11.9
0.26
-151
14.6
5.38
-155
-41.9
0.01
31
-22.2
0.08
-73
14.00
-11.6
0.26
-159
14.7
5.4
-166
-41.7
0.01
24
-21.3
0.09
-85
14.50
-11.5
0.27
-166
14.7
5.42
-176
-41.6
0.01
19
-20.7
0.09
-95
15.00
-11.4
0.27
-174
14.7
5.46
174
-41.4
0.01
15
-19.8
0.1
-105
15.50
-11.4
0.27
177
14.8
5.49
163
-41.3
0.01
9
-19.1
0.11
-113
16.00
-11.5
0.27
168
14.9
5.54
153
-41.1
0.01
3
-18.4
0.12
-121
16.50
-11.7
0.26
157
14.9
5.58
142
-40.8
0.01
0
-17.7
0.13
-126
17.00
-11.9
0.25
146
15.0
5.63
131
-40.8
0.01
-7
-17.2
0.14
-132
17.50
-12.2
0.25
132
15.1
5.66
120
-40.8
0.01
-12
-16.7
0.15
-138
18.00
-12.4
0.24
116
15.1
5.71
109
-40.5
0.01
-16
-16.2
0.16
-143
18.50
-12.4
0.24
98
15.2
5.75
97
-40.4
0.01
-23
-15.8
0.16
-148
19.00
-12.2
0.25
77
15.2
5.75
85
-40.3
0.01
-29
-15.4
0.17
-154
19.50
-11.5
0.27
56
15.2
5.73
73
-40.1
0.01
-35
-14.9
0.18
-158
20.00
-10.5
0.3
34
15.0
5.65
60
-39.9
0.01
-42
-14.6
0.19
-163
20.50
-9.2
0.35
14
14.8
5.51
46
-39.9
0.01
-48
-14.0
0.2
-166
21.00
-7.9
0.4
-5
14.5
5.31
33
-40.0
0.01
-55
-13.8
0.2
-172
21.50
-6.7
0.46
-21
14.1
5.05
19
-39.8
0.01
-63
-13.5
0.21
-176
22.00
-5.7
0.52
-36
13.5
4.72
5
-40.3
0.01
-72
-13.1
0.22
179
Note:
1. Data obtained from on-wafer measurements
5
Biasing and Operation
Assembly Techniques
The AMMC-5618 is normally biased with a single positive
drain supply connected to both VD1 and VD2 bond pads
as shown in Figure 19(a). The recommended supply voltage is 3 to 5 V.
The backside of the AMMC-5618 chip is RF ground. For
microstripline applications, the chip should be attached
directly to the ground plane (e.g., circuit carrier or heatsink) using electrically conductive epoxy [1, 2].
No ground wires are required because all ground connections are made with plated through-holes to the
backside of the device.
For best performance, the topside of the MMIC should be
brought up to the same height as the circuit surrounding
it. This can be accomplished by mounting a gold plated
metal shim (same length and width as the MMIC) under
the chip, which is of the correct thickness to make the
chip and adjacent circuit coplanar.
Gate bias pads (VG1 & VG2) are also provided to allow adjustments in gain, RF output power, and DC power dissipation, if necessary. No connection to the gate pad
is needed for single drain-bias operation. However, for
custom applications, the DC current flowing through
the input and/or output gain stage may be adjusted by
applying a voltage to the gate bias pad(s) as shown in
Figure 19(b). A negative gate-pad voltage will decrease
the drain current. The gate-pad voltage is approximately
zero volt during operation with no DC gate supply. Refer
to the Absolute Maximum Ratings table for allowed DC
and thermal conditions.
The amount of epoxy used for chip and or shim attachment should be just enough to provide a thin fillet
around the bottom perimeter of the chip or shim. The
ground plane should be free of any residue that may
jeopardize electrical or mechanical attachment.
The location of the RF bond pads is shown in Figure
20. Note that all the RF input and output ports are in a
Ground-Signal-Ground configuration.
RF connections should be kept as short as reasonable to
minimize performance degradation due to undesirable
series inductance. A single bond wire is sufficient for signal connections, however double-bonding with 0.7 mil
gold wire or the use of gold mesh is recommended for
best performance, especially near the high end of the
frequency range.
Thermosonic wedge bonding is the preferred method
for wire attachment to the bond pads. Gold mesh can
be attached using a 2 mil round tracking tool and a tool
force of approximately 22 grams with an ultrasonic power of roughly 55dB for a duration of 76 ± 8 mS. A guided
wedge at an ultrasonic power level of 64 dB can be used
for the 0.7 mil wire. The recommended wire bond stage
temperature is 150 ± 2° C.
Caution should be taken to not exceed the Absolute
Maximum Rating for assembly temperature and time.
The chip is 100 µm thick and should be handled with
care. This MMIC has exposed air bridges on the top
surface and should be handled by the edges or with a
custom collet (do not pick up die with vacuum on die
center.)
This MMIC is also static sensitive and ESD handling precautions should be taken.
Notes:
1. Ablebond 84-1 LM1 silver epoxy is recommended.
2. Eutectic attach is not recommended and may jeopardize reliability
of the device.
6
VD2
VD1
Feedback
Network
Matching
RF Output
Matching
Matching
RF Input
VG2
VG1
Figure 18. AMMC - 5618 Schematic
To power supply
To power supply
100 pF chip capacitor
gold plated shim
100 pF chip capacitor
gold plated shim
RF Input
RF Output
RF Input
RF Output
Bonding island
or small
chip-capacitor
To VG1 power supply
(a)
Figure 19. AMMC - 5618 Assembly Diagram
7
To VG2 power supply
(b)
0
143
Vd1
920
530
355
573
GND
Vd2
RF
RF
0
Vg1
0
79
0
Vg2
593
530
920
Figure 20. AMMC - 5618 Bond pad locations
(dimensions in microns)
Ordering Information:
AMMC-5618-W10 = 10 devices per tray
AMMC-5618-W50 = 50 devices per tray
For product information and a complete list of distributors, please go to our web site: www.avagotech.com
Avago, Avago Technologies, and the A logo are trademarks of Avago Technologies in the United States and other countries.
Data subject to change. Copyright © 2005-2013 Avago Technologies. All rights reserved. Obsoletes 5989-3927EN
AV02-0070EN - September 26, 2013