PRELIMINARY DATA SHEET MICRONAS INTERMETALL Edition Oct. 15, 1999 6251-511-1PD MSP 34x1G Multistandard Sound Processor Family with Virtual Dolby Surround MSP 34x1G PRELIMINARY DATA SHEET Contents Page Section Title 6 7 7 8 1. 1.1. 1.2. 1.3. Introduction Features of the MSP 34x1G Family and Differences to MSP 34xxD MSP 34x1G Version List MSP 34x1G Versions and their Application Fields 9 10 10 10 10 11 11 11 13 13 13 13 13 13 14 14 14 14 14 15 15 15 15 16 16 16 2. 2.1. 2.2. 2.2.1. 2.2.2. 2.2.3. 2.2.4. 2.3. 2.4. 2.5. 2.5.1. 2.5.2. 2.5.3. 2.5.4. 2.6. 2.6.1. 2.6.2. 2.6.3. 2.6.4. 2.7. 2.7.1. 2.7.2. 2.8. 2.9. 2.10. 2.11. Functional Description Architecture of the MSP 34x1G Family Sound IF Processing Analog Sound IF Input Demodulator: Standards and Features Preprocessing of Demodulator Signals Automatic Sound Select Preprocessing for SCART and I2S Input Signals Source Selection and Output Channel Matrix Audio Baseband Processing Automatic Volume Correction (AVC) Loudspeaker and Headphone Outputs Subwoofer Output Quasi-Peak Detector Virtual Surround System Application Tips Sweet Spot Clipping Loudspeaker Requirements Cabinet Requirements SCART Signal Routing SCART DSP In and SCART Out Select Stand-by Mode I2S Bus Interface ADR Bus Interface Digital Control I/O Pins and Status Change Indication Clock PLL Oscillator and Crystal Specifications 17 17 17 18 19 20 20 20 20 20 21 21 21 25 26 3. 3.1. 3.1.1. 3.1.2. 3.1.3. 3.1.4. 3.1.4.1. 3.1.4.2. 3.1.4.3. 3.1.4.4. 3.2. 3.3. 3.3.1. 3.3.2. 3.3.2.1. Control Interface I2C Bus Interface Device and Subaddresses Description of CONTROL Register Protocol Description Proposals for General MSP 34x1G I2C Telegrams Symbols Write Telegrams Read Telegrams Examples Start-Up Sequence: Power-Up and I2C Controlling MSP 34x1G Programming Interface User Registers Overview Description of User Registers STANDARD SELECT Register 2 MICRONAS INTERMETALL PRELIMINARY DATA SHEET MSP 34x1G Contents, continued Page Section Title 26 27 28 29 30 43 44 44 44 44 44 45 45 45 45 45 45 3.3.2.2. 3.3.2.3. 3.3.2.4. 3.3.2.5. 3.3.2.6. 3.3.2.7. 3.4. 3.5. 3.5.1. 3.5.2. 3.5.3. 3.5.4. 3.5.5. 3.5.6. 3.5.7. 3.5.8. 3.5.9. Refresh of STANDARD SELECT Register STANDARD RESULT Register Write Registers on I2C Subaddress 10hex Read Registers on I2C Subaddress 11hex Write Registers on I2C Subaddress 12hex Read Registers on I2C Subaddress 13hex Programming Tips Examples of Minimum Initialization Codes SCART1 Input to Loudspeaker in Stereo Sound SCART1 Input to Loudspeaker in 3D-PANORAMA Sound Noise Sequencer for 3D-PANORAMA Sound B/G-FM (A2 or NICAM) BTSC-Stereo BTSC-SAP with SAP at Loudspeaker Channel FM-Stereo Radio Automatic Standard Detection Software Flow for Interrupt driven STATUS Check 47 47 49 52 55 59 61 61 62 62 62 63 64 65 65 66 67 68 69 70 72 72 73 76 4. 4.1. 4.2. 4.3. 4.4. 4.5. 4.6. 4.6.1. 4.6.2. 4.6.2.1. 4.6.2.2. 4.6.2.3. 4.6.2.4. 4.6.3. 4.6.3.1. 4.6.3.2. 4.6.3.3. 4.6.3.4. 4.6.3.5. 4.6.3.6. 4.6.3.7. 4.6.3.8. 4.6.3.9. 4.6.3.10. Specifications Outline Dimensions Pin Connections and Short Descriptions Pin Descriptions Pin Configurations Pin Circuits Electrical Characteristics Absolute Maximum Ratings Recommended Operating Conditions (TA = 0 to 70 °C) General Recommended Operating Conditions Analog Input and Output Recommendations Recommendations for Analog Sound IF Input Signal Crystal Recommendations Characteristics General Characteristics Digital Inputs, Digital Outputs Reset Input and Power-Up I2C-Bus Characteristics I2S-Bus Characteristics Analog Baseband Inputs and Outputs, AGNDC Sound IF Inputs Power Supply Rejection Analog Performance Sound Standard Dependent Characteristics MICRONAS INTERMETALL 3 MSP 34x1G PRELIMINARY DATA SHEET Contents, continued Page Section Title 79 79 80 81 81 82 82 5. 5.1. 5.2. 5.3. 5.4. 5.5. 5.6. Appendix A: Overview of TV-Sound Standards NICAM 728 A2-Systems BTSC-Sound System Japanese FM Stereo System (EIA-J) FM Satellite Sound FM-Stereo Radio 83 84 85 86 86 86 86 87 87 88 89 91 91 93 93 93 93 94 94 94 94 95 95 95 95 95 95 96 96 96 96 96 96 96 96 98 98 6. 6.1. 6.2. 6.3. 6.3.1. 6.3.1.1. 6.3.1.2. 6.3.2. 6.3.3. 6.3.4. 6.3.5. 6.3.6. 6.3.7. 6.4. 6.4.1. 6.4.2. 6.4.3. 6.4.4. 6.4.5. 6.4.6. 6.4.7. 6.5. 6.5.1. 6.5.2. 6.5.3. 6.5.4. 6.5.5. 6.5.6. 6.5.7. 6.6. 6.6.1. 6.6.2. 6.7. 6.7.1. 6.7.2. 6.8. 6.9. Appendix B: Manual/Compatibility Mode Demodulator Write and Read Registers for Manual/Compatibility Mode DSP Write and Read Registers for Manual/Compatibility Mode Manual/Compatibility Mode: Description of Demodulator Write Registers Automatic Switching between NICAM and Analog Sound Function in Automatic Sound Select Mode Function in Manual Mode A2 Threshold Carrier-Mute Threshold Register AD_CV Register MODE_REG FIR-Parameter, Registers FIR1 and FIR2 DCO-Registers Manual/Compatibility Mode: Description of Demodulator Read Registers NICAM Mode Control/Additional Data Bits Register Additional Data Bits Register CIB Bits Register NICAM Error Rate Register PLL_CAPS Readback Register AGC_GAIN Readback Register Automatic Search Function for FM-Carrier Detection in Satellite Mode Manual/Compatibility Mode: Description of DSP Write Registers Additional Channel Matrix Modes Volume Modes of SCART1/2 Outputs FM Fixed Deemphasis FM Adaptive Deemphasis NICAM Deemphasis Identification Mode for A2 Stereo Systems FM DC Notch Manual/Compatibility Mode: Description of DSP Read Registers Stereo Detection Register for A2 Stereo Systems DC Level Register Demodulator Source Channels in Manual Mode Terrestric Sound Standards SAT Sound Standards Exclusions of Audio Baseband Features Phase Relationship of Analog Outputs 4 MICRONAS INTERMETALL PRELIMINARY DATA SHEET MSP 34x1G Contents, continued Page Section Title 99 7. Appendix D: MSP 34x1G Version History 100 8. Appendix E: Application Circuit 102 9. Data Sheet History License Notice: 1) “Dolby”, “Virtual Dolby Surround”, and the double-D Symbol are trademarks of Dolby Laboratories. Supply of this implementation of Dolby Technology does not convey a license nor imply a right under any patent, or any other industrial or intellectual property right of Dolby Laboratories, to use this implementation in any finished end-user or ready-to-use final product. Companies planning to use this implementation in products must obtain a license from Dolby laboratories Licensing Corporation before designing such products. MICRONAS INTERMETALL 5 MSP 34x1G PRELIMINARY DATA SHEET Multistandard Sound Processor Family with Virtual Dolby Surround The hardware and software description in this document is valid for the MSP 34x1G version A1 and following versions. signal conforming to the standard recommended by the Broadcast Television Systems Committee (BTSC). The DBX noise reduction, or alternatively, MICRONAS Noise Reduction (MNR) is performed alignment free. Other processed standards are the Japanese FM-FM multiplex standard (EIA-J) and the FM Stereo Radio standard. 1. Introduction The MSP 34x1G family of single-chip Multistandard Sound Processors covers the sound processing of all analog TV-Standards worldwide, as well as the NICAM digital sound standards. The full TV sound processing, starting with analog sound IF signal-in, down to processed analog AF-out, is performed on a single chip. Figure 1–1 shows a simplified functional block diagram of the MSP 34x1G. The MSP 34x1G has all functions of the MSP 34x0G with the addition of a virtual surround sound feature. Surround sound can be reproduced to a certain extent with two loudspeakers. The MSP 34x1G includes our virtualizer algorithm “3D-PANORAMA” which has been approved by the Dolby1) Laboratories for compliance with the "Virtual Dolby Surround" technology. In addition, the MSP 34x1G includes our “PANORAMA” algorithm. These TV sound processing ICs include versions for processing the multichannel television sound (MTS) ADC Sound IF2 Demodulator I2S1 The MSP 34x1G has built-in automatic functions: The IC is able to detect the actual sound standard automatically (Automatic Standard Detection). Furthermore, pilot levels and identification signals can be evaluated internally with subsequent switching between mono/ stereo/bilingual; no I2C interaction is necessary (Automatic Sound Selection). The ICs are produced in submicron CMOS technology. The MSP 34x1G is available in the following packages: PLCC68, PSDIP64, PSDIP52, PQFP80, and PLQFP64. Preprocessing Prescale I2S2 All MSP 34x1G versions are pin and software downward-compatible to the MSP 34x0D. The MSP 34x1G further simplifies controlling software. Standard selection requires a single I2C transmission only. Source Select Sound IF1 Current ICs have to perform adjustment procedures in order to achieve good stereo separation for BTSC and EIA-J. The MSP 34x1G has optimum stereo performance without any adjustments. Loudspeaker Sound Processing DAC Headphone Sound Processing DAC Loudspeaker Subwoofer Headphone I2S SCART1 DAC SCART2 SCART3 SCART DSP Input Select SCART1 ADC Prescale SCART4 MONO DAC SCART Output Select SCART2 Fig. 1–1: Simplified functional block diagram of the MSP 34x1G 6 MICRONAS INTERMETALL MSP 34x1G PRELIMINARY DATA SHEET 1.1. Features of the MSP 34x1G Family and Differences to MSP 34xxD Feature (New features not available for MSP 34xxD are shaded gray.) 3401 3411 3421 3431 3441 3451 3D-PANORAMA virtualizer (approved by Dolby Laboratories) with noise generator X X X X X X PANORAMA virtualizer algorithm X X X X X X X X X X X X Automatic Standard Detection of terrestrial TV standards X X X X X X Automatic Sound Selection (mono/stereo/bilingual), new registers MODUS, STATUS X X X X X X Two selectable sound IF (SIF) inputs X X X X X X Automatic Carrier Mute function X X X X X X Interrupt output programmable (indicating status change) X X X X X X Loudspeaker / Headphone channel with volume, balance, bass, treble, loudness X X X X X X AVC: Automatic Volume Correction X X X X X X Subwoofer output with programmable low-pass and complementary high-pass filter X X X X X X 5-band graphic equalizer for loudspeaker channel X X X X X X Spatial effect for loudspeaker channel; processing of all deemphasis filtering X X X X X X Four Stereo SCART (line) inputs, one Mono input; two Stereo SCART outputs X X X X X X Complete SCART in/out switching matrix X X X X X X Two I S inputs; one I S output X X X X X X All analog FM-Stereo A2 and satellite standards; AM-SECAM L standard X X X Simultaneous demodulation of (very) high-deviation FM-Mono and NICAM X X X Adaptive deemphasis for satellite (Wegener-Panda, acc. to ASTRA specification) X X X ASTRA Digital Radio (ADR) together with DRP 3510A X X X X X Standard Selection with single 2 I2C transmission 2 All NICAM standards X Demodulation of the BTSC multiplex signal and the SAP channel Alignment free digital DBX noise reduction for BTSC Stereo and SAP X X X X X X Alignment free digital MICRONAS Noise Reduction (MNR) for BTSC Stereo and SAP X BTSC stereo separation (MSP 3421/41G also EIA-J) significantly better than spec. X X X X SAP and stereo detection for BTSC system X X X X X X X Alignment-free Japanese standard EIA-J X X X Demodulation of the FM-Radio multiplex signal X X X Korean FM-Stereo A2 standard X X X 1.2. MSP 34x1G Version List Version Status Description MSP 3401G planned FM Stereo (A2) Version MSP 3411G planned NICAM and FM Stereo (A2) Version MSP 3421G planned NTSC Version (A2 Korea, BTSC with MICRONAS Noise Reduction (MNR), and Japanese EIA-J system) MSP 3431G planned BTSC Version MSP 3441G planned NTSC Version (A2 Korea, BTSC with DBX noise reduction, and Japanese EIA-J system) MSP 3451G available Global Version (all sound standards) MICRONAS INTERMETALL 7 MSP 34x1G PRELIMINARY DATA SHEET 1.3. MSP 34x1G Versions and their Application Fields Table 1–1 provides an overview of TV sound standards that can be processed by the MSP 34x1G family. In addition, the MSP 34x1G is able to handle the terrestrial FM-Radio standard. With the MSP 34x1G, a complete multimedia receiver covering all TV sound standards together with terrestrial and satellite radio sound can be built; even ASTRA Digital Radio can be processed (with a DRP 3510A coprocessor). Table 1–1: TV Stereo Sound Standards covered by the MSP 34x1G IC Family (details see Appendix A) TVSystem 3401 MSP Version Position of Sound Carrier /MHz Sound Modulation Color System Broadcast e.g. in: 5.5/5.7421875 FM-Stereo (A2) PAL Germany 5.5/5.85 FM-Mono/NICAM PAL Scandinavia, Spain L 6.5/5.85 AM-Mono/NICAM SECAM-L France I 6.0/6.552 FM-Mono/NICAM PAL UK, Hong Kong 6.5/6.2578125 FM-Stereo (A2, D/K1) SECAM-East Slovak. Rep. 6.5/6.7421875 FM-Stereo (A2, D/K2) PAL currently no broadcast 6.5/5.7421875 FM-Stereo (A2, D/K3) SECAM-East Poland 6.5/5.85 FM-Mono/NICAM (D/K, NICAM) PAL China, Hungary 6.5 7.02/7.2 7.38/7.56 etc. FM-Mono FM-Stereo PAL Europe Sat. ASTRA 4.5/4.724212 FM-Stereo (A2) NTSC Korea 4.5 FM-FM (EIA-J) NTSC Japan 4.5 BTSC-Stereo + SAP NTSC, PAL USA, Argentina 10.7 FM-Stereo Radio 3411 3401 B/G 3451 D/K M/N 3431 3421, 3441 3401 Satellite FM-Radio 33 ASTRA Digital Radio (ADR) with DRP 3510A 34 39 MHz USA, Europe 4.5 9 MHz SAW Filter Sound IF Mixer Tuner Loudspeaker 1 Subwoofer Mono Vision Demodulator 2 MSP 34x1G SCART1 Headphone 2 SCART Inputs Composite Video SCART2 2 2 2 2 SCART3 SCART4 I2S1 Dolby Pro Logic Processor DPL 351xA ADR SCART1 SCART Outputs SCART2 I2S2 ADR Decoder DRP 3510A Fig. 1–2: Typical MSP 34x1G application 8 MICRONAS INTERMETALL AGC A DEMODULATOR ANA_IN2+ D (incl. Carrier Mute) Decoded Standards: NICAM A2 AM BTSC EIA-J SAT FM-Radio Deemphasis: 50/75 µs DBX/MNR Panda1 FM/AM Prescale Stereo or A/B NICAM Stereo or A Deemphasis: J17 Virtualizer AVC Bass/ Treble or Equal- Σ Loudness Complementary Highpass Lowpass Noise Generator Beeper I2S Interface Bass/ Treble Σ DACM_L Level Adjust A DACM_SUB D DACA_L Balance Loudness A I2S Channel Matrix I2S Interface QuasiPeak Channel Quasi-Peak Detector I2S_DA_OUT I2C ReadRegister SCART A D Prescale SCART1 Channel Matrix SCART2 Channel Matrix Volume D SCART1_L/R A Volume SC1_OUT_L D SCART2_L/R A SCART Output Select SCART DSP Input Select SC3_IN_L SC3_IN_R D I2S2 Prescale SC2_IN_L SC2_IN_R Source Select I2S1 Prescale SC1_IN_L SC1_IN_R Volume DACA_R I2S Interface I2S_DA_IN2 Balance Volume Headphone Channel I2C ReadRegister ADR-Bus Interface I2S_DA_IN1 Spatial Effects DACM_R Stereo or B Prescale Standard and Sound Detection Loudspeaker Channel FM/AM PRELIMINARY DATA SHEET MICRONAS INTERMETALL ANA_IN1+ 2. Functional Description Automatic Sound Select SC1_OUT_R SC2_OUT_L SC2_OUT_R SC4_IN_L SC4_IN_R Fig. 2–1: Signal flow block diagram of the MSP 34x1G (input and output names correspond to pin names) 9 MSP 34x1G MONO_IN MSP 34x1G 2.1. Architecture of the MSP 34x1G Family Fig. 2–1 on page 9 shows a simplified block diagram of the IC. The block diagram contains all features of the MSP 3451G. Other members of the MSP 34x1G family do not have the complete set of features: The demodulator handles only a subset of the standards presented in the demodulator block; NICAM processing is only possible in the MSP 3411G and MSP 3451G. 2.2. Sound IF Processing 2.2.1. Analog Sound IF Input The input pins ANA_IN1+, ANA_IN2+, and ANA_IN− offer the possibility to connect two different sound IF (SIF) sources to the MSP 34x1G. The analog-to-digital conversion of the preselected sound IF signal is done by an A/D-converter. An analog automatic gain circuit (AGC) allows a wide range of input levels. The highpass filters formed by the coupling capacitors at pins ANA_IN1+ and ANA_IN2+ see Section 8. “Appendix E: Application Circuit” on page 100 are sufficient in most cases to suppress video components. Some combinations of SAW filters and sound IF mixer ICs, however, show large picture components on their outputs. In this case, further filtering is recommended. 2.2.2. Demodulator: Standards and Features The MSP 34x1G is able to demodulate all TV-sound standards worldwide including the digital NICAM system. Depending on the MSP 34x1G version, the following demodulation modes can be performed: A2 Systems: Detection and demodulation of two separate FM carriers (FM1 and FM2), demodulation and evaluation of the identification signal of carrier FM2. NICAM Systems: Demodulation and decoding of the NICAM carrier, detection and demodulation of the analog (FM or AM) carrier. For D/K-NICAM, the FM carrier may have a maximum deviation of 384 kHz. Very high deviation FM-Mono: Detection and robust demodulation of one FM carrier with a maximum deviation of 540 kHz. PRELIMINARY DATA SHEET BTSC-Mono + SAP: Detection and FM demodulation of the aural carrier resulting in the MTS/MPX signal. Detection and evaluation of the pilot carrier, detection and FM demodulation of the SAP subcarrier. Processing of DBX noise reduction or MICRONAS Noise Reduction (MNR). Japan Stereo: Detection and FM demodulation of the aural carrier resulting in the MPX signal. Demodulation and evaluation of the identification signal and FM demodulation of the (L−R)-carrier. FM-Satellite Sound: Demodulation of one or two FM carriers. Processing of high-deviation mono or narrow bandwidth mono, stereo, or bilingual satellite sound according to the ASTRA specification. FM-Stereo-Radio: Detection and FM demodulation of the aural carrier resulting in the MPX signal. Detection and evaluation of the pilot carrier and AM demodulation of the (L−R)-carrier. The demodulator blocks of all MSP 34x1G versions have identical user interfaces. Even completely different systems like the BTSC and NICAM systems are controlled the same way. Standards are selected by means of MSP Standard Codes. Automatic processes handle standard detection and identification without controller interaction. The key features of the MSP 34x1G demodulator blocks are Standard Selection: The controlling of the demodulator is minimized: All parameters, such as tuning frequencies or filter bandwidth, are adjusted automatically by transmitting one single value to the STANDARD SELECT register. For all standards, specific MSP standard codes are defined. Automatic Standard Detection: If the TV sound standard is unknown, the MSP 34x1G can automatically detect the actual standard, switch to that standard, and respond the actual MSP standard code. Automatic Carrier Mute: To prevent noise effects or FM identification problems in the absence of an FM carrier, the MSP 34x1G offers a carrier mute feature, which is activated automatically if the TV sound standard is selected by means of the STANDARD SELECT register. If no FM carrier is available at one of the two MSP demodulator channels, the corresponding demodulator output is muted. BTSC-Stereo: Detection and FM demodulation of the aural carrier resulting in the MTS/MPX signal. Detection and evaluation of the pilot carrier, AM demodulation of the (L−R)-carrier and detection of the SAP subcarrier. Processing of DBX noise reduction or MICRONAS Noise Reduction (MNR). 10 MICRONAS INTERMETALL MSP 34x1G PRELIMINARY DATA SHEET 2.2.4. Automatic Sound Select In the Automatic Sound Select mode, the dematrix function is automatically selected based on the identification information in the STATUS register. No I2C interaction is necessary when the broadcasted sound mode changes (e.g. from mono to stereo). The demodulator supports the identification check by switching between mono compatible standards (standards that have the same FM mono carrier) automatically and non-audible. If B/G-FM or B/G-NICAM is selected, the MSP will switch between these standards. The same action is performed for the standards: D/K1-FM, D/K2-FM, and D/K-NICAM. Switching is only done in the absence of any stereo or bilingual identification. If identification is found, the MSP keeps the detected standard. In case of high bit-error rates, the MSP 34x1G automatically falls back from digital NICAM sound to analog FM or AM mono. – “Stereo or B” channel: Analog or digital mono sound, stereo if available. In case of bilingual broadcast, it contains language B (on left and right). Fig 2–2 shows the source channel assignment of the demodulated signals in case of manual mode. If manual mode is required, more information can be found in the section “Demodulator Source Channels in Manual Mode” on page 96. Fig 2–3 and Table 2–2 show the source channel assignment of the demodulated signals in case of Automatic Sound Select mode for all sound standards. Note: The analog primary input channel contains the signal of the mono FM/AM carrier or the L+R signal of the MPX carrier. The secondary input channel contains the signal of the 2nd FM carrier, the L−R signal of the MPX carrier, or the SAP signal. 2.3. Preprocessing for SCART and I2S Input Signals The SCART and I2S inputs need only be adjusted in level by means of the SCART and I2S prescale registers. primary channel LS Ch. Matrix FM/AM FM-Matrix secondary channel Prescale NICAM A NICAM NICAM B Prescale FM/AM NICAM (Stereo or A/B) Table 2–1 summarizes all actions that take place when Automatic Sound Select is switched on. To provide more flexibility, the Automatic Sound Select block prepares four different source channels of demodulated sound (Fig 2–3). By choosing one of the four demodulator channels, the preferred sound mode can be selected for each of the output channels (loudspeaker, headphone, etc.). This is done by means of the Source Select registers. The following source channels of demodulated sound are defined: – “FM/AM” channel: Analog mono sound, stereo if available. In case of NICAM, analog mono only (FM or AM mono). – “Stereo or A/B” channel: Analog or digital mono sound, stereo if available. In case of bilingual broadcast, it contains both languages A (left) and B (right). MICRONAS INTERMETALL 0 Source Select The NICAM signals must be processed by a deemphasis filter and adjusted in level. The analog demodulated signals must be processed by a deemphasis filter, adjusted in level, and dematrixed. The correct deemphasis filters are already selected by setting the standard in the STANDARD SELECT register. The level adjustment has to be done by means of the FM/ AM and NICAM prescale registers. The necessary dematrix function depends on the selected sound standard and the actual broadcasted sound mode (mono, stereo, or bilingual). It can be manually set by the FM Matrix Mode register or automatically set by the Automatic Sound Selection. – “Stereo or A” channel: Analog or digital mono sound, stereo if available. In case of bilingual broadcast, it contains language A (on left and right). Output-Ch. Matrices must be set according the standard 1 SC2 Ch. Matrix Fig. 2–2: Source channel assignment of demodulated signals in Manual Mode primary channel FM/AM secondary channel Prescale NICAM A NICAM B FM/AM 0 Stereo or A/B 1 NICAM Stereo or A 3 Prescale Stereo or B 4 Automatic Sound Select LS Ch. Matrix Source Select 2.2.3. Preprocessing of Demodulator Signals Output-Ch. Matrices must be set once to stereo SC2 Ch. Matrix Fig. 2–3: Source channel assignment of demodulated signals in Automatic Sound Select Mode 11 MSP 34x1G PRELIMINARY DATA SHEET Table 2–1: Performed actions of the Automatic Sound Selection Selected TV Sound Standard Performed Actions B/G-FM, D/K-FM, M-Korea, and M-Japan Evaluation of the identification signal and automatic switching to mono, stereo, or bilingual. Preparing four demodulator source channels according to Table 2–2. Identification is acquired after 500 ms. B/G-NICAM, L-NICAM, I-NICAM, and D/K-NICAM Evaluation of NICAM-C-bits and automatic switching to mono, stereo, or bilingual. Preparing four demodulator source channels according to Table 2–2. NICAM detection is acquired within 150 ms. In case of bad or no NICAM reception, the MSP switches automatically to FM/AM mono and switches back to NICAM if possible. A hysteresis prevents periodical switching. B/G-FM, B/G-NICAM or D/K1-FM, D/K2-FM, D/K3-FM, and D/K-NICAM Automatic searching for stereo/bilingual-identification in case of mono transmission. Automatic and nonaudible changes between Dual-FM and FM-NICAM standards while listening to the basic FM-Mono sound carrier. Example: If starting with B/G-FM-Stereo, there will be a periodical alternation to B/G-NICAM in the absence of FM-Stereo/Bilingual or NICAM-identification. Once an identification is detected, the MSP keeps the corresponding standard. BTSC-STEREO, FM Radio Evaluation of the pilot signal and automatic switching to mono or stereo. Preparing four demodulator source channels according to Table 2–2. Detection of the SAP carrier. Pilot detection is acquired after 200 ms. BTSC-SAP In the absence of SAP, the MSP switches to BTSC-Stereo if available. If SAP is detected, the MSP switches automatically to SAP (see Table 2–2). Table 2–2: Sound modes for the demodulator source channels with Automatic Sound Select Source Channels in Automatic Sound Select Mode Broadcasted Sound Standard Selected MSP Standard Code3) Broadcasted Sound Mode FM/AM Stereo or A/B Stereo or A Stereo or B (source select: 0) (source select: 1) (source select: 3) (source select: 4) M-Korea B/G-FM D/K-FM M-Japan 02 03, 081) 04, 05, 07, 0B1) 30 MONO Mono Mono Mono Mono STEREO Stereo Stereo Stereo Stereo BILINGUAL: Languages A and B Left = A Right = B Left = A Right = B A B NICAM not available or error rate too high analog Mono analog Mono analog Mono analog Mono MONO analog Mono NICAM Mono NICAM Mono NICAM Mono STEREO analog Mono NICAM Stereo NICAM Stereo NICAM Stereo BILINGUAL: Languages A and B analog Mono Left = NICAM A Right = NICAM B NICAM A NICAM B MONO Mono Mono Mono Mono STEREO Stereo Stereo Stereo Stereo MONO+SAP Mono Mono Mono Mono STEREO+SAP Stereo Stereo Stereo Stereo MONO+SAP Left = Mono Right = SAP Left = Mono Right = SAP Mono SAP STEREO+SAP Left = Mono Right = SAP Left = Mono Right = SAP Mono SAP MONO Mono Mono Mono Mono STEREO Stereo Stereo Stereo Stereo B/G-NICAM L-NICAM I-NICAM D/K-NICAM D/K-NICAM 08, 032) 09 0A 0B, 042), 052) 0C (with high deviation FM) 20, 21 20 BTSC 21 FM Radio 1) 2) 3) 12 40 The Automatic Sound Select process will automatically switch to the mono compatible analog standard. The Automatic Sound Select process will automatically switch to the mono compatible digital standard. The MSP Standard Codes are defined in Table 3–7 on page 25. MICRONAS INTERMETALL MSP 34x1G PRELIMINARY DATA SHEET 2.4. Source Selection and Output Channel Matrix The Source Selector makes it possible to distribute all source signals (one of the demodulator source channels, SCART, or I2S input) to the desired output channels (loudspeaker, headphone, etc.). All input and output signals can be processed simultaneously. Each source channel is identified by a unique source address. For each output channel, the sound mode can be set to sound A, sound B, stereo, or mono by means of the output channel matrix. output level [dBr] −12 −18 −24 −30 −24 −18 −12 −6 0 +6 input level [dBr] If Automatic Sound Select is on, the output channel matrix can stay fixed to stereo (transparent) for demodulated signals. Fig. 2–4: Simplified AVC characteristics 2.5. Audio Baseband Processing 2.5.2. Loudspeaker and Headphone Outputs 2.5.1. Automatic Volume Correction (AVC) The following baseband features are implemented in the loudspeaker and headphone output channels: bass/treble, loudness, balance, and volume. A square wave beeper can be added to the loudspeaker and headphone channel. The loudspeaker channel additionally performs: equalizer (not simultaneously with bass/treble), spatial effects, and a subwoofer crossover filter. Different sound sources (e.g. terrestrial channels, SAT channels, or SCART) fairly often do not have the same volume level. Advertisements during movies usually have a higher volume level than the movie itself. This results in annoying volume changes. The Automatic Volume Correction (AVC) solves this problem by equalizing the volume level. To prevent clipping, the AVC’s gain decreases quickly in dynamic boost conditions. To suppress oscillation effects, the gain increases rather slowly for low level inputs. The decay time is programmable by means of the AVC register (see page 34). For input signals ranging from −24 dBr to 0 dBr, the AVC maintains a fixed output level of −18 dBr. Fig. 2–4 shows the AVC output level versus its input level. For prescale and volume registers set to 0 dB, a level of 0 dBr corresponds to full scale input/output. This is – SCART input/output 0 dBr = 2.0 Vrms 2.5.3. Subwoofer Output The subwoofer signal is created by combining the left and right channels directly behind the loudness block using the formula (L+R)/2. Due to the division by 2, the D/A converter will not be overloaded, even with full scale input signals. The subwoofer signal is filtered by a third-order low-pass with programmable corner frequency followed by a level adjustment. At the loudspeaker channels, a complementary high-pass filter can be switched on. Subwoofer and loudspeaker output use the same volume (Loudspeaker Volume Register). – Loudspeaker and Aux output 0 dBr = 1.4 Vrms 2.5.4. Quasi-Peak Detector The quasi-peak readout register can be used to read out the quasi-peak level of any input source. The feature is based on following filter time constants: attack time: 1.3 ms decay time: 37 ms MICRONAS INTERMETALL 13 MSP 34x1G PRELIMINARY DATA SHEET 2.6. Virtual Surround System Application Tips 2.6.3. Loudspeaker Requirements 2.6.1. Sweet Spot The loudspeakers used and their positioning inside the TV set will greatly influence the performance of the virtualizer. The algorithm works with the direct sound path. Reflected sound waves reduce the effect. So it’s most important to have as much direct sound as possible, compared to indirect sound. Good results are only obtained in a rather close area along the middle axis between the two loudspeakers: the sweet spot. Moving away from this position degrades the effect. 2.6.2. Clipping For the test at Dolby Labs, it is very important to have no clipping effects even with worst case signals. That is, 2 Vrms input signal may not clip. The SCART Input Prescale register has to be set to values of 19hex (25dec) or lower (see SCART Input Prescale on page 31). Test signals: sine sweep with 2 VRMS; L only, R only, L&R equal phase, L&R anti phase. Listening tests: Dolby Trailers (train trailer, city trailer, canyon trailer...) To obtain the approval for a TV set, Dolby Laboratories require mounting the loudspeakers in front of the set. Loudspeakers radiating to the side of the TV set will not produce convincing effects. Good directionality of the loudspeakers towards the listener is optimal. The virtualizer was specially developed for implementation in TV sets. Even for rather small stereo TV's, sufficient sound effects can be obtained. For small sets, the loudspeaker placement should be to the side of the CRT; for large screen sets (or 16:9 sets), mounting the loudspeakers below the CRT is acceptable (large separation is preferred, low frequency speakers should be outmost to avoid cancellation effects). Using external loudspeakers with a large stereo base will not create optimal effects. The loudspeakers should be able to reproduce a wide frequency range. The most important frequency range starts from 160 Hz and ranges up to 5 kHz. Great care has to be taken with systems that use one common subwoofer: A single loudspeaker cannot reproduce virtual sound locations. The crossover frequency must be lower than 120 Hz. 2.6.4. Cabinet Requirements During listening tests at Dolby Laboratories, no resonances in the cabinet should occur. Good material to check for resonances are the Dolby Trailers or other dynamic sound tracks. 14 MICRONAS INTERMETALL MSP 34x1G PRELIMINARY DATA SHEET 2.7. SCART Signal Routing 2.8. I2S Bus Interface 2.7.1. SCART DSP In and SCART Out Select It is possible to route in an external coprocessor for special effects, like surround processing and sound field processing. Routing can be done with each input source and output channel via the I2S inputs and outputs. The SCART DSP Input Select and SCART Output Select blocks include full matrix switching facilities. To design a TV set with four pairs of SCART-inputs and two pairs of SCART-outputs, no external switching hardware is required. The switches are controlled by the ACB user register (see page 40). 2.7.2. Stand-by Mode If the MSP 34x1G is switched off by first pulling STANDBYQ low and then (after >1 µs delay) switching off the 5-V, but keeping the 8-V power supply (‘Standby’-mode), the SCART switches maintain their position and function. This allows the copying from selected SCART-inputs to SCART-outputs in the TV set’s stand-by mode. In case of power on or starting from stand-by (switching on the 5-V supply, RESETQ going high 2 ms later), all internal registers except the ACB register (page 40) are reset to the default configuration (see Table 3–5 on page 22). The reset position of the ACB register becomes active after the first I2C transmission into the Baseband Processing part (subaddress 12hex). By transmitting the ACB register first, the reset state can be redefined. Two possible interface formats are supported: 1. The SONY format: I2S_WS changes at the word boundaries. 2. The PHILIPS format: I2S_WS changes one I2S_CL period before the word boundaries. The I2S bus interface consists of five pins: 1. I2S_DA_IN1, I2S_DA_IN2: For input, four channels (two channels per line, 2*16 bits) per sampling cycle (32 kHz) are transmitted. 2. I2S_DA_OUT: For output, two channels (2*16 bits) per sampling cycle (32 kHz) are transmitted. 3. I2S_CL: Gives the timing for the transmission of I2S serial data (1.024 MHz). 4. I2S_WS: The I2S_WS word strobe line defines the left and right sample. The MSP 34x1G normally serves as the master on the I2S interface. In this case, the clock and word strobe lines are driven by the MSP 34x1G. In slave mode, these lines are input to the MSP 34x1G and the master clock is synchronized to 576 times the I2S_WS rate (32 kHz). NICAM operation is not possible in this mode. All I2S options can be set by means of the MODUS register (see page 28). A precise I2S timing diagram is shown in Fig. 4–26 on page 70. MICRONAS INTERMETALL 15 MSP 34x1G PRELIMINARY DATA SHEET 2.9. ADR Bus Interface 2.11. Clock PLL Oscillator and Crystal Specifications For the ASTRA Digital Radio System (ADR), the MSP 3401G, MSP 3411G and MSP 3451G performs preprocessing such as carrier selection and filtering. Via the 3-line ADR-bus, the resulting signals are transferred to the DRP 3510A coprocessor, where the source decoding is performed. To be prepared for an upgrade to ADR with an additional DRP board, the following lines of MSP 34x1G should be provided on a feature connector: The MSP 34x1G derives all internal system clocks from the 18.432-MHz oscillator. In NICAM or in I2SSlave mode, the clock is phase-locked to the corresponding source. Therefore, it is not possible to use NICAM and I2S-Slave mode at the same time. – AUD_CL_OUT – I2S_DA_IN1 or I2S_DA_IN2 – I2S_DA_OUT – I2S_WS – I2S_CL – ADR_CL, ADR_WS, ADR_DA For more details, please refer to the DRP 3510A data sheet. For proper performance, the MSP clock oscillator requires a 18.432-MHz crystal. Note that for the phase-locked modes (NICAM, I2S-Slave), crystals with tighter tolerance are required. Remark on using the crystal: External capacitors at each crystal pin to ground are required. They are necessary for tuning the open-loop frequency of the internal PLL and for stabilizing the frequency in closed-loop operation. The higher the capacitors, the lower the resulting clock frequency. The nominal free running frequency should match 18.432 MHz as closely as possible. Clock measurements should be done at pin AUD_CL_OUT. This pin must be activated for this purpose (see Table 3–9 on page 28). 2.10.Digital Control I/O Pins and Status Change Indication The static level of the digital input/output pins D_CTR_I/O_0/1 is switchable between HIGH and LOW via the I2C-bus by means of the ACB register (see page 40). This enables the controlling of external hardware switches or other devices via I2C-bus. The digital input/output pins can be set to high impedance by means of the MODUS register (see page 28). In this mode, the pins can be used as input. The current state can be read out of the STATUS register (see page 29). Optionally, the pin D_CTR_I/O_1 can be used as an interrupt request signal to the controller, indicating any changes in the read register STATUS. This makes polling unnecessary, I2C bus interactions are reduced to a minimum (see STATUS register on page 29 and MODUS register on page 28). 16 MICRONAS INTERMETALL PRELIMINARY DATA SHEET 3. Control Interface 3.1. I2C Bus Interface 3.1.1. Device and Subaddresses The MSP 34x1G is controlled via the I2C bus slave interface. MSP 34x1G performed some other function (for example, servicing an internal interrupt), it will hold the clock line I2C_CL LOW to force the transmitter into a wait state. The positions within a transmission where this may happen are indicated by ’Wait’ in section 3.1.3. The maximum wait period of the MSP during normal operation mode is less than 1 ms. The IC is selected by transmitting one of the MSP 34x1G device addresses. In order to allow up to three MSP ICs to be connected to a single bus, an address select pin (ADR_SEL) has been implemented. With ADR_SEL pulled to high, low, or left open, the MSP 34x1G responds to different device addresses. A device address pair is defined as a write address (80, 84, or 88 hex) and a read address (81, 85, or 89 hex) (see Table 3–1). Internal hardware error handling: Writing is done by sending the device write address, followed by the subaddress byte, two address bytes, and two data bytes. Reading is done by sending the write device address, followed by the subaddress byte and two address bytes. Without sending a stop condition, reading of the addressed data is completed by sending the device read address (81, 85, or 89 hex) and reading two bytes of data. Refer to section 3.1.3. for the I2C bus protocol and to section “Programming Tips” on page 44 for proposals of MSP 34x1G I2C telegrams. See Table 3–2 for a list of available subaddresses. 1. MSP 34x1G-versions until A1: To indicate the error status, all further acknowledge bits will be left high. The MSP can then be reset by transmitting the reset condition to CONTROL while ignoring the missing acknowledge bits. Besides the possibility of hardware reset, the MSP can also be reset by means of the RESET bit in the CONTROL register by the controller via I2C bus. Due to the internal architecture of the MSP 34x1G, the IC cannot react immediately to an I2C request. The typical response time is about 0.3 ms. If the MSP cannot accept another complete byte of data until it has MICRONAS INTERMETALL In case of any internal hardware error (e.g. interruption of the power supply of the MSP), the MSP’s wait period is extended to 1.8 ms. After this time period elapses, the MSP releases data and clock lines. Indication and solving of the error status: 2. MSP 34x1G-versions from A2 on: To indicate the error status, the remaining acknowledge bits of the actual I2C-protocol will be left high. Additionally, bit[14] of CONTROL is set to one. The MSP can then be reset via the I2C bus by transmitting the reset condition to CONTROL. Indication of reset (only versions from A2 on): Any reset, even caused by an unstable reset line etc., is indicated in bit[15] of CONTROL. A general timing diagram of the I2C bus is shown in Fig. 4–25 on page 68. 17 MSP 34x1G PRELIMINARY DATA SHEET Table 3–1: I2C Bus Device Addresses ADR_SEL Low High Left Open Mode Write Read Write Read Write Read MSP device address 80 hex 81 hex 84 hex 85 hex 88 hex 89 hex Table 3–2: I2C Bus Subaddresses Name Binary Value Hex Value Mode Function CONTROL 0000 0000 00 Read/Write Write: Software reset of MSP (see Table 3–3) Read: Hardware error status of MSP TEST 0000 0001 01 Write only for internal use WR_DEM 0001 0000 10 Write write address demodulator RD_DEM 0001 0001 11 Write read address demodulator WR_DSP 0001 0010 12 Write write address DSP RD_DSP 0001 0011 13 Write read address DSP 3.1.2. Description of CONTROL Register Table 3–3: CONTROL as a Write Register Name Subaddress Bit[15] (MSB) Bits[14:0] CONTROL 00 hex 1 : RESET 0 : normal 0 Table 3–4: CONTROL as a Read Register (only MSP 34x1G-versions from A2 on) Name Subaddress Bit[15] (MSB) Bit[14] Bits[13:0] CONTROL 00 hex Reset status after last reading of CONTROL: 0 : no reset occured 1 : reset occured Internal hardware status: 0 : no error occured 1 : internal error occured not of interest Reading of CONTROL will reset the bits[15,14] of CONTROL. After Power-on, bit[15] of CONTROL will be set; it must be read once to be resetted. 18 MICRONAS INTERMETALL MSP 34x1G PRELIMINARY DATA SHEET 3.1.3. Protocol Description Write to DSP or Demodulator S Wait write device address ACK sub-addr ACK addr-byte ACK addr-byte ACK data-byte- ACK data-byte ACK P high low high low Read from DSP or Demodulator S Wait write device address ACK sub-addr ACK addr-byte ACK addr-byte ACK S high low read device address Wait ACK data-byte- ACK data-byte NAK P high low Write to Control or Test Registers S Wait write device address Note: S = P= ACK = NAK = Wait = ACK sub-addr ACK data-byte ACK data-byte ACK P high low I2C-Bus Start Condition from master I2C-Bus Stop Condition from master Acknowledge-Bit: LOW on I2C_DA from slave (= MSP, light gray) or master (= controller dark gray) Not Acknowledge-Bit: HIGH on I2C_DA from master (dark gray) to indicate ‘End of Read’ or from MSP indicating internal error state I2C-Clock line is held low, while the MSP is processing the I2C command. This waiting time is max. 1 ms 1 0 I2C_DA S P I2C_CL Fig. 3–1: I2C bus protocol (MSB first; data must be stable while clock is high) MICRONAS INTERMETALL 19 MSP 34x1G PRELIMINARY DATA SHEET 3.1.4. Proposals for General MSP 34x1G I2C Telegrams 3.1.4.1. Symbols write device address (80hex, 84hex or 88hex) read device address (81hex, 85hex or 89hex) Start Condition Stop Condition Address Byte Data Byte daw dar < > aa dd 3.1.4.2. Write Telegrams <daw 00 d0 00> <daw 10 aa aa dd dd> <daw 12 aa aa dd dd> write to CONTROL register write data into demodulator write data into DSP 3.1.4.3. Read Telegrams <daw 11 aa aa <dar dd dd> <daw 13 aa aa <dar dd dd> read data from demodulator read data from DSP 3.1.4.4. Examples <80 <80 <80 <80 <80 00 00 10 11 12 80 00 00 02 00 00> 00> 20 00 03> 00 <81 dd dd> 08 01 20> RESET MSP statically Clear RESET Set demodulator to stand. 03hex Read STATUS Set loudspeaker channel source to NICAM and Matrix to STEREO More examples of typical application protocols are listed in section “Programming Tips” on page 44. 20 MICRONAS INTERMETALL PRELIMINARY DATA SHEET MSP 34x1G 3.2. Start-Up Sequence: Power-Up and I2C Controlling After POWER ON or RESET (see Fig. 4–24), the IC is in an inactive state. All registers are in the reset position (see tables 3–5 and 3–6), the analog outputs are muted. The controller has to initialize all registers for which a non-default setting is necessary. 3.3. MSP 34x1G Programming Interface 3.3.1. User Registers Overview The MSP 34x1G is controlled by means of user registers. The complete list of all user registers is given in the following tables. The registers are partitioned into the Demodulator section (Subaddress 10hex for writing, 11hex for reading) and the Baseband Processing sections (Subaddress 12hex for writing, 13hex for reading). Write and read registers are 16-bit wide, whereby the MSB is denoted bit [15]. Transmissions via I2C bus have to take place in 16-bit words (two byte transfers, with the most significant byte transferred first). All write registers, except the demodulator write registers, are readable. Unused parts of the 16-bit write registers must be zero. Addresses not given in this table must not be written. For reasons of software compatibility to the MSP 34x0D, an Manual/Compatibility Mode is available. More read and write registers together with a detailed description of this mode can be found in the “Appendix B: Manual/Compatibility Mode” on page 83. An overview of all MSP 34x1G Write Registers is shown in Table 3–5; all Read Registers are given in Table 3–6. MICRONAS INTERMETALL 21 MSP 34x1G PRELIMINARY DATA SHEET Table 3–5: List of MSP 34x1G Write Registers Write Register Address (hex) Bits Description and Adjustable Range Reset See Page Initial Programming of complete Demodulator 00 00 26 00 00 28 33 I2C Subaddress = 10hex ; Registers are not readable STANDARD SELECT MODUS 00 20 00 30 [15..0] [15..0] Demodulator, Automatic and I2S options I2C Subaddress = 12hex ; Registers are all readable by using I2C Subaddress = 13hex Volume loudspeaker channel 00 00 Volume / Mode loudspeaker channel Balance loudspeaker channel [L/R] 00 01 Balance mode loudspeaker [15..8] [+12 dB ... −114 dB, MUTE] MUTE [7..0] 1/8 dB Steps, Reduce Volume / Tone Control / Compromise 00hex [15..8] [0...100 / 100% and 100 / 0...100%] [−127...0 / 0 and 0 / −127...0 dB] 100%/100% [7..0] [Linear mode / logarithmic mode] linear mode 34 Bass loudspeaker channel 00 02 [15..8] [+20 dB ... −12 dB] 0 dB 35 Treble loudspeaker channel 00 03 [15..8] [+15 dB ... −12 dB] 0 dB 36 Loudness loudspeaker channel 00 04 [15..8] [0 dB ... +17 dB] 0 dB 37 [7..0] [NORMAL, SUPER_BASS] NORMAL [15..8] [−100%...OFF...+100%] OFF [7..0] [SBE, SBE+PSE] SBE+PSE [15..8] [+12 dB ... −114 dB, MUTE] MUTE [7..0] 1/8 dB Steps, Reduce Volume / Tone Control 00hex [15..8] [+12 dB ... −114 dB, MUTE] MUTE 39 Loudness filter characteristic Spatial effect strength loudspeaker ch. 00 05 Spatial effect mode/customize Volume headphone channel 00 06 Volume / Mode headphone channel Volume SCART1 output channel Loudspeaker source select 00 07 00 08 Loudspeaker channel matrix Headphone source select 00 09 Headphone channel matrix SCART1 source select 00 0A SCART1 channel matrix I2S source select 00 0B 2 I S channel matrix Quasi-peak detector source select 00 0C Quasi-peak detector matrix 2 2 38 33 [15..8] [FM/AM, NICAM, SCART, I S1, I S2] FM/AM 32 [7..0] [SOUNDA, SOUNDB, STEREO, MONO...] SOUNDA 32 2 2 [15..8] [FM/AM, NICAM, SCART, I S1, I S2] FM/AM 32 [7..0] [SOUNDA, SOUNDB, STEREO, MONO...] SOUNDA 32 [15..8] [FM/AM, NICAM, SCART, I2S1, I2S2] FM/AM 32 [7..0] [SOUNDA, SOUNDB, STEREO, MONO...] SOUNDA 32 [15..8] [FM/AM, NICAM, SCART, I2S1, I2S2] FM/AM 32 [7..0] [SOUNDA, SOUNDB, STEREO, MONO...] SOUNDA 32 2 2 [15..8] [FM/AM, NICAM, SCART, I S1, I S2] FM/AM 32 [7..0] [SOUNDA, SOUNDB, STEREO, MONO...] SOUNDA 32 Prescale SCART input 00 0D [15..8] [00hex ... 7Fhex] 00hex 31 Prescale FM/AM 00 0E [15..8] [00hex ... 7Fhex] 00hex 30 [7..0] [NO_MAT, GSTEREO, KSTEREO] NO_MAT 31 FM matrix Prescale NICAM 00 10 [15..8] [00hex ... 7Fhex] (MSP 3411G, MSP 3451G only) 00hex 31 Prescale I2S2 00 12 [15..8] [00hex ... 7Fhex] 10hex 31 ACB : SCART Switches a. D_CTR_I/O 00 13 [15..0] Bits [15..0] 00hex 40 Beeper 00 14 [15..0] [00hex ... 7Fhex]/[00hex ... 7Fhex] 00/00hex 40 Prescale I2S1 00 16 [15..8] [00hex ... 7Fhex] 10hex 31 Mode tone control 00 20 [15..8] [BASS/TREBLE, EQUALIZER] BASS/TREB 35 22 MICRONAS INTERMETALL MSP 34x1G PRELIMINARY DATA SHEET Table 3–5: List of MSP 34x1G Write Registers, continued Write Register Address (hex) Bits Description and Adjustable Range Reset See Page Equalizer loudspeaker ch. band 1 00 21 [15..8] [+12 dB ... −12 dB] 0 dB 36 Equalizer loudspeaker ch. band 2 00 22 [15..8] [+12 dB ... −12 dB] 0 dB 36 Equalizer loudspeaker ch. band 3 00 23 [15..8] [+12 dB ... −12 dB] 0 dB 36 Equalizer loudspeaker ch. band 4 00 24 [15..8] [+12 dB ... −12 dB] 0 dB 36 Equalizer loudspeaker ch. band 5 00 25 [15..8] [+12 dB ... −12 dB] 0 dB 36 Automatic Volume Correction 00 29 [15..8] [off, on, decay time] off 34 Subwoofer level adjust 00 2C [15..8] [0 dB ... −30 dB, mute] 0 dB 39 Subwoofer corner frequency 00 2D [15..8] [50 Hz ... 400 Hz] 00hex 39 [7..0] [off, on] off 39 [15..8] [0...100 / 100% and 100 / 0...100%] [−127...0 / 0 and 0 / −127...0 dB] 100 %/100 % 34 [7..0] [Linear mode / logarithmic mode] linear mode Subwoofer complementary high-pass Balance headphone channel [L/R] 00 30 Balance mode headphone Bass headphone channel 00 31 [15..8] [+20 dB ... −12 dB] 0 dB 35 Treble headphone channel 00 32 [15..8] [+15 dB ... −12 dB] 0 dB 36 Loudness headphone channel 00 33 [15..8] [0 dB ... +17 dB] 0 dB 37 [7..0] [NORMAL, SUPER_BASS] NORMAL [15..8] [+12 dB ... −114 dB, MUTE] 00hex 39 FM 32 Loudness filter characteristic Volume SCART2 output channel SCART2 source select 00 40 00 41 SCART2 channel matrix I2S1, I2S2] [15..8] [FM, NICAM, SCART, [7..0] [SOUNDA, SOUNDB, STEREO, MONO...] SOUNDA 32 Virtual Surround OFF/ON switch 00 48 [15..8] [OFF/ON] 00hex 41 Virtual Surround spatial effect strength 00 49 [15..8] [0% - 100%] 00hex 41 Virtual Surround 3D effect strength 00 4A [15..8] [0% - 100%] 00hex 41 Virtual Surround mode 00 4B [15..0] [PANORAMA/3D-PANORAMA] 00hex 41 Noise generator 00 4D [15..0] [OFF/ON, Noise_L, Noise_C, Noise_R, Noise_S] 00hex 42 MICRONAS INTERMETALL 23 MSP 34x1G PRELIMINARY DATA SHEET Table 3–6: List of MSP 34x1G Read Registers Read Register Address (hex) Bits Description and Adjustable Range See Page I2C Subaddress = 11hex ; Registers are not writable STANDARD RESULT 00 7E [15..0] Result of Automatic Standard Detection (see Table 3–8) 29 STATUS 02 00 [15..0] Monitoring of internal settings e.g. Stereo, Mono, Mute etc. . 29 2 I C Subaddress = 13hex ; Registers are not writable Quasi peak readout left 00 19 [15..0] [00hex ... 7FFFhex]16 bit two’s complement 43 Quasi peak readout right 00 1A [15..0] [00hex ... 7FFFhex]16 bit two’s complement 43 MSP hardware version code 00 1E [15..8] [00hex ... FFhex] 43 [7..0] [00hex ... FFhex] 43 [15..8] [00hex ... FFhex] 43 [7..0] [00hex ... FFhex] 43 MSP major revision code MSP product code MSP ROM version code 24 00 1F MICRONAS INTERMETALL MSP 34x1G PRELIMINARY DATA SHEET 3.3.2. Description of User Registers Table 3–7: Standard Codes for STANDARD SELECT register MSP Standard Code (Data in hex) TV Sound Standard Sound Carrier Frequencies in MHz MSP 34x1G Version Automatic Standard Detection 00 01 Start Automatic Standard Detection all Standard Selection 00 02 M-Dual FM-Stereo 4.5/4.724212 3401, -11, -21, -41, -51 00 03 B/G -Dual FM-Stereo1) 5.5/5.7421875 3401, -11, -51 00 04 D/K1-Dual FM-Stereo2) 6.5/6.2578125 00 05 D/K2-Dual FM-Stereo2) 6.5/6.7421875 00 06 D/K -FM-Mono with HDEV33), not detectable by Automatic Standard Detection, HDEV33) SAT-Mono (i.e. Eutelsat, s. Table 6–17) 6.5 00 07 D/K3-Dual FM-Stereo 6.5/5.7421875 00 08 B/G -NICAM-FM 00 09 L -NICAM-AM 00 0A I -NICAM-FM 1) 5.5/5.85 3411, -51 6.5/5.85 6.0/6.552 2) 6.5/5.85 00 0B D/K -NICAM-FM 00 0C D/K -NICAM-FM with HDEV24), not detectable by Automatic Standard Detection, for China 6.5/5.85 00 0D D/K -NICAM-FM with HDEV33), not detectable by Automatic Standard Detection, for China 6.5/5.85 00 20 BTSC-Stereo 4.5 3421, -31, -41, -51 00 21 BTSC-Mono + SAP 00 30 M-EIA-J Japan Stereo 4.5 3421, -41, -51 00 40 FM-Stereo Radio 10.7 3421, -31, -41, -51 00 50 SAT-Mono (s. Table 6–17) 6.5 3401, -11, -51 00 51 SAT-Stereo (s. Table 6–17) 7.02/7.20 00 60 SAT ADR (Astra Digital Radio) 7.2 1) 2) 3) 4) In case of Automatic Sound Select, the B/G-codes 3hex and 8hex are equivalent. In case of Automatic Sound Select, the D/K-codes 4hex, 5hex and Bhex are equivalent. HDEV3: Max. FM deviation must not exceed 540 kHz HDEV2: Max. FM deviation must not exceed 360 kHz MICRONAS INTERMETALL 25 MSP 34x1G PRELIMINARY DATA SHEET 3.3.2.1. STANDARD SELECT Register 3.3.2.2. Refresh of STANDARD SELECT Register The TV sound standard of the MSP 34x1G demodulator is determined by the STANDARD SELECT register. There are two ways to use the STANDARD SELECT register: A general refresh of the STANDARD SELECT register is not allowed. However, the following method enables watching the MSP 34x1G “alive” status and detection of accidental resets (only versions A2 and later): – Setting up the demodulator for a TV sound standard by sending the corresponding standard code with a single I2C-Bus transmission. – Starting the Automatic Standard Detection for terrestrial TV standards. This is the most comfortable way to set up the demodulator. Within 0.5 s, the detection and set-up of the actual TV sound standard is performed. The detected standard can be read out of the STANDARD RESULT register by the control processor. This feature is recommended for the primary set-up of a TV set. Outputs should be muted during Automatic Standard Detection. – After Power-on, bit[15] of CONTROL will be set; it must be read once to enable the reset-detection feature. – Reading of the CONTROL register and checking the reset indicator bit[15] . – If bit[15] is “0”, any refresh of the STANDARD SELECT register is not allowed. – If bit[15] is “1”, indicating a reset, a refresh of the STANDARD SELECT register and all other MSPG registers is necessary. The Standard Codes are listed in Table 3–7. Selecting a TV sound standard via the STANDARD SELECT register initializes the demodulator. This includes: AGC, tuning frequency, band-pass filters, demodulation mode (FM, AM, or NICAM), carrier mute, deemphasis, and identification mode. If a present sound standard is impossible for a specific MSP version, it switches to the analog mono sound of this standard. In that case stereo or bilingual processing will not be possible. For a complete setup of the TV sound processing from analog IF input to the source selection, the transmissions as shown in Section 3.5. are necessary. Note: The FM matrix is set automatically if Automatic Sound Select is active (MODUS[0]=1). In this case, the FM matrix will be initialized with “Sound A Mono”. During operation, the FM matrix will be automatically selected according to the actual identification information. For reasons of software compatibility to the MSP 34x0D, a Manual/Compatibility mode is available. A detailed description of this mode can be found on page 83. 26 MICRONAS INTERMETALL MSP 34x1G PRELIMINARY DATA SHEET 3.3.2.3. STANDARD RESULT Register If Automatic Standard Detection is selected in the STANDARD SELECT register, status and result of the Automatic Standard Detection process can be read out of the STANDARD RESULT register. The possible results are based on the mentioned Standard Code and are listed in Table 3–8. Table 3–8: Results of the Automatic Standard Detection Broadcasted Sound Standard STANDARD RESULT Register Read 007Ehex Automatic Standard Detection could not find a sound standard 0000hex In cases where no sound standard has been detected (no standard present, too much noise, strong interferers, etc.) the STANDARD RESULT register contains 00 00hex. In that case, the controller has to start further actions (for example, set the standard according to a preference list or by manual input). B/G-FM 0003hex B/G-NICAM 0008hex I 000Ahex FM-Radio 0040hex As long as the STANDARD RESULT register contains a value greater than 07 FFhex, the Automatic Standard Detection is still active. During this period, the MODUS and STANDARD SELECT register must not be written. The STATUS register will be updated when the Automatic Standard Detection has finished. M-Korea M-Japan M-BTSC 0002hex (if MODUS[14,13]=00) If a present sound standard is impossible for a specific MSP version, it detects and switches to the analog mono sound of this standard. Example: The MSPs 3431G and 3441G will detect a B/G-NICAM signal as standard 3 and will switch to the analog FMMono sound. MICRONAS INTERMETALL 0020hex (if MODUS[14,13]=01) 0030hex (if MODUS[14,13]=10) L-AM D/K1 D/K2 0009hex (if MODUS[12]=0) L-NICAM D/K-NICAM 0009hex (if MODUS[12]=0) 0004hex (if MODUS[12]=1) 000Bhex (if MODUS[12]=1) Automatic Standard Detection still active >07FFhex 27 MSP 34x1G PRELIMINARY DATA SHEET 3.3.2.4. Write Registers on I2C Subaddress 10hex Table 3–9: Write Registers on I2C Subaddress 10hex Register Address Function Name STANDARD SELECTION 00 20hex STANDARD_SEL STANDARD SELECTION Register Defines TV Sound or FM-Radio Standard bit [15:0] 00 01hex 00 02hex ... 00 60hex start Automatic Standard Detection Standard Codes (see Table 3–7)) MODUS 00 30hex MODUS MODUS Register General MSP 34x1G Options bit [0] 0/1 off/on: Automatic Sound Select bit [1] 0/1 disable/enable STATUS change indication by means of the digital I/O pin D_CTR_I/O_1 Necessary condition: MODUS[3] = 0 (active) bit [2] 0 undefined, must be 0 bit [3] 0 1 state of digital output pins D_CTR_I/O_0 and _1 active: D_CTR_I/O_0 and _1 are output pins (can be set by means of the ACB register. see also: MODUS[1]) tristate: D_CTR_I/O_0 and _1 are input pins (level can be read out of STATUS[4,3]) bit [4] 0/1 active/tristate state of I2S output pins bit [5] 0/1 master/slave mode of I2S interface (must be set to 0 (= Master) in case of NICAM mode) bit [6] 0/1 Sony/Philips format of I2S word strobe bit [7] 0/1 active/tristate state of audio clock output pin AUD_CL_OUT bit [8] 0/1 ANA_IN_1+/ANA_IN_2+; select analog sound IF input pin bit [11:9] 0 undefined, must be 0 Preference in Automatic Standard Detection: 0 1 detected 6.5 MHz carrier is interpreted as:1) standard L (SECAM) standard D/K1, D/K2 or D/K NICAM 0 1 2 3 detected 4.5 MHz carrier is interpreted as:1) standard M (Korea) standard M (BTSC) standard M (Japan) carrier at 4.5 MHz is ignored (chroma carrier) 0 undefined, must be 0 bit [12] bit [14:13] bit [15] 1) Valid 28 at the next start of Automatic Standard Detection. MICRONAS INTERMETALL MSP 34x1G PRELIMINARY DATA SHEET 3.3.2.5. Read Registers on I2C Subaddress 11hex Table 3–10: Read Registers on I2C Subaddress 11hex Register Address Function Name STANDARD RESULT 00 7Ehex STANDARD RESULT Register STANDARD_RES Readback of the detected TV Sound or FM-Radio Standard bit [15:0] 00 00hex Automatic Standard Detection could not find a sound standard MSP Standard Codes (see Table 3–8) 00 02hex ... 00 40hex >07 FFhex Automatic Standard Detection still active STATUS 02 00hex STATUS Register STATUS Contains all user relevant internal information about the status of the MSP bit [0] undefined bit [1] 0 1 detected primary carrier (Mono or MPX carrier) no primary carrier detected bit [2] 0 1 detected secondary carrier (2nd A2 or SAP carrier) no secondary carrier detected bit [3] 0/1 low/high level of digital I/O pin D_CTR_I/O_0 bit [4] 0/1 low/high level of digital I/O pin D_CTR_I/O_1 bit [5,9] 00 01 10 analog sound standard (FM or AM) active not obtainable digital sound (NICAM) available (MSP 3411G and MSP 3451G only) bad reception condition of digital sound (NICAM) due to: a. high error rate b. unimplemented sound code c. data transmission only 11 bit [6] 0/1 mono/stereo indication bit [7] 0/1 “1” indicates independent mono sound (only for NICAM on MSP 3411G and MSP 3451G) bit [8] 0/1 “1” indicates bilingual sound mode or SAP present bit [15:10] undefined If STATUS change indication is activated by means of MODUS[1]: Each change in the STATUS register sets the digital I/O pin D_CTR_I/O_1 to high level. Reading the STATUS register resets D_CTR_I/O_1. MICRONAS INTERMETALL 29 MSP 34x1G PRELIMINARY DATA SHEET 3.3.2.6. Write Registers on I2C Subaddress 12hex Table 3–11: Write Registers on I2C Subaddress 12hex Register Address Function Name PREPROCESSING 00 0Ehex PRE_FM FM/AM Prescale bit [15:8] 00hex ... 7Fhex 00hex Defines the input prescale gain for the demodulated FM or AM signal off (RESET condition) For all FM modes except satellite FM and AM-mode, the combinations of prescale value and FM deviation listed below lead to internal full scale. FM mode bit [15:8] 7Fhex 48hex 30hex 24hex 18hex 13hex 28 kHz FM deviation 50 kHz FM deviation 75 kHz FM deviation 100 kHz FM deviation 150 kHz FM deviation 180 kHz FM deviation (limit) FM high deviation mode (HDEV2, MSP Standard Code = Chex) bit [15:8] 30hex 14hex 150 kHz FM deviation 360 kHz FM deviation (limit) FM very high deviation mode (HDEV3, MSP Standard Code = 6 and Dhex) bit [15:8] 20hex 1Ahex 450 kHz FM deviation 540 kHz FM deviation (limit) Satellite FM with adaptive deemphasis bit [15:8] 10hex recommendation AM mode (MSP Standard Code = 9) bit [15:8] 7Chex recommendation for SIF input levels from 0.1 Vpp to 0.8 Vpp (Due to the AGC being switched on, the AM-output level remains stable and independent of the actual SIF-level in the mentioned input range) 30 MICRONAS INTERMETALL MSP 34x1G PRELIMINARY DATA SHEET Table 3–11: Write Registers on I2C Subaddress 12hex, continued Register Address Function Name (continued) FM Matrix Modes FM_MATRIX 00 0Ehex Defines the dematrix function for the demodulated FM signal bit [7:0] 00hex 01hex 02hex 03hex 04hex no matrix (used for bilingual and unmatrixed stereo sound) German stereo (Standard B/G) Korean stereo (also used for BTSC, EIA-J and FM Radio) sound A mono (left and right channel contain the mono sound of the FM/AM mono carrier) sound B mono In case of Automatic Sound Select, the FM Matrix Mode is set automatically, i.e. the low-part of any I2C transmission to the register 00 0Ehex is ignored. To enable a Forced Mono Mode for all analog stereo systems by overriding the internal pilot or identification evaluation, the following steps must be transmitted: 1. MODUS with bit[0] = 0 (Automatic Sound Select off) 2. FM Presc./Matrix with FM Matrix = Sound A Mono (SAP: Sound B Mono) 3. Select FM/AM source channel, with channel matrix set to “Stereo” (transparent) 00 10hex NICAM Prescale PRE_NICAM Defines the input prescale value for the digital NICAM signal bit [15:8] 00hex ... 7Fhex prescale gain examples: off 00hex 0 dB gain 20hex 9 dB gain (recommendation) 5Ahex +12 dB gain (maximum gain) 7Fhex 00 16hex 00 12hex I2S1 Prescale I2S2 Prescale PRE_I2S1 PRE_I2S2 Defines the input prescale value for digital I2S input signals bit [15:8] 00hex ... 7Fhex prescale gain examples: off 00hex 0 dB gain (recommendation) 10hex +18 dB gain (maximum gain) 7Fhex 00 0Dhex SCART Input Prescale PRE_SCART Defines the input prescale value for the analog SCART input signal bit [15:8] 00hex ... 7Fhex prescale gain examples: off 00hex 0 dB gain (2 VRMS input leads to digital full scale) 19hex Due to the Dolby requirements, this is the maximum value allowed to prohibit clipping of a 2 VRMS input signal. +14 dB gain (400 mVRMS input leads to digital full scale) 7Fhex MICRONAS INTERMETALL 31 MSP 34x1G PRELIMINARY DATA SHEET Table 3–11: Write Registers on I2C Subaddress 12hex, continued Register Address Function Name SOURCE SELECT AND OUTPUT CHANNEL MATRIX 00 08hex 00 09hex 00 0Ahex 00 41hex 00 0Bhex 00 0Chex Source for: Loudspeaker Output Headphone Output SCART1 DA Output SCART2 DA Output I2S Output Quasi-Peak Detector bit [15:8] 0 SRC_MAIN SRC_AUX SRC_SCART1 SRC_SCART2 SRC_I2S SRC_QPEAK “FM/AM”: demodulated FM or AM mono signal 1 “Stereo or A/B”: demodulator Stereo or A/B signal (in manual mode, this source is identical to the NICAM source in the MSP 3410D) 3 “Stereo or A”: demodulator Stereo Sound or Language A (only defined for Automatic Sound Select) 4 “Stereo or B”: demodulator Stereo Sound or Language B (only defined for Automatic Sound Select) 2 SCART input 5 I2S1 input 6 I2S2 input For demodulator sources, see Table 2–2. 00 08hex 00 09hex 00 0Ahex 00 41hex 00 0Bhex 00 0Chex Matrix Mode for: Loudspeaker Output Headphone Output SCART1 DA Output SCART2 DA Output I2S Output Quasi-Peak Detector bit [7:0] MAT_MAIN MAT_AUX MAT_SCART1 MAT_SCART2 MAT_I2S MAT_QPEAK Sound A Mono (or Left Mono) 00hex Sound B Mono (or Right Mono) 10hex Stereo (transparent mode) 20hex Mono (sum of left and right inputs divided by 2) 30hex special modes are available (see Section 6.5.1. on page 95) In Automatic Sound Select mode, the demodulator source channels are set according to Table 2–2. Therefore, the matrix modes of the corresponding output channels should be set to “Stereo” (transparent). 32 MICRONAS INTERMETALL MSP 34x1G PRELIMINARY DATA SHEET Table 3–11: Write Registers on I2C Subaddress 12hex, continued Register Address Function Name LOUDSPEAKER AND HEADPHONE PROCESSING 00 00hex 00 06hex VOL_MAIN VOL_AUX Volume Loudspeaker Volume Headphone bit [15:8] volume table with 1 dB step size +12 dB (maximum volume) 7Fhex 7Ehex +11 dB ... 74hex +1 dB 73hex 0 dB −1 dB 72hex ... 02hex −113 dB 01hex −114 dB 00hex Mute (reset condition) Fast Mute (needs about 75 ms until the signal is comFFhex pletely ramped down) bit [7:5] higher resolution volume table 0 +0 dB 1 +0.125 dB increase in addition to the volume table ... 7 +0.875 dB increase in addition to the volume table bit [4] 0 bit [3:0] clipping mode 0 reduce volume 1 reduce tone control 2 compromise mode must be set to 0 With large scale input signals, positive volume settings may lead to signal clipping. The MSP 34x1G loudspeaker and headphone volume function is divided into a digital and an analog section. With Fast Mute, volume is reduced to mute position by digital volume only. Analog volume is not changed. This reduces any audible DC plops. To turn volume on again, the volume step that has been used before Fast Mute was activated must be transmitted. If the clipping mode is set to “Reduce Volume”, the following rule is used: To prevent severe clipping effects with bass, treble, or equalizer boosts, the internal volume is automatically limited to a level where, in combination with either bass, treble, or equalizer setting, the amplification does not exceed 12 dB. If the clipping mode is “Reduce Tone Control”, the bass or treble value is reduced if amplification exceeds 12 dB. If the equalizer is switched on, the gain of those bands is reduced, where amplification together with volume exceeds 12 dB. If the clipping mode is “Compromise Mode”, the bass or treble value and volume are reduced half and half if amplification exceeds 12 dB. If the equalizer is switched on, the gain of those bands is reduced half and half, where amplification together with volume exceeds 12 dB. Example: Red. Volume Red. Tone Con. Compromise MICRONAS INTERMETALL Vol.: +6 dB 3 6 4.5 Bass: +9 dB 9 6 7.5 Treble: +5 dB 5 5 5 33 MSP 34x1G PRELIMINARY DATA SHEET Table 3–11: Write Registers on I2C Subaddress 12hex, continued Register Address Function Name 00 29hex Automatic Volume Correction (AVC) Loudspeaker Channel AVC bit [15:12] 00hex 08hex AVC off (and reset internal variables) AVC on bit [11:8] 8 sec decay time 4 sec decay time 2 sec decay time 20 ms decay time (intended for quick adaptation to the average volume level after channel change) 08hex 04hex 02hex 01hex Note: To reset the internal variables, the AVC should be switched off and then on again during any channel or source change. For standard applications, the recommended decay time is 4 sec. Note: AVC should not be used in any Dolby Prologic mode (with DPL 35xx), except in PANORAMA or 3D-PANORAMA mode, when only the loudspeaker output is active. 00 01hex 00 30hex BAL_MAIN BAL_AUX Balance Loudspeaker Channel Balance Headphone Channel bit [3:0] Balance Mode linear 0hex logarithmic 1hex bit [15:8] Linear Mode Left muted, Right 100% 7Fhex Left 0.8%, Right 100% 7Ehex ... Left 99.2%, Right 100% 01hex Left 100%, Right 100% 00hex Left 100%, Right 99.2% FFhex ... Left 100%, Right 0.8% 82hex Left 100%, Right muted 81hex bit [15:8] Logarithmic Mode Left −127 dB, Right 0 dB 7Fhex Left −126 dB, Right 0 dB 7Ehex ... Left −1 dB, Right 0 dB 01hex Left 0 dB, Right 0 dB 00hex Left 0 dB, Right −1 dB FFhex ... Left 0 dB, Right −127 dB 81hex Left 0 dB, Right −128 dB 80hex Positive balance settings reduce the left channel without affecting the right channel; negative settings reduce the right channel leaving the left channel unaffected. 34 MICRONAS INTERMETALL MSP 34x1G PRELIMINARY DATA SHEET Table 3–11: Write Registers on I2C Subaddress 12hex, continued Register Address Function Name 00 20hex Tone Control Mode Loudspeaker Channel TONE_MODE bit [15:8] 00hex FFhex bass and treble is active equalizer is active Defines whether Bass/Treble or Equalizer is activated for the loudspeaker channel. Bass and Equalizer cannot work simultaneously. If Equalizer is used, Bass, and Treble coefficients must be set to zero and vice versa. 00 02hex 00 31hex Bass Loudspeaker Channel Bass Headphone Channel BASS_MAIN BASS_AUX bit [15:8] normal range +12 dB 60hex 58hex +11 dB ... 08hex +1 dB 00hex 0 dB −1 dB F8hex ... A8hex −11 dB A0hex −12 dB bit [15:8] extended range 7Fhex +20 dB 78hex +18 dB 70hex +16 dB 68hex +14 dB Higher resolution is possible: an LSB step in the normal range results in a gain step of about 1/8 dB, in the extended range about 1/4 dB. With positive bass settings, internal clipping may occur even with overall volume less than 0 dB. This will lead to a clipped output signal. Therefore, it is not recommended to set bass to a value that, in conjunction with volume, would result in an overall positive gain. MICRONAS INTERMETALL 35 MSP 34x1G PRELIMINARY DATA SHEET Table 3–11: Write Registers on I2C Subaddress 12hex, continued Register Address Function Name 00 03hex 00 32hex Treble Loudspeaker Channel Treble Headphone Channel TREB_MAIN TREB_AUX bit [15:8] 78hex 70hex ... 08hex 00hex F8hex ... A8hex A0hex +15 dB +14 dB +1 dB 0 dB −1 dB −11 dB −12 dB Higher resolution is possible: an LSB step results in a gain step of about 1/8 dB. With positive treble settings, internal clipping may occur even with overall volume less than 0 dB. This will lead to a clipped output signal. Therefore, it is not recommended to set treble to a value that, in conjunction with volume, would result in an overall positive gain. 00 21hex 00 22hex 00 23hex 00 24hex 00 25hex EQUAL_BAND1 EQUAL_BAND2 EQUAL_BAND3 EQUAL_BAND4 EQUAL_BAND5 Equalizer Loudspeaker Channel Band 1 (below 120 Hz) Equalizer Loudspeaker Channel Band 2 (center: 500 Hz) Equalizer Loudspeaker Channel Band 3 (center: 1.5 kHz) Equalizer Loudspeaker Channel Band 4 (center: 5 kHz) Equalizer Loudspeaker Channel Band 5 (above: 10 kHz) bit [15:8] 60hex 58hex ... 08hex 00hex F8hex ... A8hex A0hex +12 dB +11 dB +1 dB 0 dB −1 dB −11 dB −12 dB Higher resolution is possible: an LSB step results in a gain step of about 1/8 dB. With positive equalizer settings, internal clipping may occur even with overall volume less than 0 dB. This will lead to a clipped output signal. Therefore, it is not recommended to set equalizer bands to a value that, in conjunction with volume, would result in an overall positive gain. 36 MICRONAS INTERMETALL PRELIMINARY DATA SHEET MSP 34x1G Table 3–11: Write Registers on I2C Subaddress 12hex, continued Register Address Function Name 00 04hex 00 33hex Loudness Loudspeaker Channel Loudness Headphone Channel LOUD_MAIN LOUD_AUX bit [15:8] Loudness Gain +17 dB 44hex 40hex +16 dB ... 04hex +1 dB 00hex 0 dB bit [7:0] Loudness Mode normal (constant volume at 1 kHz) 00hex Super Bass (constant volume at 2 kHz) 04hex Higher resolution of Loudness Gain is possible: An LSB step results in a gain step of about 1/4 dB. Loudness increases the volume of low- and high-frequency signals, while keeping the amplitude of the 1-kHz reference frequency constant. The intended loudness has to be set according to the actual volume setting. Because loudness introduces gain, it is not recommended to set loudness to a value that, in conjunction with volume, would result in an overall positive gain. The corner frequency for bass amplification can be set to two different values. In Super Bass mode, the corner frequency is shifted up. The point of constant volume is shifted from 1 kHz to 2 kHz. MICRONAS INTERMETALL 37 MSP 34x1G PRELIMINARY DATA SHEET Table 3–11: Write Registers on I2C Subaddress 12hex, continued Register Address Function Name 00 05hex Spatial Effects Loudspeaker Channel SPAT_MAIN bit [15:8] Effect Strength Enlargement 100% 7Fhex Enlargement 50% 3Fhex ... Enlargement 1.5% 01hex Effect off 00hex reduction 1.5% FFhex ... reduction 50% C0hex reduction 100% 80hex bit [7:4] Spatial Effect Mode Stereo Basewidth Enlargement (SBE) and 0hex Pseudo Stereo Effect (PSE). (Mode A) Stereo Basewidth Enlargement (SBE) only. (Mode B) 2hex bit [3:0] Spatial Effect High-Pass Gain max. high-pass gain 0hex 2/3 high-pass gain 2hex 1/3 high-pass gain 4hex min. high-pass gain 6hex automatic 8hex Spatial effects should not be used together with 3D-PANORAMA or PANORAMA. There are several spatial effect modes available: In mode A (low byte = 00hex), the spatial effect depends on the source mode. If the incoming signal is mono, Pseudo Stereo Effect is active; for stereo signals, Pseudo Stereo Effect and Stereo Basewidth Enlargement is effective. The strength of the effect is controllable by the upper byte. A negative value reduces the stereo image. A strong spatial effect is recommended for small TV sets where loudspeaker spacing is rather close. For large screen TV sets, a more moderate spatial effect is recommended. In mode B, only Stereo Basewidth Enlargement is effective. For mono input signals, the Pseudo Stereo Effect has to be switched on. It is worth mentioning, that all spatial effects affect amplitude and phase response. With the lower 4 bits, the frequency response can be customized. A value of 0hex yields a flat response for center signals (L = R), but a high-pass function for L or R only signals. A value of 6hex has a flat response for L or R only signals, but a low-pass function for center signals. By using 8hex, the frequency response is automatically adapted to the sound material by choosing an optimal high-pass gain. 38 MICRONAS INTERMETALL MSP 34x1G PRELIMINARY DATA SHEET Table 3–11: Write Registers on I2C Subaddress 12hex, continued Register Address Function Name SUBWOOFER OUTPUT CHANNEL 00 2Chex Subwoofer Level Adjustment bit [15:8] 00hex FFhex ... E3hex E2hex ... 80hex 00 2Dhex 0 dB −1 dB −29 dB −30 dB Mute Subwoofer Corner Frequency bit [15:8] 5...40 00hex 01hex SUBW_FREQ corner frequency in 10-Hz steps (range: 50...400 Hz) Subwoofer Complementary High-Pass Filter bit [7:0] SUBW_LEVEL SUBW_HP loudspeaker channel unfiltered a complementary high-pass is processed in the loudspeaker output channel SCART OUTPUT CHANNEL 00 07hex 00 40hex Volume SCART1 Output Channel Volume SCART2 Output Channel VOL_SCART1 VOL_SCART2 bit [15:8] volume table with 1 dB step size +12 dB (maximum volume) 7Fhex 7Ehex +11 dB ... 74hex +1 dB 73hex 0 dB −1 dB 72hex ... 02hex −113 dB 01hex −114 dB 00hex Mute (reset condition) bit [7:5] higher resolution volume table 0 +0 dB 1 +0.125 dB increase in addition to the volume table ... 7 +0.875 dB increase in addition to the volume table bit [4:0] 01hex MICRONAS INTERMETALL this must be 01hex 39 MSP 34x1G PRELIMINARY DATA SHEET Table 3–11: Write Registers on I2C Subaddress 12hex, continued Register Address Function Name SCART SWITCHES AND DIGITAL I/O PINS 00 13hex ACB_REG ACB Register Defines the level of the digital output pins and the position of the SCART switches bit [15] 0/1 low/high of digital output pin D_CTR_I/O_0 (MODUS[3]=0) bit [14] 0/1 low/high of digital output pin D_CTR_I/O_1 (MODUS[3]=0) bit [13:5] SCART DSP Input Select xxxx00xx0 SCART1 to DSP input (RESET position) xxxx01xx0 MONO to DSP input (Sound A Mono must be selected in the channel matrix mode for the corresponding output channels) xxxx10xx0 SCART2 to DSP input xxxx11xx0 SCART3 to DSP input xxxx00xx1 SCART4 to DSP input xxxx11xx1 mute DSP input bit [13:5] SCART1 Output Select xx00xxx0x SCART3 input to SCART1 output (RESET position) xx01xxx0x SCART2 input to SCART1 output xx10xxx0x MONO input to SCART1 output xx11xxx0x SCART1 DA to SCART1 output xx00xxx1x SCART2 DA to SCART1 output xx01xxx1x SCART1 input to SCART1 output xx10xxx1x SCART4 input to SCART1 output xx11xxx1x mute SCART1 output bit [13:5] SCART2 Output Select 00xxxx0xx SCART1 DA to SCART2 output (RESET position) 01xxxx0xx SCART1 input to SCART2 output 10xxxx0xx MONO input to SCART2 output 00xxxx1xx SCART2 DA to SCART2 output 01xxxx1xx SCART2 input to SCART2 output 10xxxx1xx SCART3 input to SCART2 output 11xxxx1xx SCART4 input to SCART2 output 11xxxx0xx mute SCART2 output The RESET position becomes active at the time of the first write transmission on the control bus to the audio processing part. By writing to the ACB register first, the RESET state can be redefined. BEEPER 00 14hex Beeper Volume and Frequency BEEPER bit [15:8] Beeper Volume off 00hex maximum volume 7Fhex bit [7:0] 40 Beeper Frequency 16 Hz (lowest) 01hex 1 kHz 40hex 4 kHz FFhex MICRONAS INTERMETALL MSP 34x1G PRELIMINARY DATA SHEET Table 3–11: Write Registers on I2C Subaddress 12hex, continued Register Address Function Name VIRTUAL SURROUND PROCESSING 00 48hex Virtual Surround OFF/ON Switch VIRT_ON bit [15:8] bit [7:0] 00hex 01hex virtual surround sound off (normal baseband processing) virtual surround processing 00hex must be 0 Be sure to switch off Spatial Effects Loudspeaker Channel (register 0005hex) if 3D-PANORAMA is in use. 00 49hex Virtual Surround Spatial Effects VIRT_SPAT bit [15:8] Spatial Effect Strength Enlargement 100% 7Fhex Enlargement 50% 3Fhex ... Enlargement 1.5% 01hex Effect off 00hex bit [7:0] 00hex must be 0 Increases the perceived basewidth of the reproduced left and right front channels. Recommended value: 50% = 40hex. In contrast to the spatial effect for the loudspeaker channel, the surround spatial effect is optimized for virtual surround. 00 4Ahex Virtual Surround 3D Effect Strength VIRT_3DEFF bit [15:8] Virtual Surround Effect Strength Effect 100% 7Fhex Effect 50% 3Fhex ... Effect 1.5% 01hex Effect off 00hex bit [7:0] 00hex must be 0 Strength of the surround effect in PANORAMA or 3D-PANORAMA mode. Recommended value: 66% = 54hex. 00 4Bhex Virtual Surround Mode bit [15:8] 00hex must be 0 bit [7:0] PANORAMA virtualizer 3D-PANORAMA virtualizer 50hex 60hex MICRONAS INTERMETALL VIRT_MODE 41 MSP 34x1G PRELIMINARY DATA SHEET Table 3–11: Write Registers on I2C Subaddress 12hex, continued Register Address Function Name NOISE GENERATOR 00 4Dhex NOISE_CHAN Noise Generator bit [15:8] 00hex 80hex Noise generator off Noise generator on bit [7:0] Noise on left channel Noise on center channel Noise on right channel Noise on surround channel A0hex B0hex C0hex D0hex Determines the active channel for the noise generator. 42 MICRONAS INTERMETALL MSP 34x1G PRELIMINARY DATA SHEET 3.3.2.7. Read Registers on I2C Subaddress 13hex Table 3–12: Read Registers on I2C Subaddress 13hex Register Address Function Name QUASI-PEAK DETECTOR READOUT 00 19hex 00 1Ahex Quasi-Peak Detector Readout Left Quasi-Peak Detector Readout Right QPEAK_L QPEAK_R bit [15..0] 0hex... 7FFFhex values are 16 bit two’s complement (only positive) MSP 34X1G VERSION READOUT REGISTERS 00 1Ehex MSP Hardware Version Code bit [15..8] 01hex MSP_HARD MSP 34x1G - A1 A change in the hardware version code defines hardware optimizations that may have influence on the chip’s behavior. The readout of this register is identical to the hardware version code in the chip’s imprint. MSP Major Revision Code bit [7..0] 07hex MSP_REVISION MSP 34x1G - A1 The major revision code of the MSP 34x1G is 7. 00 1Fhex MSP_PRODUCT MSP Product Code bit [15..8] 01hex 0Bhex 1Fhex 29hex 33hex MSP 3401G - A1 MSP 3411G - A1 MSP 3431G - A1 MSP 3441G - A1 MSP 3451G - A1 By means of the MSP-Product Code, the control processor is able to decide which TV sound standards have to be considered. MSP ROM Version Code bit [7..0] 41hex 42hex MSP_ROM MSP 34x1G - A1 MSP 34x1G - A2 A change in the ROM version code defines internal software optimizations, that may have influence on the chip’s behavior, e.g. new features may have been included. While a software change is intended to create no compatibility problems, customers that want to use the new functions can identify new MSP 34x1G versions according to this number. To avoid compatibility problems with MSP 3410B and MSP 34x0D, an offset of 40hex is added to the ROM version code of the chip’s imprint. MICRONAS INTERMETALL 43 MSP 34x1G PRELIMINARY DATA SHEET 3.4. Programming Tips 3.5. Examples of Minimum Initialization Codes This section describes the preferred method for initializing the MSP 34x1G. The initialization is grouped into four sections: analog signal path, demodulator input, input processing for SCART and I2S, and output processing. See Fig. 2–1 on page 9 for a complete signal flow. Initialization of the MSP 34x1G according to these listings reproduces sound of the selected standard on the loudspeaker output. All numbers are hexadecimal. The examples have the following structure: 1. Perform an I2C controlled reset of the IC. 2. Write MODUS register (with Automatic Sound Select). SCART Signal Path 1. Select analog input for the SCART baseband processing (SCART DSP Input Select) by means of the ACB register. 2. Select the source for each analog SCART output (SCART Output Select) by means of the ACB register. Demodulator Input For a complete setup of the TV sound processing from analog IF input to the source selection, the following steps must be performed: 1. Set MODUS register to the preferred mode and Sound IF input. 3. Set Source Selection for loudspeaker channel (with matrix set to STEREO). 4. Set Prescale (FM and/or NICAM and dummy FM matrix). 5. Write STANDARD SELECT register. 6. Set Volume loudspeaker channel to 0 dB. 3.5.1. SCART1 Input to Loudspeaker in Stereo Sound <80 00 00 00 80 00> // reset <80 00 00 00 00 00> <80 12 00 08 02 20> // source loudspeaker = scart, stereo <80 12 00 0d 19 00> // prescale scart <80 12 00 00 73 00> // volume main = 0dB 2. Choose preferred prescale (FM and NICAM) values. 3. Write STANDARD SELECT register. 3.5.2. SCART1 Input to Loudspeaker in 3D-PANORAMA Sound If Automatic Sound Select is not active, the following step has to be done repeatedly: <80 00 00 00 80 00> 4. Choose FM matrix according to the sound mode indicated in the STATUS register. <80 12 00 08 02 20> // source loudspeaker = scart, stereo <80 12 00 0d 19 00> // prescale scart 2S SCART and I Inputs 1. Select preferred prescale for SCART. // reset <80 00 00 00 00 00> <80 12 00 00 73 00> // volume main = 0dB <80 12 00 48 01 00> // virtual surround sound: on <80 12 00 49 40 00> // Surround spatial effect = 50% <80 12 00 4a 54 00> // panorama sound effect = 66% 2. Select preferred prescale for I2S inputs (set to 0 dB after RESET). <80 12 00 4b 00 60> // Surround mode = 3d_panorama <80 12 00 4d 00 00> // Noise Sequencer = off Output Channels 3.5.3. Noise Sequencer for 3D-PANORAMA Sound 1. Select the source channel and matrix for each output channel. // switch into 3D-PANORAMA sound (s.a.). Then: 2. Set audio baseband processing. 3. Select volume for each output channel. <80 12 00 4d 80 a0> // noise L [wait for 2 seconds] <80 12 00 4d 80 b0> // noise C [wait for 2 seconds] <80 12 00 4d 80 c0> // noise R [wait for 2 seconds] <80 12 00 4d 80 d0> // noise S [wait for 2 seconds] // switch back to normal operation <80 12 00 4d 00 00> 44 // Noise Sequencer = off MICRONAS INTERMETALL MSP 34x1G PRELIMINARY DATA SHEET 3.5.4. B/G-FM (A2 or NICAM) 3.5.7. FM-Stereo Radio <80 00 80 00> <80 00 80 00> // Softreset <80 00 00 00> // Softreset <80 00 00 00> <80 10 00 30 20 03> // MODUS-Register: Automatic = on <80 10 00 30 20 03> // MODUS-Register: Automatic = on <80 12 00 08 03 20> // Source Sel. = (St or A) & Ch. Matr. = St <80 12 00 08 03 20> // Source Sel. = (St or A) & Ch. Matr. = St <80 12 00 0E 24 03> // FM/AM-Prescale = 24hex, FM-Matrix = MONO/SOUNDA <80 12 00 0E 24 03> // FM/AM-Prescale = 24hex, FM-Matrix = Sound A Mono <80 12 00 10 00 5A> // NICAM-Prescale = 5Ahex <80 10 00 20 00 40> // Standard Select: FM-STEREO-RADIO <80 10 00 20 00 03> or <80 10 00 20 00 08> // Standard Select: A2 B/G or NICAM B/G <80 12 00 00 73 00> // Loudspeaker Volume 0 dB <80 12 00 00 73 00> // Loudspeaker Volume 0 dB 3.5.8. Automatic Standard Detection A detailed software flow diagram is shown in Fig. 3–2 on page 46. 3.5.5. BTSC-Stereo <80 00 80 00> // Softreset <80 00 80 00> <80 00 00 00> <80 10 00 30 20 03> // MODUS-Register: Automatic = on <80 12 00 08 03 20> // Source Sel. = (St or A) & Ch. Matr. = St <80 12 00 0E 24 03> // FM/AM-Prescale = 24hex, FM-Matrix = Sound A Mono <80 10 00 20 00 20> // Standard Select: BTSC-STEREO <80 12 00 00 73 00> // Loudspeaker Volume 0 dB // Softreset <80 00 00 00> <80 10 00 30 20 03> // MODUS-Register: Automatic = on <80 12 00 08 03 20> // Source Sel. = (St or A) & Ch. Matr. = St <80 12 00 0E 24 03> // FM/AM-Prescale = 24hex, FM-Matrix = Sound A Mono <80 12 00 10 00 5A> // NICAM-Prescale = 5Ahex // Standard Select: Automatic Standard Detection <80 10 00 20 00 01> 3.5.6. BTSC-SAP with SAP at Loudspeaker Channel // Wait till STANDARD RESULT contains a value ≤ 07FF <80 00 80 00> // Softreset // IF STANDARD RESULT contains 0000 // do some error handling <80 00 00 00> <80 10 00 30 20 03> // MODUS-Register: Automatic = on // ELSE <80 12 00 08 04 20> // Source Sel. = (St or B) & Ch. Matr. = St <80 12 00 00 73 00> <80 12 00 0E 24 03> // FM/AM-Prescale = 24hex, FM-Matrix = Sound A Mono <80 10 00 20 00 21> // Standard Select: BTSC-SAP <80 12 00 00 73 00> // Loudspeaker Volume 0 dB // Loudspeaker Volume 0 dB 3.5.9. Software Flow for Interrupt driven STATUS Check A detailed software flow diagram is shown in Fig. 3–2 on page 46. If the D_CTR_I/O_1 pin of the MSP 34x1G is connected to an interrupt input pin of the controller, the following interrupt handler can be applied to be automatically called with each status change of the MSP 34x1G. The interrupt handler may adjust the TV display according to the new status information. Interrupt Handler: <80 11 02 00 <81 dd dd> // Read STATUS // adjust TV display with given status information // Return from Interrupt MICRONAS INTERMETALL 45 MSP 34x1G PRELIMINARY DATA SHEET Write MODUS Register: Example for the essential bits: [0] = 1 Automatic Sound Select = on [1] = 1 Enable interrupt if STATUS changes [8] = 0 ANA_IN1+ is selected Define Preference for Automatic Standard Detection: [12] = 0 If 6.5 MHz, set SECAM-L [14:13] = 3 Ignore 4.5 MHz carrier Write SOURCE SELECT Settings Example: set loudspeaker Source Select to "Stereo or A" set headphone Source Select to "Stereo or B" set SCART_Out Source Select to "Stereo or A/B" set Channel Matrix mode for all outputs to "Stereo" Write FM/AM-Prescale Write NICAM-Prescale Write 01 into STANDARD SELECT Register (Start Automatic Standard Detection) set previous standard or set standard manually according picture information yes Result = 0 ? no expecting MSPG-interrupt In case of MSPGInterrupt to Controller: Read STATUS Adjust TV-Display If Bilingual, adjust Source Select setting if required Fig. 3–2: Software flow diagram for a Minimum demodulator setup for a European Multistandard TV set applying the Automatic Sound Select feature 46 MICRONAS INTERMETALL MSP 34x1G PRELIMINARY DATA SHEET 4. Specifications 0.9 ± 0.2 4.1. Outline Dimensions 1.1 x 45 ° 1.2 x 45° 61 2 2 7.5 24.2 ± 0.1 0.71 ± 0.05 25.14 ± 0.12 23.3 ± 0.3 9 16 x 1.27 = 20.32 60 1.27 10 ± 0.1 1 0.48 ± 0.06 9 16 x 1.27 = 20.32 ± 0.1 1.27 7.5 26 0.23 ± 0.04 9 44 27 1.9 ±0.05 43 4.05 ±0.1 25.14 ± 0.12 4.75 ±0.15 24.2 ± 0.1 0.1 SPGS0027-2(P68)/1E Fig. 4–1: 68-Pin Plastic Leaded Chip Carrier Package (PLCC68) Weight approximately 4.8 g Dimensions in mm SPGS0016-5(P52)/1E SPGS0016-5(P64)/1E 64 33 27 1 26 32 0.8 ±0.2 3.8 ±0.1 47.0 ±0.1 57.7 ±0.1 15.6 ±0.1 14 ±0.1 0.6 ±0.2 4.0 ±0.1 1 52 19.3 ±0.1 18 ±0.05 1 ±0.05 1.778 0.48 ±0.06 3.2 ±0.2 0.28 ±0.06 20.3 ±0.5 31 x 1.778 = 55.1 ±0.1 Fig. 4–2: 64-Pin Plastic Shrink Dual-Inline Package (PSDIP64) Weight approximately 9.0 g Dimensions in mm MICRONAS INTERMETALL 1.778 0.48 ±0.06 2.8 ±0.2 0.28 ±0.06 1 ±0.05 16.3 ±1 25 x 1.778 = 44.4 ±0.1 Fig. 4–3: 52-Pin Plastic Shrink Dual-Inline Package (PSDIP52) Weight approximately 5.5 g Dimensions in mm 47 MSP 34x1G PRELIMINARY DATA SHEET 23 x 0.8 = 18.4 ± 0.1 0.17 ± 0.04 64 0.8 41 16 14 ± 0.1 0.37 ± 0.05 17.2 ± 0.15 9.8 80 8 1.8 10.3 5 15 x 0.8 = 12.0 ± 0.1 8 1.8 0.8 40 65 25 1 1.3 ± 0.05 24 2.7 ± 0.1 23.2 ± 0.15 3 ±0.2 20 ± 0.1 0.1 SPGS705000-1(P80)/1E Fig. 4–4: 80-Pin Plastic Quad Flat Pack (PQFP80) Weight approximately 1.61 g Dimensions in mm 15 x 0.5 = 7.5 ± 0.1 0.145 32 64 17 1 0.22 ± 0.05 16 1.4 ± 0.05 1.75 12 ± 0.2 15 x 0.5 = 7.5 ± 0.1 49 0.5 33 12 ± 0.2 1.75 0.5 10 ± 0.1 48 ± 0.055 1.5 ± 0.1 0.1 10 ± 0.1 D0025/3E Fig. 4–5: 64-Pin Plastic Low-Profile Quad Flat Pack (PLQFP64) Weight approximately 3.5 g Dimensions in mm 48 MICRONAS INTERMETALL MSP 34x1G PRELIMINARY DATA SHEET 4.2. Pin Connections and Short Descriptions NC = not connected; leave vacant LV = if not used, leave vacant OBL = obligatory; connect as described in circuit diagram DVSS: if not used, connect to DVSS AHVSS: connect to AHVSS Pin No. Pin Name Type Connection Short Description (if not used) PLCC 68-pin PSDIP 64-pin PSDIP 52-pin PQFP 80-pin PLQFP 64-pin 1 16 14 9 8 ADR_WS 2 − − − − NC 3 15 13 8 7 ADR_DA 4 14 12 7 6 5 13 11 6 6 12 10 7 11 8 LV ADR word strobe LV Not connected OUT LV ADR data output I2S_DA_IN1 IN LV I2S1 data input 5 I2S_DA_OUT OUT LV I2S data output 5 4 I2S_WS IN/OUT LV I2S word strobe 9 4 3 I2S_CL IN/OUT LV I2S clock 10 8 3 2 I2C_DA IN/OUT OBL I2C data 9 9 7 2 1 I2C_CL IN/OUT OBL I2C clock 10 8 − 1 64 NC LV Not connected 11 7 6 80 63 STANDBYQ IN OBL Stand-by (low-active) 12 6 5 79 62 ADR_SEL IN OBL I2C Bus address select 13 5 4 78 61 D_CTR_I/O_0 IN/OUT LV D_CTR_I/O_0 14 4 3 77 60 D_CTR_I/O_1 IN/OUT LV D_CTR_I/O_1 15 3 − 76 59 NC LV Not connected 16 2 − 75 58 NC LV Not connected 17 − − − − NC LV Not connected 18 1 2 74 57 AUD_CL_OUT LV Audio clock output (18.432 MHz) 19 64 1 73 56 TP LV Test pin 20 63 52 72 55 XTAL_OUT OUT OBL Crystal oscillator 21 62 51 71 54 XTAL_IN IN OBL Crystal oscillator 22 61 50 70 53 TESTEN IN OBL Test pin 23 60 49 69 52 ANA_IN2+ IN AVSS via 56 pF / LV IF input 2 (can be left AVSS via 56 pF / LV IF common (can be left vacant, only if IF input 1 is also not in use) 24 59 48 68 MICRONAS INTERMETALL 51 ANA_IN− OUT OUT IN vacant, only if IF input 1 is also not in use) 49 MSP 34x1G PRELIMINARY DATA SHEET Pin No. Pin Name Type Connection Short Description (if not used) PLCC 68-pin PSDIP 64-pin PSDIP 52-pin PQFP 80-pin PLQFP 64-pin 25 58 47 67 50 ANA_IN1+ 26 57 46 66 49 − − − 65 − − − − − 27 LV IF input 1 AVSUP OBL Analog power supply 5 V − AVSUP OBL Analog power supply 5 V 64 − NC LV Not connected − 63 − NC LV Not connected 56 45 62 48 AVSS OBL Analog ground − − − 61 − AVSS OBL Analog ground 28 55 44 60 47 MONO_IN LV Mono input − − − 59 − NC LV Not connected 29 54 43 58 46 VREFTOP OBL Reference voltage IF A/D converter 30 53 42 57 45 SC1_IN_R IN LV SCART 1 input, right 31 52 41 56 44 SC1_IN_L IN LV SCART 1 input, left 32 51 − 55 43 ASG1 AHVSS Analog Shield Ground 1 33 50 40 54 42 SC2_IN_R IN LV SCART 2 input, right 34 49 39 53 41 SC2_IN_L IN LV SCART 2 input, left 35 48 − 52 40 ASG2 AHVSS Analog Shield Ground 2 36 47 38 51 39 SC3_IN_R IN LV SCART 3 input, right 37 46 37 50 38 SC3_IN_L IN LV SCART 3 input, left 38 45 − 49 37 ASG4 AHVSS Analog Shield Ground 4 39 44 − 48 36 SC4_IN_R IN LV SCART 4 input, right 40 43 − 47 35 SC4_IN_L IN LV SCART 4 input, left 41 − − 46 − NC LV or AHVSS Not connected 42 42 36 45 34 AGNDC OBL Analog reference voltage 43 41 35 44 33 AHVSS OBL Analog ground − − − 43 − AHVSS OBL Analog ground − − − 42 − NC LV Not connected − − − 41 − NC LV Not connected 44 40 34 40 32 CAPL_M OBL Volume capacitor MAIN 45 39 33 39 31 AHVSUP OBL Analog power supply 8 V 46 38 32 38 30 CAPL_A OBL Volume capacitor AUX 50 IN IN MICRONAS INTERMETALL MSP 34x1G PRELIMINARY DATA SHEET Pin No. Pin Name Type Connection Short Description (if not used) PLCC 68-pin PSDIP 64-pin PSDIP 52-pin PQFP 80-pin PLQFP 64-pin 47 37 31 37 29 SC1_OUT_L OUT LV SCART output 1, left 48 36 30 36 28 SC1_OUT_R OUT LV SCART output 1, right 49 35 29 35 27 VREF1 OBL Reference ground 1 50 34 28 34 26 SC2_OUT_L OUT LV SCART output 2, left 51 33 27 33 25 SC2_OUT_R OUT LV SCART output 2, right 52 − − 32 − NC LV Not connected 53 32 − 31 24 NC LV Not connected 54 31 26 30 23 DACM_SUB LV Subwoofer output 55 30 − 29 22 NC LV Not connected 56 29 25 28 21 DACM_L OUT LV Loudspeaker out, left 57 28 24 27 20 DACM_R OUT LV Loudspeaker out, right 58 27 23 26 19 VREF2 OBL Reference ground 2 59 26 22 25 18 DACA_L OUT LV Headphone out, left 60 25 21 24 17 DACA_R OUT LV Headphone out, right − − − 23 − NC LV Not connected − − − 22 − NC LV Not connected 61 24 20 21 16 RESETQ OBL Power-on-reset 62 23 − 20 15 NC LV Not connected 63 22 − 19 14 NC LV Not connected 64 21 19 18 13 NC LV Not connected 65 20 18 17 12 I2S_DA_IN2 LV I2S2-data input 66 19 17 16 11 DVSS OBL Digital ground − − − 15 − DVSS OBL Digital ground − − − 14 − DVSS OBL Digital ground 67 18 16 13 10 DVSUP OBL Digital power supply 5 V − − − 12 − DVSUP OBL Digital power supply 5 V − − − 11 − DVSUP OBL Digital power supply 5 V 68 17 15 10 9 ADR_CL LV ADR clock 1) Due OUT IN IN OUT to the compatibility with MSP 3410B, it is possible to connect with DVSS as well. MICRONAS INTERMETALL 51 MSP 34x1G PRELIMINARY DATA SHEET 4.3. Pin Descriptions Pin numbers refer to the 80-pin PQFP package. Pins 22, 23, NC – Pins not connected. Pin 1, NC – Pin not connected. Pins 24, 25, DACA_R/L – Headphone Outputs (Fig. 4–21) Output of the headphone signal. A 1-nF capacitor to AHVSS must be connected to these pins. The DC offset on these pins depends on the selected headphone volume. Pin 2, I2C_CL – I2C Clock Input/Output (Fig. 4–12) Via this pin, the I2C-bus clock signal has to be supplied. The signal can be pulled down by the MSP in case of wait conditions. Pin 3, I2C_DA – I2C Data Input/Output (Fig. 4–12) Via this pin, the I2C-bus data is written to or read from the MSP. Pin 4, I2S_CL – I2S Clock Input/Output (Fig. 4–15) Clock line for the I2S bus. In master mode, this line is driven by the MSP; in slave mode, an external I2S clock has to be supplied. Pin 5, I2S_WS – I2S Word Strobe Input/Output (Fig. 4–15) Word strobe line for the I2S bus. In master mode, this line is driven by the MSP; in slave mode, an external I2S word strobe has to be supplied. Pin 6, I2S_DA_OUT – I2S Data Output (Fig. 4–11) Output of digital serial sound data of the MSP on the I2S bus. Pin 7, I2S_DA_IN1 – I2S Data Input 1 (Fig. 4–13) First input of digital serial sound data to the MSP via the I2S bus. Pin 26, VREF2 – Reference Ground 2 Reference analog ground. This pin must be connected separately to the single ground point (AHVSS). VREF2 serves as a clean ground and should be used as the reference for analog connections to the loudspeaker and headphone outputs. Pins 27, 28, DACM_R/L – Loudspeaker Outputs (Fig. 4–21) Output of the loudspeaker signal. A 1-nF capacitor to AHVSS must be connected to these pins. The DC offset on these pins depends on the selected loudspeaker volume. Pin 29, NC – Pin not connected. Pin 30, DACM_SUB – Subwoofer Output (Fig. 4–21) Output of the subwoofer signal. A 1-nF capacitor to AHVSS must be connected to this pin. Due to the low frequency content of the subwoofer output, the value of the capacitor may be increased for better suppression of high-frequency noise. The DC offset on this pin depends on the selected loudspeaker volume. Pin 8, ADR_DA – ADR Bus Data Output (Fig. 4–11) Output of digital serial data to the DRP 3510A via the ADR bus. Pins 31, 32 NC – Pin not connected. Pin 9, ADR_WS – ADR Bus Word Strobe Output (Fig. 4–11) Word strobe output for the ADR bus. Pins 33, 34, SC2_OUT_R/L – SCART2 Outputs (Fig. 4–23) Output of the SCART2 signal. Connections to these pins must use a 100-Ω series resistor and are intended to be AC-coupled. Pin 10, ADR_CL – ADR Bus Clock Output (Fig. 4–11) Clock line for the ADR bus. Pins 11, 12, 13, DVSUP* – Digital Supply Voltage Power supply for the digital circuitry of the MSP. Must be connected to a +5 V power supply. Pins 14, 15, 16, DVSS* – Digital Ground Ground connection for the digital circuitry of the MSP. Pin 17, I2S_DA_IN2 – I2S Data Input 2 (Fig. 4–13) Second input of digital serial sound data to the MSP via the I2S bus. Pin 35, VREF1 – Reference Ground 1 Reference analog ground. This pin must be connected separately to the single ground point (AHVSS). VREF1 serves as a clean ground and should be used as the reference for analog connections to the SCART outputs. Pins 36, 37, SC1_OUT_R/L – SCART1 Outputs (Fig. 4–23) Output of the SCART1 signal. Connections to these pins must use a 100-Ω series resistor and are intended to be AC-coupled. Pins 18, 19, 20, NC – Pins not connected. Pin 21, RESETQ – Reset Input (Fig. 4–13) In the steady state, high level is required. A low level resets the MSP 34x1G. 52 MICRONAS INTERMETALL MSP 34x1G PRELIMINARY DATA SHEET Pin 38, CAPL_A – Volume Capacitor Headphone (Fig. 4–18) A 10-µF capacitor to AHVSUP must be connected to this pin. It serves as a smoothing filter for headphone volume changes in order to suppress audible plops. The value of the capacitor can be lowered to 1-µF if faster response is required. The area encircled by the trace lines should be minimized; keep traces as short as possible. This input is sensitive for magnetic induction. Pin 39, AHVSUP* – Analog Power Supply High Voltage Power is supplied via this pin for the analog circuitry of the MSP (except IF input). This pin must be connected to the +8 V supply. Pin 40, CAPL_M – Volume Capacitor Loudspeaker (Fig. 4–18) A 10-µF capacitor to AHVSUP must be connected to this pin. It serves as a smoothing filter for loudspeaker volume changes in order to suppress audible plops. The value of the capacitor can be lowered to 1 µF if faster response is required. The area encircled by the trace lines should be minimized; keep traces as short as possible. This input is sensitive for magnetic induction. Pins 53, 54 SC2_IN_L/R – SCART2 Inputs (Fig. 4–20) The analog input signal for SCART2 is fed to this pin. Analog input connection must be AC-coupled. Pin 55, ASG1 – Analog Shield Ground 1 Analog ground (AHVSS) should be connected to this pin to reduce cross-coupling between SCART inputs. Pins 56, 57 SC1_IN_L/R – SCART1 Inputs (Fig. 4–20) The analog input signal for SCART1 is fed to this pin. Analog input connection must be AC-coupled. Pin 58, VREFTOP – Reference Voltage IF A/D Converter (Fig. 4–17) Via this pin, the reference voltage for the IF A/D converter is decoupled. It must be connected to AVSS pins with a 10-µF and a 100-nF capacitor in parallel. Traces must be kept short. Pin 59, NC – Pin not connected. Pin 60 MONO_IN – Mono Input (Fig. 4–20) The analog mono input signal is fed to this pin. Analog input connection must be AC-coupled. Pins 61, 62, AVSS* – Analog Power Supply Voltage Ground connection for the analog IF input circuitry of the MSP. Pins 41, 42, NC – Pins not connected. Pins 63, 64, NC – Pins not connected. Pins 43, 44, AHVSS* – Analog Power Supply High Voltage Ground connection for the analog circuitry of the MSP (except IF input). Pin 45, AGNDC – Internal Analog Reference Voltage This pin serves as the internal ground connection for the analog circuitry (except IF input). It must be connected to the VREF pins with a 3.3-µF and a 100-nF capacitor in parallel. This pins shows a DC level of typically 3.73 V. Pins 65, 66, AVSUP* – Analog Power Supply Voltage Power is supplied via this pin for the analog IF input circuitry of the MSP. This pin must be connected to the +5 V supply. Pin 67, ANA_IN1+ – IF Input 1 (Fig. 4–17) The analog sound IF signal is supplied to this pin. Inputs must be AC-coupled. This pin is designed as symmetrical input: ANA_IN1+ is internally connected to one input of a symmetrical op amp, ANA_IN- to the other. Pin 46, NC – Pin not connected. Pins 47, 48, SC4_IN_L/R – SCART4 Inputs (Fig. 4–20) The analog input signal for SCART4 is fed to this pin. Analog input connection must be AC-coupled. Pin 49, ASG4 – Analog Shield Ground 4 Analog ground (AHVSS) should be connected to this pin to reduce cross-coupling between SCART inputs. Pins 50, 51, SC3_IN_L/R – SCART3 Inputs (Fig. 4–20) The analog input signal for SCART3 is fed to this pin. Analog input connection must be AC-coupled. Pin 68, ANA_IN− – IF Common (Fig. 4–17) This pins serves as a common reference for ANA_IN1/ 2+ inputs. Pin 69, ANA_IN2+ – IF Input 2 (Fig. 4–17) The analog sound if signal is supplied to this pin. Inputs must be AC-coupled. This pin is designed as symmetrical input: ANA_IN2+ is internally connected to one input of a symmetrical op amp, ANA_IN− to the other. Pin 70, TESTEN – Test Enable Pin (Fig. 4–13) This pin enables factory test modes. For normal operation, it must be connected to ground. Pin 52, ASG2 – Analog Shield Ground 2 Analog ground (AHVSS) should be connected to this pin to reduce cross-coupling between SCART inputs. MICRONAS INTERMETALL 53 MSP 34x1G PRELIMINARY DATA SHEET Pins 71, 72 XTAL_IN, XTAL_OUT – Crystal Input and Output Pins (Fig. 4–16) These pins are connected to an 18.432 MHz crystal oscillator which is digitally tuned by integrated shunt capacitances. An external clock can be fed into XTAL_IN. The audio clock output signal AUD_CL_OUT is derived from the oscillator. External capacitors at each crystal pin to ground (AVSS) are required. It should be verified by layout, that no supply current for the digital circuitry is flowing through the ground connection point. Pin 73, TP – This pin enables factory test modes. For normal operation, it must be left vacant. Pin 74, AUD_CL_OUT – Audio Clock Output (Fig. 4–16) This is the 18.432 MHz main clock output. Pins 75, 76, NC – Pins not connected. Pins 77, 78, D_CTR_I/O_1/0 – Digital Control Input/ Output Pins (Fig. 4–15) These pins serve as general purpose input/output pins. Pin D_CTR_I/O_1 can be used as an interrupt request pin to the controller. Pin 79, ADR_SEL – I2C Bus Address Select (Fig. 4–14) By means of this pin, one of three device addresses for the MSP can be selected. The pin can be connected to ground (I2C device addresses 80/81hex), to +5 V supply (84/85hex), or left open (88/89hex). Pin 80, STANDBYQ – Stand-by In normal operation, this pin must be High. If the MSP 34x1G is switched off by first pulling STANDBYQ low and then (after >1 µs delay) switching off the 5 V, but keeping the 8-V power supply (‘Stand-by’-mode), the SCART switches maintain their position and function. * Application Note: All ground pins should be connected to one low-resistive ground plane. All supply pins should be connected separately with short and low-resistive lines to the power supply. Decoupling capacitors from DVSUP to DVSS, AVSUP to AVSS, and AHVSUP to AHVSS are recommended as closely as possible to these pins. Decoupling of DVSUP and DVSS is most important. We recommend using more than one capacitor. By choosing different values, the frequency range of active decoupling can be extended. In our application boards we use: 220 pF, 470 pF, 1.5 nF, and 10 µF. The capacitor with the lowest value should be placed nearest to the DVSUP and DVSS pins. 54 MICRONAS INTERMETALL MSP 34x1G PRELIMINARY DATA SHEET 4.4. Pin Configurations ADR_WS NC ADR_CL ADR_DA DVSUP I2S_DA_IN1 DVSS I2S_DA_OUT I2S_DA_IN2 I2S_WS NC I2S_CL NC I2C_DA NC I2C_CL RESETQ 9 8 7 6 5 4 3 2 1 68 67 66 65 64 63 62 61 NC 10 60 DACA_R STANDBYQ 11 59 DACA_L ADR_SEL 12 58 VREF2 D_CTR_I/O_0 13 57 DACM_R D_CTR_I/O_1 14 56 DACM_L NC 15 55 NC NC 16 54 DACM_SUB NC 17 53 NC AUD_CL_OUT 18 52 NC TP 19 51 SC2_OUT_R XTAL_OUT 20 50 SC2_OUT_L XTAL_IN 21 49 VREF1 TESTEN 22 48 SC1_OUT_R ANA_IN2+ 23 47 SC1_OUT_L ANA_IN− 24 46 CAPL_A ANA_IN1+ 25 45 AHVSUP AVSUP 26 44 CAPL_M MSP 34x1G 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 AHVSS AVSS MONO_IN AGNDC VREFTOP NC SC1_IN_R SC4_IN_L SC1_IN_L SC4_IN_R ASG1 ASG4 SC2_IN_R SC3_IN_L SC2_IN_L SC3_IN_R ASG2 Fig. 4–6: 68-pin PLCC package MICRONAS INTERMETALL 55 MSP 34x1G PRELIMINARY DATA SHEET 64 TP TP 1 52 XTAL_OUT 2 63 XTAL_OUT AUD_CL_OUT 2 51 XTAL_IN NC 3 62 XTAL_IN D_CTR_I/O_1 3 50 TESTEN D_CTR_I/O_1 4 61 TESTEN D_CTR_I/O_0 4 49 ANA_IN2+ D_CTR_I/O_0 5 60 ANA_IN2+ ADR_SEL 5 48 ANA_IN− ADR_SEL 6 59 ANA_IN− STANDBYQ 6 47 ANA_IN1+ STANDBYQ 7 58 ANA_IN+ I2C_CL 7 46 AVSUP NC 8 57 AVSUP I2C_DA 8 45 AVSS I2C_CL 9 56 AVSS I2S_CL 9 44 MONO_IN I2C_DA 10 55 MONO_IN I2S_WS 10 43 VREFTOP I2S_CL 11 54 VREFTOP I2S_DA_OUT 11 42 SC1_IN_R I2S_WS 12 53 SC1_IN_R I2S_DA_IN1 12 41 SC1_IN_L I2S_DA_OUT 13 52 SC1_IN_L ADR_DA 13 40 SC2_IN_R I2S_DA_IN1 14 51 ASG1 ADR_WS 14 39 SC2_IN_L ADR_DA 15 50 SC2_IN_R ADR_CL 15 38 SC3_IN_R ADR_WS 16 49 SC2_IN_L DVSUP 16 ADR_CL 17 48 ASG2 DVSS DVSUP 18 47 SC3_IN_R DVSS 19 46 SC3_IN_L I2S_DA_IN2 20 45 NC 21 NC MSP 34x1G 1 NC MSP 34x1G AUD_CL_OUT 37 SC3_IN_L 17 36 AGNDC I2S_DA_IN2 18 35 AHVSS NC 19 34 CAPL_M ASG4 RESETQ 20 33 AHVSUP 44 SC4_IN_R DACA_R 21 32 CAPL_A 22 43 SC4_IN_L DACA_L 22 31 SC1_OUT_L NC 23 42 AGNDC VREF2 23 30 SC1_OUT_R RESETQ 24 41 AHVSS DACM_R 24 29 VREF1 DACA_R 25 40 CAPL_M DACM_L 25 28 SC2_OUT_L DACA_L 26 39 AHVSUP DACM_SUB 26 27 SC2_OUT_R VREF2 27 38 CAPL_A DACM_R 28 37 SC1_OUT_L DACM_L 29 36 SC1_OUT_R NC 30 35 VREF1 DACM_SUB 31 34 SC2_OUT_L NC 32 33 SC2_OUT_R Fig. 4–8: 52-pin PSDIP package Fig. 4–7: 64-pin PSDIP package 56 MICRONAS INTERMETALL MSP 34x1G PRELIMINARY DATA SHEET SC2_IN_L SC2_IN_R ASG2 SC3_IN_R ASG1 SC3_IN_L SC1_IN_L ASG4 SC1_IN_R SC4_IN_R VREFTOP SC4_IN_L NC NC MONO_IN AGNDC AVSS AHVSS AVSS AHVSS NC NC NC NC AVSUP 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 65 40 CAPL_M AVSUP 66 39 AHVSUP ANA_IN1+ 67 38 CAPL_A ANA_IN− 68 37 SC1_OUT_L ANA_IN2+ 69 36 SC1_OUT_R TESTEN 70 35 VREF1 XTAL_IN 71 34 SC2_OUT_L XTAL_OUT 72 33 SC2_OUT_R TP 73 32 NC AUD_CL_OUT 74 31 NC NC 75 30 DACM_SUB NC 76 29 NC D_CTR_I/O_1 77 28 DACM_L D_CTR_I/O_0 78 27 DACM_R ADR_SEL 79 26 VREF2 STANDBYQ 80 25 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 MSP 34x1G 1 2 3 4 5 6 7 8 9 DACA_L DACA_R NC I2C_CL NC I2C_DA NC I2S_CL RESETQ I2S_WS NC I2S_DA_OUT NC I2S_DA_IN1 NC ADR_DA I2S_DA_IN2 ADR_WS DVSS ADR_CL DVSS DVSUP DVSUP DVSS DVSUP Fig. 4–9: 80-pin PQFP package MICRONAS INTERMETALL 57 MSP 34x1G PRELIMINARY DATA SHEET SC2_IN_L ASG2 SC2_IN_R SC3_IN_R ASG1 SC3_IN_L SC1_IN_L ASG4 SC1_IN_R SC4_IN_R VREFTOP SC4_IN_L MONO_IN AGNDC AVSS AHVSS 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 AVSUP 49 32 CAPL_M ANA_IN1+ 50 31 AHVSUP ANA_IN− 51 30 CAPL_A ANA_IN2+ 52 29 SC1_OUT_L TESTEN 53 28 SC1_OUT_R XTAL_IN 54 27 VREF1 XTAL_OUT 55 26 SC2_OUT_L TP 56 25 SC2_OUT_R AUD_CL_OUT 57 24 NC NC 58 23 DACM_SUB NC 59 22 NC D_CTR_I/OUT1 60 21 DACM_L D_CTR_I/OUT0 61 20 DACM_R ADR_SEL 62 19 VREF2 STANDBYQ 63 18 DACA_L NC 64 17 DACA_R MSP 34x1G 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 RESETQ I2C_CL I2C_DA NC I2S_CL NC I2S_WS NC I2S_DA_OUT I2S_DA_IN2 I2S_DA_IN1 ADR_DA ADR_WS DVSS DVSUP ADR_CL Fig. 4–10: 64-pin PLQFP package 58 MICRONAS INTERMETALL MSP 34x1G PRELIMINARY DATA SHEET 4.5. Pin Circuits Pin numbers refer to the PQFP80 package. DVSUP DVSUP P P N N GND GND Fig. 4–11: Output Pins 6, 8, 9, and 10 (I2S_DA_OUT, ADR_DA, ADR_WS, ADR_CL) Fig. 4–15: Input/Output Pins 4, 5, 77, and 78 (I2S_CL, I2S_WS, D_CTR_I/O_1, D_CTR_I/O_0) P N GND Fig. 4–12: Input/Output Pins 2 and 3 (I2C_CL, I2C_DA) 3−30 pF 500 kΩ N 2.5 V 3−30 pF Fig. 4–16: Output/Input Pins 71, 72, and 74 (XTAL_IN, XTAL_OUT, AUD_CL_OUT) Fig. 4–13: Input Pins 7, 17, 21, 70, and 80 (I2S_DA_IN1, I2S_DA_IN2, RESETQ, TESTEN, STANDBYQ) ANA_IN1+ ANA_IN2+ DVSUP A D 23 kΩ ANA_IN− VREFTOP 23 kΩ GND ADR_SEL Fig. 4–14: Input Pin 79 (ADR_SEL) MICRONAS INTERMETALL Fig. 4–17: Input Pins 58, 67, 68, and 69 (VREFTOP, ANA_IN1+, ANA_IN-, ANA_IN2+) 59 MSP 34x1G PRELIMINARY DATA SHEET 125 kΩ ≈ 3.75 V 0...2 V Fig. 4–18: Capacitor Pins 38 and 40 (CAPL_A, CAPL_M) Fig. 4–22: Pin 45 (AGNDC) 26 pF 24 kΩ ≈ 3.75 V 120 kΩ 300 Ω Fig. 4–19: Input Pin 60 (MONO_IN) ≈ 3.75 V 40 kΩ ≈ 3.75 V Fig. 4–23: Output Pins 33, 34, 36, and 37 (SC_2_OUT_R/L, SC_1_OUT_R/L) Fig. 4–20: Input Pins 47, 48, 50, 51, 53, 54, 56, and 57 (SC4-1_IN_L/R) AHVSUP 0...1.2 mA 3.3 kΩ Fig. 4–21: Output Pins 24, 25, 27, 28 and 30 (DACA_R/L, DACM_R/L, DACM_SUB) 60 MICRONAS INTERMETALL MSP 34x1G PRELIMINARY DATA SHEET 4.6. Electrical Characteristics 4.6.1. Absolute Maximum Ratings Symbol Parameter Pin Name Min. Max. Unit TA Ambient Operating Temperature − 0 701) °C TS Storage Temperature − −40 125 °C VSUP1 First Supply Voltage AHVSUP −0.3 9.0 V VSUP2 Second Supply Voltage DVSUP −0.3 6.0 V VSUP3 Third Supply Voltage AVSUP −0.3 6.0 V dVSUP23 Voltage between AVSUP and DVSUP AVSUP, DVSUP −0.5 0.5 V PTOT Power Dissipation PLCC68 PSDIP64 PSDIP52 PQFP80 PLQFP64 AHVSUP, DVSUP, AVSUP 1200 1300 1200 1000 9601) mW mW mW mW mW −0.3 VSUP2+0.3 V VIdig Input Voltage, all Digital Inputs IIdig Input Current, all Digital Pins − −20 +20 mA2) VIana Input Voltage, all Analog Inputs SCn_IN_s,3) MONO_IN −0.3 VSUP1+0.3 V IIana Input Current, all Analog Inputs SCn_IN_s,3) MONO_IN −5 +5 mA2) IOana Output Current, all SCART Outputs SCn_OUT_s3) 4), 5) 4), 5) IOana Output Current, all Analog Outputs except SCART Outputs DACp_s3) 4) 4) ICana Output Current, other pins connected to capacitors CAPL_p,3) AGNDC 4) 4) 1) 2) 3) 4) 5) PLQFP64: 65 °C positive value means current flowing into the circuit “n” means “1”, “2”, “3”, or “4”, “s” means “L” or “R”, “p” means “M” or “A” The analog outputs are short-circuit proof with respect to First Supply Voltage and ground. Total chip power dissipation must not exceed absolute maximum rating. Stresses beyond those listed in the “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only. Functional operation of the device at these or any other conditions beyond those indicated in the “Recommended Operating Conditions/Characteristics” of this specification is not implied. Exposure to absolute maximum ratings conditions for extended periods may affect device reliability. MICRONAS INTERMETALL 61 MSP 34x1G PRELIMINARY DATA SHEET 4.6.2. Recommended Operating Conditions (TA = 0 to 70 °C) 4.6.2.1. General Recommended Operating Conditions Symbol Parameter Pin Name Min. Typ. Max. Unit VSUP1 First Supply Voltage (8-V Operation) AHVSUP 7.6 8.0 8.7 V 4.75 5.0 5.25 V First Supply Voltage (5-V Operation) VSUP2 Second Supply Voltage DVSUP 4.75 5.0 5.25 V VSUP3 Third Supply Voltage AVSUP 4.75 5.0 5.25 V tSTBYQ1 STANDBYQ Setup Time before Turn-off of Second Supply Voltage STANDBYQ, DVSUP 1 µs 4.6.2.2. Analog Input and Output Recommendations Symbol Parameter Pin Name Min. Typ. CAGNDC AGNDC-Filter-Capacitor AGNDC −20% 3.3 µF −20% 100 nF −20% 330 nF Ceramic Capacitor in Parallel SCn_IN_s1) CinSC DC-Decoupling Capacitor in front of SCART Inputs VinSC SCART Input Level VinMONO Input Level, Mono Input MONO_IN RLSC SCART Load Resistance SCn_OUT_s1) CLSC SCART Load Capacitance CVMA Main/AUX Volume Capacitor CAPL_M, CAPL_A CFMA Main/AUX Filter Capacitor DACM_s, DACA_s1) 1) 62 Max. 2.0 VRMS 2.0 VRMS 10 kΩ 6.0 1 nF µF 10 −10% Unit +10% nF “n” means “1”, “2”, or “3”, “s” means “L” or “R”, “p” means “M” or “A” MICRONAS INTERMETALL MSP 34x1G PRELIMINARY DATA SHEET 4.6.2.3. Recommendations for Analog Sound IF Input Signal Symbol Parameter Pin Name Min. Typ. CVREFTOP VREFTOP-Filter-Capacitor VREFTOP −20 % 10 µF −20 % 100 nF Ceramic Capacitor in Parallel ANA_IN1+, ANA_IN2+, ANA_IN− 0 Max. 9 Unit FIF_FMTV Analog Input Frequency Range for TV Applications FIF_FMRADIO Analog Input Frequency for FM-Radio Applications VIF_FM Analog Input Range FM/NICAM 0.1 0.8 3 Vpp VIF_AM Analog Input Range AM/NICAM 0.1 0.45 0.8 Vpp RFMNI Ratio: NICAM Carrier/FM Carrier (unmodulated carriers) BG: I: −20 −23 −7 −10 0 0 dB dB −25 −11 0 dB 10.7 MHz MHz RAMNI Ratio: NICAM Carrier/AM Carrier (unmodulated carriers) RFM Ratio: FM-Main/FM-Sub Satellite 7 dB RFM1/FM2 Ratio: FM1/FM2 German FM-System 7 dB RFC Ratio: Main FM Carrier/ Color Carrier 15 − − dB RFV Ratio: Main FM Carrier/ Luma Components 15 − − dB PRIF Passband Ripple − − ±2 dB SUPHF Suppression of Spectrum above 9.0 MHz (not for FM Radio) 15 − dB FMMAX Maximum FM-Deviation (approx.) normal mode HDEV2: high deviation mode HDEV3: very high deviation mode ±180 ±360 ±540 kHz kHz kHz MICRONAS INTERMETALL 63 MSP 34x1G PRELIMINARY DATA SHEET 4.6.2.4. Crystal Recommendations Symbol Parameter Pin Name Min. Typ. Max. Unit General Crystal Recommendations fP Crystal Parallel Resonance Frequency at 12 pF Load Capacitance 18.432 RR Crystal Series Resistance 8 25 Ω C0 Crystal Shunt (Parallel) Capacitance 6.2 7.0 pF CL External Load Capacitance1) XTAL_IN, XTAL_OUT MHz PSDIP approx. 1.5 PLCC approx. 3.3 P(L)QFP approx. 3.3 pF pF pF Crystal Recommendations for Master-Slave Applications (MSP-clock must perform synchronization to I2S clock) fTOL Accuracy of Adjustment −20 +20 ppm DTEM Frequency Variation versus Temperature −20 +20 ppm C1 Motional (Dynamic) Capacitance 19 fCL Required Open Loop Clock Frequency (Tamb = 25 °C) AUD_CL_OUT 18.431 24 fF 18.433 MHz Crystal Recommendations for FM / NICAM Applications (No MSP-clock synchronization to I2S clock possible) fTOL Accuracy of Adjustment −30 +30 ppm DTEM Frequency Variation versus Temperature −30 +30 ppm C1 Motional (Dynamic) Capacitance 15 fCL Required Open Loop Clock Frequency (Tamb = 25 °C) AUD_CL_OUT 18.4305 fF 18.4335 MHz Crystal Recommendations for all analog FM/AM Applications (No MSP-clock synchronization to I2S clock possible) fTOL Accuracy of Adjustment −100 +100 ppm DTEM Frequency Variation versus Temperature −50 +50 ppm fCL Required Open Loop Clock Frequency (Tamb = 25 °C) 18.429 18.435 MHz AUD_CL_OUT Amplitude Recommendation for Operation with External Clock Input (Cload after reset typ. 22 pF) VXCA External Clock Amplitude XTAL_IN 0.7 Vpp 1)External capacitors at each crystal pin to ground are required. They are necessary to tune the open-loop frequency of the internal PLL and to stabilize the frequency in closed-loop operation. Due to different layouts, the accurate capacitor size should be determined with the customer PCB. The suggested values (1.5...3.3 pF) are figures based on experience and should serve as “start value”. To define the capacitor size, reset the MSP without transmitting any further I2C telegrams. Measure the frequency at AUD_CL_OUT-pin. Change the capacitor size until the free running frequency matches 18.432 MHz as closely as possible. The higher the capacity, the lower the resulting clock frequency. 64 MICRONAS INTERMETALL MSP 34x1G PRELIMINARY DATA SHEET 4.6.3. Characteristics at TA = 0 to 70 °C, fCLOCK = 18.432 MHz, VSUP1 = 7.6 to 8.7 V, VSUP2 = 4.75 to 5.25 V for min./max. values at TA = 60 °C, fCLOCK = 18.432 MHz, VSUP1 = 8 V, VSUP2 = 5 V for typical values, TJ = Junction Temperature MAIN (M) = Loudspeaker Channel, AUX (A) = Headphone Channel 4.6.3.1. General Characteristics Symbol Parameter Pin Name First Supply Current (active) (8-V Operation) AHVSUP Min. Typ. Max. Unit 9.6 6.3 17.1 11.2 24.6 16.1 mA mA 6.4 4.2 11.4 7.5 16.4 10.7 mA mA Test Conditions Supply ISUP1A Analog Volume for Main and Aux at 0 dB Analog Volume for Main and Aux at −30 dB First Supply Current (active) (5-V Operation) Analog Volume for Main and Aux at 0 dB Analog Volume for Main and Aux at −30 dB ISUP2A Second Supply Current (active) DVSUP 50 65 85 mA ISUP3A Third Supply Current (active) AVSUP 20 35 45 mA ISUP1S First Supply Current (8-V Operation) (standby mode) at Tj = 27 °C AHVSUP 3.5 5.6 7.7 mA STANDBYQ = low 2.3 3.7 5.1 mA STANDBYQ = low First Supply Current (5-V Operation) (standby mode) at Tj = 27 °C Clock fCLOCK Clock Input Frequency DCLOCK Clock High to Low Ratio tJITTER Clock Jitter (Verification not provided in Production Test) VxtalDC DC-Voltage Oscillator tStartup Oscillator Startup Time at VDD Slew-rate of 1 V/1 µs XTAL_IN, XTAL_OUT VACLKAC Audio Clock Output AC Voltage AUD_CL_OUT VACLKDC Audio Clock Output DC Voltage routHF_ACL HF Output Resistance MICRONAS INTERMETALL XTAL_IN 18.432 45 MHz 55 % 50 ps 2.5 0.4 1.2 V 2 1.8 0.4 0.6 140 ms Vpp load = 40 pF VSUP3 Imax = 0.2 mA Ω 65 MSP 34x1G PRELIMINARY DATA SHEET 4.6.3.2. Digital Inputs, Digital Outputs Symbol Parameter Pin Name Min. Typ. Max. Unit 0.2 VSUP2 Test Conditions Digital Input Levels VDIGIL Digital Input Low Voltage STANDBYQ D_CTR_I/O_0/1 VDIGIH Digital Input High Voltage ZDIGI Input Impedance IDLEAK Digital Input Leakage Current VDIGIL Digital Input Low Voltage VDIGIH Digital Input High Voltage 0.8 IADRSEL Input Current Address Select Pin −500 0.5 VSUP2 −1 ADR_SEL 5 pF 1 µA 0.2 VSUP2 0 V < UINPUT< DVSUP D_CTR_I/O_0/1: tri-state VSUP2 −220 220 µA UADR_SEL= DVSS 500 µA UADR_SEL= DVSUP 0.4 V IDDCTR = 1 mA V IDDCTR = −1 mA Digital Output Levels VDCTROL Digital Output Low Voltage VDCTROH Digital Output High Voltage 66 D_CTR_I/O_0 D_CTR_I/O_1 4.0 MICRONAS INTERMETALL MSP 34x1G PRELIMINARY DATA SHEET 4.6.3.3. Reset Input and Power-Up Symbol Parameter Pin Name Min. RESETQ Typ. Max. Unit 0.45 0.55 VSUP2 0.7 0.8 VSUP2 5 pF 1 µA Test Conditions RESETQ Input Levels VRHL Reset High-Low Transition Voltage VRLH Reset Low-High Transition Voltage ZRES Input Impedance IRES Input Pin Leakage Current -1 0 V < UINPUT< DVSUP DVSUP AVSUP 4.5V t/ms RESETQ Low-to-High Threshold Note: The reset should not reach high level before the oscillator has started. This requires a reset delay of >2 ms 0.7× DVSUP 0.45...0.55× DVSUP High-to-Low Threshold 0.7 x DVSUP means 3.5 Volt with DVSUP = 5.0 V t/ms Reset Delay >2 ms Internal Reset High Low t/ms Fig. 4–24: Power-up sequence MICRONAS INTERMETALL 67 MSP 34x1G PRELIMINARY DATA SHEET 4.6.3.4. I2C-Bus Characteristics Symbol Parameter Pin Name 2 Min. Typ. I2C_CL, I2C_DA Max. Unit 0.3 VSUP2 VI2CIL I C-Bus Input Low Voltage VI2CIH I2C-Bus Input High Voltage 0.6 VSUP2 tI2C1 I2C Start Condition Setup Time 120 ns tI2C2 I2C Stop Condition Setup Time 120 ns tI2C5 I2C-Data Setup Time before Rising Edge of Clock 55 ns tI2C6 I2C-Data Hold Time after Falling Edge of Clock 55 ns tI2C3 I2C-Clock Low Pulse Time 500 ns tI2C4 I2C-Clock High Pulse Time 500 ns fI2C I2C-BUS Frequency VI2COL I2C-Data Output Low Voltage II2COH I2C-Data Output High Leakage Current tI2COL1 I2C-Data Output Hold Time after Falling Edge of Clock 15 ns tI2COL2 I2C-Data Output Setup Time before Rising Edge of Clock 100 ns I2C_CL I2C_CL, I2C_DA Test Conditions 1.0 MHz 0.4 V II2COL = 3 mA 1.0 µA VI2COH = 5 V fI2C = 1 MHz 1/FI2C TI2C4 I2C_CL TI2C1 TI2C5 TI2C3 TI2C6 TI2C2 I2C_DA as input TI2COL2 TI2COL1 I2C_DA as output Fig. 4–25: I2C bus timing diagram 68 MICRONAS INTERMETALL MSP 34x1G PRELIMINARY DATA SHEET 4.6.3.5. I2S-Bus Characteristics Symbol Parameter Pin Name VI2SIL Input Low Voltage VI2SIH Input High Voltage I2S_DA_IN1/2 I2S_CL I2S_WS ZI2SI Input Impedance IDLEAKI2SI Input Leakage Current tI2S1 I2S-Data Input Setup Time before Rising Edge of Clock tI2S2 I2S-Data Input Hold Time after Falling Edge of Clock fI2SWS I2S-Word Strobe Input Frequency when MSP in I2S-Slave Mode I2S_WS 32.0 kHz fI2SCL I2S-Clock Input Frequency when MSP in I2S-Slave-Mode I2S_CL 1.024 MHz RI2SCL I2S-Clock Input Ratio when MSP in I2S-Slave-Mode tI2SWS1 I2S-Word Strobe Input Setup Time before Rising Edge of Clock when MSP in I2S-Slave-Mode tI2SWS2 I2S-Word Strobe Input Hold Time after Falling Edge of Clock when MSP in I2S-Slave-Mode VI2SOL I2S Output Low Voltage VI2SOH I2S Output High Voltage I2S_WS, I2S_CL, I2S_DA_OUT fI2SWS I2S-Word Strobe Output Frequency I2S_WS I2S_CL 2 fI2SCL I S-Clock Output Frequency tI2S1/I2S2 I2S-Clock High/Low-Ratio tI2S3 I2S-Data Setup Time before Rising Edge of Clock tI2S4 I2S-Data Hold Time after Falling Edge of Clock tI2S5 I2S-Word Strobe Setup Time before Rising Edge of Clock tI2S6 I2S-Word Strobe Hold Time after Falling Edge of Clock MICRONAS INTERMETALL Min. Typ. VSUP2 5 pF 1 µA 20 ns 0 ns ns 0 ns 0.4 V II2SOL = 1 mA V II2SOH = −1 mA 32.0 kHz NICAM-PLL closed 1024 kHz 4.0 1.0 1.1 200 ns 180 I2S_CL, I2S_WS 0 V < UINPUT< DVSUP I2S slave mode 1.1 60 0.9 I2S_CL, I2S_DA_OUT 0.2 Test Conditions VSUP2 0.9 I2S_WS, I2S_CL Unit 0.5 −1 I2S_DA_IN1/2, I2S_CL Max. 200 CL = 30 pF ns ns 180 ns 69 MSP 34x1G PRELIMINARY DATA SHEET (Data: MSB first) FI2SWS I2S_WS SONY Mode PHILIPS Mode PHILIPS/SONY Mode programmable by MODUS[6] SONY Mode PHILIPS Mode Detail C I2S_CL Detail A I2S_DAIN R LSB L MSB L LSB R MSB R LSB L LSB 16 bit right channel 16 bit left channel Detail B I2S_DAOUT R LSB L MSB L LSB R MSB R LSB L LSB 16 bit left channel Detail C 16 bit right channel Detail A,B FI2SCL I2S_CL I2S_CL TI2SWS1 TI2S1 TI2SWS2 I2S_WS as INPUT TI2S2 I2S_DA_IN TI2S5 TI2S3 TI2S6 I2S_WS as OUTPUT TI2S4 I2S_DA_OUT Fig. 4–26: I2S bus timing diagram 4.6.3.6. Analog Baseband Inputs and Outputs, AGNDC Symbol Parameter Pin Name Min. Typ. Max. Unit Test Conditions AGNDC 3.67 3.77 3.87 V Rload ≥10 MΩ AGNDC Open Circuit Voltage (5-V Operation) 2.41 2.51 2.61 V AGNDC Output Resistance (8-V Operation) 70 125 180 kΩ AGNDC Output Resistance (5-V Operation) 47 83 120 kΩ Analog Ground VAGNDC0 RoutAGN AGNDC Open Circuit Voltage (8-V Operation) 3 V ≤ VAGNDC ≤ 4 V Analog Input Resistance RinSC SCART Input Resistance from TA = 0 to 70 °C SCn_IN_s1) 25 40 58 kΩ fsignal = 1 kHz, I = 0.05 mA RinMONO MONO Input Resistance from TA = 0 to 70 °C MONO_IN 15 24 35 kΩ fsignal = 1 kHz, I = 0.1 mA 1) 70 “n” means “1”, “2”, “3”, or “4”; “s” means “L” or “R” MICRONAS INTERMETALL MSP 34x1G PRELIMINARY DATA SHEET Symbol Parameter Pin Name Min. SCn_IN_s,1) MONO_IN Typ. Max. Unit Test Conditions 2.00 2.25 VRMS fsignal = 1 kHz 1.13 1.51 VRMS 460 500 Ω Ω −70 +70 mV SCn_IN_s,1) MONO_IN → SCn_OUT_s1) −1.0 +0.5 dB fsignal = 1 kHz −0.5 +0.5 dB with resp. to 1 kHz SCn_OUT_s1) 1.8 1.9 2.0 VRMS fsignal = 1 kHz 1.17 1.27 1.37 VRMS 2.1 2.1 3.3 4.6 5.0 kΩ kΩ 1.80 2.04 61 2.28 V mV 1.12 1.36 40 1.60 V mV Effective Signal Level at Main/ AUX-Output during full-scale Digital Input Signal from I2S for Analog Volume at 0 dB (8-V Operation) 1.23 1.37 1.51 VRMS Effective Signal Level at Main/ AUX-Output during full-scale Digital Input Signal from I2S for Analog Volume at 0 dB (5-V Operation) 0.76 0.90 1.04 VRMS Audio Analog-to-Digital-Converter VAICL Effective Analog Input Clipping Level for Analog-to-DigitalConversion (8-V Operation) Effective Analog Input Clipping Level for Analog-to-DigitalConversion (5-V Operation) SCART Outputs RoutSC SCART Output Resistance at Tj = 27 °C from TA = 0 to 70 °C dVOUTSC Deviation of DC-Level at SCART Output from AGNDC Voltage ASCtoSC Gain from Analog Input to SCART Output frSCtoSC Frequency Response from Analog Input to SCART Output Bandwidth: 0 to 20000 Hz VoutSC Effective Signal Level at SCART-Output during full-scale Digital Input Signal from I2S (8-V Operation) SCn_OUT_s1) 200 200 Effective Signal Level at SCART-Output during full-scale Digital Input Signal from I2S (5-V Operation) 330 fsignal = 1 kHz, I = 0.1 mA Main and AUX Outputs RoutMA Main/AUX Output Resistance at Tj = 27 °C from TA = 0 to 70 °C VoutDCMA DC-Level at Main/AUX-Output for Analog Volume at 0 dB for Analog Volume at −30 dB (8-V Operation) DACp_s1) DC-Level at Main/AUX-Output for Analog Volume at 0 dB for Analog Volume at −30 dB (5-V Operation) VoutMA 1) “n” means “1”, “2”, “3”, or “4”; MICRONAS INTERMETALL “s” means “L” or “R”; fsignal = 1 kHz, I = 0.1 mA fsignal = 1 kHz “p” means “M” or “A” 71 MSP 34x1G PRELIMINARY DATA SHEET 4.6.3.7. Sound IF Inputs Symbol Parameter Pin Name Min. Typ. Max. Unit Test Conditions RIFIN Input Impedance ANA_IN1+, ANA_IN2+, ANA_IN− 1.5 6.8 2 9.1 2.5 11.4 kΩ kΩ Gain AGC = 20 dB Gain AGC = 3 dB DCVREFTOP DC Voltage at VREFTOP VREFTOP 2.45 2.65 2.75 V DCANA_IN DC Voltage on IF Inputs ANA_IN1+, ANA_IN2+, ANA_IN− 1.3 1.5 1.7 V XTALKIF Crosstalk Attenuation 40 dB BWIF 3 dB Bandwidth ANA_IN1+, ANA_IN2+, ANA_IN− 10 MHz AGC AGC Step Width 0.85 fsignal = 1 MHz Input Level = −2 dBr dB 4.6.3.8. Power Supply Rejection Symbol Parameter Pin Name Min. Typ. Max. Unit Test Conditions PSRR: Rejection of Noise on AHVSUP at 1 kHz PSRR AGNDC AGNDC 80 dB From Analog Input to I S Output MONO_IN, SCn_IN_s1) 70 dB From Analog Input to SCART Output MONO_IN, SCn_IN_s1) SCn_OUT_s1) 70 dB From I2S Input to SCART Output SCn_OUT_s1) 60 dB 80 dB 2 2 From I S Input to MAIN or AUX Output 1) 72 “n” means “1”, “2”, “3”, or “4”; DACp_s “s” means “L” or “R”; 1) “p” means “M” or “A” MICRONAS INTERMETALL MSP 34x1G PRELIMINARY DATA SHEET 4.6.3.9. Analog Performance Symbol Parameter Pin Name Min. Typ. from Analog Input to I2S Output MONO_IN, SCn_IN_s1) 85 from Analog Input to SCART Output MONO_IN, SCn_IN_s1) → SCn_OUT_s1) from I2S Input to SCART Output SCn_OUT_s1) from I2S Input to Main/AUX-Output for Analog Volume at 0 dB for Analog Volume at −30 dB DACp_s1) Max. Unit Test Conditions 88 dB Input Level = −20 dB with resp. to VAICL, fsig = 1 kHz, equally weighted 20 Hz...16 kHz 93 96 dB Input Level = −20 dB, fsig = 1 kHz, equally weighted 20 Hz...20 kHz 85 88 dB Input Level = −20 dB, fsig = 1 kHz, equally weighted 20 Hz...15 kHz 85 78 88 83 dB dB Specifications for 8-V Operation SNR THD 1) Signal-to-Noise Ratio Input Level = −20 dB, fsig = 1 kHz, equally weighted 20 Hz...15 kHz Total Harmonic Distortion from Analog Input to I2S Output MONO_IN, SCn_IN_s1) 0.01 0.03 % Input Level = −3 dBr with resp. to VAICL, fsig = 1 kHz, equally weighted 20 Hz...16 kHz from Analog Input to SCART Output MONO_IN, SCn_IN_s → SCn_OUT_s1) 0.01 0.03 % Input Level = −3 dBr, fsig = 1 kHz, equally weighted 20 Hz...20 kHz from I2S Input to SCART Output SCn_OUT_s1) 0.01 0.03 % Input Level = −3 dBr, fsig = 1 kHz, equally weighted 20 Hz...16 kHz from I2S Input to Main or AUX Output DACA_s, DACM_s1) 0.01 0.03 % Input Level = −3 dBr, fsig = 1 kHz, equally weighted 20 Hz...16 kHz “n” means “1”, “2”, “3”, or “4”; MICRONAS INTERMETALL “s” means “L” or “R”; “p” means “M” or “A” 73 MSP 34x1G Symbol PRELIMINARY DATA SHEET Parameter Pin Name Min. Typ. from Analog Input to I2S Output MONO_IN, SCn_IN_s1) 82 from Analog Input to SCART Output MONO_IN, SCn_IN_s1) → SCn_OUT_s1) from I2S Input to SCART Output SCn_OUT_s1) from I2S Input to Main/AUX-Output for Analog Volume at 0 dB for Analog Volume at −30 dB DACp_s1) Max. Unit Test Conditions 85 dB Input Level = −20 dB with resp. to VAICL, fsig = 1 kHz, equally weighted 20 Hz...16 kHz 90 93 dB Input Level = −20 dB, fsig = 1 kHz, equally weighted 20 Hz...20 kHz 82 85 dB Input Level = −20 dB, fsig = 1 kHz, equally weighted 20 Hz...15 kHz 82 75 85 80 dB dB Specifications for 5-V Operation SNR THD 1) 74 Signal-to-Noise Ratio Input Level = −20 dB, fsig = 1 kHz, equally weighted 20 Hz...15 kHz Total Harmonic Distortion 0.1 % Input Level = −3 dBr with resp. to VAICL, fsig = 1 kHz, equally weighted 20 Hz...16 kHz MONO_IN, SCn_IN_s → SCn_OUT_s1) 0.1 % Input Level = −3 dBr, fsig = 1 kHz, equally weighted 20 Hz...20 kHz from I2S Input to SCART Output SCn_OUT_s1) 0.1 % Input Level = −3 dBr, fsig = 1 kHz, equally weighted 20 Hz...16 kHz from I2S Input to Main or AUX Output DACA_s, DACM_s1) 0.1 % Input Level = −3 dBr, fsig = 1 kHz, equally weighted 20 Hz...16 kHz from Analog Input to I2S Output MONO_IN, SCn_IN_s1) from Analog Input to SCART Output “n” means “1”, “2”, “3”, or “4”; “s” means “L” or “R”; 0.03 “p” means “M” or “A” MICRONAS INTERMETALL MSP 34x1G PRELIMINARY DATA SHEET Symbol Parameter Pin Name Min. Typ. Max. Unit Test Conditions XTALK Specifications for 8-V and 5-V Operation XTALK Crosstalk Attenuation − PLCC68 − PSDIP64 Input Level = −3 dB, fsig = 1 kHz, unused analog inputs connected to ground by Z < 1 kΩ between left and right channel within SCART Input/Output pair (L→R, R→L) equally weighted 20 Hz...20 kHz SCn_IN → SCn_OUT1) PLCC68 PSDIP64 80 80 dB dB SC1_IN or SC2_IN → I2S Output PLCC68 PSDIP64 80 80 dB dB SC3_IN → I2S Output PLCC68 PSDIP64 80 80 dB dB I2S Input → SCn_OUT1) PLCC68 PSDIP64 80 80 dB dB between left and right channel within Main or AUX Output pair I2S Input → DACp1) equally weighted 20 Hz...16 kHz PLCC68 PSDIP64 80 75 dB dB between SCART Input/Output pairs D = disturbing program O = observed program D: MONO/SCn_IN → SCn_OUT O: MONO/SCn_IN → SCn_OUT1) PLCC68 PSDIP64 100 100 dB dB D: MONO/SCn_IN → SCn_OUT or unsel. O: MONO/SCn_IN → I2S Output PLCC68 PSDIP64 100 95 dB dB D: MONO/SCn_IN → SCn_OUT O: I2S Input → SCn_OUT1) PLCC68 PSDIP64 100 100 dB dB D: MONO/SCn_IN → unselected O: I2S Input → SC1_OUT1) PLCC68 PSDIP64 100 100 dB dB Crosstalk between Main and AUX Output pairs I2S Input → DACp1) XTALK PLCC68 PSDIP64 95 90 dB dB (equally weighted 20 Hz...16 kHz) same signal source on left and right disturbing channel, effect on each observed output channel (equally weighted 20 Hz...20 kHz) same signal source on left and right disturbing channel, effect on each observed output channel Crosstalk from Main or AUX Output to SCART Output and vice versa D = disturbing program O = observed program 1) (equally weighted 20 Hz...20 kHz same signal source on left and right disturbing channel, effect on each observed output channel D: MONO/SCn_IN/DSP → SCn_OUT O: I2S Input → DACp1) PLCC68 PSDIP64 85 80 dB dB SCART output load resistance 10 kΩ D: MONO/SCn_IN/DSP → SCn_OUT O: I2S Input → DACp1) PLCC68 PSDIP64 90 85 dB dB SCART output load resistance 30 kΩ D: I2S Input → DACp O: MONO/SCn_IN → SCn_OUT1) PLCC68 PSDIP64 100 95 dB dB D: I2S Input → DACM O: I2S Input → SCn_OUT1) PLCC68 PSDIP64 100 95 dB dB “n” means “1”, “2”, “3”, or “4”; MICRONAS INTERMETALL “s” means “L” or “R”; “p” means “M” or “A” 75 MSP 34x1G PRELIMINARY DATA SHEET 4.6.3.10. Sound Standard Dependent Characteristics Symbol Parameter Pin Name Min. DACp_s, SCn_OUT_s1) −1.5 Typ. Max. Unit Test Conditions +1.5 dB 2.12 kHz, Modulator input level = 0 dBref dB NICAM: −6 dB, 1 kHz, RMS unweighted 0 to 15 kHz, Vol = 9 dB NIC_Presc = 7Fhex Output level 1 VRMS at DACp_s NICAM Characteristics (MSP Standard Code = 8) dVNICAMOUT Tolerance of Output Voltage of NICAM Baseband Signal S/NNICAM S/N of NICAM Baseband Signal THDNICAM Total Harmonic Distortion + Noise of NICAM Baseband Signal 0.1 % 2.12 kHz, Modulator input level = 0 dBref BERNICAM NICAM: Bit Error Rate 1 10−7 FM+NICAM, norm conditions fRNICAM NICAM Frequency Response , 20...15000 Hz −1.0 +1.0 dB Modulator input level = −12 dB dBref; RMS XTALKNICAM NICAM Crosstalk Attenuation (Dual) 80 dB SEPNICAM NICAM Channel Separation (Stereo) 80 dB 72 FM Characteristics (MSP Standard Code = 3) DACp_s, SCn_OUT_s1) −1.5 dVFMOUT Tolerance of Output Voltage of FM Demodulated Signal S/NFM S/N of FM Demodulated Signal THDFM Total Harmonic Distortion + Noise of FM Demodulated Signal fRFM FM Frequency Response 20...15000 Hz −1.0 XTALKFM FM Crosstalk Attenuation (Dual) SEPFM FM Channel Separation (Stereo) +1.5 73 DACp_s, SCn_OUT_s1) dB 1 FM-carrier, 50 µs, 1 kHz, 40 kHz deviation; RMS dB 1 FM-carrier 5.5 MHz, 50 µs, 1 kHz, 40 kHz deviation; RMS, unweighted 0 to 15 kHz (for S/N); full input range, FM-Prescale = 46hex, Vol = 0 dB → Output Level 1 VRMS at DACp_s 0.1 % +1.0 dB 1 FM-carrier 5.5 MHz, 50 µs, Modulator input level = −14.6 dBref; RMS 80 dB 2 FM-carriers 5.5/5.74 MHz, 50 µs, 1 kHz, 40 kHz deviation; Bandpass 1 kHz 50 dB 2 FM-carriers 5.5/5.74 MHz, 50 µs, 1 kHz, 40 kHz deviation; RMS AM Characteristics (MSP Standard Code = 9) S/NAM(1) S/NAM(2) THDAM fRRM S/N of AM Demodulated Signal measurement condition: RMS/Flat MSP 34x1G Version A1 MSP 34x1G Version A2 and later S/N of AM Demodulated Signal measurement condition: QP/CCIR MSP 34x1G Version A1 MSP 34x1G Version A2 and later 44 55 dB dB 35 45 dB dB Total Harmonic Distortion + Noise of AM Demodulated Signal MSP 34x1G Version A1 MSP 34x1G Version A2 and later RM Frequency Response 50...12000 Hz 1) “n” means “1”, “2”, “3”, or “4”; 76 DACp_s, SCn_OUT_s1) “s” means “L” or “R”; −2.5 0.8 0.6 % % +1.0 dB SIF level: 0.1−0.8 Vpp AM-carrier 54% at 6.5 MHz Vol = 0 dB, FM/AM prescaler set for output = 0.5 VRMS at Loudspeaker out; Standard Code = 09hex no video/chroma components “p” means “Loudspeaker (Main)’’ or ‘‘Headphone (AUX)’’ MICRONAS INTERMETALL MSP 34x1G PRELIMINARY DATA SHEET Symbol Parameter Pin Name Min. Typ. Max. Unit Test Conditions 68 dB 57 dB 1 kHz L or R or SAP, 100% modulation, 75 µs deemphasis, RMS unweighted 0 to 15 kHz BTSC Characteristics (MSP Standard Code = 20hex, 21hex) S/NBTSC S/N of BTSC Stereo Signal S/N of BTSC-SAP Signal THDBTSC DACp_s, SCn_OUT_s1) THD+N of BTSC Stereo Signal 0.1 % THD+N of BTSC SAP Signal 0.5 % Frequency Response of BTSC Stereo, 50 Hz...12 kHz −0.5 0.5 dB Frequency Response of BTSCSAP, 50 Hz...9 kHz −1.0 0.6 dB Stereo → SAP 76 dB SAP → Stereo 80 dB SEPBTSC Stereo Separation 50 Hz...10 kHz 50 Hz...12 kHz 35 30 dB dB FMpil Pilot deviation threshold fRBTSC XTALKBTSC Stereo off → on ANA_IN1+, ANA_IN2+ Stereo on → off fPilot Pilot Frequency Range ANA_IN1+ ANA_IN2+ 3.2 3.5 kHz 1.2 1.5 kHz 15.563 15.843 kHz 1 kHz L or R or SAP, 100% 75 µs EIM2), DBX NR, RMS unweighted 0 to 15 kHz L or R or SAP, 1%...66% EIM2), DBX NR 1 kHz L or R or SAP, 100% modulation, 75 µs deemphasis, Bandpass 1 kHz L or R 1%...66% EIM2), DBX NR 4.5 MHz carrier modulated with fh = 15.743 kHz SIF level = 100 mVpp indication: STATUS Bit[6] standard BTSC stereo signal, sound carrier only BTSC Characteristics (MSP Standard Code = 20hex, 21hex) with a minimum IF input signal level of 70 mVpp (measured without any video/chroma signal components) S/NBTSC S/N of BTSC Stereo Signal S/N of BTSC-SAP Signal THDBTSC fRBTSC XTALKBTSC SEPBTSC 1) 2) DACp_s, SCn_OUT_s1) 64 dB 55 dB THD+N of BTSC Stereo Signal 0.15 % THD+N of BTSC SAP Signal 0.8 % Frequency Response of BTSC Stereo, 50 Hz...12 kHz −0.5 0.5 dB Frequency Response of BTSCSAP, 50 Hz...9 kHz −1.0 0.6 dB Stereo → SAP 75 dB SAP → Stereo 75 dB Stereo Separation 50 Hz...10 kHz 50 Hz...12 kHz 35 30 dB dB 1 kHz L or R or SAP, 100% modulation, 75 µs deemphasis, RMS unweighted 0 to 15 kHz 1 kHz L or R or SAP, 100% 75 µs EIM2), DBX NR, RMS unweighted 0 to 15 kHz L or R or SAP, 1%...66% EIM2), DBX NR 1 kHz L or R or SAP, 100% modulation, 75 µs deemphasis, Bandpass 1 kHz L or R 1%...66% EIM2), DBX NR “n” means “1”, “2”, “3”, or “4”; “s” means “L” or “R”; “p” means “M” or “A” EIM refers to 75-µs Equivalent Input Modulation. It is defined as the audio-signal level which results in a stated percentage modulation, when the DBX encoding process is replaced by a 75-µs preemphasis network. MICRONAS INTERMETALL 77 MSP 34x1G Symbol PRELIMINARY DATA SHEET Parameter Pin Name Min. Typ. Max. Unit Test Conditions 60 dB 60 dB 1 kHz L or R, 100% modulation, 75 µs deemphasis, RMS unweighted 0 to 15 kHz EIA-J Characteristics (MSP Standard Code = 30hex) S/NEIAJ S/N of EIA-J Stereo Signal S/N of EIA-J Sub-Channel THDEIAJ fREIAJ XTALKEIAJ SEPEIAJ DACp_s, SCn_OUT_s1) THD+N of EIA-J Stereo Signal 0.2 % THD+N of EIA-J Sub-Channel 0.3 % Frequency Response of EIA-J Stereo, 50 Hz...12 kHz −0.5 0.5 dB Frequency Response of EIA-J Sub-Channel, 50 Hz...12 kHz −1.0 0.5 dB Main → SUB 66 dB Sub → MAIN 80 dB Stereo Separation 50 Hz...5 kHz 50 Hz...10 kHz 35 28 dB dB 68 dB 100% modulation, 75 µs deemphasis 1 kHz L or R, 100% modulation, 75 µs deemphasis, Bandpass 1 kHz EIA-J Stereo Signal, L or R 100% modulation FM-Radio Characteristics (MSP Standard Code = 40hex) S/NUKW S/N of FM-Radio Stereo Signal THDUKW THD+N of FM-Radio Stereo Signal fRUKW Frequency Response of FM-Radio Stereo 50 Hz...15 kHz −1.0 SEPUKW Stereo Separation 50 Hz...15 kHz 45 fPilot Pilot Frequency Range 1) 78 “n” means “1”, “2”, “3”, or “4”; DACp_s, SCn_OUT_s1) 0.1 ANA_IN1+ ANA_IN2+ “s” means “L” or “R”; 18.844 +0.5 % 1 kHz L or R, 100% modulation, 75 µs deemphasis, RMS unweighted 0 to 15 kHz L or R, 1%...100% modulation, 75 µs deemphasis dB dB 19.125 kHz standard FM radio stereo signal “p” means “M” or “A” MICRONAS INTERMETALL MSP 34x1G PRELIMINARY DATA SHEET 5. Appendix A: Overview of TV-Sound Standards 5.1. NICAM 728 Table 5–1: Summary of NICAM 728 sound modulation parameters Specification I B/G L D/K Carrier frequency of digital sound 6.552 MHz 5.85 MHz 5.85 MHz 5.85 MHz Transmission rate 728 kbit/s Type of modulation Differentially encoded quadrature phase shift keying (DQPSK) Spectrum shaping Roll-off factor by means of Roll-off filters Carrier frequency of analog sound component 1.0 0.4 6.0 MHz FM mono 5.5 MHz FM mono 0.4 0.4 6.5 MHz AM mono terrestrial cable 6.5 MHz FM mono Power ratio between vision carrier and analog sound carrier 10 dB 13 dB 10 dB 16 dB 13 dB Power ratio between analog and modulated digital sound carrier 10 dB 7 dB 17 dB 11 dB China/Hu ngary Poland 12 dB 7 dB Table 5–2: Summary of NICAM 728 sound coding characteristics Characteristics Values Audio sampling frequency 32 kHz Number of channels 2 Initial resolution 14 bit/sample Companding characteristics near instantaneous, with compression to 10 bits/sample in 32-samples (1 ms) blocks Coding for compressed samples 2’s complement Preemphasis CCITT Recommendation J.17 (6.5 dB attenuation at 800 Hz) Audio overload level +12 dBm measured at the unity gain frequency of the preemphasis network (2 kHz) MICRONAS INTERMETALL 79 MSP 34x1G PRELIMINARY DATA SHEET 5.2. A2-Systems Table 5–3: Key parameters for A2 Systems of Standards B/G, D/K, and M Characteristics Sound Carrier FM1 Sound Carrier FM2 TV-Sound Standard B/G D/K M B/G D/K M Carrier frequency in MHz 5.5 6.5 4.5 5.7421875 6.2578125 6.7421875 5.7421875 4.724212 Vision/sound power difference 13 dB 20 dB Sound bandwidth Preemphasis Frequency deviation (nom/max) 40 Hz to 15 kHz 50 µs 75 µs ±27/±50 kHz ±17/±25 kHz 50 µs 75 µs ±27/±50 kHz ±15/±25 kHz Transmission Modes Mono transmission Stereo transmission Dual sound transmission mono (L+R)/2 language A mono (L+R)/2 R (L−R)/2 language B Identification of Transmission Mode Pilot carrier frequency 54.6875 kHz Max. deviation portion ±2.5 kHz Type of modulation / modulation depth AM / 50% Modulation frequency 80 mono: unmodulated stereo: 117.5 Hz dual: 274.1 Hz 55.0699 kHz 149.9 Hz 276.0 Hz MICRONAS INTERMETALL MSP 34x1G PRELIMINARY DATA SHEET 5.3. BTSC-Sound System Table 5–4: Key parameters for BTSC-Sound Systems Aural Carrier Carrier frequency (fhNTSC = 15.734 kHz) (fhPAL = 15.625 kHz) 4.5 MHz BTSC-MPX-Components (L+R) Pilot (L−R) SAP Prof. Ch. Baseband fh 2 fh 5 fh 6.5 fh Sound bandwidth in kHz 0.05 - 15 0.05 - 15 0.05 - 12 0.05 - 3.4 Preemphasis 75 µs DBX DBX 150 µs 50 kHz1) 15 kHz 3 kHz AM 10 kHz FM 3 kHz FM Max. deviation to Aural Carrier 73 kHz (total) 25 kHz1) 5 kHz Max. Freq. Deviation of Subcarrier Modulation Type 1) Sum does not exceed 50 kHz due to interleaving effects 5.4. Japanese FM Stereo System (EIA-J) Table 5–5: Key parameters for Japanese FM-Stereo Sound System EIA-J Aural Carrier FM (L+R) (L−R) Identification 4.5 MHz Baseband 2 fh 3.5 fh Sound bandwidth 0.05 - 15 kHz 0.05 - 15 kHz − Preemphasis 75 µs 75 µs none 25 kHz 20 kHz 2 kHz 10 kHz FM 60% AM Carrier frequency (fh = 15.734 kHz) Max. deviation portion to Aural Carrier 47 kHz EIA-J-MPX-Components Max. Freq. Deviation of Subcarrier Modulation Type Transmitter-sided delay 20 µs 0 µs 0 µs Mono transmission L+R − unmodulated Stereo transmission L+R L−R 982.5 Hz Bilingual transmission Language A Language B 922.5 Hz MICRONAS INTERMETALL 81 MSP 34x1G PRELIMINARY DATA SHEET 5.5. FM Satellite Sound Table 5–6: Key parameters for FM Satellite Sound Carrier Frequency Maximum FM Deviation Sound Mode Bandwidth Deemphasis 6.5 MHz 85 kHz Mono 15 kHz 50 µs 7.02/7.20 MHz 50 kHz Mono/Stereo/Bilingual 15 kHz adaptive 7.38/7.56 MHz 50 kHz Mono/Stereo/Bilingual 15 kHz adaptive 7.74/7.92 MHz 50 kHz Mono/Stereo/Bilingual 15 kHz adaptive 5.6. FM-Stereo Radio Table 5–7: Key parameters for FM-Stereo Radio Systems Aural Carrier Carrier frequency (fp = 19 kHz) 10.7 MHz FM-Radio-MPX-Components (L+R) Pilot (L−R) RDS/ARI Baseband fp 2 fp 3 fh Sound bandwidth in kHz 0.05 - 15 0.05 - 15 Preemphasis: − USA − Europe 75 µs 50 µs 75 µs 50 µs Max. deviation to Aural Carrier 82 75 kHz (100%) 90% 10% 90% 5% MICRONAS INTERMETALL PRELIMINARY DATA SHEET MSP 34x1G 6. Appendix B: Manual/Compatibility Mode To adapt the modes of the STANDARD SELECT register to individual requirements and for reasons of compatibility to the MSP 34x0D, the MSP 34x1G offers an Manual/Compatibility Mode, which provides sophisticated programming of the MSP 34x1G. Using the STANDARD SELECT register generally provides a more economic way to program the MSP 34x1G and will result in optimal behavior. Therefore, it is not recommended to use the Manual/Compatibility mode. Only in those cases, where compatibility with MSP 34x0D is strictly required, should the Manual/Compatibility mode be used. Note: In case of Automatic Sound Select (MODUS[0]=1), any modifications of the demodulator write registers listed below, except AUTO_FM/AM, are ignored. MICRONAS INTERMETALL 83 MSP 34x1G PRELIMINARY DATA SHEET 6.1. Demodulator Write and Read Registers for Manual/Compatibility Mode Table 6–1: Demodulator Write Registers; Subaddress: 10hex; these registers are not readable! Demodulator Write Registers Address (hex) MSPVersion Description Reset Mode Page AUTO_FM/AM 00 21 3411, 34511) 1. MODUS[0]=1 (Automatic Sound Select): Switching Level threshold of Automatic Switching between NICAM and FM/AM in case of bad NICAM reception 00 00 86 2. MODUS[0]=0 (Manual Mode): Activation and configuration of Automatic Switching between NICAM and FM/AM in case of bad NICAM reception A2_Threshold 00 22 all A2 Stereo Identification Threshold 00 19hex 87 CM_Threshold 00 24 all Carrier-Mute Threshold 00 2Ahex 87 AD_CV 00 BB all SIF-input selection, configuration of AGC, and Carrier-Mute Function 00 00 88 MODE_REG 00 83 3411, 34511) Controlling of MSP-Demodulator and Interface options. As soon as this register is applied, the MSP 34x1G works in the MSP 34x0D Compatibility Mode. 00 00 89 Warning: In this mode, BTSC, EIA-J, and FM-Radio are disabled. Only MSP 34x0D features are available; the use of MODUS and STATUS register is not allowed. The MSP 34x1G is reset to the normal mode by first programming the MODUS register followed by transmitting a valid standard code to the STANDARD SELECTION register. FIR1 FIR2 00 01 00 05 FIR1-filter coefficients channel 1 (6 ⋅ 8 bit) FIR2-filter coefficients channel 2 (6 ⋅ 8 bit), + 3 ⋅ 8 bit offset (total 72 bit) 00 00 91 DCO1_LO DCO1_HI 00 93 00 9B Increment channel 1 Low Part Increment channel 1 High Part 00 00 91 DCO2_LO DCO2_HI 00 A3 00 AB Increment channel 2 Low Part Increment channel 2 High Part PLL_CAPS 00 1F Not of interest for the customer Switchable PLL capacitors to tune open-loop frequency 00 56 94 1) not in BTSC, EIA-J, and FM-Radio mode Table 6–2: Demodulator Read Registers; Subaddress: 11hex; these registers are not writable! Demodulator Read Registers Address (hex) MSPVersion Description Page C_AD_BITS 00 23 3411, 3451 NICAM-Sync bit, NICAM-C-Bits, and three LSBs of additional data bits 93 ADD_BITS 00 38 NICAM: bit [10:3] of additional data bits 93 CIB_BITS 00 3E NICAM: CIB1 and CIB2 control bits 93 ERROR_RATE 00 57 NICAM error rate, updated with 182 ms 94 PLL_CAPS 02 1F Not for customer use 94 AGC_GAIN 02 1E Not for customer use 94 84 MICRONAS INTERMETALL MSP 34x1G PRELIMINARY DATA SHEET 6.2. DSP Write and Read Registers for Manual/Compatibility Mode Table 6–3: DSP-Write Registers; Subaddress: 12hex, all registers are readable as well Write Register Address (hex) Bits Operational Modes and Adjustable Range Reset Mode Page Volume SCART1 channel: Ctrl. mode 00 07 [7..0] [Linear mode / logarithmic mode] 00hex 95 FM Fixed Deemphasis 00 0F [15..8] [50 µs, 75 µs, OFF] 50 µs 95 [7..0] [OFF, WP1] OFF 95 FM Adaptive Deemphasis Identification Mode 00 15 [7..0] [B/G, M] B/G 96 FM DC Notch 00 17 [7..0] [ON, OFF] ON 96 Volume SCART2 channel: Ctrl. mode 00 40 [7..0] [Linear mode / logarithmic mode] 00hex 95 Table 6–4: DSP Read Registers; Subaddress: 13hex, all registers are not writable Additional Read Registers Address (hex) Bits Output Range Stereo detection register for A2 Stereo Systems 00 18 [15..8] [80hex ... 7Fhex] 8 bit two’s complement 96 DC level readout FM1/Ch2-L 00 1B [15..0] [8000hex ... 7FFFhex] 16 bit two’s complement 96 DC level readout FM2/Ch1-R 00 1C [15..0] [8000hex ... 7FFFhex] 16 bit two’s complement 96 MICRONAS INTERMETALL Page 85 MSP 34x1G PRELIMINARY DATA SHEET 6.3. Manual/Compatibility Mode: Description of Demodulator Write Registers 6.3.1. Automatic Switching between NICAM and Analog Sound In case of bad NICAM reception or loss of the NICAM-carrier, the MSP 34x1G offers an Automatic Switching (fall back) to the analog sound (FM/AMMono), without the necessity of the controller reading and evaluating any parameters. If a proper NICAM signal returns, switching back to this source is performed automatically as well. The feature evaluates the NICAM ERROR_RATE and switches, if necessary, all output channels which are assigned to the NICAM source, to the analog source, and vice versa. An appropriate hysteresis algorithm avoids oscillating effects (see Fig. 6–1). STATUS[9] and C_AD_BITS[11] (Addr: 0023 hex) provide information about the actual NICAM-FM/AM-status. Individual configuration of the threshold can be done using Table 6–5, whereby the bits 0 and 11 of AUTO_FM are ignored. It is recommended to use the internal setting used by the standard selection. The optimum NICAM sound can be assigned to the MSP output channels by selecting one of the “Stereo or A/B”, “Stereo or A”, or “Stereo or B” source channels. 6.3.1.2. Function in Manual Mode If the manual mode (MODUS[0]=0) is required, the activation and configuration of the Automatic Switching feature has to be done as described in Table 6–5. Note, that the channel matrix of the corresponding output channels must be set according to the NICAM mode and need not to be changed in the FM/AM-fallback case. Example: Required threshold = 500: bits [10:1]=00 1111 1010 6.3.1.1. Function in Automatic Sound Select Mode Selected Sound The Automatic Sound Select feature (MODUS[0]=1) includes the procedure mentioned above. By default, the internal ERROR_RATE threshold is set to 700dec. i.e. : NICAM – NICAM → analog Sound if ERROR_RATE > 700 – analog Sound → NICAM if ERROR_RATE < 700/2 The ERROR_RATE value of 700 corresponds to a BER of approximately 5.46*10-3/s. analog Sound ERROR_RATE threshold/2 threshold Fig. 6–1: Hysteresis for Automatic Switching Table 6–5: Coding of Automatic NICAM/Analog Sound Switching; Reset Status: Mode 0 Mode Description AUTO_FM [11:0] Addr. = 00 21hex ERROR_RATEThreshold/dec Source Select: Input at NICAM Path1) 0 Compatible to MSP 3410B, i.e. automatic switching is disabled Bit Bits Bit [0] =0 [10:1] = 0 [11] = 0 none always NICAM; Mute in case of no NICAM available 1 Automatic Switching with internal threshold (Default, if Automatic Sound Select is on) Bit Bit Bit [0] =1 [10:1] = 0 [11] = 0 700 NICAM or FM/AM, depending on ERROR_RATE 2 Automatic Switching with external threshold (Customizing of Automatic Sound Select) Bit Bit set by customer; recommended range: 50...2000 Bit [0] =1 [10:1] = 25..1000 = threshold/2 [11] =0 Forced analog mono mode, i.e. Automatic Switching is disabled (Customizing of Automatic Sound Select) Bit Bit Bit [0] =1 [10:1] = 0 [11] = 1 none 3 1) always FM/AM In case of Automatic Sound Select (MODUS[0] = 1), the NICAM path may be assigned to “Stereo or A/B”, “Stereo or A”, or “Stereo or B” source channels (see Table 2–2 on page 12). In case of Automatic Sound Select (MODUS[0] = 1), bit [0] of AUTO_FM is ignored 86 MICRONAS INTERMETALL MSP 34x1G PRELIMINARY DATA SHEET 6.3.2. A2 Threshold The threshold between Stereo/Bilingual and Mono Identification for the A2 Standard has been made programmable according to the user’s preferences. An internal hysteresis ensures robustness and stability. Table 6–6: Write Register on I2C Subaddress 10hex : A2 Threshold Register Address Function Name A2 THRESHOLD Register A2_THRESH THRESHOLDS 00 22hex (write) Defines threshold of all A2 and EIA_J standards for Stereo and Bilingual detection bit [11..0] 7F0hex ... 190hex ... 0A0hex force Mono Identification bit [15..12] must be set to 0 default setting after reset minimum Threshold for stable detection recommended range : 0A0hex...3C0hex 6.3.3. Carrier-Mute Threshold The Carrier-Mute threshold has been made programmable according to the user’s preferences. An internal hysteresis ensures stable behavior. Table 6–7: Write Register on I2C Subaddress 10hex : Carrier-Mute Threshold Register Address Function Name Carrier-Mute THRESHOLD Register CM_THRESH THRESHOLDS 00 24hex (write) Defines threshold for the carrier mute feature bit [6..0] bit [15..7] 00hex ... 2Ahex ... 7Fhex Carrier-Mute always ON (both channels muted) default setting after reset Carrier-Mute always OFF (both channels forced on) must be set to 0 recommended range : 14hex...50hex MICRONAS INTERMETALL 87 MSP 34x1G PRELIMINARY DATA SHEET 6.3.4. Register AD_CV The use of this register is no longer recommended. Use it only in cases where compatibility to the MSP 34x0D is required. Using the STANDARD SELECTION register together with the MODUS register provides a more economic way to program the MSP 34x1G. Table 6–8: AD_CV Register; reset status: all bits are “0” AD_CV (00 BBhex) Automatic setting by STANDARD SELECT Register Bit Function Settings 2-8, 0A-60hex 9 [0] not used must be set to 0 0 0 [1−6] Reference level in case of Automatic Gain Control = on (see Table 6–9). Constant gain factor when Automatic Gain Control = off (see Table 6–10). 101000 100011 [7] Determination of Automatic Gain or Constant Gain 0 = constant gain 1 = automatic gain 1 1 [8] Selection of Sound IF source (identical to MODUS[8]) 0 = ANA_IN1+ 1 = ANA_IN2+ X X [9] MSP-Carrier-Mute Feature 0 = off: no mute 1 = on: mute as described in section 2.2.2. 1 0 [10−15] not used must be set to 0 0 0 X : not affected while choosing the TV sound standard by means of the STANDARD SELECT Register Table 6–9: Reference Values for Active AGC (AD_CV[7] = 1) Application Input Signal Contains AD_CV [6:1] Ref. Value AD_CV [6:1] in integer Range of Input Signal at pin ANA_IN1+ and ANA_IN2+ − FM Standards 1 or 2 FM Carriers 101000 40 0.10 − 3 Vpp1) − NICAM/FM 1 FM and 1 NICAM Carrier 101000 40 0.10 − 3 Vpp1) − NICAM/AM 1 AM and 1 NICAM Carrier 100011 35 0.10 − 1.4 Vpp (recommended: 0.10 − 0.8 Vpp) − NICAM only 1 NICAM Carrier only 010100 20 0.05 − 1.0 Vpp SAT 1 or more FM Carriers 100011 35 0.10 − 3 Vpp1) ADR FM and ADR carriers see DRP 3510A data sheet Terrestrial TV 1) 88 For signals above 1.4 Vpp, the minimum gain of 3 dB is switched, and overflow of the A/D converter may result. Due to the robustness of the internal processing, the IC works up to and even more than 3 Vpp, if norm conditions of FM/NICAM or FM1/FM2 ratio are supposed. In this overflow case, a loss of FM-S/N ratio of about 10 dB may appear. MICRONAS INTERMETALL MSP 34x1G PRELIMINARY DATA SHEET Table 6–10: AD_CV parameters for Constant Input Gain (AD_CV[7]=0) Step AD_CV [6:1] Constant Gain Gain Input Level at pin ANA_IN1+ and ANA_IN2+ 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 000000 000001 000010 000011 000100 000101 000110 000111 001000 001001 001010 001011 001100 001101 001110 001111 010000 010001 010010 010011 010100 3.00 dB 3.85 dB 4.70 dB 5.55 dB 6.40 dB 7.25 dB 8.10 dB 8.95 dB 9.80 dB 10.65 dB 11.50 dB 12.35 dB 13.20 dB 14.05 dB 14.90 dB 15.75 dB 16.60 dB 17.45 dB 18.30 dB 19.15 dB 20.00 dB maximum input level: 3 Vpp (FM) or 1 Vpp (NICAM)1) 1) maximum input level: 0.14 Vpp For signals above 1.4 Vpp, the minimum gain of 3 dB is switched and overflow of the A/D converter may result. Due to the robustness of the internal processing, the IC works up to and even more than 3 Vpp, if norm conditions of FM/NICAM or FM1/FM2 ratio are supposed. In this overflow case, a loss of FM-S/N ratio of about 10 dB may appear. 6.3.5. Register MODE_REG Note: The use of this register is no longer recommended. It should be used only in cases where software compatibility to the MSP 34x0D is required. Using the STANDARD SELECTION register together with the MODUS register provides a more economic way to program the MSP 34x1G. As soon as this register is applied, the MSP 34x1G works in the MSP 34x0D Compatibility Mode. In this mode: BTSC, EIA-J, and FM-Radio are disabled. Only MSP 34x0D features are available; the use of MODUS and STATUS register is not allowed. The MSP 34x1G is reset to the normal mode by first programming the MODUS register, followed by transmitting a valid standard code to the STANDARD SELECTION register. The register ‘MODE_REG’ contains the control bits determining the operation mode of the MSP 34x1G in the MSP 34x0D Compatibility Mode; Table 6–11 explains all bit positions. MICRONAS INTERMETALL 89 MSP 34x1G PRELIMINARY DATA SHEET Table 6–11: Control word ‘MODE_REG’; reset status: all bits are “0” MODE_REG 00 83hex Bit Function [0] not used [1] DCTR_TRI [2] Comment Automatic setting by STANDARD SELECT Register Definition 2-5 8, A, B 9 0 : must be used 0 0 0 Digital control out 0/1 tri-state 0 : active 1 : tri-state X X X I2S_TRI I2S outputs tri-state (I2S_CL, I2S_WS, I2S_DA_OUT) 0 : active 1 : tri-state X X X [3] I2S Mode1) Master/Slave mode of the I2S bus 0 : Master 1 : Slave X X X [4] I2S_WS Mode WS due to the Sony or Philips-Format 0 : Sony 1 : Philips X X X [5] Audio_CL_OUT Switch Audio_Clock_Output to tri-state 0 : on 1 : tri-state X X X [6] NICAM1) Mode of MSP-Ch1 0 : FM 1 : Nicam 0 1 1 [7] not used 0 : must be used 0 0 0 [8] FM AM Mode of MSP-Ch2 0 : FM 1 : AM 0 0 1 [9] HDEV High Deviation Mode (channel matrix must be sound A) 0 : normal 1 : high deviation mode 0 0 0 [11:10] not used 0 : must be used 0 0 0 [12] MSP-Ch1 Gain see also Table 6–13 0 : Gain = 6 dB 1 : Gain = 0 dB 0 0 0 [13] FIR1-Filter Coeff. Set see also Table 6–13 0 : use FIR1 1 : use FIR2 1 0 0 [14] ADR Mode of MSP-Ch1/ ADR-Interface 0 : normal mode/tri-state 1 : ADR-mode/active 0 0 0 [15] AM-Gain Gain for AM Demodulation 0 : 0 dB (default. of MSPB) 1 :12 dB (recommended) 1 1 1 X: not affected by short-programming 90 MICRONAS INTERMETALL MSP 34x1G PRELIMINARY DATA SHEET Table 6–12: Loading sequence for FIR-coefficients FIR1 00 01hex (MSP-Ch1: NICAM/FM2) No. Symbol Name Bits 1 NICAM/FM2_Coeff. (5) 8 2 NICAM/FM2_Coeff. (4) 8 3 NICAM/FM2_Coeff. (3) 8 4 NICAM/FM2_Coeff. (2) 8 5 NICAM/FM2_Coeff. (1) 8 6 NICAM/FM2_Coeff. (0) 8 The loading sequences must be obeyed. To change a coefficient set, the complete block FIR1 or FIR2 must be transmitted. Value Note: For compatibility with MSP 3410B, IMREG1 and IMREG2 have to be transmitted. The value for IMREG1 and IMREG2 is 004. Due to the partitioning to 8-bit units, the values 04hex, 40hex, and 00hex arise. see Table 6–13 6.3.7. DCO-Registers Note: The use of this register is no longer recommended. It should be used only in cases where software-compatibility to the MSP 34x0D is required. Using the STANDARD SELECTION register together with the MODUS register provides a more economic way to program the MSP 34x1G. FIR2 00 05hex (MSP-Ch2: FM1/AM) No. Symbol Name Bits Value 1 IMREG1 8 04hex 2 IMREG1/ IMREG2 8 40hex 3 IMREG2 8 00hex 4 FM/AM_Coef (5) 8 5 FM/AM_Coef (4) 8 6 FM/AM_Coef (3) 8 7 FM/AM_Coef (2) 8 If manual setting of the tuning frequency is required, a set of 24-bit registers determining the mixing frequencies of the quadrature mixers can be written manually into the IC. In Table 6–14, some examples of DCO registers are listed. It is necessary to divide them up into low part and high part. The formula for the calculation of the registers for any chosen IF frequency is as follows: 8 FM/AM_Coef (1) 8 INCRdec = int(f/fs ⋅ 224) 9 FM/AM_Coef (0) 8 with: int = integer function f = IF frequency in MHz fS = sampling frequency (18.432 MHz) see Table 6–13 6.3.6. FIR-Parameter, Registers FIR1 and FIR2 Note: The use of this register is no longer recommended. It should be used only in cases where software compatibility to the MSP 34x0D is required. Using the STANDARD SELECTION register together with the MODUS register provides a more economic way to program the MSP 34x1G. When selecting a TV-sound standard by means of the STANDARD SELECT register, all frequency tuning is performed automatically. Conversion of INCR into hex-format and separation of the 12-bit low and high parts lead to the required register values (DCO1_HI or _LO for MSP-Ch1, DCO2_HI or LO for MSP-Ch2). Data-shaping and/or FM/AM bandwidth limitation is performed by a pair of linear phase Finite Impulse Response filters (FIR-filter). The filter coefficients are programmable and are either configured automatically by the STANDARD SELECT register or written manually by the control processor via the control bus. Two not necessarily different sets of coefficients are required: one for MSP-Ch1 (NICAM or FM2) and one for MSP-Ch2 (FM1 = FM-mono). In Table 6–13 several coefficient sets are proposed. To load the FIR-filters, the following data values are to be transferred 8 bits at a time embedded LSB-bound in a 16-bit word. MICRONAS INTERMETALL 91 MSP 34x1G PRELIMINARY DATA SHEET Table 6–13: 8-bit FIR-coefficients (decimal integer); reset status: all coefficients are “0” Coefficients for FIR1 00 01hex and FIR2 00 05hex Terrestrial TV Standards FM - Satellite FIR filter corresponds to a band-pass with a bandwidth of B = 130 to 500 kHz B frequency fc B/G-, D/KNICAM-FM Coef(i) INICAM-FM LNICAM-AM B/G-, D/K-, M-Dual FM 130 kHz 180 kHz 200 kHz 280 kHz 380 kHz 500 kHz Autosearch FIR2 FIR2 FIR2 FIR2 FIR2 FIR2 FIR2 FIR2 FIR1 FIR2 FIR1 FIR2 FIR1 FIR2 0 −2 3 2 3 −2 −4 3 73 9 3 −8 −1 −1 −1 1 −8 18 4 18 −8 −12 18 53 18 18 −8 −9 −1 −1 2 −10 27 −6 27 −10 −9 27 64 28 27 4 −16 −8 −8 3 10 48 −4 48 10 23 48 119 47 48 36 5 2 2 4 50 66 40 66 50 79 66 101 55 66 78 65 59 59 5 86 72 94 72 86 126 72 127 64 72 107 123 126 126 ModeREG[12] 0 0 0 0 1 1 1 1 1 1 0 ModeREG[13] 0 0 0 1 1 1 1 1 1 1 0 For compatibility, except for the FIR2-AM and the Autosearch-sets, the FIR-filter programming as used for the MSP 3410B is also possible. ADR coefficients are listed in the DRP data sheet. Table 6–14: DCO registers for the MSP 34x1G; reset status: DCO_HI/LO = “0000” DCO1_LO 00 93hex, DCO1_HI 00 9Bhex; DCO2_LO 00 A3hex, DCO2_HI 00 ABhex Freq. MHz DCO_HI/hex DCO_LO/hex Freq. MHz DCO_HI/hex DCO_LO/hex 4.5 03E8 000 5.04 5.5 5.58 5.7421875 0460 04C6 04D8 04FC 0000 038E 0000 00AA 5.76 5.85 5.94 0500 0514 0528 0000 0000 0000 6.0 6.2 6.5 6.552 0535 0561 05A4 05B0 0555 0C71 071C 0000 6.6 6.65 6.8 05BA 05C5 05E7 0AAA 0C71 01C7 7.02 0618 0000 7.2 0640 0000 7.38 0668 0000 7.56 0690 0000 92 MICRONAS INTERMETALL MSP 34x1G PRELIMINARY DATA SHEET 6.4. Manual/Compatibility Mode: Description of Demodulator Read Registers Note: The use of these register is no longer recommended. It should be used only in cases where software compatibility to the MSP 34x0D is required. Using the STANDARD SELECTION register together with the STATUS register provides a more economic way to program the MSP 34x1G and to retrieve information from the IC. All registers except C_AD_BITs are 8 bits wide. They can be read out of the RAM of the MSP 34x1G if the MSP 34x0D Compatibility Mode is required. All transmissions take place in 16-bit words. The valid 8-bit data are the 8 LSBs of the received data word. If the Automatic Sound Select feature is not used, the NICAM or FM-identification parameters must be read and evaluated by the controller in order to enable appropriate switching of the channel select matrix of the baseband processing part. The FM-identification registers are described in section 6.6.1. To handle the NICAM-sound and to observe the NICAM-quality, at least the registers C_AD_BITS and ERROR_RATE must be read and evaluated by the controller. Additional data bits and CIB bits, if supplied by the NICAM transmitter, can be obtained by reading the registers ADD_BITS and CIB_BITS. Table 6–15: NICAM operation modes as defined by the EBU NICAM 728 specification C4 C3 C2 C1 Operation Mode 0 0 0 0 Stereo sound (NICAMA/B), independent mono sound (FM1) 0 0 0 1 Two independent mono signals (NICAMA, FM1) 0 0 1 0 Three independent mono channels (NICAMA, NICAMB, FM1) 0 0 1 1 Data transmission only; no audio 1 0 0 0 Stereo sound (NICAMA/B), FM1 carries same channel 1 0 0 1 One mono signal (NICAMA). FM1 carries same channel as NICAMA 1 0 1 0 Two independent mono channels (NICAMA, NICAMB). FM1 carries same channel as NICAMA 1 0 1 1 Data transmission only; no audio x 1 x x Unimplemented sound coding option (not yet defined by EBU NICAM 728 specification) AUTO_FM: monitor bit for the AUTO_FM Status: 0: NICAM source is NICAM 1: NICAM source is FM Note: It is no longer necessary to read out and evaluate the C_AD_BITS. All evaluation is performed in the MSP and indicated in the STATUS register. 6.4.1. NICAM Mode Control/Additional Data Bits Register NICAM operation mode control bits and A[2:0] of the additional data bits. Format: 6.4.2. Additional Data Bits Register 11 ... 7 6 5 4 3 2 1 0 Contains the remaining 8 of the 11 additional data bits. The additional data bits are not yet defined by the NICAM 728 system. Auto _FM ... A[2] A[1] A[0] C4 C3 C2 C1 S Format: MSB C_AD_BITS 00 23hex LSB Important: “S” = Bit[0] indicates correct NICAM-synchronization (S = 1). If S = 0, the MSP 3411/3451G has not yet synchronized correctly to frame and sequence, or has lost synchronization. The remaining read registers are therefore not valid. The MSP mutes the NICAM output automatically and tries to synchronize again as long as MODE_REG[6] is set. The operation mode is coded by C4-C1 as shown in Table 6–15. MSB ADD_BITS 00 38hex 7 6 5 4 3 2 1 0 A[10] A[9] A[8] A[7] A[6] A[5] A[4] A[3] 6.4.3. CIB Bits Register CIB bits 1 and 2 (see NICAM 728 specifications). Format: MSB MICRONAS INTERMETALL LSB CIB_BITS 00 3Ehex LSB 7 6 5 4 3 2 1 0 x x x x x x CIB1 CIB2 93 MSP 34x1G PRELIMINARY DATA SHEET 6.4.7. Automatic Search Function for FM-Carrier Detection in Satellite Mode 6.4.4. NICAM Error Rate Register ERROR_RATE 00 57hex Error free 0000hex maximum error rate 07FFhex The AM demodulation ability of the MSP 34x1G offers the possibility to calculate the “field strength” of the momentarily selected FM carrier, which can be read out by the controller. In SAT receivers, this feature can be used to make automatic FM carrier search possible. Average error rate of the NICAM reception in a time interval of 182 ms, which should be close to 0. The initial and maximum value of ERROR_RATE is 2047. This value is also active if the NICAM bit of MODE_REG is not set. Since the value is achieved by filtering, a certain transition time (approx. 0.5 sec) is unavoidable. Acceptable audio may have error rates up to a value of 700 int. Individual evaluation of this value by the controller and an appropriate threshold may define the fallback mode from NICAM to FM/AM-Mono in case of poor NICAM reception. The bit error rate per second (BER) can be calculated by means of the following formula: BER = ERROR_RATE * 12.3*10−6 /s 6.4.5. PLL_CAPS Readback Register It is possible to read out the actual setting of the PLL_CAPS. In standard applications, this register is not of interest for the customer. PLL_CAPS 02 1Fhex L minimum frequency 1111 1111 FFhex nominal frequency 0101 0110 RESET 56hex maximum frequency 0000 0000 00hex PLL_CAPS 02 1Fhex H PLL open xxxx xxx0 PLL closed xxxx xxx1 For this, the MSP has to be switched to AM-mode (MODE_REG[8]), FM-Prescale must be set to 7Fhex = +127dec, and the FM DC notch (see section 6.5.7.) must be switched off. The sound-IF frequency range must now be “scanned” in the MSP-channel 2 by means of the programmable quadrature mixer with an appropriate incremental frequency (i.e. 10 kHz). After each incrementation, a field strength value is available at the quasi-peak detector output (quasipeak detector source must be set to FM), which must be examined for relative maxima by the controller. This results in either continuing search or switching the MSP back to FM demodulation mode. During the search process, the FIR2 must be loaded with the coefficient set “AUTOSEARCH”, which enables small bandwidth, resulting in appropriate field strength characteristics. The absolute field strength value (can be read out of “quasi-peak detector output FM1”) also gives information on whether a main FM carrier or a subcarrier was detected; and as a practical consequence, the FM bandwidth (FIR1/2) and the deemphasis (50 µs or adaptive) can be switched accordingly. Due to the fact that a constant demodulation frequency offset of a few kHz leads to a DC level in the demodulated signal, further fine tuning of the found carrier can be achieved by evaluating the “DC Level Readout FM1”. Therefore, the FM DC Notch must be switched on, and the demodulator part must be switched back to FM-demodulation mode. For a detailed description of the automatic search function, please refer to the corresponding MSP Windows software. 6.4.6. AGC_GAIN Readback Register It is possible to read out the actual setting of AGC_GAIN in Automatic Gain Mode. In standard applications, this register is not of interest for the customer. AGC_GAIN 02 1Ehex max. amplification (20 dB) 0001 0100 14hex min. amplification (3 dB) 0000 0000 00hex 94 MICRONAS INTERMETALL MSP 34x1G PRELIMINARY DATA SHEET 6.5. Manual/Compatibility Mode: Description of DSP Write Registers 6.5.2. Volume Modes of SCART1/2 Outputs 6.5.1. Additional Channel Matrix Modes Loudspeaker Matrix 00 08hex L Headphone Matrix 00 09hex L SCART1 Matrix 00 0Ahex L SCART2 Matrix 00 41hex L I2S Matrix 00 0Bhex L Quasi-Peak Detector Matrix 00 0Chex L SUM/DIFF 0100 0000 40hex AB_XCHANGE 0101 0000 50hex PHASE_CHANGE_B 0110 0000 60hex PHASE_CHANGE_A 0111 0000 70hex A_ONLY 1000 0000 80hex B_ONLY 1001 0000 90hex Volume Mode SCART1 00 07hex [3:0] Volume Mode SCART2 00 40hex [3:0] linear 0000 RESET 0hex logarithmic 0001 1hex Volume SCART1 00 07hex H Volume SCART2 00 40hex H OFF 0000 0000 RESET 00hex 0 dB gain (digital full scale (FS) to 2 VRMS output) 0100 0000 40hex +6 dB gain (−6 dBFS to 2 VRMS output) 0111 1111 7Fhex Linear Mode This table shows additional modes for the channel matrix registers. The sum/difference mode can be used together with the quasi-peak detector to determine the sound material mode. If the difference signal on channel B (right) is near to zero, and the sum signal on channel A (left) is high, the incoming audio signal is mono. If there is a significant level on the difference signal, the incoming audio is stereo. Note: SCART Volume linear mode will not be supported in the future (documented for compatibility reasons only). 6.5.3. FM Fixed Deemphasis FM Deemphasis 00 0Fhex H 50 µs 0000 0000 RESET 00hex 75 µs 0000 0001 01hex OFF 0011 1111 3Fhex 6.5.4. FM Adaptive Deemphasis FM Adaptive Deemphasis WP1 00 0Fhex L OFF 0000 0000 RESET 00hex WP1 0011 1111 3Fhex 6.5.5. NICAM Deemphasis A J17 Deemphasis is always applied to the NICAM signal. It is not switchable. MICRONAS INTERMETALL 95 MSP 34x1G PRELIMINARY DATA SHEET 6.5.6. Identification Mode for A2 Stereo Systems Identification Mode 00 15hex L Standard B/G (German Stereo) 0000 0000 RESET 00hex Standard M (Korean Stereo) 0000 0001 01hex Reset of Ident-Filter 0011 1111 3Fhex To shorten the response time of the identification algorithm after a program change between two FM-Stereo capable programs, the reset of the ident-filter can be applied. Sequence: 1. Program change 6.6.1. Stereo Detection Register for A2 Stereo Systems Stereo Detection Register 00 18hex H Stereo Mode Reading (two’s complement) MONO near zero STEREO positive value (ideal reception: 7Fhex) BILINGUAL negative value (ideal reception: 80hex) Note: It is no longer necessary to read out and evaluate the A2 identification level. All evaluation is performed in the MSP and indicated in the STATUS register. 2. Reset ident-filter 3. Set identification mode back to standard B/G or M 6.6.2. DC Level Register 4. Read stereo detection register 6.5.7. FM DC Notch The DC compensation filter (FM DC Notch) for FM input can be switched off. This is used to speed up the automatic search function (see Section 6.4.7.). In normal FM-mode, the FM DC Notch should be switched on. FM DC Notch 00 17hex L ON 0000 0000 Reset 00hex OFF 0011 1111 3Fhex 6.6. Manual/Compatibility Mode: Description of DSP Read Registers All readable registers are 16-bit wide. Transmissions via I2C bus have to take place in 16-bit words. Some of the defined 16-bit words are divided into low and high byte, thus holding two different control entities. These registers are not writable. DC Level Readout FM1 (MSP-Ch2) 00 1Bhex H+L DC Level Readout FM2 (MSP-Ch1) 00 1Chex H+L DC Level [8000hex ... 7FFFhex] values are 16 bit two’s complement The DC level register measures the DC component of the incoming FM signals (FM1 and FM2). This can be used for seek functions in satellite receivers and for IF FM frequencies fine tuning. A too low demodulation frequency (DCO) results in a positive DC-level and vice versa. For further processing, the DC content of the demodulated FM signals is suppressed. The time constant τ, defining the transition time of the DC Level Register, is approximately 28 ms. 6.7. Demodulator Source Channels in Manual Mode 6.7.1. Terrestric Sound Standards Table 6–16 shows the source channel assignment of the demodulated signals in case of manual mode for all terrestric sound standards. See Table 2–2 for the assignment in the Automatic Sound Select mode. In manual mode for terrestric sound standards, only two demodulator sources are defined. 6.7.2. SAT Sound Standards Table 6–17 shows the source channel assignment of the demodulated signals for SAT sound standards. 96 MICRONAS INTERMETALL MSP 34x1G PRELIMINARY DATA SHEET Table 6–16: Manual Sound Select Mode for Terrestric Sound Standards Source Channels of Sound Select Block Broadcasted Sound Standard Selected MSP Standard Code Broadcasted Sound Mode FM Matrix B/G-FM D/K-FM M-Korea M-Japan 03 04, 05 02 30 MONO B/G-NICAM L-NICAM I-NICAM D/K-NICAM D/K-NICAM 08 09 0A 0B 0C (with high deviation FM) 20 BTSC FM/AM Stereo or A/B (use 0 for channel select) (use 1 for channel select) Sound A Mono Mono Mono STEREO German Stereo Korean Stereo Stereo Stereo BILINGUAL, Languages A and B No Matrix Left = A Right = B Left = A Right = B NICAM not available or NICAM error rate too high Sound A Mono analog Mono no sound MONO Sound A Mono analog Mono NICAM Mono STEREO Sound A Mono analog Mono NICAM Stereo BILINGUAL, Languages A and B Sound A Mono analog Mono Left = NICAM A Right = NICAM B MONO Sound A Mono Mono Mono STEREO Korean Stereo Stereo Stereo MONO + SAP Sound A Mono Mono Mono STEREO + SAP Korean Stereo Stereo Stereo Sound A Mono Mono Mono No Matrix Left = Mono Right = SAP Left = Mono Right = SAP MONO Sound A Mono Mono Mono STEREO Korean Stereo Stereo Stereo MONO 21 with AUTO_FM: analog Mono STEREO MONO + SAP STEREO + SAP FM-Radio 40 Table 6–17: Manual Sound Select Modes for SAT-Modes (FM Matrix is set automatically) Source Channels of Sound Select Block for SAT-Modes Broadcasted Sound Standard FM SAT Selected MSP Standard Code Broadcasted Sound Mode FM/AM Stereo or A/B Stereo or A Stereo or B (source select: 0) (source select: 1) (source select: 3) (source select: 4) 6, 50hex MONO Mono Mono Mono Mono 51hex STEREO Stereo Stereo Stereo Stereo BILINGUAL Left = A (FM1) Right = B (FM2) Left = A (FM1) Right = B (FM2) A (FM1) B (FM2) MICRONAS INTERMETALL 97 MSP 34x1G PRELIMINARY DATA SHEET 6.8. Exclusions of Audio Baseband Features In general, all functions can be switched independently. Two exceptions exist: 1. NICAM cannot be processed simultaneously with the FM2 channel. 2. FM adaptive deemphasis cannot be processed simultaneously with FM-identification. 6.9. Phase Relationship of Analog Outputs The analog output signals: Loudspeaker, headphone, and SCART2 all have the same phases. The user does not need to correct output phases when using these analog outputs directly. The SCART1 output has opposite phase. Using the I2S-outputs for other DSPs or D/A converters, care must be taken to adjust for the correct phase. If the attached coprocessor is one of the MSP family, the following schematics help to determine the phase relationship. I2S_IN1/2 I2S_OUT1/2 Loudspeaker Headphone SCART1-Ch. Audio Baseband Processing SCART1 SCART1 SCART2 SCART3 SCART4 SCART DSP Input Select SCART2-Ch. SCART2 MONO MONO, SCART1...4 SCART Output Select Fig. 6–2: Phase diagram of the MSP 34x1G 98 MICRONAS INTERMETALL PRELIMINARY DATA SHEET MSP 34x1G 7. Appendix D: MSP 34x1G Version History MSP 3451G-A1 First release MSP 3451G-A2 – CONTROL register now readable for more status information – new D/K standard for Poland – improved I2C hardware problem handling – improved AM-performance MICRONAS INTERMETALL 99 MSP 34x1G PRELIMINARY DATA SHEET 8. Appendix E: Application Circuit IF 2 IN if ANA_IN2+ not used Signal GND 100 nF 8 V(5 V) + 3.3 µF ANA_IN1+ + + 10 µF XTAL_OUT (63) 20 AGNDC (42) 42 VREFTOP (54) 29 56 pF 18.432 MHz + 56 pF ANA_IN2+ (60) 23 ANA_IN− (59) 24 56 pF ANA_IN1+ (58) 25 56 pF 100 nF 100 pF 1 KΩ 10 µF CAPL_A (38) 46 10 µF - IF 1 IN XTAL_IN (62) 21 Tuner 1 C s. section 4.6.2. CAPL_M (40) 44 Tuner 2 Alternative circuit for ANA_IN1+for more attenuation of video components: 1 µF DACM_L (29) 56 330 nF 28 (55) MONO_IN 1 nF 1 µF 1 nF 1 µF LOUD SPEAKER DACM_R (28) 57 330 nF 330 nF 31 (52) SC1_IN_L 30 (53) SC1_IN_R DACM_SUB (31) 54 32 (51) ASG1 AHVSS 330 nF 330 nF 1 nF 34 (49) SC2_IN_L 1 µF 33 (50) SC2_IN_R 35 (48) ASG2 AHVSS 330 nF DACA_L (26) 59 37 (46) SC3_IN_L 1 nF 36 (47) SC3_IN_R 330 nF 38 (45) ASG4 AHVSS 330 nF 5V 330 nF 1 nF 40 (43) SC4_IN_L MSP 34x1G 39 (44) SC4_IN_R SC1_OUT_L (37) 47 11 (7) STANDBYQ 5V HEAD PHONE 1 µF DACA_R (25) 60 SC1_OUT_R (36) 48 DVSS 12 (6) ADR_SEL SC2_OUT_L (34) 50 DVSS 8 (10) I2C_DA 9 (9) I2C_CL SC2_OUT_R (33) 51 1 (16) ADR_WS 100 Ω 22 µF + 100 Ω 22 µF + 100 Ω 22 µF + 100 Ω 22 µF + 68 (17) ADR_CL 3 (15) ADR_DA D_CTR_I/O_0 (5) 13 6 (12) I2S_WS D_CTR_I/O_1 (4) 14 7 (11) I2S_CL 4 (14) I2S_DA_IN1 AUD_CL_OUT (1) 18 65 (20) I2S_DA_IN2 100 58 (27) VREF2 49 (35) VREF1 45 (39) AHVSUP 27 (56) AVSS 8V (5 V) AHVSS Note: Pin numbers refer to the PLCC68 package, numbers in brackets refer to the PSDIP64 package. AHVSS 66 (19) DVSS 26 (57) AVSUP 5V 470 pF 1.5 nF 10 µF AHVSS 5V 470 pF 1.5 nF 10 µF AHVSS 220 pF 470 pF 1.5 nF 10 µF AVSS (from Controller, see section 4.6.3.3.) 67 (18) DVSUP 61 (24) RESETQ RESETQ 43 (41) AHVSS TESTEN (61) 22 5 (13) I2S_DA_OUT MICRONAS INTERMETALL PRELIMINARY DATA SHEET MICRONAS INTERMETALL MSP 34x1G 101 MSP 34x1G PRELIMINARY DATA SHEET 9. Data Sheet History 1. Preliminary data sheet: “MSP 34x1G Multistandard Sound Processor Family with Virtual Dolby Surround”, Edition Oct. 15, 1999, 6251-511-1PD. First release of the preliminary data sheet. MICRONAS INTERMETALL GmbH Hans-Bunte-Strasse 19 D-79108 Freiburg (Germany) P.O. Box 840 D-79008 Freiburg (Germany) Tel. +49-761-517-0 Fax +49-761-517-2174 E-mail: [email protected] Internet: http://www.intermetall.de Printed in Germany Order No. 6251-511-1PD 102 All information and data contained in this data sheet is without any commitment, is not to be considered as an offer for conclusion of a contract nor shall it be construed as to create any liability. Any new issue of this data sheet invalidates previous issues. Product availability and delivery dates are exclusively subject to our respective order confirmation form; the same applies to orders based on development samples delivered. By this publication, MICRONAS INTERMETALL GmbH does not assume responsibility for patent infringements or other rights of third parties which may result from its use. Reprinting is generally permitted, indicating the source. However, our prior consent must be obtained in all cases. MICRONAS INTERMETALL