Fairchild FSDM0265RN Green mode fairchild power switch Datasheet

www.fairchildsemi.com
FSDH321, FSDL321
Green Mode Fairchild Power Switch (FPSTM)
Features
• Internal Avalanche Rugged Sense FET
• Consumes only 0.65W at 240VAC & 0.3W load with
Advanced Burst-Mode Operation
• Frequency Modulation for low EMI
• Precision Fixed Operating Frequency
• Internal Start-up Circuit
• Pulse by Pulse Current Limiting
• Abnormal Over Current Protection
• Over Voltage Protection
• Over Load Protection
• Internal Thermal Shutdown Function
• Auto-Restart Mode
• Under Voltage Lockout
• Low Operating Current (max 3mA)
• Adjustable Peak Current Limit
• Built-in Soft Start
Applications
• SMPS for STB, Low cost DVD
• Auxiliary Power for PC
• Adaptor for Charger
Description
The FSDx321(x stands for H, L) are integrated Pulse Width
Modulators (PWM) and Sense FETs specifically designed
for high performance offline Switch Mode Power Supplies
(SMPS) with minimal external components. Both devices
are integrated high voltage power switching regulators
which combine an avalanche rugged Sense FET with a current mode PWM control block. The integrated PWM controller features include: a fixed oscillator with frequency
modulation for reduced EMI, Under Voltage Lock Out
(UVLO) protection, Leading Edge Blanking (LEB), optimized gate turn-on/turn-off driver, Thermal Shut Down
(TSD) protection, Abnormal Over Current Protection
(AOCP) and temperature compensated precision current
sources for loop compensation and fault protection circuitry.
When compared to a discrete MOSFET and controller or
RCC switching converter solution, the FSDx321 reduce total
component count, design size, weight and at the same time
increase efficiency, productivity, and system reliability. Both
devices are a basic platform well suited for cost effective
designs of flyback converters.
OUTPUT POWER TABLE
230VAC ±15%(3)
85-265VAC
PRODUCT
Adapter(1)
Open
Frame(2)
Adapter(1)
Open
Frame(2)
FSDL321
11W
17W
8W
12W
FSDH321
11W
17W
8W
12W
FSDL0165RN
13W
23W
11W
17W
FSDM0265RN
16W
27W
13W
20W
FSDH0265RN
16W
27W
13W
20W
FSDL0365RN
19W
30W
16W
24W
FSDM0365RN
19W
30W
16W
24W
FSDL321L
11W
17W
8W
12W
FSDH321L
11W
17W
8W
12W
FSDL0165RL
13W
23W
11W
17W
FSDM0265RL
16W
27W
13W
20W
FSDH0265RL
16W
27W
13W
20W
FSDL0365RL
19W
30W
16W
24W
FSDM0365RL
19W
30W
16W
24W
Table 1. Notes: 1. Typical continuous power in a non-ventilated enclosed adapter measured at 50°C ambient. 2.
Maximum practical continuous power in an open frame
design at 50°C ambient. 3. 230 VAC or 100/115 VAC with
doubler.
Typical Circuit
AC
IN
DC
OUT
Vstr
Ipk
Drain
PWM
Vfb
Vcc
Source
Figure 1. Typical Flyback Application
Rev.1.0.2
©2004 Fairchild Semiconductor Corporation
FSDH321, FSDL321
Internal Block Diagram
Vcc
Vstr
5
2
Istart
+
V BURL /V BURH
-
Soft start
8V/12V
Vcc good
Vcc
V BURH
I B_PEAK
Vcc
Drain
6,7,8
Internal
Bias
Vref
Freq.
Modulation
Vcc
OSC
I delay
V FB
I FB
Normal
2.5R
Ipk
S
Q
R
Q
PWM
3
Burst
Gate
driver
R
4
LEB
V SD
Vcc
1 GND
S
Q
R
Q
Vovp
TSD
Vcc good
AOCP
Vocp
Figure 2. Functional Block Diagram of FSDx321
2
FSDH321, FSDL321
Pin Definitions
Pin Number
Pin Name
1
GND
Sense FET source terminal on primary side and internal control ground.
Vcc
Positive supply voltage input. Although connected to an auxiliary transformer winding, current is supplied from pin 5 (Vstr) via an internal switch during
startup (see Internal Block Diagram section). It is not until Vcc reaches the
UVLO upper threshold (12V) that the internal start-up switch opens and device power is supplied via the auxiliary transformer winding.
Vfb
The feedback voltage pin is the non-inverting input to the PWM comparator.
It has a 0.9mA current source connected internally while a capacitor and optocoupler are typically connected externally. A feedback voltage of 6V triggers over load protection (OLP). There is a time delay while charging
between 3V and 6V using an internal 5uA current source, which prevents
false triggering under transient conditions but still allows the protection
mechanism to operate under true overload conditions.
Ipk
Pin to adjust the current limit of the Sense FET. The feedback 0.9mA current
source is diverted to the parallel combination of an internal 2.8kΩ resistor
and any external resistor to GND on this pin to determine the current limit.
If this pin is tied to Vcc or left floating, the typical current limit will be 0.7A.
Vstr
This pin connects directly to the rectified AC line voltage source. At start up
the internal switch supplies internal bias and charges an external storage
capacitor placed between the Vcc pin and ground. Once the Vcc reaches
12V, the internal switch is disabled.
Drain
The Drain pin is designed to connect directly to the primary lead of the transformer and is capable of switching a maximum of 650V. Minimizing the
length of the trace connecting this pin to the transformer will decrease leakage inductance.
2
3
4
5
6, 7, 8
Pin Function Description
Pin Configuration
8DIP
8LSOP
GND 1
8 Drain
Vcc 2
7 Drain
Vfb 3
6 Drain
Ipk 4
5 Vstr
Figure 3. Pin Configuration (Top View)
3
FSDH321, FSDL321
Absolute Maximum Ratings
(Ta=25°C, unless otherwise specified)
Parameter
Symbol
Value
Unit
VSTR,MAX
650
V
VDRAIN,MAX
650
V
VDGR
650
V
Gate-Source (GND) Voltage
VGS
±20
V
Drain Current Pulsed (1)
IDM
1.5
ADC
Continuous Drain Current (Tc=25°C)
ID
0.7
ADC
Continuous Drain Current (Tc=100°C)
ID
0.32
ADC
EAS
10
mJ
Maximum Vstr Pin Voltage
Maximum Drain Pin Voltage
Drain-Gate Voltage (RGS=1MΩ)
Single Pulsed Avalanche
Energy (2)
VCC,MAX
20
V
Input Voltage Range
VFB
−0.3 to Vstop
V
Total Power Dissipation
PD
1.25
W
Operating Junction Temperature.
TJ
+150
°C
Operating Ambient Temperature.
TA
-25 to +85
°C
TSTG
-55 to +150
°C
Maximum Supply Voltage
Storage Temperature Range.
Note:
1. Repetitive rating: Pulse width limited by maximum junction temperature
2. L = 24mH, starting Tj = 25°C
4
FSDH321, FSDL321
Electrical Characteristics (Sense FET Part)
(Ta = 25°C unless otherwise specified)
Parameter
Symbol
Condition
Min.
Typ.
Max.
Unit
Sense FET SECTION
Drain-Source Breakdown Voltage
BVDSS
VGS=0V, ID=50µA
650
720
-
V
Startup Voltage (Vstr) Breakdown
BVSTR
VCC=0V, ID=1mA
650
720
-
V
VDS=Max. Rating,
VGS=0V
-
-
25
µA
VDS=0.8Max. Rating,
VGS=0V, TC=125°C
-
-
200
µA
RDS(ON)
VGS=10V, ID=0.5A
-
14
19
Ω
gfs
VDS=50V, ID=0.5A
1.0
1.3
-
S
-
162
-
-
18
-
-
3.8
-
Zero Gate Voltage Drain Current
Static Drain-Source on Resistance
(Note)
Forward Trans conductance (Note)
IDSS
Input Capacitance
CISS
Output Capacitance
COSS
Reverse Transfer Capacitance
CRSS
Turn on Delay Time
td(on)
Rise Time
Turn Off Delay Time
Fall Time
tr
td(off)
tf
Total Gate Charge
(Gate-Source + Gate-Drain)
Qg
Gate-Source Charge
Qgs
Gate-Drain (Miller) Charge
Qgd
VGS=0V, VDS=25V,
f=1MHz
VDD=0.5B VDSS,
ID=1.0A
(MOSFET switching time
is essentially
independent of
operating temperature)
VGS=10V, ID=1.0A,
VDS=0.5B VDSS
(MOSFET switching time
is essentially
independent of operating
temperature)
-
9.5
-
-
19
-
-
33
-
-
42
-
-
7.0
-
-
3.1
-
-
0.4
-
pF
ns
nC
Note:
1. Pulse test: Pulse width ≤ 300µS, duty ≤ 2%
2.
1S = --R
5
FSDH321, FSDL321
Electrical Characteristics (Control Part) (Continued)
(Ta=25°C unless otherwise specified)
Parameter
Symbol
Condition
Min.
Typ.
Max.
Unit
UVLO SECTION
Start Threshold Voltage
VSTART
VFB=GND
11
12
13
V
Stop Threshold Voltage
VSTOP
VFB=GND
7
8
9
V
90
100
110
±2.5
±3
±3.5
45
50
55
±1.0
±1.5
±2.0
-
±5
±10
%
FSDH321
62
67
72
%
FSDL321
71
77
83
%
0.70
0.90
1.1
mA
5.5
6.0
6.5
V
3.5
5.0
6.5
µA
0.4
0.5
0.6
V
0.25
0.35
0.45
V
-
150
-
mV
OSCILLATOR SECTION
Initial Accuracy
FOSC
Frequency Modulation
FMOD
Initial Accuracy
FOSC
Frequency Modulation
FMOD
Frequency Change With Temperature (2)
∆F/∆T
Maximum Duty Cycle
Dmax
FSDH321
FSDL321
-25°C ≤ Ta ≤ +85°C
kHz
kHz
FEEDBACK SECTION
Feedback Source Current
IFB
Shutdown Feedback Voltage
VSD
Shutdown Delay Current
IDELAY
Ta=25°C, Vfb = 0V
Ta=25°C, Vfb = 4V
BURST MODE SECTION
VBURH
Burst Mode Voltage
VBURL
Tj = 25°C
Hysteresis
CURRENT LIMIT(SELF-PROTECTION)SECTION
Peak Current Limit(3)
ILIM
Tj = 25°C
0.60
0.70
0.80
A
Current Limit Delay(1)
TCLD
Tj = 25°C
-
600
-
ns
TSS
Vfb = 4V
10
15
20
ms
125
145
-
°C
18
19
20
V
0.7
0.85
1.0
mA
1
3
5
mA
SOFT START SECTION
Soft Start Time
PROTECTION SECTION
Thermal Shutdown Temperature (1)
Over Voltage Protection
TSD
-
VOVP
TOTAL STANDBY CURRENT SECTION
Startup Charging Current
ICH
VCC=0V
Operating Supply Current
(Control Part Only)
IOP
VCC = 14V, Vfb = 0V
Note:
1. These parameters, although guaranteed, are not 100% tested in production
2. These parameters, although guaranteed, are tested in EDS (wafer test) process
3. di/dt = 250mA/uS
6
FSDH321, FSDL321
Comparison Between FSDM311 and FSDx321
Function
FSDM311
FSDx321
FSDx321 Advantages
Soft-Start
15mS
15mS
• Gradually increasing current limit
during soft-start further reduces peak
current and voltage component
stresses
• Eliminates external components used
for soft-start in most applications
• Reduces or eliminates output
overshoot
External Current Limit
not applicable
Programmable of
default current limit
• Smaller transformer
• Allows power limiting (constant overload power)
• Allows use of larger device for lower
losses and higher efficiency.
Frequency Modulation
not applicable
±1.5KHz @50KHz
±3.0KHz @100KHz
• Reduced conducted EMI
Burst Mode Operation
Yes-built into
controller
Yes-built into
controller
• Improve light load efficiency
• Reduces no-load consumption
• Transformer audible noise reduction
Drain Creepage at
Package
7.62mm
7.62mm
• Greater immunity to arcing as a result
of build-up of dust, debris and other
contaminants
7
FSDH321, FSDL321
Typical Performance Characteristics (Control Part)
1.20
1.20
1.00
1.00
Normalized
Normalized
(These characteristic graphs are normalized at Ta = 25°C)
0.80
0.60
0.40
0.80
0.60
0.40
0.20
0.20
0.00
0.00
-50
0
50
100
-50
150
0
T emp[ ℃]
1.20
1.00
1.00
Normalized
Normalized
1.20
0.80
0.60
0.40
0.20
150
0.80
0.60
0.40
0.20
0.00
0.00
-50
0
50
100
150
-50
0
T emp[ ℃]
50
100
150
T emp[ ℃]
Operating supply current (Iop)
Maximum duty cycle (Dmax)
1.20
1.20
1.00
1.00
Normalized
Nomalized
100
Frequency Modulation (FMOD)
Operating Frequency (Fosc)
0.80
0.60
0.40
0.20
0.80
0.60
0.40
0.20
0.00
0.00
-50
0
50
100
T emp[ ℃]
Start Threshold Voltage (Vstart)
8
50
T emp[ ℃]
150
-50
0
50
100
T emp[ ℃]
Stop Threshold Voltage (Vstop)
150
FSDH321, FSDL321
1.20
1.20
1.00
1.00
Normalized
Normalized
Typical Performance Characteristics (Continued)
0.80
0.60
0.40
0.80
0.60
0.40
0.20
0.20
0.00
0.00
-50
0
50
100
-50
150
0
Feedback Source Current (Ifb)
150
100
150
Peak current limit (ILIM)
1.20
1.20
1.00
1.00
Normalized
Normalized
100
T emp[ ℃]
T emp[ ℃]
0.80
0.60
0.40
0.20
0.80
0.60
0.40
0.20
0.00
0.00
-50
0
50
100
150
-50
0
T emp[ ℃]
50
T emp[ ℃]
Startup Charging Current (Ich)
Start up Current (Istart)
1.20
1.20
1.00
1.00
Normalized
Normalized
50
0.80
0.60
0.40
0.80
0.60
0.40
0.20
0.20
0.00
0.00
-50
0
50
100
T emp[ ℃]
Burst peak current (Iburst)
150
-50
0
50
100
150
Temp[℃]
Over Voltage Protection (Vovp)
9
FSDH321, FSDL321
Functional Description
1. Startup : In previous generations of Fairchild Power
Switches (FPSTM) the Vstr pin had an external resistor to the
DC input voltage line. In this generation the startup resistor
is replaced by an internal high voltage current source and a
switch that shuts off when 15mS goes by after the supply
voltage, Vcc, gets above 12V. The source turns back on if
Vcc drops below 8V.
Vcc
Vfb
Vo
0.9mA
FB
3
OSC
D1
Cfb
D2
28R
Vfb*
Gate
driver
R
431
VSD
Vin,dc
Vref
2uA
OLP
Istr
Figure 5. Pulse width modulation (PWM) circuit
Vstr
Vcc
UVLO <8V
on
J-FET
15m S After UVLO
start(>12V)
off
Figure 4. High voltage current source
2. Feedback Control : The FSDx321 employs current mode
control, shown in figure 5. An opto-coupler (such as the
H11A817A) and shunt regulator (such as the KA431) are
typically used to implement the feedback network. Comparing the feedback voltage with the voltage across the Rsense
resistor plus an offset voltage makes it possible to control the
switching duty cycle. When the reference pin voltage of the
KA431 exceeds the internal reference voltage of 2.5V, the
H11A817A LED current increases, thus pulling down the
feedback voltage and reducing the duty cycle. This event
typically happens when the input voltage is increased or the
output load is decreased.
3. Leading edge blanking (LEB) : At the instant the internal
Sense FET is turned on, there usually exists a high current
spike through the Sense FET, caused by the primary side
capacitance and secondary side rectifier diode reverse recovery. Excessive voltage across the Rsense resistor would lead
to incorrect feedback operation in the current mode PWM
control. To counter this effect, the FPSTM employs a leading
edge blanking (LEB) circuit. This circuit inhibits the PWM
comparator for a short time (TLEB) after the Sense FET is
turned on.
10
4. Protection Circuit : The FPSTM has several protective functions such as over load protection (OLP), over voltage protection (OVP), abnormal over current protection (AOCP),
under voltage lock out (UVLO) and thermal shutdown
(TSD). Because these protection circuits are fully integrated
inside the IC without external components, the reliability is
improved without increasing cost. Once the fault condition
occurs, switching is terminated and the Sense FET remains
off. This causes Vcc to fall. When Vcc reaches the UVLO
stop voltage, 8V, the protection is reset and the internal high
voltage current source charges the Vcc capacitor via the Vstr
pin. When Vcc reaches the UVLO start voltage,12V, the
FPSTM resumes its normal operation. In this manner, the
auto-restart can alternately enable and disable the switching
of the power Sense FET until the fault condition is eliminated.
4.1 Over Load Protection (OLP) : Overload is defined as the
load current exceeding a pre-set level due to an unexpected
event. In this situation, the protection circuit should be activated in order to protect the SMPS. However, even when the
SMPS is in the normal operation, the over load protection
circuit can be activated during the load transition. In order to
avoid this undesired operation, the over load protection circuit is designed to be activated after a specified time to determine whether it is a transient situation or an overload
situation. In conjunction with the Ipk current limit pin (if
used) the current mode feedback path would limit the current
in the Sense FET when the maximum PWM duty cycle is
attained. If the output consumes more than this maximum
power, the output voltage (Vo) decreases below the set voltage. This reduces the current through the opto-coupler LED,
which also reduces the opto-coupler transistor current, thus
increasing the feedback voltage (Vfb). If Vfb exceeds 3V, the feedback input diode is blocked and the 5uA Idelay current source starts
to charge Cfb slowly up to Vcc. In this condition, Vfb continues
increasing until it reaches 6V, when the switching operation is terminated as shown in figure 6. The delay time for shutdown is the
time required to charge Cfb from 3V to 6V with 5uA.
FSDH321, FSDL321
enabled and monitors the current through the sensing resistor. The voltage across the resistor is then compared with a
preset AOCP level. If the sensing resistor voltage is greater
than the AOCP level, pulse by pulse AOCP is triggered
regardless of uncontrollable LEB time. Here, pulse by pulse
AOCP stops Sense FET within 350nS after it is activated.
Vcc
8V
OLP
6V
FPS switching
Following Vcc
3V
Delay current (5uA) charges the Cfb
t1
t2
t1 = −
1
RC
t 2 = C fb
In (1 −
fb
t3
t4
V ( t 1)
); V ( t1) = 3V , R = 2 . 8 K Ω , C fb = C
R
t
fb _ fig . 2
(V (t1 + t 2) − V (t1))
; I delay = 5uA,V (t1 + t 2) − V (t1) = 3V
I delay
Figure 6. Over load protection
4.2 Thermal Shutdown (TSD) : The Sense FET and the control IC are integrated, making it easier for the control IC to
detect the temperature of the Sense FET. When the temperature exceeds approximately 140°C, thermal shutdown is acti-
4.4 Over Voltage Protection (OVP) : In case of malfunction in the secondary side feedback circuit, or feedback loop
open caused by a defect of solder, the current through the
opto-coupler transistor becomes almost zero. Then, Vfb
climbs up in a similar manner to the over load situation, forcing the preset maximum current to be supplied to the SMPS
until the over load protection is activated. Because excess
energy is provided to the output, the output voltage may
exceed the rated voltage before the over load protection is
activated, resulting in the breakdown of the devices in the
secondary side. In order to prevent this situation, an over
voltage protection (OVP) circuit is employed. In general,
Vcc is proportional to the output voltage and the FPSTM uses
Vcc instead of directly monitoring the output voltage. If
VCC exceeds 19V, OVP circuit is activated resulting in termination of the switching operation. In order to avoid undesired activation of OVP during normal operation, Vcc should
be properly designed to be below 19V.
vated.
4.3 Abnormal Over Current Protection (AOCP) :
PWM
COMPARATOR
Vfb
CLK
LEB
Drain
Out Driver
Vsense
AOCP
COMPARATOR
S
Q
R
5. Soft Start : The FPSTM has an internal soft start circuit that
increases the feedback voltage together with the Sense FET
current slowly after it starts up. The typical soft start time is
15msec, as shown in figure 8, where progressive increments
of Sense FET current are allowed during the start-up phase.
The pulse width to the power switching device is progressively increased to establish the correct working conditions
for transformers, inductors, and capacitors. The voltage on
the output capacitors is progressively increased with the
intention of smoothly establishing the required output voltage. It also helps to prevent transformer saturation and
reduce the stress on the secondary diode.
Rsense
VAOCP
Drain current
[A]
Figure 7. AOCP Function & Block
Even though the FPSTM has OLP (Over Load Protection)
and current mode PWM feedback, these are not enough to
protect the FPSTM when a secondary side diode short or a
transformer pin short occurs. In addition to start-up, softstart is also activated at each restart attempt during autorestart and when restarting after latch mode is activated. The
FPSTM has an internal AOCP (Abnormal Over Current Protection) circuit as shown in figure 7. When the gate turn-on
signal is applied to the power Sense FET, the AOCP block is
0.7A
0.4A
Tss
11
FSDH321, FSDL321
D R A IN
5V
Burst Operation
Burst Operation
Feedback
Normal Operation
S W IT C H
OFF
GND
I_ o v e r
0.5V
0.5V
Rsense
0.3V
0.35V
Current
waveform
Switching OFF
Switching OFF
Figure 8. Soft Start Function
Figure 10. Circuit for Burst Operation
6. Burst operation :In order to minimize power dissipation in
standby mode, the FPSTM enters burst mode operation.
+
0.35V/0.5V
0.3/0.5V
-
0.5V
0.5V
Vcc
IB_PEAK
Vcc
Idelay
FB
Vcc
IFB
Normal
PWM
3
2.5R
Burst
R
MOSFET
Current
7. Frequency Modulation : EMI reduction can be accomplished by modulating the switching frequency of a switched
power supply. Frequency modulation can reduce EMI by
spreading the energy over a wider frequency range than the
band width measured by the EMI test equipment. The
amount of EMI reduction is directly related to the depth of
the reference frequency. As can be seen in Figure 11, the frequency changes from 97KHz to 100KHz (from 48.5KHz to
51.5KHz ; FSDL321)in 4mS for the FSDH321. Frequency
modulation allows the use of a cost effective inductor instead
of an AC input mode choke to satisfy the requirements of
world wide EMI limits.
Internal
Oscillator
Figure 9. Circuit for Burst operation
103kHz
As the load decreases, the feedback voltage decreases. As shown in
figure 10, the device automatically enters burst mode when the
feedback voltage drops below VBURH(500mV). Switching still continues but the current limit is set to a fixed limit internally to minimize flux density in the transformer. The fixed current limit is
larger than that defined by Vfb = VBURH and therefore, Vfb is
driven down further. Switching continues until the feedback
voltage drops below VBURL(350mV). At this point switching
stops and the output voltages start to drop at a rate dependent
on the standby current load. This causes the feedback voltage to rise. Once it passes VBURH(500mV) switching resumes.
The feedback voltage then falls and the process repeats. Burst
mode operation alternately enables and disables switching of
the power Sense FET thereby reducing switching loss in
Standby mode.
12
Drain to
Source
voltage
Drain to
Vds
Waveform
6kHz
97kHz
100kHz
103kHz
Turn-on
Turn-off
Figure 11. Frequency Modulation Waveform for FSDH321
FSDH321, FSDL321
8. Adjusting Current limit function: As shown in fig 12, a
combined 2.8KΩ internal resistance is connected into the
non-inverting lead on the PWM comparator. A external
resistance of Y on the current limit pin forms a parallel resistance with the 2.8KΩ when the internal diodes are biased by
the main current source of 900uA.
5uA
900uA
Feed
Back
3
2 KΩ
4
Current
Limit
PWM
comparator
0.8 KΩ
AK Ω
Rsense
SenseFET
Sense
Figure 12. Peak current adjustment
For example, FSDH321 has a typical Sense FET current limit
(ILIM) of 0.7A. The Sense FET current can be limited to 0.5 by
inserting a kΩ between the current limit pin and ground
which is derived from the following equations:
0.7: 0.5 = 2.8KΩ : XKΩ ,
X = 2KΩ,
Since X represents the resistance of the parallel network, Y
can be calculated using the following equation:
Y = X / (1 - (X/2.8KΩ)) ; Y = 7KΩ
13
FSDH321, FSDL321
Typical application circuit
1. PC Auxiliary Power Circuit (10W Output Power)
C101
10nF
630V
R102
100kΩ
1W
R101
680kΩ
1W
L201
10uH
D201
SB360
T1
EE1625
140~375
VDC
INPUT
1
10
2
7
C201
1000uF
16V
C203
470uF
16V
5V
(+/-5%)
2A
D101
UF 4007
3
M Vcc
5
IC101
FSDx321
3
D102
1N4937
Vstr
Drain 6,7,8
Vfb
Vcc
2
D103
1N4937
R103
10Ω
Ω
4
C102
47uF
50V R104
10Ω
Ω
5
C104
22nF
GND
1
C103
10uF
50V
R202
330Ω
Ω
6
PC301
H11A817A
R201
1kΩ
Ω
C301
2.2nF
IC201
KA431
R203
2kΩ
Ω
C202
100nF
R204
2kΩ
Ω
10W PC Auxiliary Power Circuit
10W PC Auxiliary Power, 150~375VDC Input Power
supply:
It shows a auxiliary power for PC. Efficiency at 10W, 150/
375VDC is ≥70%.
The PC application has the standard of standby power consumption, under 1W at the output load, 0.5W and height
input voltage, 230VAC. For this the FSDH321 also has the
burst operating function like the any other green mode FPS
like FSDM0265RN or FSDM0365RN and so on. This skill
reduces the MOSFET switching numbers and power MOSFET switching loss. This design takes advantage of self protection without external components and high switching
frequency, 100kHz. The frequency makes using a small size
transformer core possible. The EE16 or EE1625 can be used
for 10W application.
This is achieved by preventing the green FPS from switching
when the input voltage goes below a level needed to maintain output regulation, and keeping it off until the input voltage goes above the under-voltage threshold, when the AC is
turned on again. For example with the resistor, R101,
680kΩ, the threshold voltage is around 150VAC(210VDC)
at the room temperature.
Leakage inductance clamping is provided by R102 and
14
C101, keeping the DRAIN voltage below 650 V under all
conditions. And R102 dissipates power to prevent rising of
DRAIN Voltage caused by leakage inductance. The frequency modulation feature of FSDH321 allows the circuit
shown to meet CISPR2AB with simple EMI filtering. The
secondary is rectified and smoothed by D201. Similarly
D102 and D103 are also rectifiers for main power control IC
and FSDH321 respectively. The 5V output voltage require
two capacitors in parallel to meet the ripple current requirement. Switching noise filtering is provided by L201. The
output is regulated by the reference (TL431) voltage in secondary. It is sensed via R203 and R204. Resistor R201 provides bias for TL431 and R202 sets the overall DC gain.
R2012, C202 and R203 provide loop compensation.
FSDH321, FSDL321
2. Transformer Specification (10W Output Power)
1. Schematic Diagram
EE1625
N p/2
1
N p/2 2
10
3
9
Na
N 5V
Np/2
NM Vcc
N M Vcc
Na
8
4
N5V
5
7
Np/2
6
2. Winding Specification
P in ( S ! F )
W ire
T u rn s
W in d in g M e th o d
3 ! 2
0 .1 5 φ × 1
80
S o le n o id w in d in g
N p /2
In s u la tio n : P o ly e s te r T a p e t = 0 .0 5 0 m m , 3 L a y e rs
10 ! 7
N 5V
0 .5 5 φ × 1
12
S o le n o id w in d in g
In s u la tio n : P o ly e s te r T a p e t = 0 .0 5 0 m m , 3 L a y e rs
4 ! 6
N M VCC
0 .2 0 φ × 1
40
S o le n o id w in d in g
In s u la tio n : P o ly e s te r T a p e t = 0 .0 5 0 m m , 3 L a y e rs
2 ! 1
N p /2
0 .1 5 φ × 1
80
S o le n o id w in d in g
In s u la tio n : P o ly e s te r T a p e t = 0 .0 5 0 m m , 3 L a y e rs
5 ! 6
Na
0 .2 0 φ × 1
34
S o le n o id w in d in g
O u te r In s u la tio n : P o ly e s te r T a p e t = 0 .0 5 0 m m , 3 L a y e rs
3. Electric Specification and Core and Bobbin
P in
Spec.
R e m a rk
In d u c ta n c e
1 – 3
1 .8 m H
1 kH z, 1 V
L e a ka g e
1 - 3
100uH
2 n d s id e a ll s h o rt
C o re
EE1625
B o b b in
EE1625
15
FSDH321, FSDL321
Layout Considerations
SURFACE MOUNTED
COPPER AREA FOR HEAT
SINKING
DC_link Capacitor
#1 : GND
#2 : VCC
#3 : Vfb
#4 : Ipk
#5 : Vstr
#6 : Drain
#7 : Drain
#8 : Drain
Y1CAPACITOR
Figure 13. Layout Considerations for FSDx321 using 8DIP
16
- +
DC
OUT
FSDH321, FSDL321
Package Dimensions
8DIP
17
FSDH321, FSDL321
Package Dimensions (Continued)
8LSOP
18
FSDH321, FSDL321
Ordering Information
Product Number
Package
Marking Code
BVDSS
FOSC
RDS(on)
FSDH321
8DIP
DH321
650V
100KHz
14Ω
FSDL321
8DIP
DL321
650V
50KHz
14Ω
FSDH321L
8LSOP
DH321
650V
100KHz
14Ω
FSDL321L
8LSOP
DL321
650V
50KHz
14Ω
19
FSDH321, FSDL321
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PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY
LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER
DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS.
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CORPORATION. As used herein:
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which, (a) are intended for surgical implant into the body,
or (b) support or sustain life, and (c) whose failure to
perform when properly used in accordance with
instructions for use provided in the labeling, can be
reasonably expected to result in a significant injury of the
user.
2. A critical component in any component of a life support
device or system whose failure to perform can be
reasonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
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