NJRC NJU6655BCJ 64-common x 160-segment 1-icon common bitmap lcd driver Datasheet

NJU6655B
Preliminary
64-common X 160-segment + 1-icon common
Bitmap LCD Driver
! GENERAL DESCRIPTION
The NJU6655B is a bitmap LCD driver to display graphics or
characters.
It contains 10,400 bits display data RAM, microprocessor
interface circuits, instruction decoder, 64-common and
160-segment + 1-icon-common drivers.
The bit image display data is transferred to the display data
RAM by serial or 8-bit parallel interface.
65 x 160 dots graphics or 10-character 4-line by 16 x 16 dots
character with icon are displayed by NJU6655B itself.
The wide operating voltage from 2.4 to 5.5V and low operating
current are suitable for battery-powered applications.
The build-in Electrical Variable Resistance is very precision,
furthermore the rectangle outlook is very applicable to COG or
Slim TCP.
! PACKAGE OUTLINE
NJU6655BCJ
! FEATURES
#
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Direct Correspondence between Display Data RAM and LCD Pixel
Display Data RAM - 10,400 bits
225 LCD Drivers - 64-common and 160-segment + 1-icon common
Direct Microprocessor Interface for both of 68 and 80 type MPU
Serial Interface (SI, SCL, A0, CS1b, CS2)
Programmable Bias selection : 1/5,1/7,1/9 bias
Useful Instruction Set
Display On/Off Cont, Initial Display Line Set, Page Address Set, Column Address Set, Status Read,
Display Data Read/Write, ADC Select, Inverse Display, Entire Display On/Off, Bias Select, Read Modify Write,
End, Reset, Common Direction Register Set, Power control set, Feedback Resistor Ratio Set,
EVR Mode Set, EVR Register Set, Static Indicator On/Off, Static Indicator Register Set, Power Save,
Power Save Reset, n-line Inverse Drive Register Set, n-line Inverse Drive Reset, Partial Select,
Internal Oscillation Circuit ON.
Power Supply Circuits for LCD Incorporated
Voltage Booster Circuits (4-time Maximum),
Voltage Adjust Circuits, Voltage Follower x 4
Voltage Regulator Incorporated (VREF=+3%)
Precision Electrical Variable Resistance (64-step)
Low Power Consumption 130uA(Typ.).
Operating Voltage (All the voltages are based on VDD=0V.)
- Logic Operating Voltage
: -2.4V to -5.5V
- Voltage Booster Operating Voltage
: -2.4V to -6.0V
- LCD Driving Voltage
: -4.5V to -18.0V
Rectangle outlook for COG
Package Outline : Bump-chip
C-MOS Technology (Substrate : N)
Ver.2009-12-02
-1-
NJU6655B
DUMMY19
DUMMY18
DUMMY17
S156
S155
DUMMY1
DUMMY2
TEST1
SYNC
FRS
FR
CL
DOFb
SYNC
VSS
CS1b
CS2
VDD
RESb
A0
VSS
WRb
RDb
VDD
D0
D1
D2
D3
D4
D5
D6(SCL)
D7(SI)
VDD
VDD
VDD
VDD
VDD
VSS
VSS
VSS
VSS2
VSS2
VSS2
VSS2
VSS2
VOUT
VOUT
C3C3+
C1
C1+
C1C1
C2C2+
C2
C2+
VSS
VSS
VRS
VRS
DUMMY3
DUMMY4
VDD
VDD
V1
V1
V2
V2
V3
V3
V4
V4
V5
V5
VR
VDD
M/S
CLS
VSS
C86
P/S
VDD
TEST2
VSS
IRS
VDD
DUMMY5
DUMMY6
Y
X
Chip Center
: X=0um, Y=0um
Chip Size
: X=8.88mm,Y=2.77mm
Chip Thickness
: 675um ± 30um
Bump Size
: 130um x 31um
Bump Pitch
: 50um(Min.)
Bump Height
: 17.5um(Typ.)
Bump Material
: Au
Voltage Boosting Polarity
: Negative Voltage (VDD common)
Substrate
:N
S4
S3
DUMMY16
DUMMY15
DUMMY14
DUMMY13
DUMMY12
DUMMY11
S2
S1
S0
COMM
C0
C30
C31
DUMMY10
DUMMY9
DUMMY8
DUMMY7
-2-
DUMMY20
DUMMY21
DUMMY22
S157
S158
S159
C32
C33
C63
COMM
DUMMY23
DUMMY24
DUMMY25
DUMMY26
! PAD LOCATION
Ver.2009-12-02
NJU6655B
Alignment Mark 1
16um
Alignment Mark Coordinates
(-4225um, -1168um)
( 4186um, -1168um)
( 4186um, 1158um)
(-4225um, 1158um)
66um
16um
66um
Alignment Mark 2
Alignment Mark Coordinates
( 4302um, 1230um)
( -4302um, 1230um)
110um
70um
Alignment Mark 3
Alignment Mark Coordinates
(-4302um, -1250um)
( 4302um, -1250um)
70um
70um
Ver.2009-12-02
-3-
NJU6655B
! PAD COORDINATES
PAD No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
-4-
Terminal
DUMMY1
DUMMY2
TEST1
SYNC
FRS
FR
CL
DOFb
SYNC
VSS
CS1b
CS2
VDD
RESb
A0
VSS
WRb
RDb
VDD
D0
D1
D2
D3
D4
D5
D6(SCL)
D7(SI)
VDD
VDD
VDD
VDD
VDD
VSS
VSS
VSS
VSS2
VSS2
VSS2
VSS2
VSS2
VOUT
VOUT
C3C3C1+
C1+
C1C1C2C2-
X= um
-4092
-4042
-3919
-3796
-3637
-3417
-3197
-2976
-2756
-2598
-2474
-2317
-2194
-2071
-1914
-1790
-1667
-1510
-1387
-1229
-1008
-788
-567
-347
-127
94
314
472
522
572
622
672
722
772
822
872
922
972
1022
1072
1122
1172
1222
1272
1322
1372
1422
1472
1522
1572
Y= um
-1213
-1213
-1213
-1213
-1213
-1213
-1213
-1213
-1213
-1213
-1213
-1213
-1213
-1213
-1213
-1213
-1213
-1213
-1213
-1213
-1213
-1213
-1213
-1213
-1213
-1213
-1213
-1213
-1213
-1213
-1213
-1213
-1213
-1213
-1213
-1213
-1213
-1213
-1213
-1213
-1213
-1213
-1213
-1213
-1213
-1213
-1213
-1213
-1213
-1213
Chip Size 8.88 x 2.77mm(Chip Center X=0um, Y=0um)
PAD No.
Terminal
X= um
Y= um
51
C2+
1622
-1213
52
C2+
1672
-1213
53
VSS
1722
-1213
54
VSS
1772
-1213
55
VRS
1822
-1213
56
VRS
1872
-1213
57
DUMMY3
1922
-1213
58
DUMMY4
1972
-1213
59
VDD
2022
-1213
60
VDD
2072
-1213
61
V1
2122
-1213
62
V1
2172
-1213
63
V2
2222
-1213
64
V2
2272
-1213
65
V3
2322
-1213
66
V3
2372
-1213
67
V4
2422
-1213
68
V4
2472
-1213
69
V5
2522
-1213
70
V5
2572
-1213
71
VR
2622
-1213
72
VDD
2672
-1213
73
M/S
2796
-1213
74
CLS
2953
-1213
75
VSS
3076
-1213
76
C86
3199
-1213
77
P/S
3356
-1213
78
VDD
3480
-1213
79
TEST2
3603
-1213
80
VSS
3726
-1213
81
IRS
3849
-1213
82
VDD
3972
-1213
83
DUMMY5
4022
-1213
84
DUMMY6
4072
-1213
85
DUMMY7
4265
-1037
86
DUMMY8
4265
-987
87
DUMMY9
4265
-937
88
DUMMY10
4265
-887
89
C31
4265
-837
90
C30
4265
-787
91
C29
4265
-737
92
C28
4265
-687
93
C27
4265
-637
94
C26
4265
-587
95
C25
4265
-537
96
C24
4265
-487
97
C23
4265
-437
98
C22
4265
-387
99
C21
4265
-337
100
C20
4265
-287
Ver.2009-12-02
NJU6655B
PAD No.
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
Ver.2009-12-02
Terminal
C19
C18
C17
C16
C15
C14
C13
C12
C11
C10
C9
C8
C7
C6
C5
C4
C3
C2
C1
C0
COMM
S0
S1
S2
DUMMY11
DUMMY12
DUMMY13
DUMMY14
DUMMY15
DUMMY16
S3
S4
S5
S6
S7
S8
S9
S10
S11
S12
S13
S14
S15
S16
S17
S18
S19
S20
S21
S22
X= um
4265
4265
4265
4265
4265
4265
4265
4265
4265
4265
4265
4265
4265
4265
4265
4265
4265
4265
4265
4265
4265
4265
4265
4265
4265
4265
4265
4115
4065
4015
3965
3915
3865
3815
3765
3715
3665
3615
3565
3515
3465
3415
3365
3315
3265
3215
3165
3115
3065
3015
Y= um
-237
-187
-137
-87
-37
13
63
113
163
213
263
313
363
413
463
513
563
613
663
713
763
813
863
913
963
1013
1063
1213
1213
1213
1213
1213
1213
1213
1213
1213
1213
1213
1213
1213
1213
1213
1213
1213
1213
1213
1213
1213
1213
1213
PAD No.
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
Terminal
S23
S24
S25
S26
S27
S28
S29
S30
S31
S32
S33
S34
S35
S36
S37
S38
S39
S40
S41
S42
S43
S44
S45
S46
S47
S48
S49
S50
S51
S52
S53
S54
S55
S56
S57
S58
S59
S60
S61
S62
S63
S64
S65
S66
S67
S68
S69
S70
S71
S72
X= um
2965
2915
2865
2815
2765
2715
2665
2615
2565
2515
2465
2415
2365
2315
2265
2215
2165
2115
2065
2015
1965
1915
1865
1815
1765
1715
1665
1615
1565
1515
1465
1415
1365
1315
1265
1215
1165
1115
1065
1015
965
915
865
815
765
715
665
615
565
515
Y= um
1213
1213
1213
1213
1213
1213
1213
1213
1213
1213
1213
1213
1213
1213
1213
1213
1213
1213
1213
1213
1213
1213
1213
1213
1213
1213
1213
1213
1213
1213
1213
1213
1213
1213
1213
1213
1213
1213
1213
1213
1213
1213
1213
1213
1213
1213
1213
1213
1213
1213
-5-
NJU6655B
PAD No.
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
-6-
Terminal
S73
S74
S75
S76
S77
S78
S79
S80
S81
S82
S83
S84
S85
S86
S87
S88
S89
S90
S91
S92
S93
S94
S95
S96
S97
S98
S99
S100
S101
S102
S103
S104
S105
S106
S107
S108
S109
S110
S111
S112
S113
S114
S115
S116
S117
S118
S119
S120
S121
S122
X= um
465
415
365
315
265
215
165
115
65
15
-35
-85
-135
-185
-235
-285
-335
-385
-435
-485
-535
-585
-635
-685
-735
-785
-835
-885
-935
-985
-1035
-1085
-1135
-1185
-1235
-1285
-1335
-1385
-1435
-1485
-1535
-1585
-1635
-1685
-1735
-1785
-1835
-1885
-1935
-1985
Y= um
1213
1213
1213
1213
1213
1213
1213
1213
1213
1213
1213
1213
1213
1213
1213
1213
1213
1213
1213
1213
1213
1213
1213
1213
1213
1213
1213
1213
1213
1213
1213
1213
1213
1213
1213
1213
1213
1213
1213
1213
1213
1213
1213
1213
1213
1213
1213
1213
1213
1213
PAD No.
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
Terminal
S123
S124
S125
S126
S127
S128
S129
S130
S131
S132
S133
S134
S135
S136
S137
S138
S139
S140
S141
S142
S143
S144
S145
S146
S147
S148
S149
S150
S151
S152
S153
S154
S155
S156
DUMMY17
DUMMY18
DUMMY19
DUMMY20
DUMMY21
DUMMY22
S157
S158
S159
C32
C33
C34
C35
C36
C37
C38
X= um
-2035
-2085
-2135
-2185
-2235
-2285
-2335
-2385
-2435
-2485
-2535
-2585
-2635
-2685
-2735
-2785
-2835
-2885
-2935
-2985
-3035
-3085
-3135
-3185
-3235
-3285
-3335
-3385
-3435
-3485
-3535
-3585
-3635
-3685
-4015
-4065
-4115
-4265
-4265
-4265
-4265
-4265
-4265
-4265
-4265
-4265
-4265
-4265
-4265
-4265
Y= um
1213
1213
1213
1213
1213
1213
1213
1213
1213
1213
1213
1213
1213
1213
1213
1213
1213
1213
1213
1213
1213
1213
1213
1213
1213
1213
1213
1213
1213
1213
1213
1213
1213
1213
1213
1213
1213
1063
1013
963
913
863
813
763
713
663
613
563
513
463
Ver.2009-12-02
NJU6655B
PAD No.
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
Ver.2009-12-02
Terminal
C39
C40
C41
C42
C43
C44
C45
C46
C47
C48
C49
C50
C51
C52
C53
C54
C55
C56
C57
C58
C59
C60
C61
C62
C63
COMM
DUMMY23
DUMMY24
DUMMY25
DUMMY26
X= um
-4265
-4265
-4265
-4265
-4265
-4265
-4265
-4265
-4265
-4265
-4265
-4265
-4265
-4265
-4265
-4265
-4265
-4265
-4265
-4265
-4265
-4265
-4265
-4265
-4265
-4265
-4265
-4265
-4265
-4265
Y= um
413
363
313
263
213
163
113
63
13
-37
-87
-137
-187
-237
-287
-337
-387
-437
-487
-537
-587
-637
-687
-737
-787
-837
-887
-937
-987
-1037
-7-
NJU6655B
! BLOCK DIAGRAM
C31 - - - - C0
S0 - - - - - - - - - - - - - S159
C32 - - - C63
COMM
VSS
5
V1 to V5
Internal
Power
Circuits
VR
VRS
IRS
Voltage
Followers
Shift
Register
Shift
Register
Voltage
Display Data Latch
Voltage
Converter
Common Direction
VSS2
Display Data RAM
160 X 65 = 10,400-bit
Column Address Decoder 160
Page Address Register
M/S
FR
FRS
CL
CLS
SYNC
DOFb
Display
Timing
Column Address Counter 8bit
I/O Buffer
Initial Display Line
C3-
Line Counter
C2+/C2-
Line Address Decoder
-
Low Address Decoder
C1 /C1
Common
Timing
Regulator
VOUT
+
Common
Drivers
Segment
Drivers
Common
Drivers
COMM
VDD
Column Address Register 8bit
Oscillator
Multiplexer
Instruction
Decoder
Status
Bus Holder
Busy Flag
Internal Bus Line
Reset
RESb
-8-
MPU Interface
CS1b
CS2
A0
RDb
WRb
C86
D7
(SI)
D6
(SCL)
P/S
D0 to D5
Ver.2009-12-02
NJU6655B
! TERMINAL DISCRIPTION
No.
SYMBOL
I/O
FUNCTION
1,2,57,58, DUMMY1
Dummy terminals.
83 to 88,
to
These are open terminals electrically.
125 to 130, DUMMY26
285 to 290,
327 to 330
13,19,
Power Power supply terminal.
VDD
28 to 32
59,60,72,
78,82
10,16,
VSS
GND Ground terminal.
33 to 35
53,54,75,
80
36 to 40
VSS2
Power Reference voltage for voltage booster.
55,56
VRS
Power External reference voltage input terminal.
Normally open.
V1
Power LCD driving voltage supplying terminal.
61,62
63,64
V2
When the internal voltage booster is not used, supply each level of LCD driving
65,66
voltage from outside with following relation.
V3
67,68
V4
VDD≥V1≥V2≥V3≥V4≥V5≥VOUT
69,70
V5
When the internal power supply is on, the internal circuits generate and supply
following LCD bias voltage from V1 to V4 terminal.
Bias
V1
V2
V3
V4
1/5 Bias
V5+4/5VLCD
V5+3/5VLCD
V5+2/5VLCD V5+1/5VLCD
1/7 Bias
V5+6/7VLCD
V5+5/7VLCD
V5+2/7VLCD V5+1/7VLCD
1/9 Bias
V5+8/9VLCD
V5+7/9VLCD
V5+2/9VLCD V5+1/9VLCD
(VLCD=VDD-V5)
C1+
O
Boosted capacitor connecting terminals used for voltage booster.
45,46
C147,48
51,52
C2+
C249,50
43,44
C341,42
VOUT
O
Voltage booster output terminal.
Connect the boosted capacitor between this terminal and VSS2.
71
VR
I
Voltage adjustment terminal
Connect external feedback resistor to control the LCD driving voltage V5. This
terminal is effective when IRS=”L”.
20 to 27
D0 to D7
I/O
Data input/output terminals.
(26, 27)
(SCL, SI)
P/S="H" : Tri-state bi-directional Data I/O terminal in 8-bit parallel operation.
P/S="L" : D7=Serial data input terminal. D6=Serial data clock signal input terminal.
D0 to D5 terminals are Hi-impedance.
Data from SI is loaded at the rising edge of SCL and latched as the parallel data at
8th rising edge of SCL. When CS1b="H", D0 to D7 terminals are Hi-impedance.
15
A0
I
Data discrimination signal input terminal.
Connect to the Address bus of MPU. The data on the D0 to D7 is distinguished between
Display data and Instruction by status of A0.
A0
H
L
Distinction
Display Data
Instruction
14
Ver.2009-12-02
RESb
I
Reset terminal.
When the RESb terminal goes to “L”, the initialization is performed.
Reset operation is executing during “L” state of RESb.
-9-
NJU6655B
No.
SYMBOL
CS1b
CS2
RDb
(E)
I/O
I
17
WRb
(R/W)
I
76
C86
I
MPU interface type selection terminal.
This terminal must connect to VDD or VSS.
C86
H
L
State
68 Type
80 Type
77
P/S
I
Serial or parallel interface selection terminal.
11
12
18
I
FUNCTION
Chip select terminal.
Data Input/Output are available during CS1b=”L” and CS2=”H”.
<In case of 80 Type MPU>
RDb signal of 80 type MPU input terminal. Active "L"
During this signal is "L" , D0 to D7 terminals are output.
<In case of 68 Type MPU>
Enable signal of 68 type MPU input terminal. Active "H"
<In case of 80 Type MPU>
Connect to the 80 type MPU WRb signal. Active "L".
The data on the data bus input synchronizing the rise edge of this signal.
<In case of 68 Type MPU>
The read/write control signal of 68 type MPU input terminal.
R/W
H
L
State
Read
Write
P/S
74
CLS
I
73
M/S
I
7
CL
I/O
- 10 -
Chip Select
Data/Instruction
Data
Read/Write
Serial
Clock
SCL(D6)
“H”
CS1b,CS2
A0
D0toD7 RDb,WRb
A0
SI(D7)
“L”
CS1b,CS2
In case of the serial interface (P/S="L")
RAM data and status read operation do not work in mode of the serial interface.
RDb and WRb must be fixed "H" or "L", and D0 to D5 are high impedance.
Terminal to select whether or enable or disable the display clock internal oscillator
circuit.
CLS=”H” : Internal oscillator circuit is enable
CLS=”L” : Internal oscillator circuit is disabled (requires external input)
When CLS=”L”, input the display clock through the CL terminal.
This terminal selects the master/slave operation for the NJU6655.
Master operation outputs the timing signals that are required for the LCD display, while
slave operation inputs the timing signals required for the LCD, synchronizing the LCD
system.
M/S = ”H” : Master operation
M/S = ”L” : Slave operation
The following is true depending on the M/S and CLS status:
Power
CL
FR
FRS
DOFb
M/S CLS
OSC.
Supply
Circuit
“H” Available Available Output Output Output Output
“H”
“L” Not Avail. Available Input Output Output Output
“L”
*
Not Avail. Not Avail. Input
Input Output Input
*:Don’t Care
Display clock input/output terminal.
The following is true depending on the M/S and CLS status.
M/S
CLS
CL
“H”
Output
“H”
“L”
Input
“L”
*
Input
*:Don’t Care
Ver.2009-12-02
NJU6655B
No.
SYMBOL
FR
I/O
I/O
4,9
SYNC
I/O
8
DOFb
I/O
81
IRS
I
5
FRS
O
C31 to C0
O
6
89 to 120
FUNCTION
LCD alternating current signal I/O terminal.
M/S=”H” : Output
M/S=”L” : Input
LCD synchronizing current signal I/O terminal.
M/S=”H” : Output
M/S=”L” : Input
LCD Display blanking control terminal.
M/S=”H” : Output terminal. Display “On” = “H”, Display “Off” = “L”
M/S=”L” : Input terminal. External control. Refer to the following table.
DOFb
Instruction
H
L
Display On
On
Off
Display Off
Off
Off
Internal Feedback Resistor Select
IRS=“H” : Internal feedback
IRS=“L” : External feedback resistor
This setting is effective in the master operation. It is ineffective in the slave operation
but should be fixed to “H” or “L”.
The output terminal for the static drive.
This terminal is used in conjunction with the SYNC terminal.
LCD driving signal output terminals.
-Common output terminals : C0 to C63
-Segment output terminals : S0 to S159
Common output terminals
The following output voltages are selected by the combination of alternating (FR)
signal and Common scanning data.
122 to 124, S0 to S159
131 to 284,
291 to 293
O
Scan Data
H
L
294 to 325
C32 to C63
O
H
L
COMM
O
3
TEST1
O
79
TEST2
I
Ver.2009-12-02
Output Voltage
H
L
H
L
V5
VDD
V1
V4
Segment output terminals
The following output voltages are selected by the combination of alternating (FR)
signal and display data in the RAM.
RAM Data
121,326
FR
FR
H
L
H
L
Output Voltage
Normal
Reverse
VDD
V2
V5
V3
V2
VDD
V5
V3
COM output terminals for the indicator.
Both terminals output the same signal. Leave these open if they are not used.
Maker test only.
Normally open.
Maker test only.
This terminal must connect to VSS.
- 11 -
NJU6655B
! FUNCTIONAL DESCRIPTION
(1) Description for each blocks
(1-1) Busy Flag (BF)
During internal operation, the LSI is being busy and can’t accept any instructions except “status read”. The BF
data is output through D7 terminal by the “status read” instruction.
When the cycle time (tcyc) mentioned in the “AC characteristics” is satisfied, the BF check isn’t required after
each instruction, so that MPU processing performance can be improved.
(1-2) Initial display line register
The initial display line register assigns a DDRAM line address, which corresponds to COM0 by “initial display
line set” instruction. It is used for not only normal display but also vertical display scrolling and page switching
without changing the contents of the DDRAM.
However, the 65th address for icon display can’t be assigned for initial display line address.
(1-3) Line counter
The line counter provides a DDRAM line address. It initializes its contents at the switching of frame timing signal
(FR), and also counts-up in synchronization with common timing signal.
(1-4) Column address counter
The column address counter is an 8-bit preset counter, which provides a DDRAM column address, and it is
independent of below-mentioned page address register.
It will increment (+1) the column address whenever “display data read” or “display data write” instructions are
issued. However, the counter will be locked when no-existing address above A0H are addressed. The count-lock will
be able to be released by the “column address set” instruction again. The counter can invert the correspondence
between the column address and segment driver direction by means of “ADC set” instruction.
(1-5) Page address register
The page address register provides a DDRAM page address.
The last page address “8” should be used for icon display because the only D0 is valid.
(1-6) Display data RAM (DDRAM)
The DDRAM contains 10,400-bit, and stores display data, which are 1-to-1 correspondents to LCD panel pixels.
When normal display mode, the display data “1” turns on and “0” turns off LCD pixels. When inverse display
mode, “1” turns off and “0” turns on.
- 12 -
Ver.2009-12-02
NJU6655B
Page Address
Line
Address
Display Pattern
Data
00H
01
02
03
04
05
06
07
08
09
0A
0B
0C
0D
0E
0F
10
11
12
13
14
15
16
17
18
19
1A
D0
D1
D2
D3,D2,D1,D0
(0,0,0,0)
D3
PAGE 0
D4
D5
D6
D7
D0
D1
D2
D3,D2,D1,D0
(0,0,0,1)
D3
PAGE 1
D4
D5
D6
D7
D0
D1
D2
D3,D2,D1,D0
(0,0,1,0)
D3
PAGE 2
D4
D5
D6
D7
D0
D1
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
36
37
38
39
3A
3B
3C
3D
3E
3F
D6
D7
D0
D1
D3,D2,D1,D0
(0,1,1,1)
D2
PAGE 7
D3
D4
D6
D7
(1,0,0,0)
Column
Address
ADC
PAGE 8
D0
D0="0" 00 01 02 03 04 05 06
D0="1" 9F 9E 9D 9C 9B 9A 99
Segment Drivers
0
1
2
3
4
5
6
C57
C58
C59
C60
C61
C62
C63
C0
C1
C2
C3
C4
C5
C6
C7
C8
C9
C10
C11
C12
C13
C14
C15
C16
C17
C18
:
:
:
:
C46
C47
C48
C49
C50
C51
C52
C53
C54
C55
COMM*
9E
01
----------------
Common
Driver
C56
9F
00
158 159
For example the Initial
display is 08H.
Fig.1 Display data RAM (DDRAM) Map
* : COMM is independent of the “Initial display line set” instruction and always corresponds to the 65th line.
Ver.2009-12-02
- 13 -
NJU6655B
(1-7) Common direction register
The common direction register is selected by the "Partial Select" and "Common Direction
instructions as shown in Table 1. When using the partial display function, the COM0 - COM15
COM63 terminals cannot be used.
Table 1. Common direction
Common drivers
Partial
Common
Select
Direction
Register Set
D3
PAD No. 114
83
309
D0
Pin name C0
C31
C63
0
0
COM0
COM31
COM63
0
1
COM63
COM32
COM0
PAD No. 98
83
293
Pin name C16
C31
C47
1
0
COM16
COM31
COM47
1
1
COM47
COM32
COM16
Register Set"
and COM48 -
278
C32
COM32
COM31
278
C32
COM32
COM31
(1-8) Reset circuit
The reset circuit initializes the LSI to the following status by using of the reset signal into the RESb terminal.
-Reset status using the RESb terminal:
1. Display off
2. Normal display (Non-inverse display)
3. ADC select : Normal mode (D0="0")
4. Power control register clear : D2,D1,D0=”0,0,0”
5. Serial interface register clear
6. LCD bias select : D1,D0=”0,0”(1/9 bias)
7. Power save reset
8. Entire display off
: Normal mode
9. Internal oscillation circuit stop
10.Partial select : D0=”0”(1/65 duty)
11.Static indicator off
Static indicator register : D1,D2=”0,0”
12.Read modify write off
13.Initial display line address : 00H
14.Column address
: 00H
15.Page address
: 0 page
16.Common direction register : D3=”0”(Normal)
17.Feedback resistors ratio : D2,D1,D0=”0,0,0”
18.EVR mode off and EVR register: D5,D4,D3,D2,D1,D0=”1,0,0,0,0,0”
19.n-line inverse drive register : D3,D2,D1,D0=”0,0,0,0”(n-line inverse reset)
20.Test mode reset (Test mode 1 and Test mode 2)
The RES terminal should be connected to MPU’s reset terminal, and the reset operation should be executed at the
same timing of the MPU reset. As described in the “BUS TIMING CHARACTERISTICS”, it is necessary to input
1.5us(min.) or over “L” level signal into the RES terminal in order to carry out the reset operation. The LSI will
return to normal operation after about 1.5us(max.) from the rising edge of the reset signal.
The reset operation by RESb="L" initializes each register setting as above reset status, but the internal oscillation
circuit and output terminals (D0 to D7) are not affected.
The reset operation is necessary to avoid malfunctions.
Note 1) The “Reset” instruction in Table.4 can’t be substituted for the reset operation by using of the RES terminal. It
executes above-mentioned only 11 to 20 items.
Note 2) The reset terminal is susceptible to external noise, so design PCB layout in consideration for the noise.
Note 3) In case of using external power supply for LCD driving voltage, the RESb terminal is required to be being “L”
level when the external power supply is turned-on.
- 14 -
Ver.2009-12-02
NJU6655B
(1-9) LCD driving circuits
(a) Common and segment drivers
LCD drivers consist of 64-common drivers, 160-segment divers and 1-icon-common driver.
As shown in “■ LCD driving waveform”, LCD driving waveforms are generated by the combination of display data,
common timing signal and internal FR timing signal.
(b) Display data latch circuit
The display data latch circuit temporally stores 160-bit display data transferred from the DDRAM in the synchronization
with the common timing signal, and then it transfers these stored data to the segment drivers.
“Display on/off”, “inverse display on/off” and “entire display on/off” instructions control only the contents of this latch
circuit, they can’t change the contents of the DDRAM.
In addition, the LCD display isn’t affected by the DDRAM accuses during its displaying because the data read-out
timing from this latch circuit to the segment drivers is independent of accessing timing to the DDRAM.
(c) Line counter and latch signal or latch Circuits
The clock line counter and latch signal to the latch circuits are generated from the internal display clock (CL). The line
address of display data RAM is renewed synchronizing with display clock (CL).
160bits display data are latched in display latch circuits synchronizing with display clock, and then output to the LCD
driving circuits. The display data transfer to the LCD driving circuits is executed independently with RAM access by the
MPU.
(d) Display timing generator
The display timing generates the timing signal for the display system by combination of the master clock CL and driving
signal FR ( refer to Fig.2 ) The frame signal FR and LCD alternative signal generate LCD driving waveform on the
2-frame alternative driving method or the n-line inverse driving method.
Ver.2009-12-02
- 15 -
NJU6655B
(e) Common timing generation
The common timing is generated by display clock CL (refer to Fig.2)
64
65
1
2
3
4
5
6
7
8
62
63
64
65
1
2
3
4
5
CL
FR
VDD
V1
C0
V4
V5
VDD
V1
C1
V4
V5
RAM DATA
VDD
V2
Sn
V3
V5
Fig.2-1 2-frame alternating drive mode
64
65
1
2
3
4
5
6
7
8
62
63
64
65
1
2
3
4
5
CL
FR
VDD
V1
C0
V4
V5
VDD
V1
C1
V4
V5
RAM DATA
VDD
V2
Sn
V3
V5
Fig.2-2 n-line inverse drive mode (n=7, line inverting register sets to 6)
- 16 -
Ver.2009-12-02
NJU6655B
(f) Oscillator
This is the low power consumption CR oscillator which provides the display clock and voltage converter timing clock.
(g) Internal power circuits
The internal power circuits are composed of x4 boost voltage converter, output voltage regulator including 64-step EVR
and voltage followers.
The optimum values of the external passive components for the internal power circuits, such as capacitors for V1 to V5
terminals and feed back resistors for VR terminal, depend on LCD panel size. Therefore, it is necessary to evaluate the
actual LCD module with these external components in order to determine the optimum values.
Each portion of the internal power circuits is controlled by “power control set” instruction as shown in Table.2. In
addition, the combination of power supply circuits is described in Table.3.
Table.2 Power control set
Status
Portions
D2
D1
D0
“1”
ON
ON
ON
Voltage converter
Voltage regulator
Voltage followers
“0”
OFF
OFF
OFF
Table.3 Power supply combinations
Status
D2
D1
D0
Voltage
converter
Voltage
regulator
Voltage
followers
External
voltage
1) Using all internal power circuits
2) Using voltage regulator and Voltage
1
1
1
ON
ON
ON
VSS2
Capacitor
terminals
Use
0
1
1
OFF
ON
ON
VOUT,VSS2
Open
3) Using voltage followers
0
0
1
OFF
4) Using only external power supply
0
0
0
OFF
* Capacitor input terminals: C1+, C1-, C2+, C2-, C3* Do not use other combinations except examples in Table.3.
OFF
OFF
ON
OFF
VOUT,V5,VSS2
VOUT,V1~V5
Open
Open
followers
The internal LCD power supply is designed to drive small LCD panels such as cellular phones. Thus, if the IC is used to
drive a large panel, make sure whether it works with the internal power supply or needs an external power supply.
The selections of external components for the LCD bias circuit, the voltage booster and the feedback loop depend on
panel sizes, so make sure what are the best values in the particular application.
Ver.2009-12-02
- 17 -
NJU6655B
○Power Supply applications
Power Control Instruction
D2 : Boost Circuit
D1 : Voltage Regulator
D0 : Voltage Follower
(1) Internal power supply Example.
All of the Internal Booster, Voltage Regulator,
Voltage Follower using
(D2,D1,D0) = (1,1,1)
(2) Only VOUT Supply from outside Example.
Internal Voltage Regulator,
Voltage Follower using.
(D2,D1,D0) = (0,1,1)
VDD
+
+
+
+
+
+
VDD
C1-
V1
C1+
V2
V4
V5
C2
+
C2
-
VOUT
+
+
+
+
+
+
+
+
V1
V2
V3
V4
V5
VOUT
VR
V5
(3) VOUT and V5 Supply from outside Example.
Internal Voltage Follower using.
(D2,D1,D0) = (0,0,1)
+
+
C3-
V3
VSS2
VDD
+
VSS2
VDD
VR
V5
(4) External Power Supply Example.
All of V1 to V5 and VOUT supply from outside
(D2,D1,D0) = (0,0,0)
VDD
VDD
V1
V1
V2
V2
V3
V3
V4
V4
V5
V5
VOUT
VOUT
VSS2
VSS2
: These switches should be open during the power save mode.
Note) : When using the voltage follower circuit, external resistors may be necessary to stabilize V1,V2,V3 and V4
voltages.
- 18 -
Ver.2009-12-02
NJU6655B
(2) Instruction set
The NJU6655B distinguishes the signal on the data bus D0 to D7 as an Instruction by combination of A0 , RDb and
WRb(R/W). The decode of the instruction and execution performs with only high speed Internal timing without
relation to the external clock. Therefore no busy flag check required normally. In case of serial interface, the data
input as MSB(D7) first serially. The Table. 4-1,4-2 shows the instruction codes of the NJU6655B.
Table. 4-1
Instruction
Instruction table
(*: Don’t Care)
Instruction code
A0
RDb WRb
D7
D6
D5
D4
D3
D2
D1
D0
1
0
1
1
1
0/1
Description
(a)
Display On/Off
0
1
0
1
0
(b)
Initial Display Line Set
0
1
0
0
1
(c)
Page Address Set
0
1
0
1
0
1
1
Page Address
Set the page of DD RAM to the Page
Address Register
(d)
Column Address Set
Upper Order 4bits
0
1
0
0
0
0
1
Upper Order
Column Address
Set the Upper order 4 bits Column
Address to the Register
Column Address Set
Lower Order 4bits
0
1
0
0
0
0
0
Lower Order
Column Address
Set the Lower order 4 bits Column
Address to the Register
(e)
Status Read
0
0
1
(f)
Write Display Data
1
1
0
Write Data
Write the data into the Display Data
RAM
(g)
Read Display Data
1
0
1
Read Data
Read the data from the Display Data
RAM
(h)
ADC Select
0
1
0
1
0
1
0
0
0
0
0/1
Set the DD RAM vs Segment
D0=0 :Normal D0= 1:Inverse
(i)
Normal or Inverse of
On/Off Set
0
1
0
1
0
1
0
0
1
1
0/1
0
1
0
1
0
1
0
0
1
0
0/1
Inverse the On and Off Display
D0=0 :Normal D0= 1:Inverse
Whole Display Turns On
D0=0: Normal D0=1: Whole Disp. On
(j)
Whole Display On/Off
Line Address
Status
0
0
LCD Display On/Off
D0=0:Off D0=1:On
Determine the Display Line of RAM to
COM0
0
0
(k)
LCD Bias Select
0
1
0
1
0
0
1
0
0
(l)
Read Modify Write
0
1
0
1
1
1
0
0
0
0
0
Increment the Column Address Register
when writing but no-change when
reading
(m)
End
0
1
0
1
1
1
0
1
1
1
0
Release from the Read Modify write
Mode
(n)
Reset
0
1
0
1
1
1
0
0
0
1
0
Initialize the Internal Circuits
(o)
Common Direction Select
0
1
0
1
1
0
0
0/1
*
*
*
Set the scanning order of common
drivers to the Register
D3=0 : Normal, D3=1 : Inverse
(p)
Power Control Set
0
1
0
0
0
1
0
1
Operating Mode
(q)
Feedback Resistor Ratio Set
0
1
0
0
0
1
0
0
Resistor Ratio
Ver.2009-12-02
Bias
Read out the internal Status
Select the Bias
Set the status of internal power circuits
Set the status of internal resistors ratio
(Rb/Ra)
- 19 -
NJU6655B
Table. 4-2
Instruction
(r)
(s)
(t)
Instruction table
(*: Don’t Care)
Instruction code
A0
RDb WRb
D7
D6
D5
D4
0
0
EVR Mode Set
0
1
0
1
0
EVR Register Set
0
1
0
*
*
D3
D2
D1
D0
0
0
0
1
Setting Data
Set EVR mode
Set the V5 output level to the EVR
register
Static Indicator On/Off
0
1
0
1
0
1
0
1
1
Static Indicator Register Set
0
1
0
*
*
*
*
*
*
0
0/1
Pawer Save
0
1
0
1
0
1
0
1
0
0
0/1
0
0
0
1
Mode
(u)
Pawer Save Reset
0
1
0
1
1
1
0
(v)
n-line Inverse Drive Register
Set
0
1
0
0
0
1
1
(w)
n-line Inverse Drive Reset
0
1
0
1
1
1
0
0
1
0
0
(x)
Partial Select
0
1
0
1
0
1
0
0
0
1
0/1
(y)
Internal Oscillation Circuit
On
0
1
0
1
0
1
0
1
0
1
1
(z)
NOP
0
1
0
1
1
1
0
0
0
1
1
- 20 -
Description
Number of Inverse
Lines
D0=0 : Off, D0=1 : On
Set static indicator register
D0=0 : Standby mode
D0=1 : Sleep mode
Release from the Pawer Save Mode
Set the number of inverse drive line
Release the line inverse drive
D0=0 : Off (1/65 Duty)
D0=1 : On (1/33 Duty)
Start the operation of the Internal
Oscillation circuit
Ver.2009-12-02
NJU6655B
(2-1) Explanation of Instruction Code
(a) Display On/Off
This instruction selects display turn-on or turn-off regardless of the contents of the DDRAM.
A0
0
D
RDb WRb
1
0
D7
1
D6
0
D5
1
D4
0
D3
1
D2
1
D1
1
D0
D
0: Display Off
1: Display On
(b) Initial Display Line Set
This instruction specifies the DDRAM line address which corresponds to the COM0 position.
By means of repeating this instruction, the initial display line address will be dynamically changed; it means smooth
display scrolling will be enabled.
A0
0
RDb WRb
1
0
A5
0
0
:
:
1
A4
0
0
:
:
1
D7
0
A3
0
0
:
:
1
D6
1
A2
0
0
:
:
1
D5
A5
A1
0
0
:
:
1
D4
A4
D3
A3
A0
0
1
:
:
1
D2
A2
D1
A1
D0
A0
Line Address (HEX)
00
01
:
:
3F
(c) Page Address Set
In order to access to the DDRAM for writing or reading display data, both “page address set” and “column address set”
instructions are required before accessing.
The last page address “8” should be used for icon display because the only D0 is valid.
A0
0
RDb WRb
1
0
A3
0
0
:
:
1
Ver.2009-12-02
A2
0
0
:
:
0
D7
1
D6
0
A1
0
0
:
:
0
D5
1
D4
1
A0
0
1
:
:
0
D3
A3
D2
A2
D1
A1
D0
A0
Page
0
1
:
:
8
- 21 -
NJU6655B
(d) Column Address Set
As above-mentioned, in order to access to the DDRAM for writing or reading display data, it is necessary to execute
both “page address set” and “column address set” before accessing. The 8-bit column address data will be valid when
both upper 4-bit and lower 4-bit data are set into the column address register.
Once the column address is set, it will automatically increment (+1) whenever the DDRAM will be accessed, so that the
DDRAM will be able to be continuously accessed without “column address set” instruction.
The column address will stop increment and the page address will not be changed when the last address 9FH is
addressed.
A0
0
RDb WRb
1
0
D7
0
D6
0
D5
0
D4
1
D3
A7
D2
A6
D1
A5
D0
A4
Upper 4-bit
A2
A1
A0
Lower 4-bit
0
1
0
0
0
0
0
A3
A7
0
0
:
:
1
A6
0
0
:
:
0
A5
0
0
:
:
0
A4
0
0
:
:
1
A3
0
0
:
:
1
A2
0
0
:
:
1
A1
0
0
:
:
1
A0
0
1
:
:
1
Column Address (HEX)
00
01
:
:
9F
(e) Status Read
This instruction reads out the internal status regarding “busy flag”, “ADC select”, “display on/off” and “reset”.
A0
0
RDb WRb D7
D6
0
1 BUSY ADC
D5
D4
ON/OFF RESET
D3
0
D2
0
D1
0
D0
0
BUSY
: When D7 is “1”, the LSI is being busy and can’t accept any instructions.
ADC
: It shows the correspondence between the column address and segment drivers.
When D6 is “0”, the column address (159-n) corresponds to segment driver n.
When D6 is “1”, the column address (n)
corresponds to segment driver n.
Please be careful that read out data is opposite of “ADC select” instruction data.
ON/OFF
: It shows display on or off status.
When D5 is “0”, the LSI is in display-on status.
When D5 is “1”, the LSI is in display-off status.
Please be careful that read out data is opposite of “Display On/Off” instruction data.
RESET
: It shows reset status.
When D4 is “0”, the LSI is in normal operation.
When D4 is “1”, the LSI is during reset operation.
(f) Display Data Write
This instruction writes display data into the selected column address on the DDRAM.
The column address automatically increments (+1) whenever the display data is written by this instruction, so that this
instruction can be continuously issued without “column address set” instruction.
A0
1
- 22 -
RDb WRb
1
0
D7
D6
D5
D4
D3
Write Data
D2
D1
D0
Ver.2009-12-02
NJU6655B
(g) Display Data Read
This instruction reads out the display data stored in the selected column address on the DDRAM.
The column address automatically increments (+1) whenever the display data is read out by this instruction, so that this
instruction can be continuously issued without “column address set” instruction.
After the ”column address set” instruction, a dummy read will be required, please refer to the (4-4).
In case of using serial interface mode, this instruction can’t be used.
A0
1
RDb WRb
0
1
D7
D6
D5
D4
D3
Read Data
D2
D1
D0
(h) ADC Select
This instruction selects segment driver direction.
The correspondence between the column address and segment driver direction is shown in Fig.1.
This function reduces the restrictions on the IC position of an LCD module.
A0
0
RDb WRb
1
0
D7
1
D6
0
D5
1
D4
0
D3
0
D2
0
D1
0
D0
D
0: Clockwise Output (Normal)
Segment Driver S0 to S159
1: Counterclockwise Output (Inverse) Segment Driver S159 to S0
D
(i) Inverse Display On/Off
This instruction inverses the status of turn-on or turn-off of entire LCD pixels. It doesn’t change the contents of the
DDRAM.
A0
0
D
RDb WRb
1
0
0: Normal
1: Inverse
D7
1
D6
0
D5
1
D4
0
D3
0
D2
1
D1
1
D0
D
RAM data "1" correspond to "On"
RAM data "0" correspond to "On"
(j) Whole Display On/Off
This instruction turns on entire LCD pixels regardless the contents of the DDRAM. It doesn’t change the contents of
DDRAM.
This instruction should be performed prior to the "Inverse display On/Off" instruction.
A0
0
RDb WRb
1
0
D7
1
D6
0
D
0: Normal Display
1: Whole Display Turns On
(k) Bias Select
D5
1
D4
0
D3
0
D2
1
D1
0
D0
D
D2
0
D1
A1
D0
A0
(Whole Display Off)
(Whole Display On)
This instruction selects LCD bias value.
A0
0
RDb WRb
1
0
D7
1
D6
0
D5
0
D4
1
D3
0
A1
A0
LCD Bias
1/9
0
0
1/7
1
0
1/5
0
1
Prohibited*
1
1
* : Because it may malfunction-operate, do not set (D1,D0) = (1,1).
Ver.2009-12-02
- 23 -
NJU6655B
(l) Read Modify Write
This instruction controls column address increment.
By using of this instruction, the column address can’t increment when read operation but it can increment when write
operation. This status will be continued until the below-mentioned “end” instruction will be issued.
This instruction can reduce the load of MPU, during the display data in specific DDRAM area is repeatedly changed for
cursor blink or others.
A0
0
RDb WRb
1
0
D7
1
D6
1
D5
1
D4
0
D3
0
D2
0
D1
0
D0
0
Note) In this "Read Modify Write" mode, out of display data "Read" / "Write", any instructions except "Column Address
Set" can be executed.
- The Sequence of Cursor Blink Display
Page Address Set
Set to the Start Address of Cursor
Display
Column Address Set
Read Modify Write
Dummy Read
Start the Read Modify Write
The data is ignored
Column Counter doesn’t increase
Data Read
Data inverse by MPU
Data Write
Column Counter increase
Dummy Read
Column Counter doesn’t increase
Data Read
Column Counter doesn’t increase
Data Write
Column Counter increase
Dummy Read
Column Counter doesn’t increase
Data Read
Column Counter doesn’t increase
Data Write
Column Counter increase
Repeating
End
No
End the Read Modify Write
Finish?
Yes
- 24 -
Ver.2009-12-02
NJU6655B
(m) End
The “end” instruction cancels the read modify write mode and makes the column address return to the initial value just
before “read modify write” is started.
A0
0
RDb WRb
1
0
D7
1
D6
1
D5
1
D4
0
D3
1
D2
1
D1
1
D0
0
Return
Column
Address
N
N+1
N+2
N+3
----
N+m
Read modify write
N
End
(n) Reset
This instruction reset the LSI to the following status, however it doesn’t change the contents of the DDRAM. Please be
careful that it can’t be substituted for the reset operation by using of the RESb terminal.
Reset status by “reset” instruction:
1: Static indicator register
: D1,D0 = “0,0”
2: Read modify write off
3: Initial display line address
: 00H
4: Column address
: 00H
5: Page address
: 0 page
6: Common direction register
: D3=”0”(Normal mode)
7: Feedback resistors ratio
: D2,D1,D0 = “0,0,0”
8: EVR mode off and EVR register
: D5,D4,D3,D2,D1,D0 = “1,0,0,0,0,0”
9: n-line inverse drive register
: D3,D2,D1,D0 = “0,0,0,0”
10: Test mode reset (Test mode 1 and Test mode 2)
The DD RAM is not affected of this initialization.
A0
0
RDb WRb
1
0
D7
1
D6
1
D5
1
D4
0
D3
0
D2
0
D1
1
D0
0
D3
D3
D2
*
D1
*
D0
*
(o) Common Driver Direction Select
This instruction selects common driver direction.
Please refer to (1-7) common driver direction for more detail.
A0
0
D3
Ver.2009-12-02
RDb WRb
1
0
0: Normal
1: Inverse
D7
1
D6
1
D5
0
D4
0
(*: Don’t Care)
Common driver direction (C0 to C63) or (C16 to C47)
Common driver direction (C63 to C0) or (C47 to C16)
- 25 -
NJU6655B
(p) Power Control Set
This instruction controls the status of internal power circuits. Please refer to the (1-9) LCD Driving Circuits (g) internal
power circuits for more detail.
A0
0
RDb WRb
1
0
D7
0
D6
0
D5
1
D4
0
D3
1
D2
A2
D1
A1
D0
A0
0: Voltage Converter Off
1: Voltage Converter On
0: Voltage Regulator Off
1: Voltage Regulator On
0: Voltage Followers Off
1: Voltage Followers On
A2
A1
A0
Note) The internal power supply must be Off when external power supply using.
* The wait time depends on the C4 to C8, COUT capacitors, and VDD and VLCD Voltage.
Therefore it requires the actual evaluation using the LCD module to get the correct time.
(q) Feedback Resistor Ratio Set
This instruction is used to determine the internal feedback resistor ratio.
Please refer to the (3-2) Voltage Adjust Circuits for more detail.
A0
0
- 26 -
RDb WRb
1
0
D7
0
D6
0
A2
A1
A1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
D5
1
D4
0
D3
0
D2
A2
Internal resistor ratio
1+(Rb/Ra)
4.5
5.0
5.5
6.0
6.5
7.0
7.6
8.1
D1
A1
D0
A0
VLCD
1+(Rb/Ra)
Minimum
:
:
:
:
:
:
Maximum
Ver.2009-12-02
NJU6655B
(r) EVR Set
1) EVR mode set
This instruction sets the LSI into the EVR mode, and it is always used by the combination with “EVR register set”. The
LSI can’t accept any instructions except the “EVR register set” during the EVR set mode. This mode will be released
after the “EVR register set” instruction.
A0
0
RDb WRb
1
0
D7
1
D6
0
D5
0
D4
0
D3
0
D2
0
D1
0
D0
1
2) EVR Register Set
This instruction sets 6-bit data into the EVR register to determine the output voltage “V5” of the internal voltage
regulator.
A0
0
RDb WRb
1
0
A5
0
0
:
:
1
A4
0
0
:
:
1
D7
*
A3
0
0
:
:
1
D6
*
A2
0
0
:
:
1
D5
A5
A1
0
0
:
:
1
D4
A4
D3
A3
A0
0
1
:
:
1
D2
A2
D1
A1
D0
A0
(*: Don’t Care)
VLCD
Minimum
:
:
:
Maximum
(s) Static Indicator
1) Static Indicator On/Off
This instruction selects static indicator turn-on or turn-off, and it is always used by the combination with the “ static
indicator register set”.
A0
0
D
RDb WRb
1
0
D7
1
D6
0
D5
1
D4
0
D3
1
D2
1
D1
0
D0
D
D6
*
D5
*
D4
*
D3
*
D2
*
D1
A1
D0
A0
0: Static Indicator Off
1: Static Indicator On
2) Static Indicator Register Set
A0
0
RDb WRb
1
0
A1
0
0
1
1
Ver.2009-12-02
D7
*
A0
0
1
0
1
(*: Don’t Care)
Indicator display Status
Off
On (Blink at 1.0s intervals)
On (Blink at 0.5s intervals)
On (Turn on at all time)
- 27 -
NJU6655B
(t) Power Save
This instruction sets the LSI into the power save mode. This instruction is reducing operating current as well as static
operations.
The internal status and the contents of the DDRAM will be remained just before the “Power save” instruction. In
addition, the DDRAM can be accessed during the power save mode.
There are two power save modes, sleep mode and standby mode.
A0
0
D
RDb WRb
1
0
D7
1
D6
0
D5
1
D4
0
D3
1
D2
0
D1
0
D0
D
0: Standby Mode
1: Sleep Mode
<Sleep Mode>
All functions are halted so that its operating current is reduced as low as standby current.
All LCD system stops as follows,
1) Oscillator and internal power circuits stop.
2) All common and segment drivers output VDD level.
<Standby Mode>
A part of functions are halted. The only static drive system as the indicator operates.
The LCD system except the static indicator stops as follows,
1) Internal power circuits stop. (Oscillator is operating.)
2) LCD driving is stopped. All common and segment drivers output VDD level.
3) The only static indicator is working.
(u) Pawer Save Reset
This instruction releases the power save mode.
A0
0
- 28 -
RDb WRb
1
0
D7
1
D6
1
D5
1
D4
0
D3
0
D2
0
D1
0
D0
1
Ver.2009-12-02
NJU6655B
(v) n-line Inverse Drive Register Set
This instruction specifies the number of n-line. Please refer to the (1-9)LCD Driving Circuits (e)Common timing
generation Fig.2-1, Fig.2-2 for more detail.
A0
0
RDb WRb
1
0
A3
0
0
0
:
1
1
D7
0
A2
0
0
0
:
1
1
D6
0
D5
1
A1
0
0
1
:
1
1
D4
1
D3
A3
A0
0
1
0
:
0
1
D2
A2
D1
A1
D0
A0
Inverse Lines
-(*)
2
3
:
15
16
(*) 2-frame
mode.
alternating drive
(w) n-line Inverse Drive Reset
This instruction releases n-line inversion, but does not change the contents of the n-line register.
A0
0
RDb WRb
1
0
D7
1
D6
1
D5
1
D4
0
D3
0
D2
1
D1
0
D0
0
D5
1
D4
0
D3
0
D2
0
D1
1
D0
D
(x) Patial Select
This instruction starts the partial mode operation.
A0
0
D
RDb WRb
1
0
D7
1
D6
0
0: 1/65 Duty (Partial Select Off)
1: 1/33 Duty (Partial Select On)
Display structure by Partial Select On / Off
Partial Select Off
(1/65 Duty)
COM0~COM7
COM8~COM15
COM16~COM23
COM24~COM31
COM32~COM39
COM40~COM47
COM48~COM55
COM56~COM63
COMM
160seg
64com+1
Partial Select On
(1/33 Duty)
COM0~COM7
COM8~COM15
COM16~COM23
COM24~COM31
COM32~COM39
COM40~COM47
COM48~COM55
COM56~COM63
COMM
160seg
32com+1
Active Display-block
Ver.2009-12-02
- 29 -
NJU6655B
(y) Internal Oscillation Circuit On
This setting is effective when M/S=”1” and CLS=”1”.
A0
0
RDb WRb
1
0
D7
1
D6
0
D5
1
D4
0
D3
1
D2
0
D1
1
D0
1
RDb WRb
1
0
D7
1
D6
1
D5
1
D4
0
D3
0
D2
0
D1
1
D0
1
(z)NOP
Non Operation.
A0
0
- 30 -
Ver.2009-12-02
NJU6655B
- Example for Instruction Setting (Reference)
<Conditions>
VDD=3V, 4-time booster, Using the internal feedback resistor, Using the internal oscillator, Using the n-line
inverse drive, Using the 80-type I/F.
Example for Initialize Sequence
VDD-VSS Power ON
VDD=3V, VSS=0V input
Stabilizing the Power Supply
Reset Input
←
Refer to (1-8) Reset circuit.
WAIT
←
Wait 1.5[us] or more.
Instruction Setting
A0
D6
D5
D4
D3
D2
D1
D0
ADC Select
0
1
0
1
0
1
0
0
0
0
0
Segment driver : S0 → S159
Normal or Inverse display
0
1
0
1
0
1
0
0
1
1
0
Normal display
LCD Bias Select
0
1
0
1
0
0
1
0
0
0
0
1/9 Bias
Common Direction Select
0
1
0
1
1
0
0
0
*
*
*
Common direction : C0 → C63
Feedback Resistor Ratio
0
1
0
0
0
1
0
0
1
1
1
Resistor Ratio : 8.1
EVR Mode Set
0
1
0
1
0
0
0
0
0
0
1
EVR Mode ON
EVR Register Set
0
1
0
*
*
1
0
0
0
0
0
EVR Register : ”1.0.0.0.0.0”
Static Indicator ON/OFF
0
1
0
1
0
1
0
1
1
0
0
Static indicator OFF
Static Indicator Register Set
0
1
0
*
*
*
*
*
*
0
0
Static indicator OFF
n-line Inverse Drive Register
Set
0
1
0
0
0
1
1
0
1
1
0
n-line inverse : 7
Partial Select
0
1
0
1
0
1
0
0
0
1
0
1/65 Duty
Internal Oscillation Circuit ON
0
1
0
1
0
1
0
1
0
1
1
Oscillation circuit ON
Power Control Set
0
1
0
0
0
1
0
1
1
0
0
Voltage converter ”ON”,
Voltage Regulator ”OFF,
Voltage Follower ”OFF”
0
1
0
0
0
1
0
1
1
1
0
Voltage converter ”ON”,
Voltage Regulator ”ON,
Voltage Follower ”OFF”
0
1
0
0
0
1
0
1
1
1
1
Voltage converter ”ON”,
Voltage Regulator ”ON,
Voltage Follower ”ON”
WAIT
Note)
Power Control Set
WAIT
Note)
Power Control Set
WAIT
RDb WRb D7
Note)
END
*:Don’t Care
Note) Wait time for stabilizing internal power supply differs by external components (Cout, C1~C8), VDD, and VLCD.
Make sure what is the wait time in the particular application.
Ver.2009-12-02
- 31 -
NJU6655B
Example for Display Data Write Sequence
Optional Status
Instruction Setting
A0
D6
D5
D4
D3
D2
D1
D0
Initial Display Line Set
0
1
0
0
1
0
0
0
0
0
0
Line address : 00H
Page Address Set
0
1
0
1
0
1
1
0
0
0
0
Page address : 0 page
Column Address Set
0
1
0
0
0
0
1
0
0
0
0
Column address (upper) : 0H
0
1
0
0
0
0
0
0
0
0
0
Column address (lower) : 0H
1
1
0
1
0
1
0
1
0
1
0
Writing display data
: Checker flag pattern
1
1
0
0
1
0
1
0
1
0
1
1
1
0
1
0
1
0
1
0
1
0
Write Display Data
1
1
0
0
1
0
1
0
1
0
1
(Other page requires to set from “Page
Address Set”)
Display ON/OFF
0
1
0
1
0
1
0
1
1
1
1
Display ON
Write Display Data
RDb WRb D7
Example for Power Supply OFF Sequence
Optional Status
A0
D6
D5
D4
D3
D2
D1
D0
Display ON/OFF
0
1
0
1
0
1
0
1
1
1
0
Display OFF
Power Save
0
1
0
1
0
1
0
1
0
0
1
Sleep mode
Power Control Set
0
1
0
0
0
1
0
1
0
0
0
Voltage converter ”OFF”,
Voltage Regulator ”OFF,
Voltage Follower ”OFF”
RDb WRb D7
VDD-VSS OFF
- 32 -
Ver.2009-12-02
NJU6655B
(3) Internal power circuits
(3-1) Voltage converter
The voltage converter generates maximum 4x boosted negative-voltage from the voltage between VDD and VSS2. The
boosted voltage is output from the VOUT terminal.
The internal oscillator is required to be operating when using this converter, because the divided signal provided from
the oscillator is used for the internal timing of this circuit.
The boosted voltage between VDD and VOUT must not exceed 18.0V.
The voltage converter requires external capacitors for boosting as shown in below.
# The boosted voltage and VDD, VSS2
VDD=+3V
VSS2=0V
VOUT=-3V
VOUT=-6V
VOUT=-9V
2x boost
3x boost
# Example for connecting the capacitors
4x boost
3x boost
2x boost
VSS2
VSS2
VSS2
C1-
C1-
C1-
C1+
C1+
C3C2+
Ver.2009-12-02
4x boost
+
+
C3
+
-
C2+
+
C2-
C2-
VOUT
VOUT
C1+
+
+
+
+
-
C3
C2+
C2-
VOUT
- 33 -
NJU6655B
(3-2) Voltage Adjust Circuits
The voltage adjust circuits is composed of the reference voltage circuit, 64-step E.V.R. and feedback resistors. The adjust
circuits produces the LCD driving voltage V5 on the V5 terminal, using the VOUT voltage supplied from the internal
booster.
(a) Using Internal Feedback Resistors
LCD contrast can be fine-tuned by adjusting the V5 voltage through setting the internal feedback resistors and the E.V.R.
And the V5 voltage is calculated from the foemula (1), where |V5| < |VOUT|.
VLCD
= VDD-V5
- - - - - (1)
= (1+(Rb/Ra)) x VCON
[VCON = (EVR) x (VREG)]
= (1+(Rb/Ra)) x (EVR) x VREG [EVR = (n+99) / 162]
VLCD : LCD Driving Voltage
Ra,Rb : Feedback Resistors
VCON : Contrast Control Voltage
n
: E.V.R. Setting Value
VREG : Reference Voltage
VDD
VCON
(VREG x EVR)
Internal Ra
VLCD
+
V5
VOUT
Internal Rb
Fig.3-1 Voltage adjust circuits (Using internal feedback resistors)
The VREG is the regulated voltage with temperature coefficient, as follows.
Internal Power Supply
Temperature
Coefficient
0.05[%/°C] (Typ.)
VREG
2.15[V] (Typ.)
*: The temperature coefficient has dispersion.
The V5 is adjusted in 64-step by setting 6-bit data into the E.V.R. register, as follows.
00H
01H
02H
:
:
:
3DH
3EH
3FH
- 34 -
E.V.R. Register
(0,0,0,0,0,0)
(0,0,0,0,0,1)
(0,0,0,0,1,0)
:
:
:
(1,1,1,1,0,1)
(1,1,1,1,1,0)
(1,1,1,1,1,1)
E.V.R. Value
(99/162)
(100/162)
(101/162)
:
:
:
(160/162)
(161/162)
(162/162)
VLCD
Minimum
:
:
:
:
:
:
:
Maximum
Ver.2009-12-02
NJU6655B
The ratio of the Ra and Rb (Ra/Rb) is selected out of 8 options by the "Feedback Resistor set" instruction.
The Register of Feedback Resistor
00H
(0,0,0)
01H
(0,0,1)
02H
(0,1,0)
03H
(0,1,1)
04H
(1,0,0)
05H
(1,0,1)
06H
(1,1,0)
07H
(1,1,1)
1+(Rb/Ra)
4.5
5.0
5.5
6.0
6.5
7.0
7.6
8.1
VLCD
Minimum
:
:
:
:
:
:
Maximum
* : The resistance of the feedback resistors has a certain amount of error. If it may impact on the LCD contrast external
feedback resistors should be considered.
(b) Using External Feedback Resistors
When IRS="L", the V5 voltage can be adjusted by the external feedback resistors. And the E.V.R. function is applied in
combination, and fine-tunes the LCD contrast through software. The V5 voltage is calculated from the formula (2), where
|V5| < |VOUT|.
VLCD
= VDD-V5
- - - - - (2)
= (1+(Rb/Ra)) x VCON
[VCON = (EVR) x (VREG)]
= (1+(Rb/Ra)) x (EVR) x VREG [EVR = (n+99) / 162]
VLCD : LCD Driving Voltage
Ra,Rb : Feedback Resistors
VCON : Contrast Control Voltage
n
: E.V.R. Setting Value
VREG : Reference Voltage
VDD
VCON
(VREG x EVR)
External Ra
VR
+
-
VLCD
V5
VOUT
External Rb
Fig.3-2 Voltage adjust circuits (Using external feedback resistors)
* : When using either the internal feedback resistors or E.V.R. or both, the LCD voltage generator and the buffer
amplifiers must be activated.
* : The VR terminal is only used for the external feedback resistors. This must be open when using the internal
feedback resistors.
Ver.2009-12-02
- 35 -
NJU6655B
<Design example for the adjustable range / Reference> Using external resistors(Not using variable resistor), VLCD=7V
Power supply VDD=3.0V, VSS=0V
E.V.R. register = (D5,D4,D3,D2,D1,D0) : (1,0,0,0,0,0)
By formula (2)
VLCD = VDD-V5
= (1+(Rb/Ra)) x (EVR) x VREG
7[V] = (1+(Rb/Ra)) x (131/162) x 2.15
Rb/Ra = 3.03
- - - - - (3)
In case of the current value sets 5uA, which flows to Ra and Rb
Ra+Rb = 1.4MΩ
- - - - - (4)
By formula (3), (4)
Ra+3.03Ra= 1.4MΩ
Ra
= 347kΩ
- - - - - (5)
Therefore,
Rb
= 1.4MΩ - 347kΩ
= 1053kΩ
- - - - - (6)
The adjustable range and the step voltage are calculated as follows in the formula (2).
- In case of setting 00H in the E.V.R. register,
VLCD =(1+(Rb/Ra)) x (EVR) x VREG
=(1+3.03) x [(99/162) x 2.15]
=5.29V
- In case of setting 3FH in the E.V.R. register,
VLCD =(1+(Rb/Ra)) x (EVR) x VREG
=(1+3.03) x [(162/162) x 2.15]
=8.66V
VLCD Adjustable Range
VLCD Step Voltage
- 36 -
(min.) 00H
(max.) 3FH
5.29 ---------------------------------------- 8.66[V]
53
[mV]
*: In case of VDD=3V
Ver.2009-12-02
NJU6655B
(3-3) LCD Driving Voltage Generation Circuits
The LCD driving bias voltage of V1,V2,V3,V4 are generated internally by dividing the VLCD (VLCD=VDD-V5) voltage
with the internal bleeder resistance. And it is supplied to the LCD driving circuits after the impedance conversion with
voltage follower circuit.
As shown in Fig 4, Five capacitors are required to connect to each LCD driving voltage terminal for voltage stabilizing.
And the value of capacitors C4, C5, C6, C7, and C8 are determined depending on the actual LCD panel display evaluation.
Using the internal Power Supply
Using the external Power Supply
VSS
VSS
VSS2
C1
+
+
C1-
C1-
C1+
C1+
C3-
C3-
C3
COUT
+
(2)
C2+
C2
C2+
C2-
C2-
*2
VOUT
R3
V5
VOUT
NJU6655B
V5
(1)
NJU6655B
*1
R2
VR
VR
VDD
VDD
V1
V1
R1
+
C4
+
C5
+
C6
+
C7
+
C8
V2
V2
External
Voltage
Generator
V3
V4
V4
V5
V5
Fig.4
LCD Driving Voltage Generation Circuits
*1 Short wiring or sealed wiring to the VR terminal is required due to
the high impedance of VR terminal.
*2 Following connection of VOUT is required when external power
supply using.
(1): When VSS > V5 --- VOUT=V5
(2): When VSS < V5 --- VOUT=VSS
Ver.2009-12-02
V3
Reference set up value
VLCD=VDD-V5=7.0 to 10.5V
COUT
C1~C3, C8
C4~C7
R1
R2
R3
~1.0uF
~1.0uF
0.1 ~ 0.47uF
232kΩ
115kΩ
1.053MΩ
- 37 -
NJU6655B
(4) MPU interface
(4-1) Interface type selection
NJU6655B interfaces with MPU by 8-bit bidirectional data bus (D7 to D0) or serial (SI:D7). The 8 bit parallel or serial
interface is determined by a condition of the P/S terminal connecting to "H" or "L" level as shown in Table 5. In case
of the serial interface, status and RAM data read out operation is impossible.
Table.5
P/S
H
L
Type
Parallel
Serial
Relation between P/S terminal and each I/O terminal
CS1b
A0
RDb
WRb
C86
SI(D7) SCL(D6)
D0 ~ D5
A0
RDb
WRb
C86
D7
D6
D0 ~ D5
CS1b
A0
SI
SCL
Hi-Z
CS1b
“Hi-Z” : Hi-impedance “-“ : They should be fixed to “H” or “L”.
Parallel Interface
The NJU6655B interfaces to 68 or 80 type MPU directly when the parallel interface (P/S="H") is selected. 68 type
MPU or 80 is determined by the condition of C86 terminal connecting to "H" or "L" as shown in Table 6.
C86
H
L
Table.6
Type
68 type MPU
80 type MPU
Relation between C86 terminal and each I/O terminal
CS1b
A0
RDb
WRb
D0 ~ D7
CS1b
A0
E
R/W
D0 ~ D7
CS1b
A0
RDb
WRb
D0 ~ D7
(4-2) Discrimination of Data Bus Signal
The NJU6655B discriminates the mean of signal on the data bus by the combination of A0, E, R/W, and (RDb,WRb)
signals as shown in Table 7.
Common
A0
H
H
L
L
- 38 -
68 type
R/W
H
L
H
L
Table.7 Relation between A0 terminal and 68/80 type terminal
80 type
Function
RDb
WRb
L
H
Read Display Data
H
L
Write Display Data
L
H
Status Read
H
L
Write into the Register(Instruction)
Ver.2009-12-02
NJU6655B
(4-3) Serial Interface (P/S="L")
Serial interface circuits consist of 8 bits shift register and 3 bits counter. SI and SCL input are activated when the chip
select terminal CS1b set to "L", CS2 set to "H"and P/S terminal set to "L". The 8 bits shift register and 3 bits counter are
reset to the initial condition when the chip is not selected.
The data input from SI terminal is MSB first like as the order of D7,D6,- - - - D0, and the data are entered into the shift
register synchronizing with the rise edge of the serial clock SCL. The data in the shift register are converted to parallel
data at the 8th serial clock rise edge input.
Discrimination of the display data or instruction of the serial input data is executed by the condition of A0 at the 8th
serial clock rise edge. A0="H" is display data and A0="L" is instruction. When RESb terminal becomes "L" or CS1b
terminal becomes "H" (CS2 terminal becomes "L") before 8th serial clock rise edge, NJU6655A recognizes them as a
instruction data incorrectly. Therefore a unit of serial data must be structured by 8-bit.
The time chart for the serial interface is shown in Fig. 5. To avoid the noise trouble, the short wiring is required for the
SCL input.
Note) The read out function, such as the status or RAM data read out, is not supported in this serial interface.
CS1b
CS2
SI
SCL
D7
1
D6
2
D5
3
D4
4
D3
5
D2
6
D1
7
D0
8
D7
9
10
A0
Fig.5
Ver.2009-12-02
Signal chart of serial interface
- 39 -
NJU6655B
(4-4) Access to the Display Data RAM and Internal Register
The NJU6655B is operating as one of pipe-line processor by the bus-holder connecting to the internal data bus to adjust
the operation frequency between MPU and the Display Data RAM or Internal Register.
For example, when the MPU reads out the data from the Display Data RAM, the read out data in the data read cycle
(dummy read) is held in the bus-holder, then it is read out from the bus-holder to the system bus at the next data read
cycle. When the MPU writes the data into the Display Data RAM, the data is held in the bus-holder, then it is written
into the Display Data RAM by the next data write cycle.
Therefore high speed data transmission between MPU and NJU6655B is available because of it is not limited by the
tACC and tDS as display data RAM access time and is limited by the system cycle time (R) or (W).
If the cycle time is not be kept in the MPU operation, NOP should be inserted to the system instead of the waiting
operation.
The read out operation does not read out the data in the pointed address just after the address set operation. And second
read out operation can read out the data correctly from the pointed address.
Therefore, one dummy read operation is required after address setting or write cycle as shown in Fig. 6.
The example of Read Modify Write operation is mentioned in (2-1) Instruction (l)The sequence of inverse display.
# Write Operation
CPU
WRb
N
DATA
Internal
Timing
Bus holder
N+1
N
N+2
N+1
N+3
N+2
N+3
WRb
# Read Operation
CPU
WRb
RDb
DATA
Internal
Timing
N
N
n
n+1
Address Set N
Dummy read
Data read n
Data read n+1
WRb
RDb
Column
address
N
Bus holder
Fig.6
N
N+1
n
N+2
n+1
n+2
Relation between display data write/read and internal timing
(4-5) Chip select
CS1b, CS2 are Chip Select terminals. In case of CS1b="L" and CS2=”H”, the interface with MPU is available. In case
of CS1b=”H” or CS2=”L”, the D0 to D7 are high impedance and A0, RDb, WRb, D7(SI) and D6(SCL) inputs are ignored.
If the serial interface is selected when CS1b=”H” or CS2=”L”, the shift register and the counter are reset. However, the
reset is always operated in any conditions of CS1b and CS2.
- 40 -
Ver.2009-12-02
NJU6655B
! ABSOLUTE MAXIMUMN RATINGS
PARAMETER
Supply Voltage (1)
Supply Voltage (2)
(When using 3x voltage converter)
(When using 4x voltage converter)
Supply Voltage (3)
Supply Voltage (4)
Input Voltage
Output Voltage
Operating Temperature
Storage Temperature
(Chip)
VDD
VSS
SYMBOL
VDD
Vss2
V5,VOUT
V1,V2,V3,V4
VIN
VOUT
Topr
Tstg
RATINGS
-0.3 to +7.0
-7.0 to +0.3
-6.0 to +0.3
-4.5 to +0.3
-18.0 to +0.3
V5 to +0.3
-0.3 to VDD + 0.3
-0.3 to VDD + 0.3
-40 to +85
-55 to +125
(Ta=25°C)
UNIT
V
V
V
V
V
V
°C
°C
VDD
VSS2, V1 to V4
V5
Note 1) VSS2, V1 to V5, VOUT voltage values are specified as VDD = 0V.
Note 2) The relation of VDD>V1>V2>V3>V4>V5>VOUT ; VDD>VSS>VOUT must be maintained.
In case of inputting external LCD driving voltage, LCD drive voltage should start supplying to NJU6655B at
the mean time of turning on VDD power supply or after turned on VDD.
In use of the voltage boost circuit, the condition that the supply voltage : 18V >VDD-VOUT is necessary.
Note 3) If the LSI are used on condition beyond the absolute maximum rating, the LSI may be destroyed. Using LSI
within electrical characteristics is strongly recommended for normal operation. Use beyond the electric
characteristics conditions will cause malfunction and poor reliability.
Note 4) Decoupling capacitor should be connected between VDD and VSS due to the stabilized operation for the voltage
converter.
Ver.2009-12-02
- 41 -
NJU6655B
! DC Electrical Characteristics
PARAMETER
Power Supply (1)
Power Supply (2)
Power Supply (3)
SYMBOL
VDD
Oscillation Frequency
VSS2
V5
V1,V2
V3,V4
VIHC1
VILC1
VOHC1
VOLC1
ILI
ILO
RON1
RON2
ISSQ
I5Q
CIN
fOSC
Display Clock Frequency
fCL
“H” Level Input Voltage
“L” Level Input Voltage
“H” Level Output Voltage
“L” Level Output Voltage
Leakage Current
Driver On-resistance
Stand-by Current
Output Leakage Current
Input Terminal Capacitance
CONDITIONS
Recommend→
Possible→
VDD common
VDD common
VDD common
IOH=-0.5mA
IOL= 0.5mA
All input terminals
D0 to D7 terminals, Hi-Z state
Ta=25°C V5=-14.0V
V5=-8.0V
V5=-18.0V (VDD common)
Ta=25°C
VDD=3V,Ta=25°C
External input
(VDD=2.4 to 3.6V, VSS=0V, Ta= -40 to 85°C)
MIN
TYP
MAX UNIT NOTE
2.4
3.6
V
5
2.4
5.5
V
-6.0
-2.4
V
-18
-4.5
V
0.4V5
VDD
V5
0.6V5
0.8VDD
VDD
V
VSS
0.2VDD
V
0.8VDD
VDD
V
VSS
0.2VDD
V
-1.0
1.0
uA
-3.0
3.0
uA
2.0
3.5
kΩ
6
3.2
5.4
kΩ
0.01
5
uA
0.01
15
uA
5
8
pF
7
17.0
20.8
24.6
kHz
4.25
5.20
6.15
kHz
Note 5) Although the NJU6655B can operate in wide range of the operating voltage, it shall not be guaranteed in a
sudden voltage fluctuation during the access with MPU.
Note 6) RON is the resistance values in supplying 0.1V voltage-difference between power supply terminals
(V1,V2,V3,V4) and each output terminals (common / segment). This is specified within the range of Operating
Voltage (2).
Note 7) Apply to A0, D7 to D0, RDb, WRb, CS1b, CS2, RESb, C86 and P/S terminals.
- 42 -
Ver.2009-12-02
NJU6655B
Input Voltage
VSS2
Output Voltage
On-resistance
VOUT
RQUAD
Adjustment Range
LCD Driving Voltage
Voltage Follower
Operating Voltage
Operating current
VOUT2
V5
IDDQ1
Voltage Booster
IDDQ2
IDD1
IDD2
LCD driving Voltage
Reference Voltage
Temperature
Coefficient
VLCD
VREF
TC
VDD common, 3-times boost
VDD common, 4-times boost
VDD common
4-times boost, C1-C3, COUT=1uF
VDD=3V, VSS=VSS2
Voltage boost operation off
External power supply
Voltage adjustment circuit off
External power supply
Power save mode
(Sleep mode)
Power save mode
(Standby mode)
VDD=3V, V5=-11V
All COM/SEG open, Without MPU
access, Checker flag display
Ext. Resistance Ra=Rb=910kΩ
(EVR=3FH)
1+(Rb/Ra)=4.5
Int. Resistance
(EVR=3FH)
1+(Rb/Ra)=5
1+(Rb/Ra)=5.5
1+(Rb/Ra)=6
1+(Rb/Ra)=6.5
1+(Rb/Ra)=7
1+(Rb/Ra)=7.6
1+(Rb/Ra)=8.1
Ta=25°C
VDD=3V
(VDD=2.4 to 3.6V, VSS=0V, Ta= -40 to 85°C)
-6.0
-2.4
V
-4.5
-2.4
-18.0
V
2.5
3.5
kΩ
8
-18.0
-
-6.0
-18.0
-
-4.5
0.01
5.0
4
10
130
20
200
50
uA
9
-4.43
-4.30
-4.17
V
10
-10.16
-11.29
-12.42
-13.55
-14.67
-15.80
-17.16
-18.29
-9.68
-10.75
-11.83
-12.90
-13.98
-15.05
-16.34
-17.42
2.150
-0.05
-9.19
-10.21
-11.23
-12.26
-13.28
-14.30
-15.52
-16.54
V
V
uA
V
%/°C
Note 8) The voltage adjustment circuit controls V5 within the range of the voltage follower operating voltage.
Note 9) Each operating current shall be defined as being measured in the following condition.
Note10) The LCD driving voltage spec: VLCD+ 3% (Using to External resistance) / VLCD+ 5 % (Using to Internal
resisutance).
Ver.2009-12-02
- 43 -
NJU6655B
Symbol
IDD1
IDD2
Power Control
D2
D1
D0
1
0
1
0
Voltage converter
Operating Condition
Voltage regulator
On
Off
On
Off
1
0
Voltage
followers
On
Off
External
Voltage Supply
(Input Terminal)
Use(VSS2)
Use(VOUT,V1∼V5)
IDD 1,2 measurement circuits:
:IDD1
VDD
V5
VR
NJU6655B
A
C1+
VSS
C1-
C2+
C2-
C3-
VOUT
+
+
+
+
V1 V2 V3 V4
:IDD2
VDD
V1 V2 V3 V4 V5
VR
A
NJU6655B
VSS
- 44 -
C1+
C1-
C2+
C2-
C3-
VOUT
Ver.2009-12-02
NJU6655B
! BUS TIMING CHARACTERISTICS
- Read and Write characteristics (80 type MPU)
CS2=H
*
tCYC8
A0
(1)CS1b
(2)WRb,RDb
tAW8
*
(1)WRb,RDb
(2)CS1b
tAH8
tCCL
tCCH
tDS8
D0 to D7
(Write)
tf
tDH8
tr
tACC8
tOH8
D0 to D7
(Read)
PARAMETER
Address Hold Time
Address Set Up Time
System Cycle Time
Control “L” Pulse Width (WRb)
Control “L” Pulse Width (RDb)
Control “H” Pulse Width (WRb)
Control “H” Pulse Width (RDb)
Data Set Up Time
Data Hold Time
RDb Access Time
Output Disable Time
Input Signal Rising, Falling Edge
Ver.2009-12-02
(VSS=0V, VDD=2.4 to 3.6V, Ta=-40 to 85°C)
TERMINAL SYMBOL CONDITION MIN
MAX
UNIT
A0,CS1b
tAH8
0
ns
CS2
0
ns
tAW8
tCYC8
800
ns
tCCLW
120
ns
WRb
tCCLR
240
ns
RDb
tCCHW
120
ns
tCCHR
120
ns
tDS8
80
ns
tDH8
30
ns
D0 to D7
tACC8
280
ns
CL=100pF
10
200
ns
tOH8
CS1b,CS2,
WRb,RDb,
tr, tf
15
ns
A0,D0 to D7
- 45 -
NJU6655B
PARAMETER
Address Hold Time
Address Set Up Time
System Cycle Time
Control “L” Pulse Width (WRb)
Control “L” Pulse Width (RDb)
Control “H” Pulse Width (WRb)
Control “H” Pulse Width (RDb)
Data Set Up Time
Data Hold Time
RDb Access Time
Output Disable Time
Input Signal Rising, Falling Edge
(VSS=0V, VDD=4.5 to 5.5V, Ta=-40 to 85°C)
TERMINAL SYMBOL CONDITION MIN
MAX
UNIT
tAH8
0
ns
A0,CS1b
CS2
0
ns
tAW8
tCYC8
250
ns
tCCLW
30
ns
WRb
tCCLR
70
ns
RDb
tCCHW
30
ns
tCCHR
30
ns
tDS8
30
ns
tDH8
10
ns
D0 to D7
tACC8
70
ns
CL=100pF
tOH8
5
50
ns
CS1b,CS2,
WRb,RDb,
tr, tf
15
ns
A0,D0 to D7
Note 10) Each timing is specified based on 0.2xVDD and 0.8xVDD.
* : (1) Accessed by WRb and RDb signal when CS1b="L". (2) Accessed by CS1b signal when WRb and RDb ="L".
- 46 -
Ver.2009-12-02
NJU6655B
- Read and Write characteristics (68 type MPU)
tCYC6
CS2=H
*
*
(1)E
(2)CS1b
tEWL
(1)CS1b
(2)E
tAW6
tEWH
tr
tf
tAH6
A0,R/W
tDS6
tDH6
D0 to D7
(Write)
tACC6
tOH6
D0 to D7
(Read)
PARAMETER
Address Hold Time
Address Set Up Time
System Cycle Time
Enable “H” Pulse Width (Read)
Enable “H” Pulse Width (Write)
Enable “L” Pulse Width (Read)
Enable “L” Pulse Width (Write)
Data Set Up Time
Data Hold Time
RDb Access Time
Output Disable Time
Input Signal Rising, Falling Edge
Ver.2009-12-02
(VSS=0V, VDD=2.4 to 3.6V, Ta=-40 to 85°C)
TERMINAL SYMBOL CONDITION MIN
MAX
UNIT
A0,CS1b
tAH6
0
ns
CS2
0
ns
tAW6
tCYC6
800
ns
tEWHR
240
ns
E(RDb)
tEWHW
120
ns
tEWLR
120
ns
tEWLW
120
ns
tDS6
80
ns
tDH6
30
ns
D0 to D7
tACC6
280
ns
CL=100pF
10
200
ns
tOH6
E(RDb),
R/W(WRb),
tr, tf
15
ns
A0,D0 to D7
- 47 -
NJU6655B
PARAMETER
Address Hold Time
Address Set Up Time
System Cycle Time
Enable “H” Pulse Width (Read)
Enable “H” Pulse Width (Write)
Enable “L” Pulse Width (Read)
Enable “L” Pulse Width (Write)
Data Set Up Time
Data Hold Time
RDb Access Time
Output Disable Time
Input Signal Rising, Falling Edge
(VSS=0V, VDD=4.5 to 5.5V, Ta=-40 to 85°C)
TERMINAL SYMBOL CONDITION MIN
MAX
UNIT
tAH6
0
ns
A0,CS1b
CS2
0
ns
tAW6
tCYC6
250
ns
tEWHR
70
ns
E(RDb)
tEWHW
30
ns
tEWLR
30
ns
tEWLW
30
ns
tDS6
30
ns
tDH6
10
ns
D0 to D7
tACC6
70
ns
CL=100pF
tOH6
5
50
ns
E(RDb),
R/W(WRb),
tr, tf
15
ns
A0,D0 to D7
Note 11) Each timing is specified based on 0.2xVDD and 0.8xVDD.
* : (1) Accessed by WRb and RDb signal when CS1b="L". (2) Accessed by CS1b signal when WRb and RDb ="L".
- 48 -
Ver.2009-12-02
NJU6655B
- Write characteristics (Serial interface)
CS2=H
tCSH
tCSS
CS1b
tSAS
tSAH
A0
tSCYC
tSLW
SCL
tSHW
tSDS
SI
tf
PARAMETER
Serial Clock Cycle
SCL “H” Pulse Width
SCL “L” Pulse Width
Address Set Up Time
Address Hold Time
Data Set Up Time
Data Hold Time
CS1b-SCL Time
Input Signal Rising, Falling Edge
Ver.2009-12-02
tSDH
tr
(VSS=0V, VDD=2.4 to 3.6V, Ta=-40 to 85°C)
MAX
UNIT
TERMINAL SYMBOL CONDITION MIN
tSCYC
400
ns
SCL(D6)
tSHW
150
ns
tSLW
150
ns
tSAS
250
ns
A0
tSAH
250
ns
tSDS
150
ns
SI(D7)
150
ns
tSDH
tCSS
250
ns
CS1b,CS2
250
ns
tCSH
SCL(D6),A0,
CS1b,CS2,
tr,, tf
15
ns
SI(D7)
- 49 -
NJU6655B
PARAMETER
Serial Clock Cycle
SCL “H” Pulse Width
SCL “L” Pulse Width
Address Set Up Time
Address Hold Time
Data Set Up Time
Data Hold Time
CS1b-SCL Time
Input Signal Rising, Falling Edge
(VSS=0V, VDD=4.5 to 5.5V, Ta=-40 to 85°C)
TERMINAL SYMBOL CONDITION MIN
MAX
UNIT
tSCYC
200
ns
SCL(D6)
tSHW
75
ns
75
ns
tSLW
tSAS
50
ns
A0
tSAH
100
ns
tSDS
50
ns
SI(D7)
50
ns
tSDH
tCSS
100
ns
CS1b,CS2
100
ns
tCSH
SCL(D6),A0,
CS1b,CS2,
tr,, tf
15
ns
SI(D7)
Note 12) Each timing is specified based on 0.2xVDD and 0.8xVDD.
- 50 -
Ver.2009-12-02
NJU6655B
- Display control timing characteristics
CL
(OUT)
tDFR
FR
tDSNC
SYNC
PARAMETER
FR Delay Time
SYNC Delay Time
(VSS=0V, VDD=2.4 to 3.6V, Ta=-40 to 85°C)
TERMINAL SYMBOL CONDITION
MIN
TYP
MAX
UNIT
FR
tDFR
CL=50pF
50
200
ns
SYNC
tDSNC
CL=50pF
50
200
ns
(VSS=0V, VDD=4.5 to 5.5V, Ta=-40 to 85°C)
PARAMETER
MIN
TYP
MAX
UNIT
FR Delay Time
FR
tDFR
CL=50pF
10
40
ns
SYNC Delay Time
SYNC
tDSNC
CL=50pF
10
40
ns
Note 13) Each timing is specified based on 0.2xVDD and 0.8xVDD.
(The delay time is applied to the master operation only.)
TERMINAL SYMBOL CONDITION
- Reset input timing
tRW
RESb
tR
Internal
circuit status
During reset
End of reset
(VSS=0V, VDD=2.4 to 3.6V, Ta=-40 to 85°C)
TERMINAL SYMBOL CONDITION
MIN
TYP
MAX
UNIT
PARAMETER
Reset Time
tR
1.5
us
Reset ”L” Level Pulse
RESb
tRW
1.5
us
Width
(VSS=0V, VDD=4.5 to 5.5V, Ta=-40 to 85°C)
TERMINAL SYMBOL CONDITION
MIN
TYP
MAX
UNIT
PARAMETER
Reset Time
tR
0.5
us
Reset ”L” Level Pulse
RESb
tRW
0.5
us
Width
Note 14) Each timing is specified based on 0.2xVDD and 0.8xVDD.
Ver.2009-12-02
- 51 -
NJU6655B
! LCD DRIVING WAVEFORM
0
FR
COM0
COM1
VDD
V1
V2
V3
V4
V5
COM2
VDD
V1
V2
V3
V4
V5
SEG0
VDD
V1
V2
V3
V4
V5
SEG1
VDD
V1
V2
V3
V4
V5
COM0-SEG0
V5
V4
V3
V2
V1
VDD
-V1
-V2
-V3
-V4
-V5
COM0-SEG1
V5
V4
V3
V2
V1
VDD
-V1
-V2
-V3
-V4
-V5
COM8
COM9
COM10
COM11
COM12
COM13
COM14
COM15
S S S S S
E E E E E
G G G G G
0
- 52 -
1
2
3
4
2
3
4
64 65 0
1
2
3
4
5
64 65
VDD
VSS
VDD
V1
V2
V3
V4
V5
COM0
COM1
COM2
COM3
COM4
COM5
COM6
COM7
1
Ver.2009-12-02
NJU6655B
! APPLICATION CIRCUIT
(1) Microprocessor Interface Example
The NJU6655B interfaces to 80 type or 68 type MPU directly. And the serial interface also communicate with MPU.
* : C86 terminal must be fixed VDD or VSS.
# 80 Type MPU
VCC
A0
A0
VDD
C86
A1~A7
CPU
Decoder
IORQ
D0~D7
GND
CS1b
CS2
NJU6655B
D0~D7
RD
RDb
WR
WRb
RES
RESb
P/S
VSS
RESET
# 68 Type MPU
VCC
A0
A0
VDD
C86
A1~A15
CPU
VMA
Decoder
NJU6655B
D0~D7
D0~D7
E
E
GND
CS1b
CS2
R/W
R/W
RES
RESb
P/S
VSS
RESET
# Serial Interface
VCC
A0
A0
VDD
C86
A1~A7
Decoder
CPU
GND
CS1b
CS2
Port 1
SI
Port 2
RES
SCL
RESb
VDD
OR GND
NJU6655B
VSS
P/S
RESET
Ver.2009-12-02
- 53 -
NJU6655B
(2) 65 x 320 dots Driving Application Circuits Example
(Common and Segment Drivers Extension by using two of NJU6655B)
LCD Panel : 65 x 320
SEG
SEG
M/S
M/S
COM
COM
NJU6655B
Master
CL
CL
FR
FR
SYNC
SYNC
DOFb
DOFb
NJU6655B
Slave
[CAUTION]
The specifications on this databook are only
given for information , without any guarantee
as regards either mistakes or omissions. The
application circuits in this databook are
described only to show representative usages
of the product and not intended for the
guarantee or permission of any right including
the industrial rights.
- 54 -
Ver.2009-12-02
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