ICST ICS9248-50 Frequency timing generator for pentium ii system Datasheet

Integrated
Circuit
Systems, Inc.
ICS9248-50
Frequency Timing Generator for Pentium II Systems
General Description
Features
The ICS9248-50 is the Main clock solution for Notebook
designs using the Intel 440BX style chipset. Along with an
SDRAM buffer such as the ICS9179-03, it provides all
necessary clock signals for such a system.
•
Spread spectrum may be enabled by driving pin 26, SPREAD#
active (Low) at power-on. Spread spectrum typically reduces
system EMI by 8dB to 10dB. This simplifies EMI qualification
without resorting to board design iterations or costly shielding.
The ICS9248-50 employs a proprietary closed loop design,
which tightly controls the percentage of spreading over
process and temperature variations.
•
•
•
•
Block Diagram
•
Generates the following system clocks:
- 2 CPU (2.5V) up to 100MHz.
- 6 PCI (3.3V) @ 33.3MHz (Includes one free running).
- 2 REF clks (3.3V) at 14.318MHz.
Skew characteristics:
- CPU – CPU<175ps
- PCI – PCI < 500ps
- CPU(early) – PCI = 1.5ns – 4ns.
Supports Spread Spectrum modulation for CPU and PCI
clocks, 0.5% down spread
Efficient Power management scheme through stop
clocks and power down modes.
Uses external 14.318MHz crystal, no external load cap
required for CL=18pF crystal.
28-pin (209 mil) SSOP and (6.1mm) TSSOP package
Pin Configuration
28-Pin SSOP & TSSOP
Power Groups
VDD, GND = PLL core
VDDREF, GNDREF = REF(0:1), X1, X2
VDDPCI, GNDPCI = PCICLK_F, PCICLK (0:4)
VDD48, GND48 = 48MHz, 48/24MHz
Pentium is a trademark on Intel Corporation.
9248-50 Rev - H 03/19/01
ICS reserves the right to make changes in the device data identified in
this publication without further notice. ICS advises its customers to
obtain the latest version of all device data to verify that any
information being relied upon by the customer is current and accurate.
ICS9248-50
Pin Descriptions
Pin number
Pin name
Type
Description
1
2
3
4
5,6,9,10,11
7
8
12
13
GNDREF
X1
X2
PCICLK_F
PCICLK (1:5)
GNDPCI
VDDPCI
VDD48
48 MHz
Power
Input
Output
Output
Output
Power
Power
Power
Output
14
TS#/48/24MHz
Output
15
GND48
Power
16
SEL 100/66#
Input
17
PD#
Input
18
CPU_STOP#
Input
19
VDD
Power
20
PCI-Stop#
Input
21
22
23,24
25
GND
GNDL
CPUCLK(1:0)
VDDL
Power
Power
Output
Power
26
REF1/SPREAD#
Output
27
REF0/SEL48#
Output
28
VDDREF
Power
Ground for 14.318 MHz reference clock outputs
14.318 MHz crystal input
14.318 MHz crystal output
3.3 V free running PCI clock output, will not be stopped by the PCI_STOP#
3.3 V PCI clock outputs, generating timing requirements for Pentium II Ground for PCI clock outputs
3.3 V power for the PCI clock outputs
3.3 V power for 48/24 MHz clocks
3.3 V 48 MHz clock output, fixed frequency clock typically used with USB devices
3.3 V 48 or 24 MHz output and Tri-state option, active low = tri state mode for testing,
active high = normal operation
Ground for 48/24 MHz clocks
control for the frequency of clocks at the CPU & PCICLK output pins. If logic "0" is
used the 66.6 MHz frequency is selected. If Logic "1" is used, the 100 MHz
frequency is selected. The PCI clock is multiplexed to run at 33.3 MHz for both
selected cases.
Asynchronous active low input pin used to power down the device into a low power
state. The internal clocks are disabled and the VCO and the crystal are stopped. The
latency of the power down will not be greater than 3ms.
Asynchronous active low input pin used to stop the CPUCLK in active low state, all
other clocks will continue to run. The CPUCLK will have a "Turnon " latency of at
least 3 CPU clocks.
Isolated 3.3 V power for core
Synchronous active low input used to stop the PCICLK in active low state. It will not
effect PCICLK_F or any other outputs.
Isolated ground for core
Ground for CPU clock outputs
2.5 V CPU clock outputs
2.5 V power for CPU clock outputs
3.3 V 14.318 MHz reference clock output and power-on spread spectrum enable
option. Active low = spread spectrum clocking enable. Active high = spread spectrum
clocking disable.
3.3 V 14.318 MHz reference clock output and power-on 48/24 MHz select option.
Active low = 48 MHz output at pin 14. Active high = 24 MHz output at pin 14.
3.3 V power for 14.318 MHz reference clock outputs.
2
ICS9248-50
Select Functions
(Functionality determined by TS# and SEL100/66# pin, see below)
Functionality
PCI,
PCI_F
CPUCLK
REF0
Tristate
HI - Z
HI - Z
HI - Z
Testmode
TCLK/21
TCLK/61
TCLK1
Notes:
1. TCLK is a test clock driven on the X1 (crystal in pin) input during test mode.
SEL 100/66#
TS#
Function
0
0
Tri-State
0
-
(Reserved)
0
-
(Reserved)
0
1
Active 66.6MHz CPU, 33.3 PCI
1
0
Test Mode
1
-
(Reserved)
1
-
(Reserved)
1
1
Active 100MHz CPU, 33.3 PCI
Power Management
Clock Enable Configuration
C P U _ S TO P # P C I _ S TO P #
X
X
0
0
0
1
1
0
1
1
P W R _ DW N #
0
1
1
1
1
CPUCLK
L ow
Low
Low
100/66.6MHz
100/66.6MHz
PCICLK PCICLK_F
L ow
L ow
Low
33.3MHz
33.3 MHz 33.3MHz
Low
33.3MHz
33.3 MHz 33.3MHz
REF
Stopped
Running
Running
Running
Running
Crystal
O ff
Running
Running
Running
Running
VCOs
O ff
Running
Running
Running
Running
Full clock cycle timing is guaranteed at all times after the system has initially powered up except where noted. During power
up and power down operations using the PD# pin will not cause clocks of a short or longer pulse than that of the running
clock. The first clock pulse coming out of a stopped clock condition may be slightly distorted due to clock network charging
circuitry. Board routing and signal loading may have a large impact on the initial clock distortion also.
ICS9248-50 Power Management Requirements
SIGNAL
SIGNAL STATE
C P U _ S TO P #
0 (Disabled)2
1 (Enabled)1
0 (Disabled)2
1 (Enabled)1
1 (Normal Operation)3
0 (Power Down)4
P C I _ S TO P #
PD#
L a t e n cy
No. of rising edges of free running
PCICLK
1
1
1
1
3ms
2max
Notes.
1. Clock on latency is defined from when the clock enable goes active to when the first valid clock comes out of the device.
2. Clock off latency is defined from when the clock enable goes inactive to when the last clock is driven low out of the device.
3. Power up latency is when PD# goes inactive (high) to when the first valid clocks are output by the device.
4. Power down has controlled clock counts applicable to CPUCLK, PCICLK only.
The REF will be stopped independant of these.
3
ICS9248-50
CPU_STOP# Timing Diagram
CPUSTOP# is an asychronous input to the clock synthesizer. It is used to turn off the CPUCLKs for low power operation.
CPU_STOP# is synchronized by the ICS9248-50. The minimum that the CPUCLK is enabled (CPU_STOP# high pulse) is 100
CPUCLKs. All other clocks will continue to run while the CPUCLKs are disabled. The CPUCLKs will always be stopped in a
low state and start in such a manner that guarantees the high pulse width is a full pulse. CPUCLK on latency is less than 4
CPUCLKs and CPUCLK off latency is less than 4 CPUCLKs.
Notes:
1. All timing is referenced to the internal CPUCLK.
2. CPU_STOP# is an asynchronous input and metastable conditions may exist.
This signal is synchronized to the CPUCLKs inside the ICS9248-50.
3. All other clocks continue to run undisturbed.
4. PD# and PCI_STOP# are shown in a high (true) state.
PCI_STOP# Timing Diagram
PCI_STOP# is an asynchronous input to the ICS9248-50. It is used to turn off the PCICLK (0:4) clocks for low power
operation. PCI_STOP# is synchronized by the ICS9248-50 internally. The minimum that the PCICLK (0:4) clocks are enabled
(PCI_STOP# high pulse) is at least 10 PCICLK (0:4) clocks. PCICLK (0:4) clocks are stopped in a low state and started with
a full high pulse width guaranteed. PCICLK (0:4) clock on latency cycles are only one rising PCICLK clock off latency is one
PCICLK clock.
Notes:
1. All timing is referenced to the Internal CPUCLK (defined as inside the ICS9248 device.)
2. PCI_STOP# is an asynchronous input, and metastable conditions may exist. This signal is required to be synchronized
inside the ICS9248.
3. All other clocks continue to run undisturbed.
4. PD# and CPU_STOP# are shown in a high (true) state.
4
ICS9248-50
PD# Timing Diagram
The power down selection is used to put the part into a very low power state without turning off the power to the part. PD# is
an asynchronous active low input. This signal is synchronized internally by the ICS9248-50 prior to its control action of
powering down the clock synthesizer. Internal clocks will not be running after the device is put in power down state. When
PD# is active (low) all clocks are driven to a low state and held prior to turning off the VCOs and the crystal oscillator. The
power on latency is guaranteed to be less than 3ms. The power down latency is less than three CPUCLK cycles. PCI_STOP#
and CPU_STOP# are don’t care signals during the power down operations.
Notes:
1. All timing is referenced to the Internal CPUCLK (defined as inside the ICS9248 device).
2. PD# is an asynchronous input and metastable conditions may exist. This signal is synchronized inside the ICS9248.
3. The shaded sections on the VCO and the Crystal signals indicate an active clock is being generated.
5
ICS9248-50
Absolute Maximum Ratings
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . 7.0 V
Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND –0.5 V to VDD +0.5 V
Ambient Operating Temperature . . . . . . . . . . . . 0°C to +70°C
Case Temperature . . . . . . . . . . . . . . . . . . . . . . . . 0°C to +115°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . –65°C to +150°C
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are
stress specifications only and functional operation of the device at these or any other conditions above those listed in the
operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended
periods may affect product reliability.
Electrical Characteristics - Input/Supply/Com m on O utput Param eters
T A = 0 - 70C; Supply Voltage VD D = 3.3 V +/-5% , VD D L = 2.5 V +/-5% (unles s otherwis e s tated)
PAR AM ETER
SYM B OL
C ONDITIONS
M IN
Input High Voltage
V IH
2
Input Low Voltage
V IL
V SS -0.3
Input High C urrent
IIH
V IN = V DD
Input Low Current
IIL1
V IN = 0 V; Inputs with no pull-up resisto rs
-5
Input Low Current
IIL2
V IN = 0 V; Inputs with pu ll-up resistors
-200
IDD3 .3 OP6 6 C L = 0 pF; Select @ 66M Hz
IDD3 .3 OP1 0 0 C L = 0 pF; Select @ 100M Hz
Operating
Supply C urrent
ID D 2 .5 O P 6 6 CL = 0 pF; Select @ 66.8 M Hz
ID D 2 .5 O P 1 0 0
Power Down
Supply C urrent
Input frequency
Input C apacitance 1
IDD3 .3 PD
Fi
TYP
0.1
2.0
-100
60
66
M AX UNITS
V DD+0.3
V
0.8
V
5
µA
µA
µA
180
180
mA
mA
CL = 0 pF; Select @ 100 M Hz
16
23
72
100
mA
mA
C L = 0 pF; With input address to Vdd or GND
70
600
µA
14.318
16
M Hz
36
5
45
pF
pF
V DD = 3.3 V;
11
C IN
C INX
Logic Inputs
X1 & X2 pins
Transition Time 1
T tran s
To 1st crossing of target Freq.
3
ms
Clk Stabilization 1
Skew 1
T STAB
T CPU-PCI
From V DD = 3.3 V to 1% target Freq.
3
ms
4
ns
27
VT = 1.5 V; VTL = 1.25 V
6
1.5
3
ICS9248-50
Electrical Characteristics - CPUCLK
T A = 0 - 70C; V DD = 3.3 V +/-5%, VDDL = 2.5 V +/-5%; C L = 10 - 20 pF (unless otherwise stated)
PARAM ETER
Output High Voltage
Output Low Voltage
Output High Current
Output Low Current
CONDITIONS
IOH = -12.0 mA
IOL = 12 mA
VOH = 1.7 V
VOL = 0.7 V
M IN
1.8
TYP
2.3
0.31
M AX
0.4
-27
27
UNITS
V
V
mA
mA
Rise Time
t r2 B
1
VOL = 0.4 V, VOH = 2.0 V
0.4
1.15
1.6
ns
Fall Time
t f2 B 1
VOH = 2.0 V, VOL = 0.4 V
0.4
1.4
1.6
ns
Duty Cycle
d t2 B 1
VT = 1.25 V
44
48
55
%
10
134
10
175
10.5
ps
ns
186
200
ps
-250
150
+250
ps
t sk 2 B 1
VT = 1.25 V
period(norm) VT = 1.25 V; 100M Hz
Skew
Jitter
Jitter
Jitter, Absolute
1
SYM BOL
VOH2 B
VOL2 B
IOH2 B
IOL2B
t jcy c-cy c2 B
t jab s 2 B 1
1
VT = 1.25 V
VT = 1.25 V
Guaranteed by design, not 100% tested in production.
Electrical Characteristics - REF/48M Hz/24M Hz
T A = 0 - 70C; V DD = 3.3 V +/-5%, VDDL = 2.5 V +/-5%; C L = 10 - 20 pF (unless otherwise stated)
PA RA M ETER
Output High Voltage
Output Low Voltage
Output High Current
Output Low Current
Ris e Time
Fall Time
1
1
Duty Cycle
Jitter
Jitter
1
1
1
SYM BOL
VO H 5
VO L 5
IO H 5
IO L 5
CONDITIONS
IO H = -12 mA
IO L = 9 mA
VO H = 2.0 V
VO L = 0.8 V
M IN
2.6
16
TYP
3.1
0.17
-44
42
M A X UNITS
V
0.4
V
-22
mA
mA
t r5
VO L = 0.4 V, VO H = 2.4 V
1.4
4
ns
t f5
VO H = 2.4 V, VO L = 0.4 V
1.1
4
ns
d t5
VT = 1.5 V
t j1 σ5
t jab s5
t j1 σ5
t jab s5
45
VT = 1.5 V, REF
VT = 1.5 V, REF
VT = 1.5 V, 48 M Hz
VT = 1.5 V, 48 M Hz
7
53
55
%
185
385
169
469
250
800
250
800
ps
ps
ps
ps
ICS9248-50
Electrical Characteristics - PCICLK
TA = 0 - 70C; VD D = 3.3 V +/-5%, VD D L = 2.5 V +/-5%; CL = 30 pF
PA RA M ETER
Output High Voltage
Output Low Voltage
Output High Current
Output Low Current
Ris e Time
Fall Time
1
1
Duty Cycle
Skew
Jitter
1
1
1
1
SYM BOL
VO H 1
VO L 1
IO H 1
IO L 1
CONDITIONS
IO H = -18 mA
IO L = 9.4 mA
VO H = 2.0 V
VO L = 0.8 V
M IN
2.1
TYP
3.3
0.1
16
M A X UNITS
V
0.4
V
-22
mA
57
mA
t r1
VO L = 0.4 V, VO H = 2.4 V
1.6
2
ns
t f1
VO H = 2.4 V, VO L = 0.4 V
1.8
2
ns
d t1
VT = 1.5 V
50
55
%
t sk 1
VT = 1.5 V
VT = 1.5 V
VT = 1.5 V
VT = 1.5 V
222
186
52
200
500
500
150
500
ps
ps
ps
ps
t jcy c-cy c
t j1 s
t jab s
45
Guaranteed by des ign, not 100% tes ted in production.
8
ICS9248-50
General Layout Precautions:
1) Use a ground plane on the top layer of the
PCB in all areas not used by traces.
2) Make all power traces and vias as wide as
possible to lower inductance.
Notes:
1 All clock outputs should have series
terminating resistor. Not shown in
all places to improve readibility of
diagram
2 Optional EMI capacitor should be
used on all CPU, SDRAM, and PCI
outputs.
3 Optional crystal load capacitors are
recommended.
Capacitor Values:
C1, C2 : Crystal load values determined by user
All unmarked capacitors are 0.01µF ceramic
9
ICS9248-50
SYMBOL
In Millimeters
In Inches
COMMON DIMENSIONS COMMON DIMENSIONS
MIN
MAX
MIN
MAX
A
-
2.00
-
.079
A1
0.05
-
.002
-
A2
1.65
1.85
.065
.073
b
0.22
0.38
.009
.015
c
0.09
0.25
SEE VARIATIONS
D
E
7.40
E1
5.00
5.60
0.65 BASIC
.197
.220
0.0256 BASIC
0.55
0.95
SEE VARIATIONS
.022
.037
SEE VARIATIONS
e
L
N
α
8.20
.0035
.010
SEE VARIATIONS
0°
.291
.323
8°
0°
8°
MIN
MAX
MIN
MAX
8
2.70
3.30
.106
.130
14
5.90
6.50
.232
.256
16
5.90
6.50
.232
.256
18
6.90
7.50
.271
.295
20
6.90
7.50
.271
.295
22
7.90
8.50
.311
.335
24
7.90
8.50
.311
.335
28
9.90
10.50
.390
.413
30
9.90
10.50
.390
.413
38
12.30
12.90
VARIATIONS
D mm.
N
D (inch)
.484
.508
MO-150 JEDEC
Doc.# 10-0033
6/1/00 Rev B
Ordering Information
ICS9248yF-50-T
Example:
ICS XXXX y F - PPP - T
Designation for tape and reel packaging
Pattern Number (2 or 3 digit number for parts with ROM code patterns)
Package Type
F=SSOP
Revision Designator (will not correlate with datasheet revision)
Device Type (consists of 3 or 4 digit numbers)
Prefix
ICS, AV = Standard Device
10
ICS reserves the right to make changes in the device data identified in
this publication without further notice. ICS advises its customers to
obtain the latest version of all device data to verify that any
information being relied upon by the customer is current and accurate.
ICS9248-50
SYMBOL
In Millimeters
In Inches
COMMON DIMENSIONS COMMON DIMENSIONS
MIN
MAX
MIN
MAX
A
-
1.20
-
.047
A1
0.05
0.15
.002
.006
A2
0.80
1.05
.032
.041
b
0.19
0.30
.007
.012
c
D
0.09
0.20
SEE VARIATIONS
.0035
.008
SEE VARIATIONS
E
8.10 BASIC
0.319
E1
6.00
e
6.20
.236
0.65 BASIC
L
0.45
0.75
SEE VARIATIONS
N
.244
0.0256 BASIC
.018
.030
SEE VARIATIONS
α
0°
8°
0°
8°
aaa
-
0.10
-
.004
MIN
MAX
MIN
9.60
9.80
.378
.386
MO-153 JEDEC
Doc.# 10-0038
7/6/00 Rev B
VARIATIONS
D mm.
N
6.10 mm. Body, 0.65 mm. pitch TSSOP
(0.0256 mil)
(240 mil)
28
D (inch)
MAX
Ordering Information
ICS9248yG-50-T
Example:
ICS XXXX y G - PPP - T
Designation for tape and reel packaging
Pattern Number (2 or 3 digit number for parts with ROM code patterns)
Package Type
G=TSSOP
Revision Designator (will not correlate with datasheet revision)
Device Type (consists of 3 or 4 digit numbers)
Prefix
ICS, AV = Standard Device
11
ICS reserves the right to make changes in the device data identified in
this publication without further notice. ICS advises its customers to
obtain the latest version of all device data to verify that any
information being relied upon by the customer is current and accurate.