PHILIPS HEF4021BD 8-bit static shift register Datasheet

INTEGRATED CIRCUITS
DATA SHEET
For a complete data sheet, please also download:
• The IC04 LOCMOS HE4000B Logic
Family Specifications HEF, HEC
• The IC04 LOCMOS HE4000B Logic
Package Outlines/Information HEF, HEC
HEF4021B
MSI
8-bit static shift register
Product specification
File under Integrated Circuits, IC04
January 1995
Philips Semiconductors
Product specification
HEF4021B
MSI
8-bit static shift register
Each register stage is a D-type master-slave flip-flop with
a set direct/clear direct input. Information on P0 to P7 is
asynchronously loaded into the register while PL is HIGH,
independent of CP and DS. When PL is LOW, data on
DS is shifted into the first register position and all the data
in the register is shifted one position to the right on the
LOW to HIGH transition of CP. Schmitt-trigger action in the
clock input makes the circuit highly tolerant to slower clock
rise and fall times.
DESCRIPTION
The HEF4021B is an 8-bit static shift register
(parallel-to-serial converter) with a synchronous serial
data input (DS), a clock input (CP), an asynchronous active
HIGH parallel load input (PL), eight asynchronous parallel
data inputs (P0 to P7) and buffered parallel outputs from
the last three stages (05 to O7).
Fig.1 Functional diagram.
HEF4021BP(N):
16-lead DIL; plastic
HEF4021BD(F):
16-lead DIL; ceramic (cerdip)
(SOT38-1)
(SOT74)
HEF4021BT(D):
16-lead SO; plastic
(SOT109-1)
( ): Package Designator North America
Fig.2 Pinning diagram.
FAMILY DATA, IDD LIMITS category MSI
See Family Specifications
PINNING
PL
parallel load input
P0 to P7
parallel data inputs
DS
serial data input
CP
clock input (LOW to HIGH edge-triggered)
O5 to O7
buffered parallel outputs from the last three stages
January 1995
2
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Philips Semiconductors
8-bit static shift register
January 1995
3
Product specification
HEF4021B
MSI
Fig.3 Logic diagram.
Philips Semiconductors
Product specification
HEF4021B
MSI
8-bit static shift register
FUNCTION TABLES
Serial operation
Parallel operation
INPUTS
OUTPUTS
INPUTS
OUTPUTS
DS
PL
O5
O6
O7
1
D1
L
X
X
X
2
D2
L
X
X
X
Notes
3
D3
L
X
X
X
6
X
L
D1
X
X
7
X
L
D2
D1
X
8
X
L
D3
D2
D1
X
L
1. H = HIGH state (the more positive voltage)
L = LOW state (the less positive voltage)
X = state is immaterial
= positive-going transition
= negative-going transition
Dn = either HIGH or LOW
n = number of clock pulse transitions
n
CP
n
no change
CP
DS
PL
O5
O6
O7
X
X
H
P5
P6
P7
AC CHARACTERISTICS
VSS = 0 V; Tamb = 25 °C; CL = 50 pF; input transition times ≤ 20 ns
VDD
V
SYMBOL
MIN.
TYPICAL EXTRAPOLATION
FORMULA
TYP.
MAX.
125
250
ns
98 ns + (0,55 ns/pF) CL
55
110
ns
44 ns + (0,23 ns/pF) CL
40
80
ns
32 ns + (0,16 ns/pF) CL
115
230
ns
88 ns + (0,55 ns/pF) CL
50
100
ns
39 ns + (0,23 ns/pF) CL
40
80
ns
32 ns + (0,16 ns/pF) CL
120
240
ns
93 ns + (0,55 ns/pF) CL
55
110
ns
44 ns + (0,23 ns/pF) CL
40
80
ns
32 ns + (0,16 ns/pF) CL
105
210
ns
78 ns + (0,55 ns/pF) CL
50
100
ns
39 ns + (0,23 ns/pF) CL
40
80
ns
32 ns + (0,16 ns/pF) CL
10 ns + (1,0 ns/pF) CL
Propagation delays
CP → On
HIGH to LOW
5
10
tPHL
15
5
LOW to HIGH
10
tPLH
15
PL → On
HIGH to LOW
5
10
tPHL
15
5
LOW to HIGH
10
tPLH
15
Output transition
times
HIGH to LOW
LOW to HIGH
5
60
120
ns
30
60
ns
9 ns + (0,42 ns/pF) CL
15
20
40
ns
6 ns + (0,28 ns/pF) CL
5
60
120
ns
30
60
ns
9 ns + (0,42 ns/pF) CL
20
40
ns
6 ns + (0,28 ns/pF) CL
10
10
tTHL
tTLH
15
January 1995
4
10 ns + (1,0 ns/pF) CL
Philips Semiconductors
Product specification
HEF4021B
MSI
8-bit static shift register
AC CHARACTERISTICS
VSS = 0 V; Tamb = 25 °C; CL = 50 pF; input transition times ≤ 20 ns
VDD
V
Set-up time
DS → CP
Pn → PL
Hold times
DS → CP
Pn → PL
Minimum clock
pulse width; LOW
Minimum PL
pulse width; HIGH
SYMBOL
5
MIN.
TYP.
MAX.
25
−15
ns
25
−10
ns
15
15
−5
ns
5
50
25
ns
10
tsu
30
10
ns
15
10
tsu
20
5
ns
5
40
20
ns
20
10
ns
15
10
thold
15
8
ns
5
15
−10
ns
15
0
ns
15
15
0
ns
5
70
35
ns
10
thold
10
tWCPL
30
15
ns
15
24
12
ns
5
70
35
ns
30
15
ns
10
tWPLH
15
24
12
ns
Recovery time
5
50
10
ns
for PL
10
40
5
ns
ns
Maximum clock
pulse frequency
tRPL
15
35
5
5
6
13
MHz
15
30
MHz
20
40
MHz
10
fmax
15
VDD
V
Dynamic power
dissipation per
package (P)
TYPICAL FORMULA FOR P (µW)
5
900 fi + ∑ (foCL) × VDD2
10
4 300 fi + ∑ (foCL) × VDD2
15
see also waveforms
Figs 4 and 5
12 000 fi + ∑ (foCL) × VDD
2
where
fi = input freq. (MHz)
fo = output freq. (MHz)
CL = load capacitance (pF)
∑ (foCL) = sum of outputs
VDD = supply voltage (V)
January 1995
5
Philips Semiconductors
Product specification
HEF4021B
MSI
8-bit static shift register
Fig.4 Waveforms showing minimum clock pulse width, set-up time and hold time for CP and DS.
Fig.5
Waveforms showing minimum PL pulse width, recovery time for PL, and set-up and hold times for Pn to
PL. Set-up and hold times are shown as positive values but may be specified as negative values.
January 1995
6
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