Micrel DSC2044FE2-F0018T Crystal-lessâ ¢ configurable clock generator Datasheet

DSC2044FE2-F0018
Crystal-less™ Configurable Clock Generator
General Description
Features
The DSC2044FE2-F0018 is a programmable, high
performance dual HCSL output oscillator utilizing
Micrel's proven silicon MEMS technology to provide
excellent jitter and stability while incorporating
additional device functionality. Two HCSL outputs
are controlled by separate supply voltages to allow for
high output isolation. The frequencies of the outrputs
can be identical or independently derived from a
common PLL frequency source.
The DSC2044FE2-F0018 has provision for up to eight
user-defined pre-programmed, pin-selectable output
frequency combinations.
• Frequency and output formats:
- HCSL
125/100MHz
- HCSL
125/100MHz
• Low RMS phase jitter: <1ps (typ)
• ±25ppm frequency stability
• -20°C to +70°C ext. commercial temperature range
• High supply noise rejection: -50dBc
• Pin-selectable configurations
- Up to 8 output frequency combinations
• Excellent shock & vibration immunity
- Qualified to MIL-STD-883
• High reliability
- 20x better MTF than quartz oscillators
• Supply range of 2.25 to 3.6V
• AEC-Q100 automotive qualified
• 14-pin 3.2mm x 2.5mm QFN package
Applications
• Consumer Electronics
• Storage Area Networks
- SATA, SAS, Fibre Channel
• Passive Optical Networks
- EPON, 10G-EPON, GPON, 10G-GPON
• Ethernet
- 1G, 10GBASE-T/KR/LR/SR, and FCoE
• HD/SD/SDI Video & Surveillance
• PCI Express
• Automotive
VDD/VDD2
Block Diagram
Control Circuitry
MEMS
÷2
÷ M1
CLK1+
125MHz HCSL
CLK1-
÷2
÷ M2
CLK2+
125MHz HCSL
CLK2-
PLL
FS0/FS1/FS2
OE
VSS
Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1 (408) 944-0800 • fax + 1 (408) 474-1000 • http://www.micrel.com
April 27, 2015
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Micrel, Inc.
DSC2044FE2-F0018
Ordering Information
Ordering Part Number
Industrial Temperature Range
Shipping
Package
DSC2044FE2-F0018
-20°C to +70°C
Tube
14-pin 3.2mm x 2.5mm QFN
DSC2044FE2-F0018T
-20°C to +70°C
Tape and Reel
14-pin 3.2mm x 2.5mm QFN
VDD2
NC
Pin Configuration
VDD
Devices are Green and RoHS compliant. Sample material may have only a partial top mark.
CLK2-
NC
CLK1-
GND
CLK1+
FS2
NC
FS1
CLK2+
FS0
OE
14-pin 3.2mm x 2.5mm QFN
Pin Description
Pin Number
Pin Name
Pin Type
1
OE
I
2
NC
Leave unconnected or connect to ground
3
NC
Leave unconnected or connect to ground
4
GND
PWR
5
FS0
I
Least significant bit for frequency selection, see Table 1 for details
6
FS1
I
Middle bit for frequency selection, see Table 1 for details
7
FS2
I
Most significant bit for frequency selection, see Table 1 for details
8
CLK1+
O
Positive HCSL output
9
CLK1-
O
Negative HCSL output
10
CLK2-
O
Negative HCSL output
11
CLK2+
O
Positive HCSL output
12
VDD2
PWR
Power supply for HCSL output CLK2, 1.65V to 3.6V (VDD2 ≤ VDD)
13
VDD
PWR
Power supply
14
NC
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Pin Function
Enables outputs when high and disables outputs when low
Ground
Leave unconnected or connect to ground
2
Revision 1.0
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Micrel, Inc.
DSC2044FE2-F0018
Operational Description
The DSC2044FE2-F0018 is a dual output HCSL
oscillator consisting of a MEMS resonator and a
supporting PLL IC. The two HCSL outputs are
generated through independent 8-bit programmable
dividers from the output of the internal PLL. The
two constraints are imposed on the output frequencies:
1) f2 = M x f1/N, where M and N are even integers
between 4 and 254, 2) 1.2GHz < N x f2 < 1.7GHz.
The actual frequencies output by DSC2044FE2-F0018
are controlled by an internal pre-programmed memory
(OTP). This memory stores all coefficients required
by the PLL for up to eight different frequency
combinations. Three control pins (FS0 - FS2) select
the output frequency combination.
When OE (pin 1) is floated or connected to VDD,
the DSC2044 is in operational mode. Driving OE
to ground will tri-state both output drivers (hiimpedance mode).
Output Clock Frequencies
Frequency select bits are weakly tied high so if left unconnected the default setting will be [111] and the device will output the
associated frequency highlighted in bold.
Freq Select Bits [FS2, FS1, FS0] - Default is [111]
Freq (MHz)
000
001
010
011
100
101
110
111
CLK1
100
NA
NA
NA
NA
NA
NA
125
CLK2
100
NA
NA
NA
NA
NA
NA
125
Table 1. Pin-Selectable Output Frequencies
Absolute Maximum Ratings
Item
Min.
Max.
Units
Supply Voltage
-0.3
+4.0
V
Input Voltage
-0.3
VDD + 0.3
V
Junction Temp
-
+150
°C
Storage Temp
-55
+150
°C
Soldering Temp
-
+260
°C
ESD
HBM
MM
CDM
-
4000
400
1500
Condition
40sec max.
V
1000+ years of data retention on internal memory
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DSC2044FE2-F0018
Specifications (Unless specified otherwise: T = 25°C)
Parameter
Symbol
Condition
Min.
Typ.
Supply Voltage¹
VDD
Supply Current
IDD
OE pin low - output is disabled
21
Supply Current²
IDD
OE pin high - outputs are enabled
RL = 50Ohms, F01 = F02 = 156.25MHz
60
2.25
Max.
Units
3.6
V
23
mA
mA
Frequency Stability
F
Includes frequency variation due to initial
tolerance, temp. and power supply voltage
±25
ppm
Aging
F
First year (@ 25°C)
±5
ppm
T = 25°C
5
ms
0.25 x VDD
V
Startup Time³
tSU
Input Logic Levels
Input Logic High
Input Logic Low
VIH
VIL
4
0.75 x VDD
-
Output Disable Time
tDA
5
ns
Output Enable Time4
tEN
20
ns
Pull-Up Resistor²
Pull-up exists on all digital IO
40
kOhms
HCSL Outputs
Output Logic Levels
Output Logic High
Output Logic Low
VOH
VOL
Pk to Pk Output Swing
RL = 50Ohms
0.725
-
Single-Ended
0.1
750
V
mV
4
Output Transition Time
Rise Time
Fall Time
tR
tF
20% to 80%
RL = 50Ohms, CL = 2pF
Frequency
CLK1
CLK2
[FS2, FS1, FS0] = [1, 1, 1]
Output Duty Cycle
SYM
Differential
Period Jitter 5
JPER
F01 = F02 = 156.25MHz
2.8
Integrated Phase Noise
JPH
200kHz to 20MHz @ 156.25MHz
100kHz to 20MHz @ 156.25MHz
12kHz to 20MHz @ 156.25MHz
0.25
0.37
1.7
200
400
125
125
48
ps
MHz
52
%
psRMS
2
psRMS
Notes:
1. Pin 12 VDD2, and pin 13 VDD should be filtered with 0.1uF capacitors.
2. Output is enabled if OE pin is floated or not connected.
3. tSU is time to 100ppm stable output frequency after VDD is applied and outputs are enabled.
4. Output Waveform and Test Circuit figures below define the parameters.
5. Period Jitter includes crosstalk from adjacent output.
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DSC2044FE2-F0018
Nominal Performance Parameters (Unless specified otherwise: T = 25°C, VDD = 3.3V)
Figure 1. HCSL Phase Jitter (integrated phase noise)
HCSL Output Waveform
675
OE
Figure 2. HCSL Output Waveform
MSL 1 @ 260°C refer to JSTD-020C
Ramp-Up Rate (200°C to Peak Temp)
3°C/sec Max.
Preheat Time 150°C to 200°C
60 - 180 sec
Time maintained above 217°C
60 - 150 sec
Peak Temperature
255 - 260°C
Time within 5°C of actual Peak
20 - 40 sec
Ramp-Down Rate
6°C/sec Max.
Time 25°C to Peak Temperature
8 min Max.
April 27, 2015
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Revision 1.0
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Micrel, Inc.
DSC2044FE2-F0018
Solder Reflow Profile
Figure 3. Solder Reflow Profile
Package Information7
3.2mm x 2.5mm 14 Lead Plastic Package
Notes:
6. Connect the exposed die paddle to ground.
7. Package information is correct as of the publication date. For updates and most current information, go to www.micrel.com.
Micrel makes no representations or warranties with respect to the accuracy or completeness of the information furnished in this data
sheet. This information is not intended as a warranty and Micrel does not assume responsibility for its use. Micrel reserves the right
to change circuitry, specifications and descriptions at any time without notice. No license, whether express, implied, arising by
estoppel or otherwise, to any intellectual property rights is granted by this document. Except as provided in Micrel's terms and
conditions of sale for such products, Micrel assumes no liability whatsoever, and Micrel disclaims any express or implied warranty
relating to the sale and/or use of Micrel products including liability or warranties relating to fitness for a particular purpose,
merchantability, or infringement of any patent, copyright or other intellectual property right.
Micrel products are not designed or authorized for use as components in life support appliances, devices or systems where malfunction
of a product can reasonably be expected to result in personal injury. Life support devices or systems are devices or systems that (a)
are intended for surgical implant into the body or (b) support or sustain life, and whose failure to perform can be reasonably expected
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© 2015 Micrel, Incorporated.
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