LM301A, LM201A, LM201AV Non Compensated Single Operational Amplifiers A general purpose operational amplifier that allows the user to choose the compensation capacitor best suited to his needs. With proper compensation, summing amplifier slew rates to 10 V/ms can be obtained. http://onsemi.com Features MARKING DIAGRAMS • Low Input Offset Current: 20 nA Maximum Over Temperature • • • • • Range External Frequency Compensation for Flexibility Class AB Output Provides Excellent Linearity Output Short Circuit Protection Guaranteed Drift Characteristics Pb−Free Packages are Available 8 LMx01AN AWL YYWWG PDIP−8 N SUFFIX CASE 626 8 1 1 8 VEE Inverting Input 8 VCC Non− Inverting Input SOIC−8 D SUFFIX CASE 751 1 LMx01 ALYW G 1 Output + Balance Freq Compen 10 MW 30 pF Balance x A WL, L YY, Y WW, W G G 5.1 MW 20 k VEE = 2 or 3 = Assembly Location = Wafer Lot = Year = Work Week = Pb−Free Package = Pb−Free Package Figure 1. Standard Compensation and Offset Balancing Circuit PIN CONNECTIONS Balance VUT VCC Inputs + VEE VO 1 8 Compensation 2 7 VCC 3 6 Output 4 5 Balance (Top View) VI MZ4622 or Equiv. VEE VCC 3.9 V ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 2 of this data sheet. VO VLT VEE VO = 4.8 V for VLT ≤ VI ≤ VUT VO = −0.4 V VI < VLT or VI > VUT (Pins Not Shown Are Not Connected) Figure 2. Double−Ended Limit Detector © Semiconductor Components Industries, LLC, 2005 July, 2005 − Rev. 10 1 Publication Order Number: LM301A/D LM301A, LM201A, LM201AV Balance Compensation VCC Inputs + 500 25 Output 50 450 40k 5k 20 k 250 40k 10 k 80 k 1.0 k VEE Balance Figure 3. Representative Circuit Schematic ORDERING INFORMATION Package Shipping † SOIC−8 98 Units/Rail LM301ADG SOIC−8 (Pb−Free) 98 Units/Rail LM301ADR2 SOIC−8 2500 Tape & Reel SOIC−8 (Pb−Free) 2500 Tape & Reel PDIP−8 50 Units/Rail PDIP−8 (Pb−Free) 50 Units/Rail SOIC−8 98 Units/Rail LM201ADG SOIC−8 (Pb−Free) 98 Units/Rail LM201ADR2 SOIC−8 2500 Tape & Reel SOIC−8 (Pb−Free) 2500 Tape & Reel PDIP−8 50 Units/Rail PDIP−8 (Pb−Free) 50 Units/Rail SOIC−8 2500 Tape & Reel SOIC−8 (Pb−Free) 2500 Tape & Reel Device LM301AD LM301ADR2G LM301AN LM301ANG LM201AD LM201ADR2G LM201AN LM201ANG LM201AVDR2 LM201AVDR2G †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. http://onsemi.com 2 LM301A, LM201A, LM201AV MAXIMUM RATINGS Value Rating Power Supply Voltage Symbol LM201A LM201AV LM301A Unit VCC, VEE ±22 ±22 ±18 Vdc Input Differential Voltage VID ±30 V Input Common Mode Range (Note 1) VICR ±15 V Output Short Circuit Duration tSC Continuous Power Dissipation (Package Limitation) PD Plastic Dual−In−Line Package Derate above TA = +25°C 625 5.0 Operating Ambient Temperature Range TA Storage Temperature Range Tstg −25 to +85 625 5.0 625 5.0 mW mW/°C −40 to +105 0 to +70 °C °C −65 to +150 Maximum ratings are those values beyond which device damage can occur. Maximum ratings applied to the device are individual stress limit values (not normal operating conditions) and are not valid simultaneously. If these limits are exceeded, device functional operation is not implied, damage may occur and reliability may be affected. ELECTRICAL CHARACTERISTICS (TA = +25°C, unless otherwise noted.) Unless otherwise specified, these specifications apply for supply voltages from ± 5.0 V to ± 20 V for the LM201A and LM201AV, and from ± 5.0 V to ±15 V for the LM301A. LM201A / LM201AV LM301A Symbol Min Typ Max Min Typ Max Unit Input Offset Voltage (RS ≤ 50 kW) VIO − 0.7 2.0 − 2.0 7.5 mV Input Offset Current IIO − 1.5 10 − 3.0 50 nA Input Bias Current IIB − 30 75 − 70 250 nA Input Resistance ri 1.5 4.0 − 0.5 2.0 − MW − − 1.8 − 3.0 − − − − 1.8 − 3.0 50 160 − 25 160 − V/mV Characteristic Supply Current VCC/VEE = ± 20 V VCC/VEE = ±15 V Large Signal Voltage Gain (VCC/VEE = ±15 V, VO = ±10 V, RL > 2.0 kW) ICC,IEE AV mA The following specifications apply over the operating temperature range. Input Offset Voltage (RS ≤ 50 kW) VIO − − 3.0 − − 10 mV Input Offset Current IIO − − 20 − − 70 nA Avg Temperature Coefficient of Input Offset Voltage (Note 2) TA(min) ≤ TA ≤ TA (max) DVIO/DT − 3.0 15 − 6.0 30 mV/°C Avg Temperature Coefficient of Input Offset Current (Note 2) +25°C ≤ TA ≤ TA (max) TA(min) ≤ TA ≤ 25°C DIIO/DT nA/°C − − 0.01 0.02 0.1 0.2 − − 0.01 0.02 0.3 0.6 IIB − − 100 − − 300 nA Large Signal Voltage Gain (VCC/VEE = ±15 V, VO = ±10V, RL > 2.0 kW) AVOL 25 − − 15 − − V/mV Input Voltage Range VCC/VEE = ± 20 V VCC/VEE = ±15 V VICR −15 − − − +15 − − −12 − − − +12 Common Mode Rejection (RS ≤ 50 kW) CMR 80 96 − 70 90 − dB Supply Voltage Rejection (RS ≤ 50 kW) PSR 80 96 − 70 96 − dB VO ±12 ±10 ±14 ±13 − − ±12 ±10 ±14 ±13 − − V ICC,IEE − 1.2 2.5 − − − mA Input Bias Current Output Voltage Swing (VCC/VEE = ±15 V, RL = ±10 kW, RL > 2.0 kW) Supply Currents (TA = TA(max), VCC/VEE = ± 20 V) V 1. For supply voltages less than ±15 V, the absolute maximum input voltage is equal to the supply voltage. 2. Guaranteed by design. http://onsemi.com 3 VIR, INPUT VOLTAGE RANGE (V) 20 VOR, OUTPUT VOLTAGE RANGE ( ± V) LM301A, LM201A, LM201AV Applicable to the Specified Operating Temperature Ranges 16 12 LM201A only Positive 8.0 Negative 4.0 0 0 5.0 10 15 VCC, ( −VEE), SUPPLY VOLTAGE (V) 20 Applicable to the Specified Operating Temperature Ranges 16 12 Minimum RL = 10 k 8.0 Minimum RL = 2.0 k 4.0 0 20 0 5.0 10 15 VCC, ( −VEE), SUPPLY VOLTAGE (V) Figure 4. Minimum Input Voltage Range 20 Figure 5. Minimum Output Voltage Swing 100 2.5 I CC , I EE, SUPPLY CURRENTS (mA) Applicable to the Specified Operating Temperature Ranges 94 AV, VOLTAGE GAIN (dB) LM201A only 88 LM201A only 82 76 2.0 1.5 5.0 10 15 TA = +25°C 0.5 70 0 LM201A only 1.0 0 20 0 5.0 10 15 VCC, ( −VEE), SUPPLY VOLTAGE (V) VCC, ( −VEE), SUPPLY VOLTAGE (V) Figure 6. Minimum Voltage Gain Figure 7. Typical Supply Currents 20 Single−Pole Compensation AV , VOLTAGE GAIN (dB) 160 140 315 120 270 100 80 C1 = 3.0 pF 225 Phase 180 60 135 C1 = 30 pF 40 20 0 −20 1.0 90 0 10 100 1.0 k 10 k 100 k 1.0 M Single−Pole Compensation 15 10 C1 = 3.0 pF 5.0 45 Gain VOR, OUTPUT VOLTAGE RANGE ( ±V) 180 C1 = 30 pF 0 1.0 k 10 M 10 k 100 k 1.0 M 10 M f, FREQUENCY (Hz) f, FREQUENCY (Hz) Figure 8. Open Loop Frequency Response Figure 9. Large Signal Frequency Response http://onsemi.com 4 LM301A, LM201A, LM201AV 140 8.0 6.0 4.0 2.0 Input 0 −2.0 Output −4.0 −6.0 100 225 80 180 Phase 60 135 40 90 20 45 Gain 0 −8.0 −10 0 10 20 30 40 50 60 70 80 0 0 −20 10 90 100 1.0 k 10 k 100 k 1.0 M 10 M 100 M t, TIME (ms) f, FREQUENCY (Hz) Figure 10. Voltage Follower Pulse Response Figure 11. Open Loop Frequency Response 10 VOR, OUTPUT VOLTAGE RANGE ( ± V) 18 VOR, OUTPUT VOLTAGE RANGE ( ± V) Feedforward Compensation 120 PHASE LAG (DEGREES) Single−Pole Compensation A V, VOLTAGE GAIN (dB) VIR , VOR, VOLTAGE RANGE ( ±V) 10 Feedforward Compensation 16 12 8.0 4.0 0 100 k Feedforward Compensation 8.0 Output 6.0 4.0 2.0 Input 0 −2.0 −4.0 −6.0 −8.0 −10 1.0 M f, FREQUENCY (Hz) 10 M 0 Figure 12. Large Signal Frequency Response 1.0 2.0 3.0 4.0 5.0 t, TIME (ms) 6.0 7.0 8.0 Figure 13. Inverter Pulse Response C2 R2 R1 −VI R2 VCC 2 R1 6 R3 +VI 7 3 VI VO C1 C1 ≥ 4 + 8 Frequency Compensation 1 R3 R1 Cs R1 +R2 C1 150 pF Cs = 30 pF VCC 6 3 + 4 1 VEE Balance 7 2 VO VEE Balance C2 = 1 2πfoR2 fo = 3.0 MHz Figure 14. Single−Pole Compensation Figure 15. Feedforward Compensation http://onsemi.com 5 9.0 LM301A, LM201A, LM201AV PACKAGE DIMENSIONS PDIP−8 N SUFFIX CASE 626−05 ISSUE L 8 NOTES: 1. DIMENSION L TO CENTER OF LEAD WHEN FORMED PARALLEL. 2. PACKAGE CONTOUR OPTIONAL (ROUND OR SQUARE CORNERS). 3. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 5 −B− 1 4 F −A− NOTE 2 L C J −T− N SEATING PLANE D H M K G 0.13 (0.005) M T A M B M http://onsemi.com 6 DIM A B C D F G H J K L M N MILLIMETERS MIN MAX 9.40 10.16 6.10 6.60 3.94 4.45 0.38 0.51 1.02 1.78 2.54 BSC 0.76 1.27 0.20 0.30 2.92 3.43 7.62 BSC −−− 10_ 0.76 1.01 INCHES MIN MAX 0.370 0.400 0.240 0.260 0.155 0.175 0.015 0.020 0.040 0.070 0.100 BSC 0.030 0.050 0.008 0.012 0.115 0.135 0.300 BSC −−− 10_ 0.030 0.040 LM301A, LM201A, LM201AV SOIC−8 D SUFFIX CASE 751−07 ISSUE AG NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. 751−01 THRU 751−06 ARE OBSOLETE. NEW STANDARD IS 751−07. −X− A 8 5 S B 1 0.25 (0.010) M Y M 4 K −Y− G C N DIM A B C D G H J K M N S X 45 _ SEATING PLANE −Z− 0.10 (0.004) H M D 0.25 (0.010) M Z Y S X J S SOLDERING FOOTPRINT* 1.52 0.060 7.0 0.275 4.0 0.155 0.6 0.024 1.270 0.050 SCALE 6:1 mm Ǔ ǒinches *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. http://onsemi.com 7 MILLIMETERS MIN MAX 4.80 5.00 3.80 4.00 1.35 1.75 0.33 0.51 1.27 BSC 0.10 0.25 0.19 0.25 0.40 1.27 0_ 8_ 0.25 0.50 5.80 6.20 INCHES MIN MAX 0.189 0.197 0.150 0.157 0.053 0.069 0.013 0.020 0.050 BSC 0.004 0.010 0.007 0.010 0.016 0.050 0 _ 8 _ 0.010 0.020 0.228 0.244 LM301A, LM201A, LM201AV ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATION ORDERING INFORMATION LITERATURE FULFILLMENT: N. American Technical Support: 800−282−9855 Toll Free Literature Distribution Center for ON Semiconductor USA/Canada P.O. Box 61312, Phoenix, Arizona 85082−1312 USA Phone: 480−829−7710 or 800−344−3860 Toll Free USA/Canada Japan: ON Semiconductor, Japan Customer Focus Center 2−9−1 Kamimeguro, Meguro−ku, Tokyo, Japan 153−0051 Fax: 480−829−7709 or 800−344−3867 Toll Free USA/Canada Phone: 81−3−5773−3850 Email: [email protected] http://onsemi.com 8 ON Semiconductor Website: http://onsemi.com Order Literature: http://www.onsemi.com/litorder For additional information, please contact your local Sales Representative. LM301A/D