Samsung K6T8008C2M-TF70 1mx8 bit low power and low voltage cmos static ram Datasheet

K6T8008C2M Family
CMOS SRAM
Document Title
1Mx8 bit Low Power and Low Voltage CMOS Static RAM
Revision History
Revision No. History
Draft Date
Remark
0.0
Initial draft
June 22, 1999
Advance
1.0
Finalize
- Adopt New Code system.
- Improve VIN, VOUT max. on A
’ BSOLUTE MAXIMUM RATINGS’from
7.0V to VCC+0.5V.
- Change Icc: from 12 to 10mA
- Change Icc1: from 10 to 12mA
February 29, 2000
Final
The attached datasheets are provided by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the specifications and
products. SAMSUNG Electronics will answer to yourquestions about device. If you have any questions, please contact the SAMSUNG branch offices.
1
Revision 1.00
February 2000
K6T8008C2M Family
CMOS SRAM
1Mx8 bit Low Power and Low Voltage CMOS Static RAM
FEATURES
GENERAL DESCRIPTION
• Process Technology: TFT
• Organization: 1M x8
• Power Supply Voltage: 4.5~5.5V
• Low Data Retention Voltage: 2.0V(Min)
• Three state output and TTL Compatible
• Package Type: 44-TSOP2-400F/R
The K6T8008C2M families are fabricated by SAMSUNG′s
advanced CMOS process technology. The families support
industrial operating temperature ranges for user flexibility of
system design. The families also support low data retention
voltage for battery back-up operation with low data retention
current.
PRODUCT FAMILY
Power Dissipation
Product Family
Operating Temperature
K6T8008C2M-B
Commercial(0~70°C)
K6T8008C2M-F
Industrial(-40~85°C)
Vcc Range
Speed
4.5~5.5V
55 1)/70ns
Standby
(ISB1, Max)
Operating
(ICC2, Max)
50µA
70mA
PKG Type
44-TSOP2-400F/R
80µA
1. The parameter is measured with 50pF test load.
PIN DESCRIPTION
FUNCTIONAL BLOCK DIAGRAM
Clk gen.
A4
A3
A2
A1
A0
CS1
NC
NC
I/O1
I/O2
Vcc
Vss
I/O3
I/O4
NC
NC
WE
A19
A18
A17
A16
A15
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
44-TSOP2
Forward
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
A5
A6
A7
OE
CS2
A8
NC
NC
I/O8
I/O7
Vss
Vcc
I/O6
I/O5
NC
NC
A9
A10
A11
A12
A13
A14
A5
A6
A7
OE
CS2
A8
NC
NC
I/O8
I/O7
Vss
Vcc
I/O6
I/O5
NC
NC
A9
A10
A11
A12
A13
A14
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
44-TSOP2
Reverse
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
A4
A3
A2
A1
A0
CS1
NC
NC
I/O1
I/O2
Vcc
Vss
I/O3
I/O4
NC
NC
WE
A19
A18
A17
A16
A15
Precharge circuit.
Vcc
Vss
Row
Addresses
I/O 1~I/O8
Row
select
Data
cont
Memory array
1024 rows
1024×8 columns
I/O Circuit
Column select
Data
cont
Column Addresses
Name
CS1, CS 2
Function
Name
Function
Chip Select Inputs
Vcc
Power
OE
Output Enable Input
Vss
Ground
WE
Write Enable Input
I/O 1~I/O8
Data Inputs/Outputs
A0~A19 Address Inputs
NC
No Connect
CS1
CS2
OE
Control Logic
WE
SAMSUNG ELECTRONICS CO., LTD. reserves the right to change products and specifications without notice.
2
Revision 1.00
February 2000
K6T8008C2M Family
CMOS SRAM
PRODUCT LIST
Commercial Temperature Products(0~70°C)
Part Name
Industrial Temperature Products(-40~85°C)
Function
Part Name
Function
K6T8008C2M-TB55
K6T8008C2M-TB70
44-TSOP2-F, 55ns, 5.0V, LL
44-TSOP2-F, 70ns, 5.0V, LL
K6T8008C2M-TF55
K6T8008C2M-TF70
44-TSOP2-F, 55ns, 5.0V, LL
44-TSOP2-F, 70ns, 5.0V, LL
K6T8008C2M-RB55
K6T8008C2M-RB70
44-TSOP2-R, 55ns, 5.0V, LL
44-TSOP2-R, 70ns, 5.0V, LL
K6T8008C2M-RF55
K6T8008C2M-RF70
44-TSOP2-R, 55ns, 5.0V, LL
44-TSOP2-R, 70ns, 5.0V, LL
FUNCTIONAL DESCRIPTION
CS1
CS2
OE
WE
I/O1~8
Mode
Power
H
X
X
X
High-Z
Deselected
Standby
X
L
X
X
High-Z
Deselected
Standby
L
H
H
H
High-Z
Output Disabled
Active
L
H
L
H
Dout
Read
Active
L
H
X
L
Din
Write
Active
Note: X means don′t care. (Must be low or high state)
ABSOLUTE MAXIMUM RATINGS1)
Item
Voltage on any pin relative to Vss
Voltage on Vcc supply relative to Vss
Power Dissipation
Storage temperature
Operating Temperature
Symbol
Ratings
Unit
Remark
VIN, VOUT
-0.5 to VCC+0.5V
V
-
VCC
-0.3 to 7.0
V
-
PD
1.0
W
-
TSTG
-65 to 150
°C
-
0 to 70
°C
K6T8008C2M-B
-40 to 85
°C
K6T8008C2M-F
TA
1. Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. Functional operation should be
restricted to recommended operating condition. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
3
Revision 1.00
February 2000
K6T8008C2M Family
CMOS SRAM
RECOMMENDED DC OPERATING CONDITIONS1)
Symbol
Product
Min
Typ
Max
Unit
Supply voltage
Item
Vcc
K6T8008C2M Family
4.5
5.0
5.5
V
Ground
Vss
All Family
0
0
0
Input high voltage
VIH
K6T8008C2M Family
2.2
-
Input low voltage
VIL
K6T8008C2M Family
-0.5
3)
V
Vcc+0.5
-
V
2)
0.8
V
Note:
1. Commercial Product: T A=0 to 70°C, otherwise specified.
Industrial Product: TA=-40 to 85°C, otherwise specified.
2. Overshoot: VCC+3.0V in case of pulse width ≤30ns.
3. Undershoot: -3.0V in case of pulse width ≤30ns.
4. Overshoot and undershoot are sampled, not 100% tested.
CAPACITANCE 1) (f=1MHz, TA=25°C)
Item
Symbol
Test Condition
Min
Max
Unit
Input capacitance
CIN
VIN=0V
-
8
pF
Input/Output capacitance
CIO
VIO=0V
-
10
pF
1. Capacitance is sampled, not 100% tested.
DC AND OPERATING CHARACTERISTICS
Item
Symbol
Test Conditions
Min
Typ
Max
Unit
Input leakage current
ILI
VIN=Vss to Vcc
-1
-
1
µA
Output leakage current
ILO
CS1=VIH, CS2=VIL or OE=VIH or WE=VIL, VIO=Vss to Vcc
-1
-
1
µA
Operating power supply current
ICC
IIO=0mA, CS1=VIL, CS2=VIH, WE=VIH, VIN=VIH or VIL
-
-
10
mA
ICC1
Cycle time=1µs, 100%duty, IIO=0mA, CS1≤0.2V,
CS2≥Vcc-0.2V, VIN≤0.2V or VIN≥VCC-0.2V
-
-
12
mA
ICC2
Cycle time=Min, IIO=0mA, 100% duty, CS1=VIL, CS2=VIH,
VIN=VIL or V IH
-
-
70
mA
Average operating current
Output low voltage
VOL
IOL = 2.1mA
-
-
0.4
V
Output high voltage
VOH
IOH = -1.0mA
2.4
-
-
V
Standby Current(TTL)
ISB
CS1=VIH, CS2=VIL, Other inputs=VIH or VIL
Standby Current(CMOS)
ISB1
CS≥Vcc-0.2V, Other inputs=0~Vcc
4
-
-
3
mA
K6T8008C2M-B
-
-
50
µA
K6T8008C2M-F
-
-
80
Revision 1.00
February 2000
K6T8008C2M Family
CMOS SRAM
AC OPERATING CONDITIONS
TEST CONDITIONS(Test Load and Input/Output Reference)
Input pulse level: 0.4 to 2.2V
Input rising and falling time: 5ns
Input and output reference voltage: 1.5V
Output load(see right): CL=100pF+1TTL
CL=50pF+1TTL
CL1)
1.Including scope and jig capacitance
AC CHARACTERISTICS (VCC=4.5~5.5V, Commercial product: TA=0 to 70°C, Industrial product: TA=-40 to 85°C)
Speed Bins
Parameter List
Symbol
55ns
Min
Read
Max
Min
Max
Read Cycle Time
tRC
55
-
70
-
ns
Address Access Time
tAA
-
55
-
70
ns
Chip Select to Output
tCO
-
55
-
70
ns
Output Enable to Valid Output
tOE
-
25
-
35
ns
Chip Select to Low-Z Output
Output Enable to Low-Z Output
Chip Disable to High-Z Output
tLZ
10
-
10
-
ns
tOLZ
5
-
5
-
ns
tHZ
0
20
0
25
ns
tOHZ
0
20
0
25
ns
Output Hold from Address Change
tOH
10
-
10
-
ns
Write Cycle Time
tWC
55
-
70
-
ns
Chip Select to End of Write
tCW
45
-
60
-
ns
Output Disable to High-Z Output
Write
Units
70ns
Address Set-up Time
tAS
0
-
0
-
ns
Address Valid to End of Write
tAW
45
-
60
-
ns
Write Pulse Width
tWP
40
-
50
-
ns
Write Recovery Time
tWR
0
-
0
-
ns
Write to Output High-Z
tWHZ
0
20
0
20
ns
Data to Write Time Overlap
tDW
25
-
30
-
ns
Data Hold from Write Time
tDH
0
-
0
-
ns
End Write to Output Low-Z
tOW
5
-
5
-
ns
Max
Unit
DATA RETENTION CHARACTERISTICS
Item
Symbol
Vcc for data retention
VDR
Data retention current
IDR
Data retention set-up time
tSDR
Recovery time
tRDR
Test Condition
CS1≥Vcc-0.2V1)
Vcc=3.0V,
CS1≥Vcc-0.2V1)
See data retention waveform
Min
Typ
2.0
-
5.5
V
-
-
202)
µA
0
-
-
5
-
-
ms
1. CS1 ≥Vcc-0.2V,CS2 ≥Vcc-0.2V(CS1 controlled) or CS 2≥Vcc-0.2V(CS2 controlled).
2. Industrial product=30µA
5
Revision 1.00
February 2000
K6T8008C2M Family
CMOS SRAM
TIMING DIAGRAMS
TIMING WAVEFORM OF READ CYCLE(1) (Address Controlled, CS1=OE=VIL, CS2=WE=VIH)
tRC
Address
tAA
tOH
Data Out
Data Valid
Previous Data Valid
TIMING WAVEFORM OF READ CYCLE(2) (WE=VIH)
tRC
Address
tOH
tAA
tCO1
CS1
tHZ(1,2)
CS2
tCO2
tOE
OE
Data out
High-Z
tOHZ
tOLZ
tLZ
Data Valid
NOTES (READ CYCLE)
1. tHZ and tOHZ are defined as the time at which the outputs achieve the open circuit conditions and are not referenced to output voltage
levels.
2. At any given temperature and voltage condition, tHZ(Max.) is less than tLZ (Min.) both for a given device and from device to device
interconnection.
6
Revision 1.00
February 2000
K6T8008C2M Family
CMOS SRAM
TIMING WAVEFORM OF WRITE CYCLE(1) (WE Controlled)
tWC
Address
tWR(4)
tCW(2)
CS 1
tAW
CS 2
tCW(2)
tWP(1)
WE
tAS(3)
tDW
tDH
Data Valid
Data in
tWHZ
Data out
tOW
Data Undefined
TIMING WAVEFORM OF WRITE CYCLE(2) (CS1
Controlled)
tWC
Address
tAS(3)
tCW(2)
tWR(4)
CS 1
tAW
CS 2
tWP(1)
WE
tDW
Data in
Data out
tDH
Data Valid
High-Z
High-Z
7
Revision 1.00
February 2000
K6T8008C2M Family
CMOS SRAM
TIMING WAVEFORM OF WRITE CYCLE(3) (CS2 Controlled)
tWC
Address
tAS(3)
tCW(2)
tWR(4)
CS1
tAW
CS2
tCW(2)
tWP(1)
WE
tDW
Data in
Data out
tDH
Data Valid
High-Z
High-Z
NOTES (WRITE CYCLE)
1. A write occurs during the overlap of a low CS1 , a high CS2 and a low WE. A write begins at the latest transition among CS1 goes low,
CS2 going high and WE going low : A write end at the earliest transition among CS1 going high, CS 2 going low and WE going high,
tWP is measured from the begining of write to the end of write.
2. tCW is measured from the CS1 going low or CS2 going high to the end of write.
3. tAS is measured from the address valid to the beginning of write.
4. tWR is measured from the end of write to the address change. tWR applied in case a write ends as CS1 or WE going high tWR2 applied
in case a write ends as CS2 going to low.
DATA RETENTION WAVE FORM
CS1 controlled
VCC
tSDR
Data Retention Mode
tRDR
4.5V
2.4V
VDR
CS1≥VCC - 0.2V
CS1
GND
CS2 controlled
Data Retention Mode
VCC
4.5V
CS 2
tSDR
tRDR
VDR
0.4V
CS2≤0.2V
GND
8
Revision 1.00
February 2000
K6T8008C2M Family
CMOS SRAM
PACKAGE DIMENSIONS
Unit: millimeters(inches)
44 PIN THIN SMALL OUTLINE PACKAGE TYPE II (400F)
0~8°
0.25
(
)
0.010
#44
#23
10.16
0.400
0.45 ~0.75
0.018 ~ 0.030
11.76±0.20
0.463±0.008
( 0.50 )
0.020
#1
#22
1.00±0.10
0.039±0.004
1.20
MAX.
0.047
( 0.805 )
0.032
0.35± 0.10
0.014±0.004
0.80
0.0315
0.0
0.10 MAX
0.004
0.05
MIN.
0.002
18.81
MAX.
0.741
18.41±0.10
0.725±0.004
0
+ 0.1
5
- 0.0
04
.0
+0
06 - 0.002
0.15
0~8°
44 PIN THIN SMALL OUTLINE PACKAGE TYPE II (400R)
(
#1
0.25
)
0.010
#22
10.16
0.400
0.45 ~0.75
0.018 ~ 0.030
11.76±0.20
0.463±0.008
( 0.50 )
0.020
#44
#23
1.00±0.10
0.039±0.004
1.20
MAX.
0.047
( 0.805 )
0.032
0.35±0.10
0.014±0.004
0.80
0.0315
0.05
MIN.
0.002
18.81
MAX.
0.741
18.41± 0.10
0.725±0.004
9
0
+ 0.1
5
- 0.0
04
.0
+0
02
.006 - 0.0
0.15
0
0.10
0.004 MAX
Revision 1.00
February 2000
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