AD ADS1174 ADS1178 AD S1 174 S1 17 8 SBAS373 – OCTOBER 2007 Quad/Octal, Simultaneous Sampling, 16-Bit Analog-to-Digital Converters FEATURES 1 APPLICATIONS • • • • 3-Phase Power Monitors Defibrillators and ECG Monitors Coriolis Flow Meters Vibration/Modal Analysis VREFP VREFN Input1 DS Input2 DS Input3 DS Input4 DS AVDD DVDD The ADS1174 (quad) and ADS1178 (octal) are multiple delta-sigma (ΔΣ) analog-to-digital converters (ADCs) with data rates up to 52k samples-per-second (SPS), which allow synchronous sampling of four and eight channels. These devices use identical packages, permitting drop-in expandability. The delta-sigma architecture offers near ideal 16-bit ac performance (97dB SNR, –105dB THD, 1LSB linearity) combined with 0.005dB passband ripple, and linear phase response. The high-order, chopper- stabilized modulator achieves very low drift (4μV/°C offset, 4ppm/°C gain) and low noise (1LSBPP). The on-chip finite impulse response (FIR) filter provides a usable signal bandwidth up to 90% of the Nyquist rate with 100dB of stop band attenuation while suppressing modulator and signal out-of-band noise. Two operating modes allow for optimization of speed and power: High-speed mode (32mW/Ch at 52kSPS), and Low-power mode (8mW/Ch at 10kSPS). A SYNC input control pin allows the device conversions to be started and synchronized to an external event. SPI and Frame-Sync serial interfaces are supported. The device is fully specified over the extended industrial range (–40°C to +105°C) and is available in an HTQFP-64 PowerPAD™ package. IOVDD SPI and FrameSync Interface Four Digital Filters Control Logic AGND DESCRIPTION DGND ADS1174 VREFP VREFN AVDD DRDY/FSYNC SCLK DOUT[4:1] DIN TEST[1:0] FORMAT[2:0] CLK SYNC PWDN[4:1] CLKDIV MODE Input1 DS Input2 DS Input3 DS Input4 DS Input5 DS Input6 DS Input7 DS Input8 DS AGND DVDD IOVDD SPI and FrameSync Interface DRDY/FSYNC SCLK DOUT[8:1] DIN Control Logic TEST[1:0] FORMAT[2:0] CLK SYNC PWDN[8:1] CLKDIV MODE Eight Digital Filters DGND ADS1178 1 2 3 4 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PowerPAD is a trademark of Texas Instruments. SPI is a trademark of Motorola, Inc. All other trademarks are the property of their respective owners. PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice. Copyright © 2007, Texas Instruments Incorporated PRODUCT PREVIEW • Synchronously Sample Four/Eight Channels • Selectable Operating Modes: High-Speed: 52kSPS Data Rate, 30mW/ch Low-Power: 10kSPS Data Rate, 8mW/ch • AC Performance: 25kHz Bandwidth 97dB SNR –105dB THD • Digital Filter: Linear Phase Response Passband Ripple: ±0.005dB Stop Band Attenuation: 100dB • Selectable SPI™ or Frame Sync Serial Interface • Simple Pin-Driven Control • Low Sampling Aperture Error • Specified from –40°C to +105°C • Analog Supply: 5V • I/O Supply: 1.8V to 3.3V • Digital Core Supply: 1.8V 234 ADS1174 ADS1178 www.ti.com SBAS373 – OCTOBER 2007 This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. ORDERING INFORMATION For the most current package and ordering information see the Package Option Addendum at the end of this document, or see the TI web site at www.ti.com. ABSOLUTE MAXIMUM RATINGS over operating free-air temperature range unless otherwise noted (1) ADS1174, ADS1178 UNIT AVDD to AGND –0.3 to +6.0 V DVDD, IOVDD to DGND –0.3 to +3.6 V AGND to DGND –0.3 to +0.3 V 100, Momentary mA 10, Continuous mA Analog Input to AGND –0.3 to AVDD + 0.3 V Digital Input or Output to DGND –0.3 to DVDD + 0.3 V Input Current PRODUCT PREVIEW +150 °C Operating Temperature Range –40 to +105 °C Storage Temperature Range –60 to +150 °C Maximum Junction Temperature (1) 2 Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods may degrade device reliability. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those specified is not implied. Submit Documentation Feedback Copyright © 2007, Texas Instruments Incorporated Product Folder Link(s): ADS1174 ADS1178 ADS1174 ADS1178 www.ti.com SBAS373 – OCTOBER 2007 ELECTRICAL CHARACTERISTICS All specifications at TA = –40°C to +105°C, AVDD = +5V, DVDD = +1.8V, IOVDD = +3.3V, fCLK = 27MHz, VREFP = 2.5V, VREFN = 0V, and all channels active, unless otherwise noted. ADS1174, ADS1178 PARAMETER TEST CONDITIONS MIN TYP MAX UNIT ANALOG INPUTS Full-scale input voltage (FSR (1)) VIN = (AINP – AINN) Absolute input voltage AINP or AINN to AGND Common-mode input voltage VCM = (AINP + AINN)/2 Differential input impedance ±VREF AGND – 0.1 V AVDD + 0.1 V 2.5 V High-Speed mode 28 kΩ Low-Power mode 140 kΩ DC PERFORMANCE Data rate (fDATA) No missing codes 16 High-Speed mode Low-Power mode SPS 10,547 Integral nonlinearity (INL) Differential input Offset error Offset drift SPS 0.5 TBD 0.150 TBD LSB mV μV/°C 1.8 Offset match TBD Gain error 0.1 Gain drift mV TBD 2 Gain match % ppm/°C TBD Noise Shorted input Common-mode rejection Power-supply rejection Bits 52,734 1 PRODUCT PREVIEW Resolution % TBD LSBPP fCM = 60Hz 100 dB AVDD f = 60Hz 80 dB DVDD f = 60Hz 80 dB VIN = 1kHz, –0.5dBFS 107 dB AC PERFORMANCE Crosstalk Sampling aperture match Signal-to-noise ratio (SNR) (unweighted) Total harmonic distortion (THD) (2) High-Speed mode VIN = 1kHz, –0.5dBFS Spurious-free dynamic range 200 ps 97 dB –105 dB –108 Passband ripple Passband –3dB Bandwidth Stop band attenuation Hz 0.49 fDATA Hz dB 0.547 fDATA Group delay Settling time (latency) Complete settling dB 0.453 fDATA 100 Stop band (1) (2) dB ±0.005 63.453 fDATA Hz 38/fDATA s 76/fDATA s FSR = full-scale range = 2VREF THD includes the first nine harmonics of the input signal. Submit Documentation Feedback Copyright © 2007, Texas Instruments Incorporated Product Folder Link(s): ADS1174 ADS1178 3 ADS1174 ADS1178 www.ti.com SBAS373 – OCTOBER 2007 ELECTRICAL CHARACTERISTICS (continued) All specifications at TA = –40°C to +105°C, AVDD = +5V, DVDD = +1.8V, IOVDD = +3.3V, fCLK = 27MHz, VREFP = 2.5V, VREFN = 0V, and all channels active, unless otherwise noted. ADS1174, ADS1178 PARAMETER TEST CONDITIONS MIN TYP 0.5 2.5 MAX UNIT VOLTAGE REFERENCE INPUTS Reference input voltage (VREF) 3.1 V Negative reference input (VREFN) VREF = VREFP – VREFN AGND – 0.1 VREFP – 0.5 V Positive reference input (VREFP) VREFN + 0.5 AVDD + 0.1 ADS1174 Reference Input impedance High-Speed mode Low-Power mode 13 ADS1178 Reference Input impedance High-Speed mode 1.3 Low-Power mode 6.5 V 2.6 kΩ kΩ DIGITAL INPUT/OUTPUT (IOVDD = 1.8V to 3.6V) VIH 0.7 IOVDD IOVDD V VIL DGND 0.3 IOVDD V IOH = 5mA 0.8 IOVDD IOVDD V IOL = 5mA DGND 0.2 IOVDD V ±10 μA 27 MHz VOH VOL Input leakage 0 < VIN DIGITAL < IOVDD PRODUCT PREVIEW Master clock rate (fCLK) 0.1 POWER SUPPLY AVDD 4.75 5 5.25 V DVDD 1.65 1.8 1.95 V IOVDD 1.65 3.3 3.6 V High-Speed mode 22 TBD mA Low-Power mode 5 TBD mA Power-Down mode 1 TBD μA High-Speed mode 40 TBD mA Low-Power mode 9 TBD mA Power-Down mode 1 TBD μA High-Speed mode 9 TBD mA Low-Power mode mA ADS1174 AVDD current ADS1178 AVDD current ADS1174 DVDD current ADS1178 DVDD current 2.5 TBD Power-Down mode 1 TBD μA High-Speed mode 17 TBD mA Low-Power mode 4.5 TBD mA 1 TBD μA High-Speed mode 100 TBD μA Low-Power mode 100 TBD μA 1 TBD μA High-Speed mode 150 TBD μA Low-Power mode 150 TBD μA 1 TBD μA 125 TBD mW Power-Down mode ADS1174 IOVDD current Power-Down mode ADS1178 IOVDD current Power-Down mode ADS1174 Power dissipation High-Speed mode Low-Power mode 32 TBD mW ADS1178 Power dissipation High-Speed mode 225 TBD mW Low-Power mode 60 TBD mW 4 Submit Documentation Feedback Copyright © 2007, Texas Instruments Incorporated Product Folder Link(s): ADS1174 ADS1178 ADS1174 ADS1178 www.ti.com SBAS373 – OCTOBER 2007 ADS1174/ADS1178 PIN ASSIGNMENTS AGND AVDD AINN5(1) AINP5(1) AINN6(1) AINP6(1) 54 53 52 51 50 49 AINP2 1 48 AINN7(1) AINN2 2 47 AINP7(1) AINP1 3 46 AINN8(1) AINN1 4 45 AINP8(1) AVDD 5 44 AVDD AGND 6 43 AGND DGND 7 42 PWDN1 TEST0 8 41 PWDN2 TEST1 9 40 PWDN3 39 PWDN4 ADS1174/ADS1178 NOTE: (1) Boldface pin names are for ADS1178 only; see pin descriptions. CLKDIV 10 SYNC 11 38 PWDN5(1) DIN 12 37 PWDN6(1) DOUT8(1) 13 36 PWDN7(1) DOUT7(1) 14 35 PWDN8(1) DOUT6(1) 15 34 MODE DOUT5(1) 16 33 IOVDD 23 24 25 26 27 28 29 30 IOVDD DGND DGND DVDD CLK SCLK DRDY/FSYNC FORMAT2 32 22 IOVDD FORMAT0 21 DGND 31 20 DOUT1 FORMAT1 19 18 DOUT3 DOUT2 17 DOUT4 (PowerPAD Outline) PRODUCT PREVIEW VREFP VREFN 57 VCOM AGND 58 55 AGND 59 56 AINP4 AVDD AINN4 62 60 AINP3 63 61 AINN3 64 PAP PACKAGE HTQFP-64 (TOP VIEW) ADS1174/ADS1178 PIN DESCRIPTIONS PIN NAME NO. FUNCTION AGND 6, 43, 54, 58, 59 DESCRIPTION Analog ground AINP1 3 Analog input AINP2 1 Analog input AINP3 63 Analog input AINP4 61 Analog input AINP5 51 Analog input AINP6 49 Analog input AINP7 47 Analog input AINP8 45 Analog input Analog ground; connect to DGND using a single plane. ADS1178: AINP[8:1] Positive analog input, channels 8 through 1. ADS1174: AINP[8:5] Connected to internal ESD rails. The inputs may float. AINP[4:1] Positive analog input, channels 4 through 1. Submit Documentation Feedback Copyright © 2007, Texas Instruments Incorporated Product Folder Link(s): ADS1174 ADS1178 5 ADS1174 ADS1178 www.ti.com SBAS373 – OCTOBER 2007 ADS1174/ADS1178 PIN DESCRIPTIONS (continued) PIN PRODUCT PREVIEW 6 NAME NO. FUNCTION AINN1 4 Analog input DESCRIPTION AINN2 2 Analog input AINN3 64 Analog input AINN4 62 Analog input AINN5 52 Analog input AINN6 50 Analog input AINN7 48 Analog input AINN8 46 Analog input AVDD 5, 44, 53, 60 Analog power supply ADS1178: AINN[8:1] Negative analog input, channels 8 through 1. ADS1174: AINN[8:5] Connected to internal ESD rails. The inputs may float. AINN[4:1] Negative analog input, channels 4 through 1. Analog power supply (4.75V to 5.25V). VCOM 55 Analog output AVDD/2 Unbuffered analog output. VREFN 57 Analog input Negative reference input. VREFP 56 Analog input Positive reference input. CLK 27 Digital input Master clock input (maximum 27MHz). CLKDIV 10 Digital input DGND 7, 21, 24, 25 Digital ground DIN 12 Digital input DOUT1 20 Digital output DOUT2 19 Digital output DOUT3 18 Digital output DOUT4 17 Digital output DOUT5 16 Digital output DOUT6 15 Digital output DOUT7 14 Digital output DOUT8 13 Digital output DRDY/ FSYNC 29 Digital input/output CLK input divider control: 1 = 27MHz 0 = 13.5MHz (high-speed) / 5.4MHz (low-power) Digital ground power supply. Daisy-chain data input. DVDD 26 Digital power supply FORMAT0 32 Digital input FORMAT1 31 Digital input DOUT1 is TDM data output (TDM mode). ADS1178: DOUT[8:1] Data output for channels 8 through 1. ADS1174: DOUT[8:5] Internally connected to active circuitry; outputs are driven. DOUT[4:1] Data output for channels 4 through 1. Frame-Sync protocol: frame clock input; SPI protocol: data ready output. Digital core power supply (+1.65V to +1.95V). FORMAT[2:0] Selects between Frame-Sync/SPI protocol, TDM/discrete data outputs, fixed/dynamic position TDM data, and modulator mode/normal operating mode. FORMAT2 30 Digital input IOVDD 22, 23, 33 Digital power supply MODE 34 Digital input I/O power supply (+1.65V to +3.6V). MODE: 0 = High-Speed mode 1 = Low-Power mode. MODE1 33 Digital input PWDN1 42 Digital input PWDN2 41 Digital input PWDN3 40 Digital input PWDN4 39 Digital input PWDN5 38 Digital input PWDN6 37 Digital input PWDN7 36 Digital input PWDN8 35 Digital input SCLK 28 Digital input Serial clock input. SYNC 11 Digital input Synchronize input (all channels). TEST0 8 Digital input TEST1 9 Digital input TEST[1:0] Test mode select: 00 = normal operation 11 = boundary scan test mode ADS1178: PWDN[8:1] Power-down control for channels 8 through 1. ADS1174: PWDN[8:5] must = 0V. PWDN[4:1] Power-down control for channels 4 through 1. Submit Documentation Feedback Copyright © 2007, Texas Instruments Incorporated Product Folder Link(s): ADS1174 ADS1178 ADS1174 ADS1178 www.ti.com SBAS373 – OCTOBER 2007 TIMING CHARACTERISTICS: SPI FORMAT tCLK tCPW CLK · · · tCPW tCD tCONV DRDY tSD tDS tS tSPW SCLK tSPW tMSBPD DOUT Bit 15 (MSB) tDOPD tDOHD Bit 14 tDIST Bit 13 tDIHD DIN TIMING REQUIREMENTS: SPI FORMAT SYMBOL PARAMETER tCLK CLK period (1/fCLK) MIN 37 tCPW CLK positive or negative pulse width 15 (1) tCONV Conversion period (1/fDATA) tCD (2) Falling edge of CLK to falling edge of DRDY tDS (2) Falling edge of DRDY to rising edge of first SCLK to retrieve data tMSBPD DRDY falling edge to DOUT MSB valid (propagation delay) tSD (2) Falling edge of SCLK to rising edge of DRDY tS (3) SCLK period tSPW SCLK positive or negative pulse width tDOHD (2) (4) TYP MAX 10,000 2560 22 ns CLK periods ns 1 CLK period 12 18 ns ns tCLK SCLK falling edge to new DOUT invalid (hold time) UNIT ns 256 0.4tCLK ns 0.6tCLK 10 ns ns tDOPD (2) SCLK falling edge to new DOUT valid (propagation delay) tDIST New DIN valid to falling edge of SCLK (setup time) 6 ns Old DIN valid to falling edge of SCLK (hold time) 6 ns tDIHD (1) (2) (3) (4) (4) PRODUCT PREVIEW For TA = –40°C to +105°C, IOVDD = 1.65V to 3.6V, and DVDD = 1.65V to 1.95V. 31 ns Depends on MODE[1:0] and CLKDIV selection. See Table 5 (fCLK/fDATA). Load on DRDY and DOUT = 20pF. For best performance, use fSCLK/fCLK ratios of 1, 1/2, 1/4, 1/8, etc. tDOHD (DOUT hold time) and tDIHD (DIN hold time) are specified under opposite worst-case conditions (digital supply voltage and ambient temperature). Under equal conditions, with DOUT connected directly to DIN, the timing margin is 4ns. Submit Documentation Feedback Copyright © 2007, Texas Instruments Incorporated Product Folder Link(s): ADS1174 ADS1178 7 ADS1174 ADS1178 www.ti.com SBAS373 – OCTOBER 2007 TIMING CHARACTERISTICS: FRAME-SYNC FORMAT tCPW tCLK CLK tCPW tCF tFRAME tFPW tFPW FSYNC tFS tS tSPW tSF SCLK tSPW tMSBPD DOUT Bit 15 (MSB) tDOHD Bit 14 tDIST tDOPD Bit 13 tDIHD DIN TIMING REQUIREMENTS: FRAME-SYNC FORMAT For TA = –40°C to +105°C, IOVDD = 1.65V to 3.6V, and DVDD = 1.65V to 1.95V. PRODUCT PREVIEW SYMBOL PARAMETER MIN tCLK CLK period (1/fCLK) 37 tCPW CLK positive or negative pulse width 15 tCF Falling edge of CLK to falling edge of SCLK tFRAME Frame period (1/fDATA) (1) tFPW FSYNC positive or negative pulse width 1 SCLK periods tFS Rising edge of FSYNC to rising edge of SCLK 5 ns tSF Rising edge of SCLK to rising edge of FSYNC 5 ns (2) tS SCLK period tSPW SCLK positive or negative pulse width tDOHD (3) (4) SCLK falling edge to old DOUT invalid (hold time) tDOPD (3) TYP MAX 10,000 ns ns –0.35 tCLK 0.35 tCLK 256 2560 tCLK 0.4 tSCLK UNIT ns CLK periods ns 0.6 tSCLK 6 ns ns SCLK falling edge to new DOUT valid (propagation delay) 28 ns tMSBPD FSYNC rising edge to DOUT MSB valid (propagation delay) 28 ns tDIST New DIN valid to falling edge of SCLK (setup time) 6 ns tDIHD (4) Old DIN valid to falling edge of SCLK (hold time) 6 ns (1) (2) (3) (4) 8 Depends on MODE[1:0] and CLKDIV selection. See Table 5 (fCLK/fDATA). tDOHD (DOUT hold time) and tDIHD (DIN hold time) are specified under opposite worst-case conditions (digital supply voltage and ambient temperature). Under equal conditions, with DOUT connected directly to DIN, the timing margin is 4ns. SCLK must be continuously running and limited to ratios of 1, 1/2, 1/4, and 1/8 of fCLK. Load on DOUT = 20pF. Submit Documentation Feedback Copyright © 2007, Texas Instruments Incorporated Product Folder Link(s): ADS1174 ADS1178 ADS1174 ADS1178 www.ti.com SBAS373 – OCTOBER 2007 OVERVIEW VREFP AVDD VREFN To allow tradeoffs between speed and power, two modes of operation are supported: High-Speed and Low-Power. Table 1 summarizes the performance of each mode. In High-Speed mode, the data rate is 52kSPS, and in Low-Power mode, the power dissipation is only 8mW/channel at 10.5kSPS. The ADS1174/78 is configured by simply setting the appropriate I/O pins—there are no registers to program. Data is retrieved over a serial interface that supports both SPI and Frame-Sync formats. The ADS1174/78 has a daisy-chainable output and the ability to synchronize externally, so it can be used conveniently in systems requiring more than eight channels. DVDD IOVDD PRODUCT PREVIEW The ADS1174 (quad) and ADS1178 (octal) are 16-bit, delta-sigma ADCs. They offer the combination of excellent linearity, low noise, and low power consumption. Figure 1 shows the block diagram. Note that both devices are the same, except the ADS1174 has four ADCs, and the ADS1178 has eight ADCs. The pinout and package of the ADS1178 is compatible with the ADS1174, permitting drop-in expandability. The converters are comprised of either four (ADS1174) or eight (ADS1178) advanced, 6th-order, chopper-stabilized, delta-sigma modulators followed by low-ripple, linear phase FIR filters. The modulators measure the differential input signal, VIN = (AINP – AINN), against the differential reference, VREF = (VREFP – VREFN). The digital filters receive the modulator signal and provide a low-noise digital output. S R VCOM VREF R AINP1 AINN1 AINP2 AINN2 S S VIN1 DS Modulator1 VIN2 DS Modulator2 Digital Filter1 DRDY/FSYNC SPI and Frame-Sync Interface SCLK DOUT[4:1]/[8:1](1) DIN Digital Filter2 TEST[1:0] FORMAT[2:0] CLK Control Logic AINP4/8(1) AINN4/8(1) S VIN4/8 DS Modulator4/8(1) SYNC PWDN[4:1]/[8:1](1) Digital Filter4/8(1) CLKDIV MODE AGND DGND NOTE: (1) The ADS1174 has four channels; the ADS1178 has eight channels. Figure 1. ADS1174/ADS1178 Block Diagram Table 1. Operating Mode Performance Summary (1) MODE DATA RATE (SPS) PASSBAND (Hz) SNR (dB) NOISE (LSBPP) POWER DISSIPATION PER CHANNEL (1) (mW) High-Speed 52,734 23,889 97 1 32 Low-Power 10,547 4,536 97 1 8 Measured with all channels operating. Submit Documentation Feedback Copyright © 2007, Texas Instruments Incorporated Product Folder Link(s): ADS1174 ADS1178 9 ADS1174 ADS1178 www.ti.com SBAS373 – OCTOBER 2007 FUNCTIONAL DESCRIPTION The ADS1174 and ADS1178 are delta/sigma ADCs consisting of independent converters that digitize input signals in parallel. The ADS1174 consists of four independent converters, while the ADS1178 has eight independent converters. The converter is composed of two main functional blocks to perform the ADC conversions: the modulator and the digital filter. The modulator samples the input signal together with sampling the reference voltage to produce a 1's density output stream. The density of the output stream is proportional to the analog input level relative to the reference voltage. The pulse stream is filtered by the internal digital filter where the output conversion result is produced. PRODUCT PREVIEW In operation, the signal inputs and reference inputs are sampled by the modulator at a high rate (typically 64x higher than the final output data rate). The quantization noise of the modulator is moved to a higher frequency range where the internal digital filter removes it. This process results in very low levels of noise within the signal passband. 10 Because the input signal is sampled at a very high rate, input signal aliasing does not occur until the input signal frequency is at the modulator sampling rate. This high sampling rate greatly relaxes the requirement of external antialiasing filters allowing very low passband phase errors. SAMPLING APERTURE MATCHING The converters of the ADS1174/78 operate from the same CLK input. The CLK input controls the timing of the modulator sampling instant. The converter is designed such that the sampling skew, or modulator sampling aperture match, between channels is controlled to within 200ps. Furthermore, the digital filters are synchronized to start the convolution phase at the same modulator clock cycle. This design results in excellent phase match among the ADS1174/78 channels. The phase match of one four-channel ADS1174 to that of another ADS1174 may not have the same degree of sampling match (the same is true for the 8-channel ADS1178). As a result of manufacturing variations, differences in internal propagation delay of the internal CLK signal coupled with differences of the arrival of the external CLK signal to each device may cause larger sampling match errors. Equal length CLK traces or external clock distribution devices can be used to control the arrival of the CLK signals to help reduce the sampling match error. Submit Documentation Feedback Copyright © 2007, Texas Instruments Incorporated Product Folder Link(s): ADS1174 ADS1178 ADS1174 ADS1178 www.ti.com SBAS373 – OCTOBER 2007 FREQUENCY RESPONSE 0 -2 Amplitude (dB) The digital filter sets the overall frequency response. The filter uses a multi-stage FIR topology to provide linear phase with minimal passband ripple and high stop band attenuation. The oversampling ratio of the digital filter (that is, the ratio of the modulator sampling to the output data rate: fMOD/fDATA) is 64 for both High-Speed and Low-Power modes. -1 -3 -4 -5 -6 -7 Figure 2 shows the frequency response of the ADS1174/78 normalized to fDATA. Figure 3 shows the passband ripple. The transition from passband to stop band is illustrated in Figure 4. The overall frequency response repeats at 64x multiples of the modulator frequency fMOD, as shown in Figure 5. -8 -9 -10 0.45 0.47 0.49 0.51 0.53 0.55 Normalized Input Frequency (fIN/fDATA) Figure 4. Transition Band Response 0 -20 -20 -80 -40 -100 -60 -80 -120 -100 -140 -120 0 0.2 0.6 0.4 0.8 1.0 -140 Normalized Input Frequency (fIN/fDATA) -160 0 Figure 2. Frequency Response 32 48 64 Input Frequency (fIN/fDATA) Figure 5. Frequency Response Out to fMOD 0.02 0 Amplitude (dB) 16 These image frequencies, if present in the signal and not externally filtered, will fold back (or alias) into the passband, causing errors. Table 2 lists the degree of image rejection versus external antialiasing filter order. The stop band of the ADS1174/78 provides 100dB attenuation of frequencies that begin just beyond the passband and continue out to fMOD. Placing an antialiasing, low-pass filter in front of the ADS1174/78 inputs is recommended to limit possible high-amplitude, out-of-band signals and noise. -0.02 -0.04 -0.06 -0.08 -0.10 0 0.1 0.2 0.3 0.4 0.5 Normalized Input Frequency (fIN/fDATA) Figure 3. Passband Response 0.6 Table 2. Antialiasing Filter Order Image Rejection ANTIALIASING FILTER ORDER IMAGE REJECTION (dB) (f–3dB at fDATA) 1 39 2 75 3 111 Submit Documentation Feedback Copyright © 2007, Texas Instruments Incorporated Product Folder Link(s): ADS1174 ADS1178 11 PRODUCT PREVIEW 0 -60 Gain (dB) Amplitude (dB) 20 -40 ADS1174 ADS1178 www.ti.com SBAS373 – OCTOBER 2007 PHASE RESPONSE DATA FORMAT The ADS1174/78 incorporates a multiple stage, linear phase digital filter. Linear phase filters exhibit constant delay time versus input frequency (constant group delay), which means the time delay from any instant of the input signal to the same instant of the output data is constant, and is independent of input signal frequency. This behavior results in essentially zero phase errors when analyzing multi-tone signals. The ADS1174/78 outputs 16 bits of data in two’s complement format. SETTLING TIME A positive full-scale input produces an ideal output code of 7FFFh, and the negative full-scale input produces an ideal output code of 8000h. The output clips at these codes for signals exceeding full-scale. Table 3 summarizes the ideal output codes for different input signals. Table 3. Ideal Output Code versus Input Signal As with frequency and phase response, the digital filter also determines settling time. Figure 6 shows the output settling behavior after a step change on the analog inputs normalized to conversion periods. The X-axis is given in units of conversion. Note that after the step change on the input occurs, the output data changes very little prior to 30 conversion periods. The output data is fully settled after 76 conversion periods. INPUT SIGNAL VIN (AINP – AINN) IDEAL OUTPUT CODE(1) PRODUCT PREVIEW ≥ +VREF 7FFFh ) VREF 2 15 * 1 0001h 0 0000h * VREF 2 15 * 1 FFFFh ǒ2 2* 1Ǔ v −VREF Final Value 100 15 15 8000h (1) Excludes effects of noise, INL, offset, and gain errors. Settling (%) Fully Settled Data at 76 Conversions Initial Value 0 0 10 20 30 40 50 60 70 80 Conversions (1/fDATA) Figure 6. Step Response 12 Submit Documentation Feedback Copyright © 2007, Texas Instruments Incorporated Product Folder Link(s): ADS1174 ADS1178 ADS1174 ADS1178 www.ti.com SBAS373 – OCTOBER 2007 ANALOG INPUTS (AINP, AINN) The ADS1174/78 measures each differential input signal VIN = (AINP – AINN) against the common differential reference VREF = (VREFP – VREFN). The most positive measurable differential input is +VREF, which produces the most positive digital output code of 7FFFh. Likewise, the most negative measurable differential input is –VREF, which produces the most negative digital output code of 8000h. While the ADS1174/78 measures the differential input signal, the absolute input voltage is also important. This is the voltage on either input (AINP or AINN) with respect to AGND. The range for this voltage is: –0.1V < (AINN or AINP) < AVDD + 0.1V If either input is taken below –0.4V or above (AVDD + 0.4), ESD protection diodes on the inputs may turn on. If these conditions are possible, external Schottky clamp diodes or series resistors may be required to limit the input current to safe levels (see Absolute Maximum Ratings table). The ADS1174/78 is a high-performance ADC. For optimum performance, it is critical that the appropriate circuitry be used to drive the ADS1174/78 inputs. See the Applications Information section for the recommended circuits. The ADS1174/78 uses switched-capacitor circuitry to measure the input voltage. Internal capacitors are charged by the inputs and then discharged. Figure 7 shows a conceptual diagram of these circuits. Switch S2 represents the net effect of the modulator circuitry in discharging the sampling capacitor; the actual implementation is different. The timing for switches S1 and S2 is shown in Figure 8. The sampling time (tSAMPLE) is the inverse of modulator sampling frequency (fMOD) and is a function of the mode, the CLKDIV input, and frequency of CLK, as shown in Table 4. S1 AINP 9pF S2 AINN S1 AGND AVDD ESD Protection Figure 7. Equivalent Analog Input Circuitry tSAMPLE = 1/fMOD S1 ON OFF S2 ON OFF Figure 8. S1 and S2 Switch Timing for Figure 7 Table 4. Modulator Frequency (fMOD) versus Mode Selection MODE SELECTION High-Speed Low-Power CLKDIV fMOD 1 fCLK/8 0 fCLK/4 1 fCLK/40 0 fCLK/8 The average load presented by the switched capacitor input can be modeled with an effective differential impedance, as shown in Figure 9. Note that the effective impedance is a function of fMOD. AINP Zeff = 14kW ´ (6.75MHz/fMOD) AINN Figure 9. Effective Input Impedances Submit Documentation Feedback Copyright © 2007, Texas Instruments Incorporated Product Folder Link(s): ADS1174 ADS1178 13 PRODUCT PREVIEW For optimum performance, the inputs of the ADS1174/78 are intended to be driven differentially. For single-ended input applications, one of the inputs (AINP or AINN) can be driven while the other input is fixed (typically, to AGND or +2.5V); fixing the input to +2.5V permits bipolar operation, thereby using the full range of the converter. AVDD AGND ADS1174 ADS1178 www.ti.com SBAS373 – OCTOBER 2007 VOLTAGE REFERENCE INPUTS (VREFP, VREFN) The voltage reference for the ADS1174/78 ADC is the differential voltage between VREFP and VREFN: VREF = (VREFP – VREFN). The voltage reference is common to the four channels. The reference inputs use a structure similar to that of the analog inputs with the equivalent circuitry on the reference inputs shown in Figure 10. As with the analog inputs, the load presented by the switched capacitor can be modeled with an effective impedance, as shown in Figure 11. However, the reference input impedance depends on the number of active (enabled) channels in addition to fMOD. As a result of the change of reference input impedance caused by enabling and disabling channels, the regulation and settling time of the external reference should be noted, so as not to affect the readings of other channels. VREFP VREFN PRODUCT PREVIEW AGND AGND AVDD AVDD ESD Protection Figure 10. Equivalent Reference Input Circuitry VREFP If these conditions are possible, external Schottky clamp diodes or series resistors may be required to limit the input current to safe levels (see Absolute Maximum Ratings table). Note that the valid operating range of the reference inputs is limited to the following: –0.1V ≤ VREFN ≤ VREFP – 0.5V VREFN + 0.5V ≤ VREFP ≤ AVDD + 0.1V A high-quality reference voltage with the appropriate drive strength is essential for achieving the best performance from the ADS1174/78. Noise and drift on the reference degrade overall system performance. See the Application Information section for example reference circuits. CLOCK INPUT (CLK) The ADS1174/78 requires a clock input for operation. Each ADS1174/78 converter operates from the same clock input. At the maximum data rate, the clock input can be either 27MHz or 13.5MHz (5.4MHz, low power), determined by the setting of the CLKDIV input. The selection of the external clock frequency (fCLK) does not affect the resolution (the oversampling ratio, OSR, remains fixed) or power dissipation of the ADS1174/78. However, using a slower fCLK can reduce the power consumption of an external clock driver. The output data rate scales with clock frequency, down to a minimum clock frequency of fCLK = 100kHz. Table 5 summarizes the ratio of clock input frequency (fCLK) to data rate (fDATA), maximum data rate and corresponding maximum clock input for the two operating modes. Table 5. Clock Input Options VREFN MODE SELECTION High-Speed 5.2kW Zeff = ´ (6.75MHz/fMOD) N Low-Power fCLK (MHz) CLKDIV fCLK/fDATA 27 1 512 13.5 0 256 27 1 2,560 5.4 0 512 DATA RATE (SPS) 52,734 10,547 N = number of active channels. Figure 11. Effective Reference Impedance ESD diodes protect the reference inputs. To keep these diodes from turning on, make sure the voltages on the reference pins do not go below AGND by more than 0.4V, and likewise do not exceed AVDD by 0.4V. 14 As with any high-speed data converter, a high-quality, low-jitter clock is essential for optimum performance. Crystal clock oscillators are the recommended clock source. Make sure to avoid excess ringing on the clock input; keeping the clock trace as short as possible using a 50Ω series resistor, placed close to the source end, often helps. Submit Documentation Feedback Copyright © 2007, Texas Instruments Incorporated Product Folder Link(s): ADS1174 ADS1178 ADS1174 ADS1178 www.ti.com SBAS373 – OCTOBER 2007 MODE SELECTION (MODE) SYNCHRONIZATION (SYNC) The ADS1174/78 supports two modes of operation: High-Speed and Low-Power. These modes offer optimization of speed or power. The mode selection is determined by the status of the digital input MODE pins, as shown in Table 6. The ADS1174/78 constantly monitors the status of the MODE pin during operation. The ADS1174/78 can be synchronized by pulsing the SYNC pin low and then returning the pin high. When the pin goes low, the conversion process stops, and the internal counters used by the digital filter are reset. When the SYNC pin returns high, the conversion process restarts. Synchronization allows the conversion to be aligned with an external event, such as a reference timing pulse. MODE SELECTION MAX fDATA(1) 0 High-Speed 52,734 1 Low-Power 10,547 (1) fCLK = 27MHz (CLKDIV = 1). When using the SPI protocol, DRDY is held high after a mode change occurs until settled (or valid) data are ready, as shown in Figure 12 and Table 7. In Frame-Sync protocol, the DOUT pins are held low after a mode change occurs until settled data are ready, as shown in Figure 12 and Table 7. Data can be read from the device to detect when DOUT changes to logic 1, indicating valid data. Since the converters of the ADS1174/78 operate in parallel from the same master clock and use the same SYNC input control, they are, by default, in synchronization with each other. The sampling aperture match among the channels is 200ps (typical). However, the synchronization of multiple ADS1174/78s is somewhat different. At device power-on, variations in internal reset thresholds from device to device may result in uncertainty in conversion timing. The SYNC pin can be used to synchronize multiple ADS1174/78s to within the same CLK cycle. Figure 13 illustrates the timing requirement of SYNC and CLK in SPI format. See Figure 14 for the Frame-Sync format timing requirement. MODE[1:0] Pins ADS1174/78 Mode Previous Mode New Mode tNDR-SPI SPI Protocol DRDY New Mode Valid Data Ready tNDR-FS Frame-Sync DOUT Protocol New Mode Valid Data on DOUT Figure 12. Mode Change Timing Table 7. Mode Change SYMBOL DESCRIPTION MIN tNDR-SPI Time for new data to be ready (SPI) tNDR-FS Time for new data to be ready (Frame-Sync) 127 TYP MAX UNITS 129 Conversions (1/fDATA) 128 Conversions (1/fDATA) Submit Documentation Feedback Copyright © 2007, Texas Instruments Incorporated Product Folder Link(s): ADS1174 ADS1178 15 PRODUCT PREVIEW Table 6. Mode Selection MODE ADS1174 ADS1178 www.ti.com SBAS373 – OCTOBER 2007 After synchronization, indication of valid data depends on the whether SPI or Frame-Sync format was used. In the SPI format, DRDY goes high as soon as SYNC is taken low; see Figure 13. After SYNC is returned high, DRDY stays high while the digital filter is settling. Once valid data are ready for retrieval, DRDY goes low. In the Frame-Sync format, DOUT goes low as soon as SYNC is taken low; see Figure 14. After SYNC is returned high, DOUT stays low while the digital filter is settling. Once valid data are ready for retrieval, DOUT begins to output valid data. For proper synchronization, FSYNC, SCLK, and CLK must be established before taking SYNC high, and must then remain running. tCSHD CLK tSCSU tSYN SYNC tNDR DRDY Figure 13. Synchronization Timing for SPI Protocol PRODUCT PREVIEW Table 8. SPI Protocol SYMBOL DESCRIPTION MIN TYP MAX UNITS tCSHD CLK to SYNC hold time 10 ns tSCSU SYNC to CLK setup time 5 ns tSYN Synchronize pulse width 1 tNDR Time for new data to be ready CLK periods 129 Conversions (1/fDATA) tCSHD CLK tSCSU tSYN SYNC FSYNC tNDR Valid Data DOUT Figure 14. Synchronization Timing for Frame-Sync Protocol Table 9. Frame-Sync Protocol SYMBOL 16 DESCRIPTION MIN TYP MAX UNITS tCSHD CLK to SYNC hold time 10 ns tSCSU SYNC to CLK setup time 5 ns tSYN Synchronize pulse width tNDR Time for new data to be ready 1 127 Submit Documentation Feedback CLK periods 128 Conversions (1/fDATA) Copyright © 2007, Texas Instruments Incorporated Product Folder Link(s): ADS1174 ADS1178 ADS1174 ADS1178 www.ti.com SBAS373 – OCTOBER 2007 POWER-DOWN (PWDN) 2. Wait for 129/fDATA after taking the PWDN pins high. 3. Detect for non-zero data in the powered-up channel. The ADS1174/78 measurement channels can be independently powered down by use of the PWDN inputs. To enter the power-down mode, take the respective PWDN pin low. Power-down occurs after two fCLK cycles have elapsed. This delay guards against false transitions caused by external noise. To exit power-down, return the corresponding PWDN pin high. Note that when all channels are powered down, the ADS1174/78 enters a microwatt (μW) power state where all internal biasing is powered-down. In this event, the TEST[1:0] input pins must be driven; all other input pins can float (the ADS1174/78 outputs remain driven). After powering-up one or more channels, the channels are synchronized to each other. It is not necessary to use the SYNC pin to synchronize them. As shown in Figure 15 and Table 10, a maximum of 129 conversion cycles must elapse before reading data after exiting power-down. The data from channels already running are not affected. The user software can perform the required delay time in the following ways: 1. Count the number of data conversions after taking the PWDN pin high. In discrete data format, the data are always forced to zero. When powering-up a channel in dynamic-position TDM data format mode, the channel data remain packed until the data are ready, at which time the data frame is expanded to include the just-powered channel data. See the Data Format section for details. ··· tPDWN tNDR (1) DRDY/FSYNC DOUT (Discrete Data Output Mode) Post Power-Up Data DOUT1 (TDM Mode, Dynamic Position) Normal Position Data Shift Position Normal Position DOUT1 (TDM Mode, Fixed Position) Normal Position Data Remain in Position Normal Position NOTE: (1) In SPI protocol, the timing occurs on the falling edge of DRDY/FSYNC. Powering down all channels forces DRDY/FSYNC high. Figure 15. Power-Down Timing Table 10. Power-Down Timing SYMBOL tPDWN tNDR DESCRIPTION MIN PDWN pulse width to enter Power-Down mode TYP MAX UNITS 2 CLK periods Time for new data to be ready (SPI) 129 130 Conversions (1/fDATA) Time for new data to be ready (Frame-Sync) 128 129 Conversions (1/fDATA) Submit Documentation Feedback Copyright © 2007, Texas Instruments Incorporated Product Folder Link(s): ADS1174 ADS1178 17 PRODUCT PREVIEW ··· CLK PWDN When a channel is powered down in TDM data format, the data for the powered-down channel will either be forced to zero (fixed-position TDM data mode) or be replaced by shifting the data from the next channel into the vacated data position (dynamic-position TDM data mode). ADS1174 ADS1178 www.ti.com SBAS373 – OCTOBER 2007 FORMAT[2:0] Data can be read from the ADS1174/78 with two serial interface protocols (SPI or Frame-Sync) and several options of data formats (TDM/Discrete and Fixed/Dynamic data positions). The FORMAT[2:0] inputs are used to select among the options. Table 11 lists the available options. See the DOUT Modes section for details of the DOUT modes and data positions. recommended to keep SCLK as clean as possible to prevent glitches from accidentally shifting the data. SCLK may be run as fast as the CLK frequency. SCLK may be either in free-running or stop-clock operation between conversions. For best performance, use fSCLK/fCLK ratios of 1, 1/2, 1/4, 1/8, etc. NOTE: One CLK period is required after DRDY falls, to start shifting data (see Timing Requirements: SPI Format ). DRDY/FSYNC (SPI Format) Table 11. Data Output Format FORMAT[2:0] INTERFACE PROTOCOL DOUT MODE DATA POSITION 000 SPI TDM Dynamic 001 SPI TDM Fixed 010 SPI Discrete — 011 Frame-Sync TDM Dynamic 100 Frame-Sync TDM Fixed 101 Frame-Sync Discrete — In the SPI format, this pin functions as the DRDY output. It goes low when data are ready for retrieval and then returns high on the falling edge of the first subsequent SCLK. If data are not retrieved (that is, SCLK is held low), DRDY will pulse high just before the next conversion data are ready, as shown in Figure 16. The new data are loaded within one CLK cycle before DRDY goes low. All data must be shifted out before this time to avoid being overwritten. PRODUCT PREVIEW 1/fDATA SERIAL INTERFACE PROTOCOLS 1/fCLK DRDY Data are retrieved from the ADS1174/78 using the serial interface. Two protocols are available: SPI and Frame-Sync. The same pins are used for both interfaces: SCLK, DRDY/FSYNC, DOUT[4:1] (or DOUT[8:1] for the ADS1178), and DIN. The FORMAT[2:0] pins select the desired interface protocol. SCLK Figure 16. DRDY Timing with No Readback DOUT The SPI-compatible format is a simple read-only interface. Data ready for retrieval are indicated by the falling DRDY output and are shifted out on the falling edge of SCLK, MSB first. The interface can be daisy-chained using the DIN input when using multiple ADS1174/78s. See the Daisy-Chaining section for more information. In Discrete Data Output mode, the conversion data are output on the individual DOUT pins (DOUT1, DOUT2, etc.), whereas in TDM mode, data are output only on DOUT1. The MSB data are valid on DOUT[4:1]/[8:1] when DRDY goes low. The subsequent bits are shifted out with each falling edge of SCLK. If daisy-chaining (TDM mode), the data shifted in using DIN will appear on DOUT1 after all channel data have been shifted out. SCLK DIN The serial clock (SCLK) features a Schmitt-triggered input and shifts out data on DOUT on the falling edge. It also shifts in data on the falling edge on DIN when this pin is being used for daisy-chaining. The device shifts data out on the falling edge and the user typically shifts this data in on the rising edge. Even though the SCLK input has hysteresis, it is This input is used when multiple ADS1174/78s are to be daisy-chained together. The DOUT1 pin of the first device connects to the DIN pin of the next, etc. It can be used with either the SPI or Frame-Sync formats. Data are shifted in on the falling edge of SCLK. When using only one ADS1174/78, tie DIN low. See the Daisy-Chaining section for more information. SPI SERIAL INTERFACE 18 Submit Documentation Feedback Copyright © 2007, Texas Instruments Incorporated Product Folder Link(s): ADS1174 ADS1178 ADS1174 ADS1178 www.ti.com SBAS373 – OCTOBER 2007 FRAME-SYNC SERIAL INTERFACE DRDY/FSYNC (Frame-Sync Format) Frame-Sync format is similar to the interface often used on audio ADCs. It operates in slave fashion—the user must supply framing signal FSYNC (similar to the left/right clock on stereo audio ADCs) and the serial clock SCLK (similar to the bit clock on audio ADCs). The data is output MSB first or left-justified. When using Frame-Sync format, the FSYNC and SCLK inputs must be continuously running with the required relationships shown in the Frame-Sync Timing Requirements. In Frame-Sync format, this pin is used as the FSYNC input. The frame-sync input (FSYNC) sets the frame period which must be same as the data rate. The required number of fCLK cycles to each FSYNC period depends on the mode selection and the CLKDIN input. Table 5 indicates the number of CLK cycles to each frame (fCLK/fDATA). If the FSYNC period is not the proper value, data readback will be corrupted. The serial clock (SCLK) features a Schmitt-triggered input and shifts out data on DOUT on the falling edge. It also shifts in data on the falling edge on DIN when this pin is being used for daisy-chaining. Even though SCLK has hysteresis, it is recommended to keep SCLK as clean as possible to prevent glitches from accidentally shifting the data. When using Frame-Sync format, SCLK must run continuously. If it is shut down, the data readback will be corrupted. The number of SCLKs within a frame period (FSYNC clock) can be any power of two ratio of clock cycles (1, 1/2, 1/4, etc.), as long as the number of cycles is sufficient to shift the data output from all channels within one data frame. In Discrete Data Output mode, the conversion data are shifted out on the individual DOUT pins (DOUT1, DOUT2, etc.), whereas in TDM mode, data are output only on DOUT1. The MSB data become valid on DOUT[4:1]/[8:1] on the SCLK rising edge prior to FSYNC going high. The subsequent bits are shifted out with each falling edge of SCLK. If daisy-chaining (TDM mode), the data shifted in using DIN will appear on DOUT1 after all channel data have been shifted out (that is, 4 channels × 16 bits per channel = 64 bits for the ADS1174, and 8 channels × 16 bits per channel = 128 bits for the ADS1178). DIN This input is used when multiple ADS1174/78s are to be daisy-chained together. It can be used with either SPI or Frame-Sync formats. Data are shifted in on the falling edge of SCLK. When using only one ADS1174/78, tie DIN low. See the Daisy-Chaining section for more information. Submit Documentation Feedback Copyright © 2007, Texas Instruments Incorporated Product Folder Link(s): ADS1174 ADS1178 19 PRODUCT PREVIEW SCLK DOUT ADS1174 ADS1178 www.ti.com SBAS373 – OCTOBER 2007 DOUT MODES For both SPI and Frame-Sync interface protocols, either the data are shifted out through individual channel DOUT pins in a parallel data format (Discrete mode), or the data for all channels are shifted out in series through common pin DOUT1 (TDM mode). output from another ADS1174, ADS1178, or other compatible device. Note that when all channels of the ADS1174/78 are powered-down, the interface is powered-down, rendering the DIN input powered-down as well. When one or more channels of the device are powered-down, the data format of the TDM mode can be fixed or dynamic. TDM Mode TDM Mode, Fixed-Position Data In TDM (time division multiplexed) data output mode, the data for all channels are shifted out, in series, on a single pin (DOUT1). As shown in Figure 17, the data from channel 1 are shifted out first, followed by channel 2 data, etc. After the data from the last channel are shifted out (channel 4 for the ADS1174 or channel 8 for the ADS1178), the data from the DIN input follow. The DIN is used to daisy-chain the data In this TDM data output mode, the data position of the channels remains fixed, regardless of whether channels are disabled. If a channel is powered-down, data are forced to zero but occupies the same position within the data stream. Figure 18 shows the data stream with channel 1 and channel 3 powered-down. SCLK 1 2 15 16 17 31 32 33 47 48 49 63 64 65 66 67 PRODUCT PREVIEW DOUT1 (ADS1174) CH1 CH2 CH3 CH4 DIN DOUT1 (ADS1178) CH1 CH2 CH3 CH4 CH5 113 127 128 129 CH8 130 131 DIN DRDY (SPI) FSYNC (Frame-Sync) Figure 17. TDM Mode (All Channels Enabled) SCLK 1 2 15 16 17 31 32 33 47 48 49 63 64 65 66 DOUT1 (ADS1174) CH1 CH2 CH3 CH4 DIN DOUT1 (ADS1178) CH1 CH2 CH3 CH4 CH5 67 113 127 128 129 CH8 130 131 DIN DRDY (SPI) FSYNC (Frame-Sync) Figure 18. TDM Mode, Fixed-Position Data (Channels 1 and 3 Shown Powered-Down) 20 Submit Documentation Feedback Copyright © 2007, Texas Instruments Incorporated Product Folder Link(s): ADS1174 ADS1178 ADS1174 ADS1178 www.ti.com SBAS373 – OCTOBER 2007 TDM Mode, Dynamic Position Data Discrete Data Output Mode In this TDM data output mode, when a channel is powered-down, the data from higher channels shift one position in the data stream to fill the vacated data slot. Figure 19 shows the data stream with channel 1 and channel 3 powered-down. In Discrete data output mode, the channel data are shifted out in parallel using individual channel data output pins DOUT[4:1] for the ADS1174, or DOUT[8:1] for the ADS1178. After the 16th SCLK, the channel data are forced to zero. The data are also forced to zero for powered-down channels. Figure 20 depicts the data format. SCLK 1 2 15 16 17 31 32 33 34 DOUT1 (ADS1174) CH2 CH4 DIN DOUT1 (ADS1178) CH2 CH4 CH5 35 80 81 95 CH8 96 97 98 99 DIN DRDY (SPI) PRODUCT PREVIEW FSYNC (Frame- Sync) Figure 19. TDM Mode, Dynamic Position Data (Channels 1 and 3 Shown Powered-Down) SCLK 1 2 14 DOUT1 CH1 DOUT2 CH2 DOUT3 CH3 DOUT4 CH4 DOUT5 CH5 DOUT6 CH6 DOUT7 CH7 DOUT8 CH8 15 16 ADS1178 Only DRDY (SPI) FSYNC (Frame-Sync) Figure 20. Discrete Data Output Mode Submit Documentation Feedback Copyright © 2007, Texas Instruments Incorporated Product Folder Link(s): ADS1174 ADS1178 21 ADS1174 ADS1178 www.ti.com SBAS373 – OCTOBER 2007 DAISY-CHAINING The maximum number of channels that may be daisy-chained in this way is limited by the frequency of fSCLK, the mode selection, and the CLKDIV input. The frequency of fSCLK must be high enough to completely shift the data out from all channels within one fDATA period. Table 12 lists the maximum number of daisy-chained channels when fSCLK = fCLK. Multiple ADS1174/78s can be daisy-chained together to simplify the serial interface connections. The DOUT1 data output pin of one ADS1174/78 is connected to the DIN of the next ADS1174/78. As Figure 21 illustrates, the DOUT1 pin of device 1 provides the output data to a controller, and the DIN of device 2 is grounded. Figure 22 describes the data format when reading data back in a daisy-chain configuration. SYNC SYNC CLK CLK DIN2 DIN ADS1178 U2 SYNC ADS1178 U1 DRDY CLK DOUT1 DRDY Output from Device 1 DIN DOUT1 SCLK SCLK Serial Data from Devices 1 and 2 SCLK PRODUCT PREVIEW Figure 21. Daisy-Chaining of Two ADS1178s, SPI Protocol (FORMAT[2:0] = 011 or 100) SCLK DOUT1 1 2 CH1, U1 17 18 CH2, U1 33 34 CH3, U1 49 50 CH4, U1 65 66 CH5, U1 129 130 CH1, U2 145 146 CH2, U2 257 258 DIN2 DRDY (SPI) FSYNC (Frame-Sync) Figure 22. Daisy-Chain Data Format of Figure 21 Table 12. Maximum Channels in a Daisy-Chain (fSCLK = fCLK) MODE SELECTION High-Speed Low-Power 22 CLKDIV MAXIMUM NUMBER OF CHANNELS 1 32 0 16 1 160 0 32 Submit Documentation Feedback Copyright © 2007, Texas Instruments Incorporated Product Folder Link(s): ADS1174 ADS1178 ADS1174 ADS1178 www.ti.com SBAS373 – OCTOBER 2007 To increase the number of data channels possible in a chain, a segmented DOUT scheme may be used, producing two data streams. Figure 23 illustrates four ADS1178s, with a pair of ADS1178s daisy-chained together. The channel data of each daisy-chained pair is shifted out in parallel and is received by the processor through independent data channels. Whether the interface protocol is SPI or Frame-Sync, it is recommended to synchronize all devices by tying the SYNC inputs together. When synchronized in SPI protocol, it is only necessary to monitor the DRDY output of one ADS1178. In Frame-Sync interface protocol, the data from all devices are ready on the rising edge of FSYNC. Since DOUT1 and DIN are both shifted on the falling edge of SCLK, the propagation delay on DOUT1 creates a setup time for DIN. Minimize the skew in SCLK to avoid timing violations. CLK ADS1178 U4 SYNC ADS1178 U3 SYNC ADS1178 U2 SYNC ADS1178 U1 SYNC CLK CLK CLK CLK DIN DOUT1 DIN DOUT1 DIN DOUT1 DIN FSYNC FSYNC FSYNC FSYNC SCLK SCLK SCLK SCLK DOUT1 Serial Data from Devices 3 and 4 Serial Data from Devices 1 and 2 PRODUCT PREVIEW SYNC SCLK FSYNC Figure 23. Segmented DOUT Daisy-Chain, Frame-Sync Protocol (FORMAT[2:0] = 000 or 001) Submit Documentation Feedback Copyright © 2007, Texas Instruments Incorporated Product Folder Link(s): ADS1174 ADS1178 23 ADS1174 ADS1178 www.ti.com SBAS373 – OCTOBER 2007 POWER-UP SEQUENCE Figure 24 shows the power-up sequence of the ADS1174/78. The power supplies can be sequenced in any order. Each supply has an internal reset circuit where the outputs are summed together to generate an internal global power-on reset. After the supplies have exceeded the reset thresholds, 218 fCLK cycles are counted before the converter initiates the conversion process. After all the fCLK cycles are counted, the data for 128 conversions is suppressed by the ADS1174/78 to allow output of fully-settled data. In SPI protocol, DRDY is held high during this interval. In frame-sync protocol, DOUT is forced to zero. The power supplies should be applied before any analog or digital pin is driven. The ADS1174/78 has three power supplies: AVDD, DVDD, and IOVDD. AVDD is the analog supply that powers the modulator, DVDD is the digital supply that powers the digital core, and IOVDD is the digital I/O power supply. The IOVDD and DVDD power supplies can be tied together if desired. To achieve rated performance, it is critical that the power supplies are bypassed with 0.1μF and +10μF capacitors placed as close as possible to the supply pins. A single 1μF ceramic capacitor may be substituted in place of the two capacitors. AVDD 3.5V Nom DVDD 1V Nom IOVDD 1V Nom (1) (1) (1) PRODUCT PREVIEW Internal Reset CLK 218 fCLK 128 fDATA DRDY (SPI) DOUT (Frame-Sync) Valid Data NOTE: (1) The power-supply reset thresholds are approximate. Figure 24. Power-Up Sequence 24 Submit Documentation Feedback Copyright © 2007, Texas Instruments Incorporated Product Folder Link(s): ADS1174 ADS1178 ADS1174 ADS1178 www.ti.com SBAS373 – OCTOBER 2007 The Boundary Scan test mode feature of the ADS1174/78 allows continuity testing of the digital I/O pins. In this mode, the normal functions of the digital pins are disabled and routed to each other as pairs through internal logic, as shown in Table 13. Note that some of the digital input pins become outputs. Table 13. Test Mode Pin Map (TEST[1:0] = 11) TEST MODE PIN MAP (1) (1) (2) INPUT PINS OUTPUT PINS PWDN1 DOUT1 PWDN2 DOUT2 PWDN3 DOUT3 PWDN4 DOUT4 PWDN5 (2) DOUT5 (2) PWDN6 (2) DOUT6 (2) PWDN7 (2) DOUT7 (2) PWDN8 (2) DOUT8 (2) MODE DIN FORMAT0 CLKDIV FORMAT1 DRDY/FSYNC FORMAT2 SCLK Therefore, if using boundary scan tests, the ADS1174/78 digital I/O should connect to a JTAG-compatible device. The analog input, power supply, and ground pins remain connected as normal. The test mode is engaged by the setting the pins TEST[1:0] = 11. For normal converter operation, set TEST[1:0] = 00. VCOM OUTPUT The VCOM pin is an analog output of approximately AVDD/2. This voltage may be used to set the common-mode voltage of the input buffers. However, the pin must be buffered. A 0.1μF capacitor to AGND is recommended to reduce noise pick-up. ADS1174/ADS1178 OPA350 VCOM » (AVDD/2) 0.1mF PRODUCT PREVIEW BOUNDARY SCAN TEST[1:0] INPUTS NOTE: Buffer is required if VCOM is used for any purpose. Figure 25. VCOM Output The CLK input does not have a test output; SYNC = 1 and is an output. ADS1178 only. Submit Documentation Feedback Copyright © 2007, Texas Instruments Incorporated Product Folder Link(s): ADS1174 ADS1178 25 ADS1174 ADS1178 www.ti.com SBAS373 – OCTOBER 2007 APPLICATION INFORMATION PRODUCT PREVIEW To obtain the specified performance from the ADS1174/78, the following layout and component guidelines should be considered. 1. Power Supplies: The device requires three power supplies for operation: DVDD, IOVDD, and AVDD. The range for DVDD is 1.65V to 1.95V; the range of IOVDD is 1.65V to 3.6V; and AVDD is restricted to 4.75V to 5.25V. For all supplies, use a 10μF tantalum capacitor, bypassed with a 0.1μF ceramic capacitor, placed close to the device pins. Alternatively, a single 10μF ceramic capacitor can be used. The supplies should be relatively free of noise and should not be shared with devices that produce voltage spikes (such as relays, LED display drivers, etc.). If a switching power supply source is used, the voltage ripple should be low (< 2mV) and the switching frequency outside the passband of the converter. The power supplies may be sequenced in any order. 2. Ground Plane: A single ground plane connecting both AGND and DGND pins can be used. If separate digital and analog grounds are used, connect the grounds together at the converter. 3. Digital Inputs: It is recommended to source-terminate the digital inputs to the device with 50Ω series resistors. The resistors should be placed close to the driving end of the digital source (oscillator, logic gates, DSP, etc.) This placement helps to reduce ringing on the digital lines, which may lead to degraded ADC performance. 4. Analog/Digital Circuits: Place analog circuitry (input buffer, reference) and associated tracks together, keeping them away from digital circuitry (DSP, microcontroller, logic). Avoid crossing digital tracks across analog tracks to reduce noise coupling and crosstalk. 26 5. Reference Inputs: It is recommended to use a minimum 10μF tantalum with a 0.1μF ceramic capacitor directly across the reference inputs, VREFP and VREFN. The reference input should be driven by a low-impedance source. For best performance, the reference should have less than 3μVRMS in-band noise. For references with noise higher than this, external reference filtering may be necessary. 6. Analog Inputs: The analog input pins must be driven differentially to achieve specified performance. A true differential driver or transformer (for ac applications) can be used for this purpose. Route the analog inputs tracks (AINP, AINN) as a pair from the buffer to the converter using short, direct tracks and away from digital tracks. A 1nF to 10nF capacitor should be used directly across the analog input pins, AINP and AINN. A low-k dielectric (such as COG or film type) should be used to maintain low THD. Capacitors from each analog input to ground can be used. They should be no larger than 1/10 the size of the difference capacitor (typically 100pF) to preserve the AC common-mode performance. 7. Component Placement: Place the power supply, analog input, and reference input bypass capacitors as close as possible to the device pins. This layout is particularly important for the small-value ceramic capacitors. Surface-mount components are recommended to avoid the higher inductance of leaded components. Figure 26 to Figure 28 illustrate basic connections and interfaces that can be used with the ADS1174/78. Submit Documentation Feedback Copyright © 2007, Texas Instruments Incorporated Product Folder Link(s): ADS1174 ADS1178 ADS1174 ADS1178 www.ti.com SBAS373 – OCTOBER 2007 OPA1632 +3.3V ADS1174 2.2nF Input1 (2) TMS320VC5509 IOVDD AINP1 DVDD (I/O) (1) 10mF AINN1 50W 2.2nF Input2 (2) AINP2 CLK AINN2 DRDY/FSYNC 50W SCLK 2.2nF Input3 (2) AINP3 DOUT1 AINN3 DOUT2 CLKOUT (27MHz) 50W McBSP PORT 50W CVDD (CORE) 200MHz DOUT3 2.2nF Input4 AINP4 (2) DOUT4 AINN4 +5V + SYNC AVDD PWDN2 DVDD +1.8V I/O PWDN1 (1) 10mF +1.6V (1) 10mF PWDN3 20kW PWDN4 100W OPA350 100W 100mF + VREFP + 10mF (1) 0.1mF (1) +3.3V (27MHz clock input selected) CLKDIV VREFN 0.1mF PRODUCT PREVIEW 1kW REF1004 MODE VCOM (1) 0.1mF 47W Buffered VCOM Output OPA350 JTAG (3) Device TEST0 TEST1 DIN AGND DGND (Low-Power, Frame-Sync, TDM, and Fixed-Position data selected.) FORMAT2 FORMAT1 +3.3V FORMAT0 (1) Indicates ceramic capacitors. (2) Indicates COG ceramic capacitors. (3) Optional. For boundary scan test, the ADS1174 digital I/O should connect to a JTAG-compatible device. Figure 26. ADS1174 Basic Connection Drawing 1kW 1kW 2.7nF Buffered VCOM Output +15V (2) Buffered VCOM Output (1) AINP OPA1632 49.9W 0.1mF AINN -15V +15V VOCM (1) AINP OPA1632 0.1mF (2) (1) 10nF 1kW NOTES: (1) Bypass with 10mF and 0.1mF capacitors. (2) 15nF for Low-Speed mode. Figure 27. Basic Differential Input Signal Interface 49.9W AINN -15V 1kW (2) 49.9W (1) 2.7nF 1kW 249W 10nF 49.9W VOCM VIN 1kW VIN VO DIFF = 0.25 ´ VIN VO COMM = VREF (2) 249W NOTES: (1) Bypass with 10mF and 0.1mF capacitors. (2) 56nF for Low-Speed mode. Figure 28. Basic Single-Ended Input Signal Interface Submit Documentation Feedback Copyright © 2007, Texas Instruments Incorporated Product Folder Link(s): ADS1174 ADS1178 27 ADS1174 ADS1178 www.ti.com SBAS373 – OCTOBER 2007 PowerPAD THERMALLY-ENHANCED PACKAGING The PowerPAD concept is implemented in standard epoxy resin package material. The integrated circuit is attached to the leadframe die pad using thermally conductive epoxy. The package is molded so that the leadframe die pad is exposed at a surface of the package. This exposure provides an extremely low thermal resistance to the path between the IC junction and the exterior case. The external surface of the leadframe die pad is located on the printed circuit board (PCB) side of the package, allowing the IC Die die pad to be attached to the PCB using standard flow soldering techniques. This soldering allows efficient attachment to the PCB and permits the board structure to be used as a heat-sink for the package. Using a thermal pad identical in size to the die pad and vias connected to the PCB ground plane, the board designer can now implement power packaging without additional thermal hardware (for example, external heat sinks) or the need for specialized assembly instructions. Figure 29 illustrates a cross-section view of a PowerPAD package. Mold Compount (Epoxy) Wire Bond Wire Bond PRODUCT PREVIEW Leadframe Die Pad Exposed at Base of Package Die Attach Epoxy (thermally conductive) Leadframe Figure 29. Cross-Section View of a PowerPAD Thermally-Enhanced Package 28 Submit Documentation Feedback Copyright © 2007, Texas Instruments Incorporated Product Folder Link(s): ADS1174 ADS1178 ADS1174 ADS1178 www.ti.com SBAS373 – OCTOBER 2007 Figure 30 shows the recommended layer structure for thermal management when using a PowerPad package on a 4-layer PCB design. Note that the thermal pad is placed on both the top and bottom sides of the board. The ground plane is used as the heat-sink, while the power plane is thermally isolated from the thermal vias. Figure 31 shows the required thermal pad etch pattern for the 64-lead HTQFP package used for the ADS1174/78. Nine 13mil (0.33mm) thermal vias plated with one ounce of copper are placed within the thermal pad area for the purpose of connecting the pad to the ground plane layer. The ground plane is used as a heatsink in this application. It is very important that the thermal via diameter be no larger than 13mils in order to avoid solder wicking during the reflow process. Solder wicking results in thermal voids that reduce heat dissipation efficiency and hamper heat flow away from the IC die. The via connections to the thermal pad and internal ground plane should be plated completely around the hole, as opposed to the typical web or spoke thermal relief connection. Plating entirely around the thermal via provides the most efficient thermal connection to the ground plane. Additional PowerPAD Package Information Texas Instruments publishes the PowerPAD Thermally Enhanced Package Application Report (TI literature number SLMA002), available for download at www.ti.com, which provides a more detailed discussion of PowerPAD design and layout considerations. Before attempting a board layout with the ADS1174/78, it is recommended that the hardware engineer and/or layout designer be familiar with the information contained in this document. PRODUCT PREVIEW PowerPAD PCB Layout Considerations for the ADS1174/78 Package Thermal Pad Component Traces 13mils (0.33mm) Component (top) Side Thermal Via Ground Plane Power Plane Thermal Isolation (power plane only) Solder (bottom) Side Package Thermal Pad (bottom trace) Figure 30. Recommended PCB Structure for a 4-Layer Board Submit Documentation Feedback Copyright © 2007, Texas Instruments Incorporated Product Folder Link(s): ADS1174 ADS1178 29 ADS1174 ADS1178 www.ti.com 118mils (3mm) 40mils (1mm) 40mils (1mm) SBAS373 – OCTOBER 2007 Package Outline Thermal Pad 40mils (1mm) 40mils (1mm) 118mils (3mm) 316mils (8mm) Thermal Via 13mils (0.33mm) PRODUCT PREVIEW 316mils (8mm) Figure 31. Thermal Pad Etch and Via Pattern for the 64-Lead HTQFP Package 30 Submit Documentation Feedback Copyright © 2007, Texas Instruments Incorporated Product Folder Link(s): ADS1174 ADS1178 PACKAGE OPTION ADDENDUM www.ti.com 8-Oct-2007 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Eco Plan (2) Qty ADS1174IPAPR PREVIEW HTQFP PAP 64 1000 TBD Call TI Call TI ADS1174IPAPT PREVIEW HTQFP PAP 64 250 TBD Call TI Call TI ADS1178IPAPR PREVIEW HTQFP PAP 64 1000 TBD Call TI Call TI ADS1178IPAPT PREVIEW HTQFP PAP 64 250 TBD Call TI Call TI Lead/Ball Finish MSL Peak Temp (3) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. 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