Ai2410 A1 PROs Signal Processor for Single-Chip CCD B/W Camera 64 pin LQFP (7x7) Description The Ai2410 is a signal processor for CCD B/W camera application. It combines CCD analog signal processor, timing logic controller and vertical into one single chip. Function y Timing Logic Controller y CDS (Correlated Double Sampling) y AGC (Automatic Gain Control) y Gamma Corrections y Video Driver y Vertical Driver Absolute Maximum Ratings (Ta = 25 o C ) Parameter Supply voltage Vcc , VDD Supply voltage VEE Rating Unit 7 V Reference V voltage Features Supply voltage VHH , VME VEE - 0.3 to VHH + 0.3 V y 5 steps sample and hold y Wide dynamic range -4 to 32dB of AGC y Storage Temperature TSTG − 65 ~ +150 o Built-in Opamp for AGC control loop C y 3 Mode dark-clip control Operating Temperature TOPR − 20 ~ +75 o C y 2 Mode white-clip control y Allowable Power Dissipation 500 75 ohm video driver and SAG compensation y Auto Iris and electronic shutter mode y Supports EIA/ CCIR of 510H/760H system CCD image sensors 760H: 28.63636MHz (EIA) and 28.375MHz (CCIR) PD Operating Conditions Parameter Built-in sync signal generation function y Support external sync function Rating Unit Supply Voltage Vcc , VDD 4.75 ~ 5.25 V Supply voltage VHH VEE + 25 V Supply voltage VME VEE + 10 V 510H: 19.0699MHz (EIA), 18.9375MHz (CCIR) y mW Application CCD monochrome camera Structure BiCMOS silicon monolithic IC Block Diagram Preliminary Signal Processor for Single-Chip CCD B/W Camera Ai2410 CCD Signal Processor Timing Logic Controller 2 Preliminary Signal Processor for Single-Chip CCD B/W Camera Ai2410 Vertical Driver 3 Preliminary Signal Processor for Single-Chip CCD B/W Camera Ai2410 PIN Configuration Ai2410 4 Preliminary Signal Processor for Single-Chip CCD B/W Camera Ai2410 Pin Description Timing Logic Controller No . Symbol I/O Description 3 RG O Reset gate pulse output 6 CLP1O O Pulse output for clamp 7 CLP2O O Pulse output for clamp 8 HD O Horizontal drive output 9 VD O Vertical drive output 10 CVDD 11 SPUP I Shutter speed up reference voltage/ shutter speed setting; strobe input in serial mode 12 IRIN/ED1 I Iris signal input/shutter speed setting; clock input in serial mode 13 SPDN I Shutter speed down reference voltage/ shutter speed setting; data input in serial mode 14 Vreg I Bias current supply for comparator 15 CGND 41 EXT Digital power supply Digital ground O External sync/internal sync identification signal High: external sync; Low: internal sync 42 HBAND I Selection pin for normal (510H) / high band (760H) support 43 Mode5 I Low: Normal mode; High: Test mode (with pull-down resistance) 44 GND 45 CKI I Clock Input 46 OSCOUT O Oscillation (crystal oscillator) inverter output 47 OSCIN I Oscillation (crystal oscillator) inverter input 48 VDD 49 IRENB I Low: Electronic Shutter mode; High: Auto iris mode (with pull-up resistance) 50 ENB I XSUB pulse ON/OFF control (with pull-up resistance) Digital ground Power supply Low: XSUB pulse output stop; High: XSUB pulse output 51 Mode2 I Electronic shutter speed input switchover (with pull-up resistance) Low: serial input; High: parallel input 52 Mode1 I Low: EIA; High: CCIR (with pull-down resistance) 53 HCOMP O Comparator output (H phase comparator) 54 HPLL I Horizontal drive signal input (with pull-up resistance) 55 VR/VSYN I Vertical drive signal input/composite sync input (with pull-up resistance) 56 ESYNC I Low: SYNC sync or internal sync; High: VD/HD sync (with pull-down resistance) 5 Preliminary Signal Processor for Single-Chip CCD B/W Camera Ai2410 CCD Signal Processor No Symbol 16 CLP1 I/O Specification Equivalent Circuit I Description Clamping input pin (active high) 17 Linear O Linear signal output pin :in 8 output signal turn to Vcc γ2 output 18 γ OUT O Gamma compensation signal output pin γ1 γ2 19 DET OUT O output when Pin 39 at open output when Pin 39 at 5V Output pin of AGC detection signal 20 γ IN Input pin of the gamma I compensation circuit 6 Preliminary Signal Processor for Single-Chip CCD B/W Camera 21 Ai2410 γ CLP Capacitor connecting pin for gamma input clamp 22 AGC OUT O Output pin of signal passed through AGC 23 AGC MAX I DC Maximum gain setting pin of AGC amplifier 24 OP OUT O Output pin of operational amplifier 25 OP IN+ I Non-inverted input pin of the operational amplifier (AGC detection signal input pin) 26 OP IN- Inverted input pin of the I operational amplifier 7 Preliminary Signal Processor for Single-Chip CCD B/W Camera 27 AGC I Ai2410 DC Gain control pin of AGC amplifier CONT 28 DATA I CCD signal input pin 29 PG I CCD signal input pin 30 CLP2 I Clamping input pin (active high) 32 WCCONT I 34 DCCONT I Input Voltage White clip level adjusting pin GND Preset mode 2-3.5V Control mode Input Voltage Dark clip level adjusting pin GND Preset mode 1 2 – 3.5V Control mode Vcc Preset mode 2 8 Preliminary Signal Processor for Single-Chip CCD B/W Camera 35 Ai2410 IRIS CLP Capacitor connecting pin for IRIS output clamp 36 IRIS O Output pin of the IRIS control signal 37 SAG I Input pin of SAG compensation signal. AC couple from output Pin28 Video through external capacitor 38 Video O 39 AGND Analog ground of CCD signal processor 40 AVCC Analog supply of CCD signal processor 42 HBand/FLD O VIDEO signal output pin Digital Output 0-5V Field identification signal output (High: odd field; Low: even field) 31 REF_3V - 3V reference voltage Normally leave it open or supply 3V externally. 9 Preliminary Signal Processor for Single-Chip CCD B/W Camera Ai2410 Vertical Driver No Symbol I/O Description 1 H1 O H1 clock output for CCD horizontal register drive 2 H2 O H2 clock output for CCD horizontal register drive 4 HVDD Power supply for H1 and H2 5 HGND GND for H1 and H2 57 VHH Power supply (+15V) 58 VSUB O 59 V2 O 60 V1 O 61 VME 62 V3 O 63 V4 O 64 VEE Output control (VSUB) Output control ( Vφ 2 ) Output control ( Vφ 1 ) Power supply (0V) Output control ( Vφ 3 ) Output control ( Vφ 4 ) Power supply (-8.5V) 10 Preliminary Signal Processor for Single-Chip CCD B/W Camera Ai2410 Electrical Characteristics ( Vcc =5V, Ta =25 o C ) Timing Logic Controller DC Characteristic PARAMETER SYMBOL Supply Voltage VDD Input Voltage VIH VIL CONDITIONS MIN TYP MAX UNITS 4.75 5.0 5.25 V 0.3 VDD V 0.7 VDD V VOH 1 VOL1 I OH =-2mA I OL =4mA VDD -0.8 VOH 2 VOL 2 I OH =-8mA I OL =8mA VDD -0.8 VOH 3 VOL 3 I OH =-12mA I OL =12mA VDD -0.8 I OH =-1mA I OL =1mA VDD /2 Pin 3 (OSCOUT) VOH 4 VOL 4 Feedback resistance RFB Pull-up current I PU VIL =0V -80 Pull-down current I PD VIH = VDD 40 Current consumption I DD VDD =5V Output voltage 1: All output pins except V 0.4 V those below) Output voltage 2: Pin 6 (RG) and Pin 8 V 0.4 V (HCOMP) Output voltage 3: Pin 62 (H2) and Pin 63 V 0.4 V (H1) Output voltage 4: V 0.4 V IN =GND or VDD 250k 1M 2.5M V Ω μA μA mA 28 Normal operating state AC Characteristic SYMBOL Condition Min. Max. ts2 SPDNV (ED2) setup time for IRIN (ED1) rise 20ns - th2 SPDNV (ED2) hold time for IRIN (ED1) rise 20ns - 11 Preliminary Signal Processor for Single-Chip CCD B/W Camera Ai2410 ts1 IRIN (ED1) setup time for SPUPV (ED0) rise 20ns - tw0 SPUPV (ED0) pulse width 20ns 50 μs ts0 SPUPV (ED0) setup time for IRIN (ED1) rise 20ns - CCD Signal Processor PARAMETER CONDITIONS AGC Gain AGC dynamic range MIN TYP -4 MAX UNITS 32 dB AGC MAX = 4V, AGC CONT = 1.5V and DATA IN = 100mV 18 20 dB AGC CONT = 5V and DATA IN = 500mV -4 -1 dB AGC CONT = 1.5V and DATA IN = 30mV 30 32 AGC CONT = 3.55V and DATA IN = 320mV 8 10 12 dB 2.25 2.55 2.85 V 530 630 730 mV 580 680 780 mV 1.5 2.6 3.5 dB AGC OUT DC output level of AGC OUT γ1 γ2 γ IN=500mV γ IN=500mV Linear Gain Gain between γ IN and Linear dB γ IN =500mV DET OUT DC output level of DET OUT 1.8 2.0 2.2 V IRIS DC output level of IRIS 1.1 1.3 1.5 V 8 10 12 dB 5.7 6.0 6.3 dB 270 293 316 mV Preset mode 1 -15 0 15 mV Preset mode 2 0 20 40 mV 3 5 mV Gain between DATA Input and IRIS: DATA input = 300mV Video Driver Gain between DRIVE IN and VIDEO: DRIVE IN = 700mV SYNC Level Dark Clip DC CONT = 2V DC CONT = 3.3V White Clip 80 130 780 820 860 mV 300 600 mV DRIVER IN = 1500mV WC CONT = GND WC CONT = 2.2V WC CONT = 3.3V Opamp mV 1000 1300 mV DC output level of OP OUT OP IN+ = 2.5V and OP IN- = 4V 0.8 OP IN+ = 4V and OP IN- = 2.5V 4.5 12 4.8 1.2 V V Preliminary Signal Processor for Single-Chip CCD B/W Camera Ai2410 Vertical Driver DC Characteristic Description Supply Voltage Operation Current Output Current Symbol Condition VP1 VSS Min. Typ. Max. Unit 14.5 15 15.5 V -9.5 -8.5 -7.5 V I P1 I P0 Shutter speed: 1/100000s 2.0 3.5 mA Shutter speed: 1/100000s 4.5 5.0 mA I SS Shutter speed: 1/100000s -8.5 -6.5 mA I OL V1-4 = -8V 25 37 mA I OM 1 V1-4 = -0.5V I OM 2 V1,3= 0.5V I OH V1,3 = 14.5V I OSL VSUB = -8.5V I OSH VSUB = 14.5V -15 9 13.5 -18 12 -10 mA mA -12 18 mA mA -10.5 -7 mA o AC Characteristic ( VP1 = 15V, VP 0 =GND, VSS =-8.5V and Ta =25 C Description Delay Time Rising Time Output Noise Symbol Condition Min. Typ. Max. Unit TPLM No Load 10 40 70 ns TPMH No Load 10 30 70 ns TPLH No Load 10 40 100 ns TPML No Load 10 100 200 ns TPHM No Load 10 100 180 ns TPHL No Load 10 60 100 ns TPLM VSS → VP 0 400 700 930 ns TPMH VP 0 → VP1 400 650 930 ns TPLH VSS → VP1 10 50 100 ns TPML VP 0 → VSS 200 300 500 ns TPHM VP1 → VP 0 400 600 820 ns TPHL VCLH , VCLL VP1 → VP 0 10 50 100 ns 0.5 V VCMH ,VCML 13 Preliminary Signal Processor for Single-Chip CCD B/W Camera Ai2410 14 Preliminary Signal Processor for Single-Chip CCD B/W Camera Ai2410 External Synchronization 1. External/Internal Sync Selection External or internal synchronization is selected automatically by a combination of 3 pins (VR/SYNC, HPLL and ESYNC) to which the sync signal is input externally. The table below shows the input pattern combinations. Input pattern VR/SYNC pin: SYNC signal HPLL pin : Open ESYNC pin : Open VR/SYNC pin: VD signal HPLL pin : HD signal ESYNC pin : VDD VR/SYNC pin: SYNC signal HPLL pin : Open ESYNC pin : Open EXT pin Output High High Low Sync state External sync External sync Internal sync Note ) Operation is possible even if the VD cycle of the VD input in the VD/HD sync mode is longer than normal. The EXT pin is the external/internal sync identification signal output pin. This output signal can be used as the signal to select LC oscillation for expanding the lock range for external synchronization or the oscillator for improving the oscillation accuracy for internal synchronization. 2. Reset Operation SYNC synchronization The VR1 signal component is extracted from the SYNC signal supplied externally and, for EIA,V reset is performed so that the VD pulse falls at the count of 259H (262.5-3.5H) from the fall of the VR1 pulse. For CCIR, it is reset in such a way that the VD pulse falls at the count of 309H(312.5-3.5H).For these reasons, it is a prerequisite that the SYNC signal input comply with the EIA or CCIR standard. VD/HD synchronization V reset is performed so that the VD pulse 1H later after detecting the fall of the VD(VDR) pulse supplied externally. Therefore, this enables V reset operation regardless of the field line number. The phase difference between the VDRpulse and HD pulse which is locked horizontally at PLL circuit identifies whether the field is odd or even. (VDR must have a pulse width of 2H or more.) 15 Preliminary Signal Processor for Single-Chip CCD B/W Camera Ai2410 Electronic Shutter/Auto IRIS By setting the ENB(Pin 7) high, the XSUB pulse is output for a specific period to activate the electronic shutter and auto iris. 1. Auto Iris (IRENB=high, MODE2=any level) No Symbol Function 25 IRIN/ED1 Iris signal input 23 SPDN/ED2 Shutter speed down reference voltage 24 SPUP/ED0 Shutter speed up reference voltage 2. Parallel input electronic shutter (IRENB=low, MODE2=high) No Symbol 23 SPDN/ED2 H H H H L L L L 25 IRIN/ED1 H H L L H H L L 24 SPUP/ED0 H L H L H L H L Shutter speed Function EIA: 1/100 1/250 1/500 1/1000 1/2000 1/5000 1/10000 1/100000 CCIR: 1/120 3. Serial input electronic shutter (IRENB=low, MODE2=high) The ED2 data is latched in the register at the ED1 rise, and retrieved internally at the ED0 rise. Typical shutter speed EIA CCIR Load value Shutter speed Load value Shutter speed 00h 1/100000 00h 1/80000 4Eh 1/10000 4Ah 1/10000 6Ah 1/5000 65h 1/5000 87h 1/2000 82h 1/2000 9Ch 1/1000 97h 1/1000 ACh 1/500 A7h 1/500 CAh 1/250 C5h 1/250 EDh 1/100 E1h 1/120 16 Preliminary Signal Processor for Single-Chip CCD B/W Camera Ai2410 Mode Control No. Symbol I/O Low High Remarks 7 ENB I XSUB stop XSUB output 20 IRENB I Electronic shutter Auto iris Valid only when ENB is high 16 MODE2 I Serial input Parallel input Valid only when ENB is high and IRENB is low 25 IRIN/ED1 I Auto iris control signal input pin (IRENB = high) 23 SPDN/ED2 I Shutter speed setting pin (IRENB = low) 24 SPUP/ED0 I 15 MODE1 I EIA 11 HPLL I Internal sync: HPLL (open) Valid only when ENB is high CCIR VR/SYNC (open) SYNC sync: HPLL (open) 10 VR/SYNC VR/SYNC (SYNC input) I VD/HD sync: HPLL (HD input) VR/SYNC (VD input) 9 ESYNC I SYNC sync VD/HD sync Internal sync 12 EXT O Internal sync External sync Switchover between internal and external sync is automatically identified by input state at Pin 9, 10 and 11 Mode Tables 1. Internal sync mode Interlace Field readout Frame readout O O Electronic shutter ON O O Auto iris ON O O XSUB pulse OFF 1 1 EIA for 1/60 s accumulation; CCIR for 1/50 s accumulation O: Can be used 2. SYNC sync (external sync) mode Interlace Field readout Frame readout O O Electronic shutter ON O O Auto iris ON O O XSUB pulse OFF 1 17 Preliminary Signal Processor for Single-Chip CCD B/W Camera Ai2410 1 EIA for 1/60 s accumulation; CCIR for 1/50 s accumulation O: Can be used 3. VD/HC sync (external sync) mode VD input with normal cycle Interlace XSUB pulse OFF 1 Serial input electronic VD input with longer cycle than normal interlace Field readout Frame readout Field readout Frame readout O O O X O O X X O O X X O O X X shutter ON Parallel input electronic shutter ON Auto iris ON 1 EIA for 1/60 s accumulation; CCIR for 1/50 s accumulation O: Can be used X: Cannot be used Note Only in the VD/HD sync mode, the external synchronization is possible during which VD pulses with longer cycle than normal are input to the VR/SYNC pin 18 Preliminary Signal Processor for Single-Chip CCD B/W Camera Ai2410 19 Preliminary Signal Processor for Single-Chip CCD B/W Camera Ai2410 20 Preliminary Signal Processor for Single-Chip CCD B/W Camera Ai2410 21 Preliminary Signal Processor for Single-Chip CCD B/W Camera Ai2410 22 Preliminary Signal Processor for Single-Chip CCD B/W Camera Ai2410 23 Preliminary Signal Processor for Single-Chip CCD B/W Camera Ai2410 24 Preliminary Signal Processor for Single-Chip CCD B/W Camera Ai2410 25 Preliminary Signal Processor for Single-Chip CCD B/W Camera Ai2410 26 Preliminary Signal Processor for Single-Chip CCD B/W Camera Ai2410 REVISION HISTORY Revision Description Date V1.0 Preliminary Release 9 May 2008 27 Preliminary