1 MSPS, Ultralow Power, 12-Bit ADC in 8-Lead LFCSP AD7091 Data Sheet FEATURES FUNCTIONAL BLOCK DIAGRAM VDD REGCAP Fast throughput rate of 1 MSPS Specified for VDD of 2.09 V to 5.25 V INL of ±1 LSB maximum Analog input range of 0 V to VDD Ultralow power 367 μA typical at 3 V and 1 MSPS 324 nA typical at 3 V in power-down mode Reference provided by VDD Flexible power/throughput rate management High speed serial interface: SPI®-/QSPI™-/MICROWIRE®-/ DSP-compatible Busy indicator Power-down mode 8-lead, 2 mm × 2 mm LFCSP package Temperature range: −40°C to +125°C AD7091 12-BIT SAR ADC T/H VIN SDO SERIAL INTERFACE SCLK CS CLK OSC CONVERSION CONTROL LOGIC 10494-001 CONVST GND Figure 1. 1100 VDD = 3V 1000 900 APPLICATIONS 800 POWER (μW) Battery-powered systems Handheld meters Medical instruments Mobile communications Instrumentation and control systems Data acquisition systems Optical sensors Diagnostic/monitoring functions Energy harvesting 700 600 500 400 300 200 0 0 200 400 600 800 THROUGHPUT RATE (kSPS) 1000 10494-002 100 Figure 2. Power Dissipation vs. Throughput Rate GENERAL DESCRIPTION The AD7091 is a 12-bit successive approximation register analog-to-digital converter (SAR ADC) that offers ultralow power consumption (typically 367 μA at 3 V and 1 MSPS) while achieving fast throughput rates (1 MSPS with a 50 MHz SCLK). The AD7091 operates from a single 2.09 V to 5.25 V power supply. The AD7091 also features an on-chip conversion clock and a high speed serial interface. The conversion process and data acquisition are controlled using a CONVST signal and an internal oscillator. The AD7091 has a serial interface that allows data to be read after the conversion while achieving a 1 MSPS throughput rate. The AD7091 uses advanced design and process techniques to achieve very low power dissipation at high throughput rates. Rev. A The reference is derived internally from VDD. This design allows the widest dynamic input range to the ADC; that is, the analog input range for the AD7091 is from 0 V to VDD. PRODUCT HIGHLIGHTS 1. 2. 3. 4. 5. Lowest Power 12-Bit SAR ADC Available. High Throughput Rate with Ultralow Power Consumption. Flexible Power/Throughput Rate Management. Average power scales with the throughput rate. Power-down mode allows the average power consumption to be reduced when the device is not performing a conversion. Reference Derived from the Power Supply. Single-Supply Operation. Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. 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Technical Support www.analog.com AD7091 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Converter Operation.................................................................. 10 Applications ....................................................................................... 1 ADC Transfer Function ............................................................. 10 Functional Block Diagram .............................................................. 1 Typical Connection Diagram ................................................... 11 General Description ......................................................................... 1 Analog Input ............................................................................... 11 Product Highlights ........................................................................... 1 Modes of Operation ................................................................... 12 Revision History ............................................................................... 2 Power Consumption .................................................................. 13 Specifications..................................................................................... 3 Multiplexer Applications ........................................................... 14 Timing Specifications .................................................................. 4 Serial Interface ................................................................................ 15 Absolute Maximum Ratings ............................................................ 5 Busy Indicator Enabled.............................................................. 15 Thermal Resistance ...................................................................... 5 Busy Indicator Disabled ............................................................ 16 ESD Caution .................................................................................. 5 Software Reset ............................................................................. 17 Pin Configuration and Function Descriptions ............................. 6 Interfacing with an 8-/16-Bit SPI Bus ...................................... 17 Typical Performance Characteristics ............................................. 7 Outline Dimensions ....................................................................... 18 Terminology ...................................................................................... 9 Ordering Guide .......................................................................... 18 Theory of Operation ...................................................................... 10 Circuit Information .................................................................... 10 REVISION HISTORY 6/13—Rev. 0 to Rev. A Changes to Figure 22 ...................................................................... 13 Added Multiplexer Applications Section .................................... 14 Updated Outline Dimensions ....................................................... 18 10/12—Revision 0: Initial Version Rev. A | Page 2 of 20 Data Sheet AD7091 SPECIFICATIONS VDD = 2.09 V to 5.25 V, fSAMPLE = 1 MSPS, fSCLK = 50 MHz, TA = −40°C to +125°C, unless otherwise noted. Table 1. Parameter DYNAMIC PERFORMANCE 1 Signal-to-Noise Ratio (SNR) 2 Signal-to-Noise-and-Distortion Ratio (SINAD)2 Total Harmonic Distortion (THD)2 Spurious-Free Dynamic Range (SFDR)2 Aperture Delay2 Aperture Jitter2 Full Power Bandwidth2 DC ACCURACY Resolution Integral Nonlinearity (INL)2 Differential Nonlinearity (DNL)2 Offset Error2 Gain Error2 Total Unadjusted Error (TUE)2 ANALOG INPUT Input Voltage Range DC Leakage Current Input Capacitance 3 LOGIC INPUTS Input High Voltage (VINH) Input Low Voltage (VINL) Input Current (IIN) Input Capacitance (CIN)3 LOGIC OUTPUTS Output High Voltage (VOH) Output Low Voltage (VOL) Floating State Leakage Current Floating State Output Capacitance3 Output Coding CONVERSION RATE Conversion Time Track-and-Hold Acquisition Time2, 3 Throughput Rate POWER REQUIREMENTS VDD IDD Normal Mode—Static 4 Normal Mode—Operational Power-Down Mode Test Conditions/Comments fIN = 10 kHz sine wave VDD < 2.7 V VDD ≥ 2.7 V Min Typ 67 66.3 68 69 68 At −3 dB At −0.1 dB Max dB dB dB −86 −85 5 40 1.5 1.2 −74 −75 ±0.6 ±0.3 ±0.7 ±1.2 1.1 ±1 ±0.9 +5 ±4 12 Guaranteed no missing codes to 12 bits −8.5 0 During acquisition phase Outside acquisition phase VDD ±1 7 1 0.7 × VDD Typically 10 nA, VIN = 0 V or VDD ISOURCE = 200 µA ISINK = 200 µA Unit dB dB ns ps MHz MHz Bits LSB LSB LSB LSB LSB V µA pF pF 0.3 × VDD ±1 5 V V µA pF 0.4 ±1 5 V V µA pF 650 350 1 ns ns MSPS 5.25 V 27 28 554 442 µA µA µA µA µA µA µA µA VDD − 0.2 Straight binary Full-scale step input 2.09 VIN = 0 V VDD = 5.25 V VDD = 3 V VDD = 5.25 V, fSAMPLE = 1 MSPS VDD = 3 V, fSAMPLE = 1 MSPS VDD = 3 V, fSAMPLE = 100 kSPS VDD = 5.25 V VDD = 3 V VDD = 3 V, TA = −40°C to +85°C Rev. A | Page 3 of 20 9.3 9.1 450 367 45 0.374 0.324 0.324 8.2 8 1.8 AD7091 Data Sheet Parameter Power Dissipation Normal Mode—Static4 Normal Mode—Operational Power-Down Mode Test Conditions/Comments VIN = 0 V VDD = 5.25 V VDD = 3 V VDD = 5.25 V, fSAMPLE = 1 MSPS VDD = 3 V, fSAMPLE = 1 MSPS VDD = 5.25 V VDD = 3 V Min Typ Max Unit 50 27 2.4 1.1 2 1 142 84 3 1.4 44 24 µW µW mW mW µW µW Dynamic performance is achieved when SCLK operates in burst mode. Operating a free running SCLK during the acquisition phase degrades dynamic performance. See the Terminology section. Sample tested during initial release to ensure compliance. 4 SCLK is operating in burst mode and CS is idling high. With a free running SCLK and CS pulled low, the IDD static current is increased by 60 µA typical at VDD = 5.25 V. 1 2 3 TIMING SPECIFICATIONS VDD = 2.09 V to 5.25 V, TA = −40°C to +125°C, unless otherwise noted. Signals are specified from 10% to 90% of VDD with a load capacitance of 12 pF on the output pin. 1 Table 2. Parameter fSCLK t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 tQUIET 1 Limit at TMIN, TMAX 50 8 7 0.4 tSCLK 3 0.4 tSCLK 15 10 650 6 18 8 8 100 50 Unit MHz max ns max ns max ns min ns min ns min ns max ns min ns max ns min ns max ns min ns min µs max ns min Description Frequency of serial read clock Delay from the end of a conversion until SDO exits the three-state condition Data access time after SCLK falling edge SCLK high pulse width SCLK to data valid hold time SCLK low pulse width SCLK falling edge to SDO high impedance CONVST pulse width Conversion time CS low time before the end of a conversion Delay from CS falling edge until SDO exits the three-state condition CS high time before the end of a conversion Delay from the end of a conversion until the CS falling edge Power-up time Time between the last SCLK edge and the next CONVST pulse Sample tested during initial release to ensure compliance. Rev. A | Page 4 of 20 Data Sheet AD7091 ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE TA = 25°C, unless otherwise noted. Table 3. Parameter VDD to GND Analog Input Voltage to GND Digital Input Voltage to GND Digital Output Voltage to GND Input Current to Any Pin Except Supplies1 Operating Temperature Range Storage Temperature Range Junction Temperature ESD Human Body Model (HBM) Field-Induced Charged Device Model (FICDM) 1 Table 4. Thermal Resistance Rating −0.3 V to +7 V −0.3 V to VDD + 0.3 V −0.3 V to VDD + 0.3 V −0.3 V to VDD + 0.3 V ±10 mA Package Type 8-Lead LFCSP ESD CAUTION −40°C to +125°C −65°C to +150°C 150°C ±2.5 kV ±1.5 kV Transient currents of up to 100 mA do not cause silicon controlled rectifier (SCR) latch-up. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Rev. A | Page 5 of 20 θJA 36.67 θJC 6.67 Unit °C/W AD7091 Data Sheet PIN CONFIGURATION AND FUNCTION DESCRIPTIONS VDD 1 REGCAP 3 GND 4 8 SDO AD7091 TOP VIEW (Not to Scale) 7 SCLK 6 CS 5 CONVST NOTES 1. THE EXPOSED PAD IS NOT CONNECTED INTERNALLY. FOR INCREASED RELIABILITY OF THE SOLDER JOINTS AND FOR MAXIMUM THERMAL CAPABILITY, SOLDER THE EXPOSED PAD TO THE SUBSTRATE, GND. 10494-003 VIN 2 Figure 3. Pin Configuration Table 5. Pin Function Descriptions Pin No. 1 Mnemonic VDD 2 3 VIN REGCAP 4 GND 5 CONVST 6 CS 7 8 SCLK SDO 9 EPAD Description Power Supply Input. The VDD range is from 2.09 V to 5.25 V. Decouple this supply pin to GND. Typical recommended capacitor values are 10 µF and 0.1 µF. Analog Input. The single-ended analog input range is from 0 V to VDD. Decoupling Capacitor Pin for Voltage Output from Internal Low Dropout (LDO) Regulator. Decouple this output pin separately to GND using a 1 μF capacitor. The voltage at this pin is 1.8 V typical. Ground. This pin is the ground reference point for all circuitry on the AD7091. The analog input signal should be referred to this GND voltage. Conversion Start. Active low, edge triggered logic input. The falling edge of CONVST places the track-and-hold into hold mode and initiates a conversion. Chip Select. Active low logic input. The serial bus is enabled when CS is held low; in this mode CS is used to frame the output data on the SPI bus. Serial Clock. This pin acts as the serial clock input. Serial Data Output. The conversion output data is supplied to this pin as a serial data stream. The bits are clocked out on the falling edge of the SCLK input. The data is provided MSB first. Exposed Pad. The exposed pad is not connected internally. For increased reliability of the solder joints and for maximum thermal capability, solder the exposed pad to the substrate, GND. Rev. A | Page 6 of 20 Data Sheet AD7091 TYPICAL PERFORMANCE CHARACTERISTICS 0 72 VDD = 3V TA = 25°C fIN = 10kHz fSAMPLE = 1MSPS SNR = 69.84dB SINAD = 69.56dB THD = –81.05dB –20 VDD = 5V 70 VDD = 2.7V 68 SNR (dB) AMPLITUDE (dB) –40 TA = 25°C fSAMPLE = 1MSPS –60 –80 VDD = 3V 66 64 –100 0 100 200 300 400 500 FREQUENCY (kHz) 60 10494-004 –140 Figure 4. Typical Dynamic Performance 100 INPUT FREQUENCY (kHz) Figure 7. SNR vs. Analog Input Frequency for Various Supply Voltages 1.0 0 TA = 25°C –10 fSAMPLE = 1MSPS VDD = 3V TA = 25°C fSAMPLE = 1MSPS 0.8 0.6 –20 0.4 –30 0.2 –40 THD (dB) INL (LSB) 10 1 10494-007 62 –120 0 –0.2 –50 –60 –0.4 –70 –0.6 –80 VDD = 3V –100 0 512 1024 1536 2048 2560 3072 3584 4096 CODE VDD = 2.7V 1 100 10 INPUT FREQUENCY (kHz) 10494-008 –90 –1.0 10494-005 –0.8 Figure 8. THD vs. Analog Input Frequency for Various Supply Voltages Figure 5. Typical INL Performance –50 1.0 VDD = 3V T = 25°C 0.8 A fSAMPLE = 1MSPS –55 0.6 VDD = 3V TA = 25°C fIN = 10kHz fSAMPLE = 1MSPS –60 –65 THD (dB) 0.2 0 –0.2 –70 –75 –0.4 –80 –0.6 –1.0 0 512 1024 1536 2048 2560 3072 CODE 3584 4096 Figure 6. Typical DNL Performance –90 10 100 1000 SOURCE IMPEDANCE (Ω) Figure 9. THD vs. Source Impedance Rev. A | Page 7 of 20 10000 10494-009 –85 –0.8 10494-006 DNL (LSB) 0.4 AD7091 75 Data Sheet 550 TA = 25°C fSAMPLE = 1MSPS fSAMPLE = 1MSPS VDD = 2.7V 500 VDD = 5V 65 60 55 1 10 100 INPUT FREQUENCY (kHz) 60 51,436 +25°C –40°C SUPPLY VOLTAGE (V) Figure 13. Operational Supply Current vs. Supply Voltage for Various Temperatures 6000 VDD = 3.3V TA = 25°C 65,536 SAMPLES 50 VDD VDD VDD VDD SUPPLY CURRENT (nA) 5000 40 30 20 10 8108 0 0 0 2047 2048 2049 2050 2051 CODE 5 +25°C –40°C 3 2 1 30 40 SDO CAPACITANCE LOAD (pF) 50 10494-012 VDD = 3V 20 2000 25 85 Figure 14. Power-Down Supply Current vs. Temperature for Various Supply Voltages +125°C 0 10 3000 TEMPERATURE (°C) 7 4 4000 0 –40 Figure 11. Histogram of Codes at Code Center (VDD/2) 6 = 2.09V = 3V = 3.6V = 5.25V 1000 5992 10494-011 NUMBER OF OCCURRENCES (k) 350 250 2.25 2.50 2.75 3.00 3.25 3.50 3.75 4.00 4.25 4.50 4.75 5.00 Figure 10. SINAD vs. Analog Input Frequency for Various Supply Voltages t2 DELAY (ns) +85°C 400 300 10494-010 50 +125°C 450 Figure 12. t2 Delay vs. SDO Capacitance Load, VDD = 3 V Rev. A | Page 8 of 20 125 10494-014 SINAD (dB) VDD = 3V 10494-013 SUPPLY CURRENT (µA) 70 Data Sheet AD7091 TERMINOLOGY Integral Nonlinearity (INL) INL is the maximum deviation from a straight line passing through the endpoints of the ADC transfer function. For the AD7091, the endpoints of the transfer function are zero scale (a point 0.5 LSB below the first code transition) and full scale (a point 0.5 LSB above the last code transition). Signal-to-Noise-and-Distortion Ratio (SINAD) SINAD is the measured ratio of signal to noise and distortion at the output of the ADC. The signal is the rms value of the sine wave, and noise is the rms sum of all nonfundamental signals up to half the sampling frequency (fSAMPLE/2), including harmonics, but excluding dc. Differential Nonlinearity (DNL) DNL is the difference between the measured and the ideal 1 LSB change between any two adjacent codes in the ADC. Total Unadjusted Error (TUE) TUE is a comprehensive specification that includes the gain, linearity, and offset errors. Offset Error Offset error is the deviation of the first code transition (00 … 000 to 00 … 001) from the ideal (such as GND + 0.5 LSB). Total Harmonic Distortion (THD) THD is the ratio of the rms sum of harmonics to the fundamental. For the AD7091, THD is defined as Gain Error Gain error is the deviation of the last code transition (111 … 110 to 111 … 111) from the ideal (such as VDD − 1.5 LSB) after the offset error has been adjusted out. Track-and-Hold Acquisition Time The track-and-hold amplifier returns to track mode after the end of a conversion. The track-and-hold acquisition time is the time required for the output of the track-and-hold amplifier to reach its final value, within ±0.5 LSB, after a conversion. Signal-to-Noise Ratio (SNR) SNR is the measured ratio of signal to noise at the output of the ADC. The signal is the rms amplitude of the fundamental. Noise is the sum of all nonfundamental signals up to half the sampling frequency (fSAMPLE/2), excluding dc. The ratio is dependent on the number of quantization levels in the digitization process: the more levels, the smaller the quantization noise. The theoretical signal-to-noise ratio for an ideal N-bit converter with a sine wave input is given by Signal-to-Noise Ratio = (6.02N + 1.76) dB Therefore, for a 12-bit converter, the SNR is 74 dB. THD (dB ) = 20 log V2 2 + V3 2 + V4 2 + V5 2 + V6 2 V1 where: V1 is the rms amplitude of the fundamental. V2, V3, V4, V5, and V6 are the rms amplitudes of the second through the sixth harmonics. Spurious-Free Dynamic Range (SFDR) SFDR, also known as peak harmonic or spurious noise, is defined as the ratio of the rms value of the next largest component in the ADC output spectrum (up to fSAMPLE/2 and excluding dc) to the rms value of the fundamental. Aperture Delay Aperture delay is the measured interval between the leading edge of the sampling clock and the point at which the ADC samples data. Aperture Jitter Aperture jitter is the sample-to-sample variation in the effective point in time at which the data is sampled. Full Power Bandwidth Full power bandwidth is the input frequency at which the amplitude of the reconstructed fundamental is reduced by 0.1 dB or 3 dB for a full-scale input. Rev. A | Page 9 of 20 AD7091 Data Sheet THEORY OF OPERATION The AD7091 is a 12-bit successive approximation register analog-to-digital converter (SAR ADC) that offers ultralow power consumption (typically 367 µA at 3 V and 1 MSPS) while achieving fast throughput rates (1 MSPS with a 50 MHz SCLK). The part operates from a single power supply in the range of 2.09 V to 5.25 V. The AD7091 provides an on-chip track-and-hold amplifier and an analog-to-digital converter (ADC) with a serial interface housed in a tiny 8-lead LFCSP package. This package offers considerable space-saving advantages compared with alternative solutions. The serial clock input accesses data from the part. The clock for the SAR ADC is generated internally. The analog input range is 0 V to VDD. An external reference is not required for the ADC, nor is there a reference on chip. The reference voltage for the AD7091 is derived from the power supply and, thus, provides the widest dynamic input range of 0 V to VDD. When the ADC starts a conversion, SW2 opens and SW1 moves to Position B, causing the comparator to become unbalanced (see Figure 16). The control logic and the charge redistribution DAC are used to add and subtract fixed amounts of charge from the sampling capacitor to bring the comparator back into a balanced condition. When the comparator is rebalanced, the conversion is complete. The control logic generates the ADC output code. Figure 17 shows the ADC transfer function. CHARGE REDISTRIBUTION DAC VIN SAMPLING CAPACITOR A SW1 B CONVERSION PHASE CONTROL LOGIC SW2 10494-016 CIRCUIT INFORMATION COMPARATOR GND LDO/2 Figure 16. ADC Conversion Phase ADC TRANSFER FUNCTION The AD7091 also features a power-down option to save power between conversions. The power-down feature is implemented using the standard serial interface, as described in the Modes of Operation section. The output coding of the AD7091 is straight binary. The designed code transitions occur midway between successive integer LSB values, such as 0.5 LSB, 1.5 LSB, and so on. The LSB size for the AD7091 is VDD/4096. The ideal transfer characteristic for the AD7091 is shown in Figure 17. CONVERTER OPERATION 111 ... 111 111 ... 110 Figure 15 shows the ADC during its acquisition phase; SW2 is closed and SW1 is in Position A. The comparator is held in a balanced condition, and the sampling capacitor acquires the signal on VIN. 0V 1LSB ACQUISITION PHASE CONTROL LOGIC SW2 COMPARATOR GND LDO/2 10494-015 SW1 B VDD – 1LSB ANALOG INPUT Figure 17. AD7091 Transfer Characteristic SAMPLING CAPACITOR A 1LSB = VDD /4096 011 ... 111 000 ... 010 000 ... 001 000 ... 000 CHARGE REDISTRIBUTION DAC VIN 111 ... 000 Figure 15. ADC Acquisition Phase Rev. A | Page 10 of 20 10494-017 ADC CODE The AD7091 is a SAR ADC based around a charge redistribution DAC. Figure 15 and Figure 16 show simplified schematics of the ADC. Data Sheet AD7091 VDD Figure 19 shows a typical connection diagram for the AD7091. A positive power supply in the range of 2.09 V to 5.25 V should be connected to the VDD pin. The reference is derived internally from VDD and, for this reason, VDD should be well decoupled to achieve the specified performance; typical values for the decoupling capacitors are 100 nF and 10 μF. The analog input range is 0 V to VDD. The typical value for the regulator bypass decoupling capacitor (REGCAP) is 1 μF. The conversion result is output in a 12-bit word with the MSB first. D1 R1 VIN C1 1pF D2 C2 3.6pF C3 2.5pF NOTES 1. DURING THE CONVERSION PHASE, THE SWITCH IS OPEN. DURING THE TRACK PHASE, THE SWITCH IS CLOSED. Figure 18. Equivalent Analog Input Circuit Alternatively, because the supply current required by the AD7091 is so low, a precision reference can be used as the supply source to the part. A reference from the REF19x or ADR34xx voltage reference family (REF195 or ADR3450 for 5 V, and REF193 or ADR3430 for 3 V) can be used to supply the required voltage to the ADC. This configuration is especially useful if the power supply is quite noisy, or if the system supply voltages are at some value other than 5 V or 3 V, such as 15 V. Capacitor C1 in Figure 18 is typically about 1 pF and can primarily be attributed to pin capacitance. Resistor R1 is a lumped component made up of the on resistance of a switch. This resistor is typically about 500 Ω. Capacitor C2 is the ADC sampling capacitor and typically has a capacitance of 3.6 pF. In applications where harmonic distortion and signal-to-noise ratio (SNR) are critical, the analog input should be driven from a low impedance source. Large source impedances significantly affect the ac performance of the ADC and may necessitate the use of an input buffer amplifier, as shown in Figure 19. The choice of the op amp is a function of the particular application. If the busy indicator function is required, connect a pull-up resistor of typically 100 kΩ to VDD to the SDO pin (see Figure 19). In addition, for applications in which power consumption is a concern, the power-down mode can be used to improve the power performance of the ADC (see the Modes of Operation section for more information). When no amplifier is used to drive the analog input, the source impedance should be limited to low values. The maximum source impedance depends on the amount of total harmonic distortion (THD) that can be tolerated. The THD increases as the source impedance increases and performance degrades. Figure 9 shows a graph of THD vs. source impedance when using a supply voltage of 3 V and a sampling rate of 1 MSPS. ANALOG INPUT Figure 18 shows an equivalent circuit of the AD7091 analog input structure. The D1 and D2 diodes provide ESD protection for the analog input. To prevent the diodes from becoming forward-biased and conducting current, ensure that the analog input signal never exceeds VDD by more than 300 mV. These diodes can conduct a maximum of 10 mA without causing irreversible damage to the part. To achieve the specified performance, use an external filter—such as the one-pole, low-pass RC filter shown in Figure 19—on the analog input connected to the AD7091. WITH BUSY INDICATOR VDD (2.09V to 5.25V) VDD 10μF 1μF 100nF VDD REGCAP VIN 4.7nF AD7091 SCLK MICROPROCESSOR/ MICROCONTROLLER/ DSP CS CONVST GND 10494-018 ANALOG INPUT 100kΩ SDO 51Ω 10494-019 TYPICAL CONNECTION DIAGRAM Figure 19. Typical Connection Diagram Rev. A | Page 11 of 20 AD7091 Data Sheet MODES OF OPERATION To read back data stored in the conversion result register, wait until the conversion is complete, and then pull CS low. The conversion data is subsequently clocked out on the SDO pin (see Figure 20). Because the output shift register is 12 bits wide, data is shifted out of the device as a 12-bit word under the control of the serial clock input (SCLK). After reading back the data, the user can pull CONVST low again to start another conversion after the tQUIET time has elapsed. The mode of operation of the AD7091 is selected by controlling the logic level of the CONVST signal when a conversion is complete. The two modes of operation are normal mode and power-down mode. These modes of operation provide flexible power management options, allowing optimization of the power dissipation to throughput rate ratio for different application requirements. The logic level of the CONVST pin at the end of a conversion determines whether the AD7091 remains in normal mode or enters power-down mode (see the Normal Mode section and the Power-Down Mode section). Similarly, if the device is in powerdown mode, CONVST controls whether the device returns to normal mode or remains in power-down mode. Power-Down Mode The power-down mode of operation is intended for use in applications where slower throughput rates and lower power consumption are required. In this mode, the ADC can be powered down after each conversion or after a series of conversions performed at a high throughput rate, with the ADC powered down for relatively long durations between these bursts of several conversions. When the AD7091 is in power-down mode, the serial interface remains active even though all analog circuitry is powered down. Normal Mode The normal mode of operation is intended to achieve the fastest throughput rate performance. In normal mode, the AD7091 remains fully powered at all times, so power-up times are not a concern. Figure 20 shows the general timing diagram of the AD7091 in normal mode. To enter power-down mode, pull CONVST low and keep it low prior to the end of a conversion (denoted as EOC in Figure 21). After the conversion is complete, the logic level of the CONVST pin is tested. If the CONVST signal is logic low, the part enters power-down mode. In normal mode, the conversion is initiated on the falling edge of CONVST, as described in the Serial Interface section. To ensure that the part remains fully powered at all times, CONVST must return high after t7 and remain high until the conversion is complete. At the end of a conversion (denoted as EOC in Figure 20), the logic level of CONVST is tested. The serial interface of the AD7091 is functional in power-down mode; therefore, users can read back the conversion result after the part enters power-down mode. EOC t7 CONVST t8 t12 CS t10 SDO CONVERSION DATA 1. 10494-026 NOTES IS DON’T CARE. 2. EOC IS THE END OF A CONVERSION. Figure 20. Normal Mode of Operation, Serial Interface Read Timing EOC POWER-DOWN MODE CONVST t13 t8 t12 CS t10 SDO CONVERSION DATA 1. 10494-027 NOTES IS DON’T CARE. 2. EOC IS THE END OF A CONVERSION. Figure 21. Entering and Exiting Power-Down Mode Rev. A | Page 12 of 20 Data Sheet AD7091 To exit power-down mode and power up the AD7091, pull CONVST high at any time. On the rising edge of CONVST, the device begins to power up. The power-up time of the AD7091 is 100 µs. To start the next conversion, operate the interface as described in the Normal Mode section. POWER CONSUMPTION The two modes of operation for the AD7091—normal mode and power-down mode (see the Modes of Operation section for more information)—produce different power vs. throughput rate performances. Using a combination of normal mode and power-down mode achieves the optimum power performance. To achieve optimum static current consumption, SCLK should be in burst mode and CS should idle high. Failure to adhere to these guidelines results in increased static current. Improved power consumption for the AD7091 can also be achieved by carefully selecting the VDD supply (see Figure 13). Power Consumption in Normal Mode With a 3 V VDD supply and a throughput rate of 1 MSPS, the IDD current consumption for the part in normal operational mode is 367 μA (composed of 9.1 μA of static current and 357.9 μA of dynamic current during conversion). The dynamic current consumption is directly proportional to the throughput rate. The following example calculates the power consumption of the AD7091 when operating in normal mode with a 500 kSPS throughput rate and a 3 V supply. The contribution to the total power dissipated by the normal mode static operation is 9.1 μA × 3 V = 27 μW Therefore, the total power dissipated at 500 kSPS is 537 μW + 27 μW = 564 μW Power Consumption Using a Combination of Normal Mode and Power-Down Mode A combination of normal mode and power-down mode achieves the optimum power performance. This operation can be performed at constant sampling rates of <10 kSPS. Figure 22 shows the AD7091 conversion sequence using a combination of normal mode and power-down mode with a throughput of 5 kSPS. With a VDD supply voltage of 3 V, the static current is 9.1 μA. The dynamic current is 357.9 μA at 1 MSPS. The current consumption during power-down mode is 324 nA. A conversion takes typically 650 ns to complete, and the AD7091 takes 100 μs to power up from power-down mode. The dynamic conversion time contributes 5 μW to the overall power dissipation as follows: ((5 kSPS/1 MSPS) × 357.9 μA) × 3 V = 5 μW The contribution to the total power dissipated by the normal mode static operation and the power-down mode is (((100 μs + 650 ns)/200 μs) × 9.1 μA) × 3 V + ((99.4 μs/200 μs) × 324 nA) × 3 V = 14 μW The dynamic conversion time contributes 537 μW to the overall power dissipation as follows: Therefore, the total power dissipated at 5 kSPS is 5 μW + 14 μW = 19 μW ((500 kSPS/1 MSPS) × 357.9 μA) × 3 V = 537 μW EOC CONVST 99μs POWER-DOWN 650ns CONVERSION 100μs POWER-UP CS SDO DATA 200μs 10494-022 NOTES 1. EOC IS THE END OF A CONVERSION. Figure 22. Conversion Sequence with Normal Mode and Power-Down Mode, 5 kSPS Throughput Rev. A | Page 13 of 20 AD7091 Data Sheet Figure 23 and Figure 24 show the typical power dissipation vs. throughput rate for the AD7091 at 3 V for the VDD supply. Figure 24 shows the reduction in power consumption that can be achieved when power-down mode is used compared with using only normal mode at lower throughput rates. 1100 A multiplexer can be used in the signal chain to switch multiple analog input signals to the AD7091. In such applications, control the multiplexer switch time to ensure accurate analogto digital-conversion of the input signals. To allow the AD7091 to fully acquire the input signal, the multiplexer should switch in the channel to be converted a minimum of 350 ns before initiating a conversion. The multiplexer should also hold this channel at the AD7091 for a minimum of 200 ns after the CONVST falling edge. VDD = 3V 1000 900 800 POWER (μW) MULTIPLEXER APPLICATIONS 700 600 500 400 300 200 0 0 200 400 600 800 1000 THROUGHPUT RATE (kSPS) 10494-124 100 Figure 23. Power Dissipation vs. Throughput Rate (Full Range) 100 VDD 10 1 0.01 VDD = 3V VIN = 0V 0.1 1 10 100 THROUGHPUT RATE (kSPS) 10494-123 POWER (μW) VDD (NO PD) Figure 24. Power Dissipation vs. Throughput Rate (Lower Range) Rev. A | Page 14 of 20 Data Sheet AD7091 SERIAL INTERFACE The AD7091 serial interface consists of four signals: SCLK, SDO, CONVST, and CS. The serial interface is used to access data from the result register and to control the modes of operation of the device. The busy indicator allows the host to detect when the SDO pin exits the three-state condition after the end of a conversion. When the busy indicator is enabled, 13 SCLK cycles are required: 12 clock cycles to propagate the data and an additional clock cycle to return the SDO pin to the three-state condition. The SCLK pin is the serial clock input for the device. The SDO pin outputs the conversion result; data transfers take place with respect to SCLK. The CONVST pin is used to initiate the conversion process and to select the mode of operation of the AD7091 (see the Modes of Operation section). The CS pin is used to frame the data. The falling edge of CS takes the SDO line out of a high impedance state. A rising edge on CS returns the SDO line to a high impedance state. To enable the busy indicator feature, a conversion must first be started. A high-to-low transition on CONVST initiates a conversion. This transition places the track-and-hold into hold mode and samples the analog input at this point. If the user does not want the AD7091 to enter power-down mode, CONVST should be taken high before the end of the conversion. A conversion requires 650 ns to complete. When the conversion process is finished, the track-and-hold returns to track mode. Before the end of a conversion, pull CS low to enable the busy indicator (see Figure 26). The logic level of CS at the end of a conversion determines whether the busy indicator is enabled. This feature affects the propagation of the MSB with respect to CS and SCLK. The conversion result is shifted out of the device as a 12-bit word under the control of SCLK and the logic level of CS at the end of a conversion. At the end of a conversion, SDO is driven low. SDO remains low until the MSB (DB11) of the conversion result is clocked out on the first falling edge of SCLK. DB10 to DB0 are shifted out on the subsequent falling edges of SCLK. The 13th SCLK falling edge returns SDO to a high impedance state. Data is propagated on SCLK falling edges and is valid on both the rising and falling edges of the next SCLK. The timing diagram for this operation is shown in Figure 26. BUSY INDICATOR ENABLED When the busy indicator is enabled, the SDO pin can be used as an interrupt signal to indicate that a conversion is complete. The connection diagram for this configuration is shown in Figure 25. Note that a pull-up resistor to VDD is required on the SDO pin. CS1 CONVERT VDD 100kΩ CONVST AD7091 DIGITAL HOST If another conversion is required, pull CONVST low again and repeat the cycle. DATA IN SDO SCLK IRQ 10494-023 CS CLK Figure 25. Connection Diagram with Busy Indicator EOC t7 CONVST tQUIET t8 CS t9 THREE-STATE 3 2 4 10 5 11 12 t5 t2 DB11 t6 t4 DB10 DB9 DB8 DB7 DB2 13 DB1 DB0 THREE-STATE 10494-024 t1 SDO t3 1 SCLK NOTES 1. EOC IS THE END OF A CONVERSION. Figure 26. Serial Port Timing with Busy Indicator Rev. A | Page 15 of 20 AD7091 Data Sheet BUSY INDICATOR DISABLED The conversion result is shifted out of the device as a 12-bit word under the control of SCLK and CS. The MSB (Bit DB11) is clocked out on the falling edge of CS. DB10 to DB0 are shifted out on the subsequent falling edges of SCLK. The 12th SCLK falling edge returns SDO to a high impedance state. After all the data is clocked out, pull CS high again. Data is propagated on SCLK falling edges and is valid on both the rising and falling edges of the next SCLK. The timing diagram for this operation is shown in Figure 27. To operate the AD7091 without the busy indicator, a conversion must first be started. A high-to-low transition on CONVST initiates a conversion. This transition places the track-and-hold into hold mode and samples the analog input at this point. If the user does not want the AD7091 to enter power-down mode, CONVST should be taken high before the end of the conversion. A conversion requires 650 ns to complete. When the conversion process is finished, the track-and-hold returns to track mode. To prevent the busy indicator from becoming enabled, ensure that CS is pulled high before the end of the conversion (see Figure 27). If another conversion is required, pull CONVST low again and repeat the cycle. EOC t7 CONVST tQUIET t8 t12 CS t11 t3 SCLK 3 4 5 10 11 12 t5 t10 THREE-STATE t2 DB11 DB10 t6 t4 DB9 DB8 DB7 DB2 DB1 DB0 THREE-STATE 10494-025 SDO 2 1 NOTES 1. EOC IS THE END OF A CONVERSION. Figure 27. Serial Port Timing Without Busy Indicator Rev. A | Page 16 of 20 Data Sheet AD7091 SOFTWARE RESET INTERFACING WITH AN 8-/16-BIT SPI BUS The AD7091 requires the user to initiate a software reset upon power-up. Note that failure to apply the correct software reset command may result in a device malfunction. The timing diagram for the software reset operation is shown in Figure 28. It is also possible to interface the AD7091 with a conventional 8-/16-bit SPI bus. Performing conversions and reading results can be achieved by configuring the host SPI interface for 16 bits, which results in providing an additional four SCLK cycles to complete a conversion compared with the standard interface methods (see the Busy Indicator Enabled section and the Busy Indicator Disabled section). To issue a software reset, 3. 4. Start a conversion by pulling CONVST low. Read back the conversion result by pulling CS low after the conversion is complete. Between the second and eighth SCLK cycles, pull CS high to short cycle the read operation. At the end of the next conversion, the software reset is executed. After the 13th SCLK falling edge with the busy indicator enabled or after the 12th SCLK falling edge with the busy indicator disabled, SDO returns to a high impedance state. The additional four bits should be treated as don’t care bits by the host. All other timings are as shown in Figure 26 and Figure 27, with tQUIET starting after the 16th SCLK cycle. As soon as a software reset is issued, the user can start another conversion by pulling CONVST low. A software reset can be performed by configuring the SPI bus for eight bits and performing the operation described in the Software Reset section. EOC/ SOFTWARE RESET EOC t7 t7 CONVST t8 t8 t12 CS t10 SHORT CYCLE READ SDO t3 SCLK 1 2 6 7 t5 NOTES 1. EOC IS THE END OF A CONVERSION. Figure 28. Software Reset Timing Rev. A | Page 17 of 20 8 10494-028 1. 2. AD7091 Data Sheet OUTLINE DIMENSIONS 1.70 1.60 1.50 2.10 2.00 SQ 1.90 0.50 BSC 8 5 1.10 1.00 0.90 EXPOSED PAD 0.425 0.350 0.275 4 TOP VIEW 0.60 0.55 0.50 0.05 MAX 0.02 NOM SEATING PLANE 0.30 0.25 0.20 1 BOTTOM VIEW PIN 1 INDICATOR (R 0.15) FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. 0.20 REF 01-14-2013-C PIN 1 INDEX AREA 0.15 REF Figure 29. 8-Lead Lead Frame Chip Scale Package [LFCSP_UD] 2.00 mm × 2.00 mm Body, Ultra Thin, Dual Lead (CP-8-10) Dimensions shown in millimeters ORDERING GUIDE Model1 AD7091BCPZ-RL AD7091BCPZ-RL7 EVAL-AD7091SDZ EVAL-SDP-CB1Z 1 Temperature Range −40°C to +125°C −40°C to +125°C Package Description 8-Lead Lead Frame Chip Scale Package [LFCSP_UD] 8-Lead Lead Frame Chip Scale Package [LFCSP_UD] Evaluation Board Evaluation Controller Board Z = RoHS Compliant Part. Rev. A | Page 18 of 20 Package Option CP-8-10 CP-8-10 Branding 92 92 Data Sheet AD7091 NOTES Rev. A | Page 19 of 20 AD7091 Data Sheet NOTES ©2012–2013 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D10996-0-6/13(A) Rev. A | Page 20 of 20