MC10H173 Quad 2−Input Multiplexer/ Latch The MC10H173 is a quad 2−input multiplexer with latch. This device is a functional/pinout duplication of the standard MECL 10K part, with 100% improvement in propagation delay and no increase in power supply current. • Data Propagation Delay, 1.5 ns Typical • Power Dissipation, 275 mW Typical • Improved Noise Margin 150 mV (over operating voltage and temperature range) • Voltage Compensated • MECL 10K−Compatible http://onsemi.com MARKING DIAGRAMS 16 CDIP−16 L SUFFIX CASE 620 MC10H173L AWLYYWW 1 TRUTH TABLE 16 SELECT CLOCK Q0n + 1 H L X L L H D00 D01 Q0n PDIP−16 P SUFFIX CASE 648 1 1 PLCC−20 FN SUFFIX CASE 775 DIP PIN ASSIGNMENT Q0 1 16 VCC Q1 2 15 Q2 D11 3 14 Q3 D10 4 13 D20 D01 5 12 D21 D00 6 11 D30 CLOCK 7 10 D31 VEE 8 9 SELECT A WL YY WW June, 2006 − Rev. 7 10H173 AWLYYWW = Assembly Location = Wafer Lot = Year = Work Week ORDERING INFORMATION Device Pin assignment is for Dual−in−Line Package. For PLCC pin assignment, see the Pin Conversion Tables on page 18 of the ON Semiconductor MECL Data Book (DL122/D). © Semiconductor Components Industries, LLC, 2006 MC10H173P AWLYYWW 1 Package Shipping MC10H173L CDIP−16 25 Units/Rail MC10H173P PDIP−16 25 Units/Rail MC10H173FN PLCC−20 46 Units/Rail Publication Order Number: MC10H173/D MC10H173 MAXIMUM RATINGS Symbol Rating Unit VEE Power Supply (VCC = 0) Characteristic −8.0 to 0 Vdc 0 to VEE Vdc 50 100 mA 0 to +75 °C −55 to +150 −55 to +165 °C °C VI Input Voltage (VCC = 0) Iout Output Current− Continuous − Surge TA Operating Temperature Range Tstg Storage Temperature Range − Plastic − Ceramic ELECTRICAL CHARACTERISTICS (VEE = −5.2 V ±5%) (See Note 1.) 0° Symbol 25° 75° Min Max Min Max Min Max Unit Power Supply Current − 73 − 66 − 73 mA IinH Input Current High Pins 3−7 & 10−13 Pin 9 − − 510 475 − − 320 300 − − 320 300 IinL Input Current Low 0.5 − 0.5 − 0.3 − μA VOH High Output Voltage −1.02 −0.84 −0.98 −0.81 −0.92 −0.735 Vdc VOL Low Output Voltage −1.95 −1.63 −1.95 −1.63 −1.95 −1.60 Vdc VIH High Input Voltage −1.17 −0.84 −1.13 −0.81 −1.07 −0.735 Vdc VIL Low Input Voltage −1.95 −1.48 −1.95 −1.48 −1.95 −1.45 Vdc IE Characteristic μA AC PARAMETERS tpd Propagation Delay Data Clock Select 0.7 1.0 1.0 2.3 3.7 3.6 0.7 1.0 1.0 2.3 3.7 3.6 0.7 1.0 1.0 2.3 3.7 3.6 tset Set−up Time Data Select 0.7 1.0 − − 0.7 1.0 − − 0.7 1.0 − − thold Hold Time Data Select 0.7 1.0 − − 0.7 1.0 − − 0.7 1.0 − − tr Rise Time 0.7 2.4 0.7 2.4 0.7 2.4 ns ns ns ns tf Fall Time 0.7 2.4 0.7 2.4 0.7 2.4 ns 1. Each MECL 10H series circuit has been designed to meet the dc specifications shown in the test table, after thermal equilibrium has been established. The circuit is in a test socket or mounted on a printed circuit board and transverse air flow greater than 500 Iinear fpm is maintained. Outputs are terminated through a 50−ohm resistor to −2.0 volts. http://onsemi.com 2 MC10H173 APPLICATION INFORMATION The MC10173 is a quad two−channel multiplexer with latch. It incorporates common clock and common data select inputs. The select input determines which data input is enabled. A high (H) level enables data inputs D00, D10, D20, and D30 and a low (L) level enables data inputs D01, D11, D21, D31. Any change on the data input will be reflected at the outputs while the clock is low. The outputs are latched on the positive transition of the clock. While the clock is in the high state, a change in the information present at the data inputs will not affect the output information. LOGIC DIAGRAM SELECT 9 1 Q0 D00 6 D01 5 2 Q1 D10 4 D11 3 15 Q2 D20 13 D21 12 14 Q3 D30 11 D31 10 CLOCK 7 VCC = PIN 16 VEE = PIN 8 http://onsemi.com 3 MC10H173 PACKAGE DIMENSIONS PLCC−20 FN SUFFIX PLASTIC PLCC PACKAGE CASE 775−02 ISSUE C 0.007 (0.180) M T L−M B Y BRK −N− U N S 0.007 (0.180) M T L−M S S N S D −L− −M− Z W 20 D 1 G1 X V 0.010 (0.250) S T L−M S N S VIEW D−D A 0.007 (0.180) M T L−M S N S R 0.007 (0.180) M T L−M S N S Z 0.007 (0.180) M T L−M H S N S K1 K C E G J VIEW S G1 0.010 (0.250) S T L−M S N S F 0.004 (0.100) −T− SEATING 0.007 (0.180) M T L−M S VIEW S PLANE NOTES: 1. DATUMS −L−, −M−, AND −N− DETERMINED WHERE TOP OF LEAD SHOULDER EXITS PLASTIC BODY AT MOLD PARTING LINE. 2. DIMENSION G1, TRUE POSITION TO BE MEASURED AT DATUM −T−, SEATING PLANE. 3. DIMENSIONS R AND U DO NOT INCLUDE MOLD FLASH. ALLOWABLE MOLD FLASH IS 0.010 (0.250) PER SIDE. 4. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 5. CONTROLLING DIMENSION: INCH. 6. THE PACKAGE TOP MAY BE SMALLER THAN THE PACKAGE BOTTOM BY UP TO 0.012 (0.300). DIMENSIONS R AND U ARE DETERMINED AT THE OUTERMOST EXTREMES OF THE PLASTIC BODY EXCLUSIVE OF MOLD FLASH, TIE BAR BURRS, GATE BURRS AND INTERLEAD FLASH, BUT INCLUDING ANY MISMATCH BETWEEN THE TOP AND BOTTOM OF THE PLASTIC BODY. 7. DIMENSION H DOES NOT INCLUDE DAMBAR PROTRUSION OR INTRUSION. THE DAMBAR PROTRUSION(S) SHALL NOT CAUSE THE H DIMENSION TO BE GREATER THAN 0.037 (0.940). THE DAMBAR INTRUSION(S) SHALL NOT CAUSE THE H DIMENSION TO BE SMALLER THAN 0.025 (0.635). http://onsemi.com 4 DIM A B C E F G H J K R U V W X Y Z G1 K1 INCHES MIN MAX 0.385 0.395 0.385 0.395 0.165 0.180 0.090 0.110 0.013 0.019 0.050 BSC 0.026 0.032 0.020 −−− 0.025 −−− 0.350 0.356 0.350 0.356 0.042 0.048 0.042 0.048 0.042 0.056 −−− 0.020 2_ 10 _ 0.310 0.330 0.040 −−− MILLIMETERS MIN MAX 9.78 10.03 9.78 10.03 4.20 4.57 2.29 2.79 0.33 0.48 1.27 BSC 0.66 0.81 0.51 −−− 0.64 −−− 8.89 9.04 8.89 9.04 1.07 1.21 1.07 1.21 1.07 1.42 −−− 0.50 2_ 10 _ 7.88 8.38 1.02 −−− N S MC10H173 PACKAGE DIMENSIONS −A− 16 9 1 8 −B− CDIP−16 L SUFFIX CERAMIC DIP PACKAGE CASE 620−10 ISSUE T C −T− L DIM A B C D E F G H K L M N K N SEATING PLANE NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEAD WHEN FORMED PARALLEL. 4. DIMENSION F MAY NARROW TO 0.76 (0.030) WHERE THE LEAD ENTERS THE CERAMIC BODY. M E F J G D 16 PL 0.25 (0.010) 16 PL 0.25 (0.010) M T A M −A− 9 1 8 B F S S PDIP−16 P SUFFIX PLASTIC DIP PACKAGE CASE 648−08 ISSUE R 16 T B C S H SEATING PLANE K G D M J 16 PL 0.25 (0.010) M T A MILLIMETERS MIN MAX 19.05 19.93 6.10 7.49 −−− 5.08 0.39 0.50 1.27 BSC 1.40 1.65 2.54 BSC 0.21 0.38 3.18 4.31 7.62 BSC 0_ 15 _ 0.51 1.01 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEADS WHEN FORMED PARALLEL. 4. DIMENSION B DOES NOT INCLUDE MOLD FLASH. 5. ROUNDED CORNERS OPTIONAL. L −T− INCHES MIN MAX 0.750 0.785 0.240 0.295 −−− 0.200 0.015 0.020 0.050 BSC 0.055 0.065 0.100 BSC 0.008 0.015 0.125 0.170 0.300 BSC 0_ 15 _ 0.020 0.040 M DIM A B C D F G H J K L M S INCHES MIN MAX 0.740 0.770 0.250 0.270 0.145 0.175 0.015 0.021 0.040 0.70 0.100 BSC 0.050 BSC 0.008 0.015 0.110 0.130 0.295 0.305 0_ 10 _ 0.020 0.040 MILLIMETERS MIN MAX 18.80 19.55 6.35 6.85 3.69 4.44 0.39 0.53 1.02 1.77 2.54 BSC 1.27 BSC 0.21 0.38 2.80 3.30 7.50 7.74 0_ 10 _ 0.51 1.01 ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. 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