Cirrus CS496122-CQZ Digital audio networking processor Datasheet

CS1810xx, CS4961xx, & CM-2
Digital Audio Networking Processor
CobraNet
™
Silicon Series
CS18100x, CS18101x, CS18102x, and CM-2
CS49610x, CS49611x, and CS49612x
Hardware User’s Manual
Version 2.3
Preliminary Product Information
This document contains information for a new product.
Cirrus Logic reserves the right to modify this product without notice.
©Copyright 2005 Cirrus Logic, Inc.
http://www.cirrus.com
JUN ’05
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CobraNet Hardware User’s Manual
Table of Contents
Table of Contents
List of Figures......................................................................................................................................... 4
1.0 .Introduction ..................................................................................................................................... 5
2.0 Features ........................................................................................................................................... 6
2.1 CobraNet............................................................................................................................. 6
2.2 CobraNet Interface.............................................................................................................. 6
2.3 Host Interface...................................................................................................................... 7
2.4 Asynchronous Serial Interface ............................................................................................ 7
2.5 Synchronous Serial Audio Interface.................................................................................... 7
2.6 Audio Clock Interface .......................................................................................................... 7
2.7 Audio Routing and Processing............................................................................................ 7
3.0 Hardware.......................................................................................................................................... 8
4.0 Pinout and Signal Descriptions ........................................................................................................ 9
4.1 CS1810xx & CS4961xx Package Pinouts......................................................................... 10
4.1.1 CS1810xx/CS4961xx Pinout............................................................................. 10
4.1.2 CM-2 Connector Pinout..................................................................................... 11
4.2 Signal Descriptions ...........................................................................................................12
4.2.1 Host Port Signals ..............................................................................................12
4.2.2 Asynchronous Serial Port (UART Bridge) Signals ............................................ 12
4.2.3 Synchronous Serial (Audio) Signals.................................................................. 13
4.2.4 Audio Clock Signals .......................................................................................... 13
4.2.5 Miscellaneous Signals....................................................................................... 14
4.2.6 Power and Ground Signals ............................................................................... 14
4.2.7 System Signals ................................................................................................. 15
4.3 Characteristics and Specifications .................................................................................... 16
4.3.1 Absolute Maximum Ratings .............................................................................. 16
4.3.2 Recommended Operating Conditions ............................................................... 16
4.3.3 Digital DC Characteristics ................................................................................. 16
4.3.4 Power Supply Characteristics ........................................................................... 16
5.0 Synchronization.............................................................................................................................. 17
5.1 Synchronization Modes..................................................................................................... 17
5.1.1 Internal Mode .................................................................................................... 18
5.1.2 External Word Clock Mode ............................................................................... 18
5.1.3 External Master Clock Mode ............................................................................. 18
6.0 Digital Audio Interface .................................................................................................................... 19
6.1 Digital Audio Interface Timing ........................................................................................... 20
6.1.1 Normal Mode Data Timing ................................................................................ 21
6.1.2 I2S Mode Data Timing....................................................................................... 21
6.1.3 Standard Mode Data Timing ............................................................................. 22
7.0 Host Management Interface (HMI)................................................................................................. 23
7.1 Hardware........................................................................................................................... 23
7.4 Protocol and Messages..................................................................................................... 28
7.4.1 Messages.......................................................................................................... 28
7.4.1.1. Translate Address ................................................................................. 29
7.4.1.2. Interrupt Acknowledge........................................................................... 29
7.4.1.3. Goto Packet........................................................................................... 29
7.4.1.4. Goto Translation .................................................................................... 29
7.4.1.5. Packet Received ................................................................................... 30
7.4.1.6. Packet Transmit .................................................................................... 30
7.4.1.7. Goto Counters ....................................................................................... 30
7.4.2 Status ................................................................................................................ 31
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7.4.3 Data................................................................................................................... 32
7.4.3.1. Region length ........................................................................................ 32
7.4.3.2. Writable Region ..................................................................................... 32
7.4.3.3. Translation Complete ............................................................................ 32
7.4.3.4. Packet Transmission Complete............................................................. 32
7.4.3.5. Received Packet Available .................................................................... 32
7.4.3.6. Message Togglebit ................................................................................ 32
8.0 HMI Reference Code ..................................................................................................................... 33
8.1 HMI Definitions.................................................................................................................. 33
8.2 HMI Access Code ............................................................................................................. 34
8.3 CM-1, CM-2 Auto-detection ..............................................................................................36
9.0 Mechanical Drawings and Schematics .......................................................................................... 37
9.1 CM-2 Mechanical Drawings ..............................................................................................38
9.2 CM-2 Schematics.............................................................................................................. 44
9.3 CS1810xx/CS4961xx Package ......................................................................................... 51
9.4 Temperature Specifications ..............................................................................................52
10.0 Ordering Information .................................................................................................................... 53
10.1 Device Part Numbers ...................................................................................................... 53
10.2 Device Part Numbering Scheme..................................................................................... 53
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List of Figures
List of Figures
Figure 1. CobraNet Data Services ......................................................................................................... 5
Figure 2. CobraNet Interface Hardware Block Diagram......................................................................... 8
Figure 3. Audio Clock Sub-system....................................................................................................... 17
Figure 4. Channel Structure for Synchronous Serial Audio at 64FS (One Sample Period) CS18100x/CS49610x & CS18101x/CS49611x ............................................................ 19
Figure 5. Channel Structure for Synchronous Serial Audio at 128FS (One Sample Period) CS18102x/CS49612x ................................................................................................... 19
Figure 6. Timing Relationship between FS512_OUT, DAO1_SCLK and FS1..................................... 20
Figure 7. Serial Port Data Timing Overview......................................................................................... 20
Figure 8. Audio Data Timing Detail - Normal Mode, 64FS CS18100x/CS49610x, CS18101x/CS49611x .............................................................. 21
Figure 9. Audio Data Timing Detail - Normal Mode, 128FS CS18102x/CS49612x ................................................................................................... 21
Figure 10. Audio Data Timing Detail - I2S Mode, 64FS CS18100x/CS49610x, CS18101x/CS49611x .............................................................. 21
Figure 11. Audio Data Timing Detail - I2S Mode, 128FS CS18102x & CS49612x................................................................................................ 21
Figure 12. Audio Data Timing Detail - Standard Mode, 64FS CS18100x/CS49610x, CS18101x/CS49611x .............................................................. 22
Figure 13. Audio Data Timing Detail - Standard Mode, 128FS CS18102x/CS49612x ................................................................................................... 22
Figure 14. Host Port Read Cycle Timing - Motorola Mode .................................................................. 25
Figure 15. Host Port Write Cycle Timing - Motorola Mode................................................................... 25
Figure 16. Parallal Control Port - Intel Mode Read Cycle .................................................................... 27
Figure 17. Parallel Control Port - Intel Mode Write Cycle .................................................................... 27
Figure 18. CM-2 Module Assembly Drawing, Top ............................................................................... 38
Figure 19. CM-2 Module Assembly Drawing, Bottom .......................................................................... 39
Figure 20. General PCB Dimensions ................................................................................................... 40
Figure 21. Example Configuration, Side View...................................................................................... 41
Figure 22. Faceplate Dimensions ........................................................................................................ 42
Figure 23. Connector Detail ................................................................................................................. 43
Figure 24. CM-2 RevF Schematic Page 1 of 7 .................................................................................... 44
Figure 25. CM-2 RevF Schematic Page 2 of 7 .................................................................................... 45
Figure 26. CM-2 RevF Schematic Page 3 of 7 .................................................................................... 46
Figure 27. CM-2 RevF Schematic Page 4 of 7 .................................................................................... 47
Figure 28. CM-2 RevF Schematic Page 5 of 7 .................................................................................... 48
Figure 29. CM-2 RevF Schematic Page 6 of 7 .................................................................................... 49
Figure 30. CM-2 RevF Schematic Page 7 of 7 .................................................................................... 50
Figure 31. 144-Pin LQFP Package Drawing ........................................................................................ 51
Figure 32. Device Part Numbering Explanation ................................................................................... 53
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Introduction
1.0 Introduction
This document is intended to help hardware designers integrate the CobraNetTM interface
into an audio system design. It covers the CS18100x, CS18101x, CS18102x, CS49610x,
CS49611x, and CS49612x members of the CobraNetTM Silicon Series of devices, where
“x” is the ROM version (ROM ID). This document also describes the CM-2 module with
schematics, mechanical drawings, etc.
CobraNet is a combination of hardware (the CobraNet interface), network protocol, and
firmware. CobraNet operates on a switched Ethernet network and provides the following
additional communications services.
• Isochronous (Audio) Data Transport
• Sample Clock Distribution
• Control and Monitoring Data Transport
The CobraNet interface performs synchronous-to-isochronous and isochronous-tosynchronous conversions as well as the data formatting required for transporting real-time
digital audio over the network.
The CobraNet interface has provisions for carrying and utilizing control and monitoring
data such as Simple Network Management Protocol (SNMP) through the same network
connection as the audio. Standard data transport capabilities of Ethernet are shown here
as unregulated traffic. Since CobraNet is Ethernet based, in most cases, data
communications and CobraNet applications can coexist on the same physical network.
Figure 1 illustrates the different data services available through the CobraNet system.
Isochronous
Isochronous Data
Data
(Audio)
(Audio)
Ethernet
Ethernet
Unregulated
Unregulated
Traffic
Traffic
Control
ControlData
Data
Clock
Figure 1. CobraNet Data Services
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Features
2.0 Features
2.1
CobraNet
• Real-time Digital Audio Distribution via Ethernet
• No Overall Limit on Network Channel Capacity
• Fully IEEE 802.3 Ethernet Standards Compliant
• Fiber optic and gigabit Ethernet variants are fully supported.
• Ethernet infrastructure can be used simultaneously for audio and data
communications.
• Free CobraCAD™ Audio Network Design Tool
• High-quality Audio Sample Clock Delivery Over Ethernet
• Bit-transparent 16-, 20-, and 24-bit Audio Transport
• Professional 48-kHz and 96-kHz sample rate
• Select Latency as Low as 1.33ms
• Flexible Many-to-many Network Audio Routing Capabilities
• Reduced-cost, Improved-performance, Convergent Audio Distribution
Infrastructure
2.2
CobraNet Interface
• 120 MIPS Customer-configurable Audio DSP
• Auto-negotiating 100Mbit Full-duplex Ethernet Connections
• Up to 32-channel Audio I/O Capability
• Implements CobraNet Protocol for real-time transport of audio over Ethernet.
• Local Management via 8-bit Parallel Host Port
• UDP/IP Network Stack with Dynamic IP Address Assignment via BOOTP or
RARP
• Remote Management via Simple Network Management Protocol (SNMP)
• Economical Three-chip Solution
• Available Module form factor allows for flexible integration into audio products.
• Non-volatile Storage of Configuration Parameters
• Safely Upgrade Firmware Over Ethernet Connection
• LED Indicators for Ethernet Link, Activity, Port Selection, and Conductor Status
• Watchdog Timer Output for System Integrity Assurance
• Comprehensive Power-on Self-test (POST)
• Error and Fault Reporting and Logging Mechanisms
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Features
2.3
Host Interface
• 8-bit Data, 4-bit Address
• Virtual 24-bit Addressing with 32-bit Data
• Polled, Interrupt, and DMA Modes of Operation
• Configure and Monitor CobraNet Interface
• Transmit or Receive Ethernet Packets at Near-100-Mbit Wire Speed
2.4
Asynchronous Serial Interface
• Full-duplex Capable
• 8-bit Data Format
• Supports all Standard Baud Rates
2.5
Synchronous Serial Audio Interface
• Up to Four Bi-directional Interfaces Supporting up to 32 Channels of Audio I/O
• 64FS (3.072 MHz) Bit Rate for CS18100x/CS49610x and CS18101x/
CS49611x
• 128FS (6.144 MHz) Bit Rate for CS18102x/CS49612x
• Accommodates Many Synchronous Serial Formats Including I2S
• 32-bit Data Resolution on All Audio I/O
2.6
Audio Clock Interface
• 5 Host Audio-clocking Modes for Maximum Flexibility in Digital Audio Interface
Design
• Low-jitter Master Audio Clock Oscillator (24.576 MHz)
• Synchronize to Supplied Master and/or Sample Clock
• Sophisticated jitter attenuation assures network perturbations do not affect
audio performance.
2.7
Audio Routing and Processing
• Single-channel Granularity in Routing From Synchronous Serial Audio
Interface to CobraNet Network
• Two levels of inward audio routing affords flexibility in audio I/O interface design
in the host system.
• Local Audio Loopback and Output Duplication Capability
• Peak-read Audio Metering with Ballistics
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Hardware
3.0 Hardware
Figure 2 shows a high-level view of the CobraNet CM-2 interface hardware architecture.
Clock
VCXO
Clock
CobraNet CM-2
Module
Flash
Memory
Control
Audio
Serial
Host
CS1810xx/
CS4961xx
Ethernet
Controller
Ethernet
Magnetics
Figure 2. CobraNet Interface Hardware Block Diagram
Flash memory holds the CobraNet firmware and management interface variable settings.
The CS1810xx or CS4961xx network processor is the heart of the CobraNet interface. It
implements the network protocol stacks and performs the synchronous-to-isochronous
and isochronous-to-synchronous conversions. The network processor has a role in
sample clock regeneration and performs all interactions with the host system.
The sample clock is generated by a voltage-controlled crystal oscillator (VCXO)
controlled by the network processor. The VCXO frequency is carefully adjusted to achieve
lock with the network clock.
The Ethernet controller is a standard interface chip that implements the 100-Mbit Fast
Ethernet standard. As per Ethernet requirements the interface is transformer isolated.
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Pinout and Signal Descriptions
4.0 Pinout and Signal Descriptions
This section details the chip pinout and signal interfaces for each module and is divided
as follows:
• "CS1810xx & CS4961xx Package Pinouts" on page 10
• "Host Port Signals" on page 12
• "Asynchronous Serial Port (UART Bridge) Signals" on page 12
• "Synchronous Serial (Audio) Signals" on page 13
• "Audio Clock Signals" on page 13
• "Miscellaneous Signals" on page 14
• "Power and Ground Signals" on page 14
• "System Signals" on page 15
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Pinout and Signal Descriptions
4.1
CS1810xx & CS4961xx Package Pinouts
4.1.1 CS1810xx/CS4961xx Pinout
Table 1 lists the pinout for the 144-pin LQFP CS1810xx/CS4961xx device. The interfaces
for these signals are expanded in the following sections.
Table 1. CS1810xx/CS4961xx Pin Assignments
Pin #
Pin Name
Pin #
Pin Name
Pin #
Pin Name
Pin #
Pin Name
1
VCXO_CTRL
37
DATA1
73
VDDIO
109
HADDR1
2
MCLK_SEL
38
WE
74
ADDR10
110
HADDR0
3
DBDA
39
DATA0
75
ADDR14
111
HDATA7
4
DBCK
40
DATA15
76
GND
112
HDATA6
5
NC
41
DATA14
77
ADDR13
113
VDDIO
6
NC
42
DATA13
78
NC
114
HDATA5
7
NC
43
DATA12
79
NC
115
HDATA4
8
DAO_MCLK
44
VDDIO
80
NC
116
GND
9
TEST
45
DATA11
81
NC
117
HDATA3
10
VDDD
46
DATA10
82
ADDR15
118
HDATA2
11
HS3
47
GND
83
VDDD
119
VDDD
12
NC
48
DATA9
84
ADDR16
120
HDATA1
13
GND
49
DATA8
85
ADDR17
121
HDATA0
14
DAO2_LRCLK
50
NC
86
GND
122
GND
15
DAO1_DATA3
51
NC
87
ADDR18
123
XTAL_OUT
16
DAO1_DATA2/HS2
52
NC
88
ADDR19
124
XTO
17
DAO1_DATA1/HS1
53
NC
89
OE
125
XTI
18
VDDIO
54
VDDD
90
CS1
126
GND_a
19
DAO1_DATA0/HS0
55
ADDR12
91
VDDIO
127
FILT2
20
DAO1_SCLK
56
ADDR11
92
MUTE
128
FILT1
21
GND
57
GND
93
HRESET
129
VDDA
22
DAO1_LRCLK
58
ADDR9
94
GND
130
VDDD
23
UART_TX_OE
59
ADDR8
95
WATCHDOG
131
DAI1_DATA3
24
VDDD
60
VDDIO
96
IOWAIT
132
DAI1_DATA2
25
UART_TXD
61
ADDR7
97
REFCLK_IN
133
GND
26
UART_RXD
62
ADDR6
98
VDDD
134
DAI1_DATA1
27
GND
63
GND
99
GPIO0
135
DAI1_DATA0
28
NC
64
ADDR5
100
GPIO1
136
VDDIO
29
DATA7
65
CS2
101
GND
137
DAI1_SCLK
30
DATA6
66
VDDD
102
HACK
138
DAI1_LRCLK
31
DATA5
67
ADDR4
103
HDS
139
GND
32
DATA4
68
ADDR3
104
HEN
140
HREQ
33
VDDIO
69
GND
105
HADDR3
141
NC
34
DATA3
70
ADDR2
106
HADDR2
142
NC
35
DATA2
71
ADDR1
107
HR/W
143
IRQ1
36
GND
72
ADDR0
108
GPIO2
144
IRQ2
10
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Pinout and Signal Descriptions
4.1.2 CM-2 Connector Pinout
Table 1 lists the pinout for the four pinout connectors on the CM-2 board (J1-J4). The
interfaces for these signals are expanded following the table.
Table 2. CM-2 Pin Assignments
Conn.
Pin #
Pin Name
Conn.
Pin #
B8
Pin Name
GND
Conn.
J3/J4
Pin #
A15
Pin Name
J1/J2
A1
UART_RXD
J1/J2
DAI1_DATA3
J1/J2
A2
UART_TX_OE
J1/J2
B9
VCC_+3.3V
J3/J4
A16
RSVD3
J1/J2
A3
HACK
J1/J2
B10
GND
J3/J4
A17
WATCHDOG
J1/J2
A4
HR/W
J1/J2
B11
VCC_+3.3V
J3/J4
A18
RSVD4
J1/J2
A5
HDS
J1/J2
B12
GND
J3/J4
A19
AUX_POWER2
J1/J2
A6
HREQ
J1/J2
B13
VCC_+3.3V
J3/J4
A20
AUX_POWER0
J1/J2
A7
HEN
J1/J2
B14
GND
J3/J4
B1
GND
J1/J2
A8
HADDR0
J1/J2
B15
VCC_+3.3V
J3/J4
B2
VCC_+3.3V
J1/J2
A9
HADDR1
J1/J2
B16
GND
J3/J4
B3
GND
J1/J2
A10
HADDR2
J1/J2
B17
VCC_+3.3V
J3/J4
B4
VCC_+3.3V
J1/J2
A11
HDATA0
J1/J2
B18
RSVD1
J3/J4
B5
GND
J1/J2
A12
HDATA1
J1/J2
B19
GND
J3/J4
B6
VCC_+3.3V
J1/J2
A13
HDATA2
J1/J2
B20
VCC_+3.3V
J3/J4
B7
GND
J1/J2
A14
HDATA3
J3/J4
A1
RSVD2
J3/J4
B8
VCC_+3.3V
J1/J2
A15
HDATA4
J3/J4
A2
MUTE
J3/J4
B9
GND
J1/J2
A16
HDATA5
J3/J4
A3
FS1
J3/J4
B10
VCC_+3.3V
J1/J2
A17
HDATA6
J3/J4
A4
MCLK_OUT
J3/J4
B11
GND
J1/J2
A18
HRESET
J3/J4
A5
MCLK_IN
J3/J4
B12
VCC_+3.3V
J1/J2
A19
HDATA7
J3/J4
A6
REFCLK_IN
J3/J4
B13
GND
J1/J2
A20
HADDR3
J3/J4
A7
DAO1_SCLK/DAI1_SCLK
J3/J4
B14
VCC_+3.3V
J1/J2
B1
UART_TXD
J3/J4
A8
DAO1_DATA0
J3/J4
B15
GND
J1/J2
B2
GND
J3/J4
A9
DAO1_DATA1
J3/J4
B16
GND
J1/J2
B3
VCC_+3.3V
J3/J4
A10
DAO1_DATA2
J3/J4
B17
VCC_+5V
J1/J2
B4
GND
J3/J4
A11
DAO1_DATA3
J3/J4
B18
VCC_+5V
J1/J2
B5
VCC_+3.3V
J3/J4
A12
DAI1_DATA0
J3/J4
B19
AUX_POWER3
J1/J2
B6
GND
J3/J4
A13
DAI1_DATA1
J3/J4
B20
AUX_POWER1
J1/J2
B7
VCC_+3.3V
J3/J4
A14
DAI1_DATA2
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Pinout and Signal Descriptions
4.2
Signal Descriptions
4.2.1 Host Port Signals
The host port is used to manage and monitor the CobraNet interface. Electrical operation
and protocol is detailed in the "Host Management Interface (HMI)" on page 23 of this
Manual.
The host port can operate in two modes in order to accomodate Motorola® or Intel® style
interfaces. The default mode is Motorola. Intel mode is set via a firmware modification.
Table 2-1: Host Port Signals
Signal
Description
Direction
CM-2
Pin #
CS1810xx/
CS4961xx Pin #
HDATA[7:0]
Host Data
In/Out
J1:A19,
A[17:11]
111, 112, 114,
115, 117, 118,
102, 121
HADDR[3:0]
Host Address
In
J1:A20,
A[10:8]
105, 106, 109,110
HRW
Host
Direction
In
J1:A4
107
Host port transfer direction (Motorola mode).
HRD
Host Read
In
J1:A4
107
Host Read (Intel mode).
HREQ
Host Request
Out
J1:A6
140
Host port data request.
HACK
Host Alert
Out
J1:A3
102
Host port interrupt request.
HDS
Host Strobe
In
J1:A5
103
Host port strobe (Motorola mode).
HWR
Host Write
In
J1:A5
103
Host Write (Intel mode).
HEN
Host Enable
In
J1:A7
104
Host Port Enable.
HCS
Select
In
J1:A7
104
Select (Intel mode).
Notes
Host port data.
Host port address.
4.2.2 Asynchronous Serial Port (UART Bridge) Signals
Level-shifting drive circuits are typically required between these signals and any external
connections.
Signal
Description
Direction
CM-2
Pin #
CS1810xx/
CS4961xx Pin #
UART_RXD
Asynchronous Serial
Receive Data
In
J1:A1
26
UART_TXD
Asynchronous Serial
Transmit Data
Out
J1:B1
25
UART_TX_OE
Transmit Drive Enable
Out
J1:A2
23
12
©Copyright 2005 Cirrus Logic, Inc.
Notes
Pull-up to VCC if unused.
Enable transmit (active high) drive for
two wire multi-drop interface.
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Pinout and Signal Descriptions
4.2.3 Synchronous Serial (Audio) Signals
The synchronous serial interfaces are used to bring digital audio into and out of the
system. Typically the synchronous serial is wired to ADCs and/or DACs. Detailed timing
and format is described in "Digital Audio Interface" on page 19.
Signal
Description
CM-2
Pin #
Direction
CS1810xx/
CS4961xx Pin #
Notes
Synchronous serial bit clock.
64 FS for CS18100x & CS49610x (2x1 channel)
64 FS for CS18101x & CS49611x (2x4
channels)
128 FS for CS18102x & CS49612x (4x4
channels)
Typically tied to DAI1_SCLK.
DAO1_SCLK
Audio Bit Clock
Out
J3:A7
20
DAO1_DATA[3:0]
Audio Output
Data
Out
J3:A18,
B18
15-17, 19
DAI1_DATA[3:0]
Audio Input Data
In
DAI1_SCLK
Audio Bit Clock
In
Output synchronous serial audio data
DAO1_DATA[3:1] not used for CS18100x &
CS49610x.
Input synchronous serial audio data
J3:
131, 132, 134, 135 DAI1_DATA[3:1] not used for CS18100x &
A[15:12]
CS49610x.
J4:A7
137
Should be tied to DAO1_SCLK.
Synchronous serial bit clock.
4.2.4 Audio Clock Signals
See "Synchronization" on page 17 for an overview of synchronization modes and issues.
Signal
Description
Direction
DAI1_LRCLK
Sample clock
input
In
DAO1_LRCLK
(FS1)
Sample clock
output
Out
DAO2_LRCLK
(FS1)
Sample clock
output
Out
In
CM-2
Pin #
CS1810xx/
CS4961xx Pin #
Notes
138
Should be tied to DAO1_LRCLK for all devices.
J3:A3
22
FS1 (word clock) for CS18100x/CS49610x and
CS18101x/CS49611x.
J3:A3
14
FS1 (word clock) for CS18102x & CS49612x.
97
Clock input for synchronizing network to an
external clock source, for redundancy control
and synchronization of FS divider chain to
external source. See "Synchronization" on
page 17 for more detail.
REFCLK_IN
Reference clock
J3:A6
MCLK_IN
Master audio
clock input
In
J3:A5
8*
For systems featuring multiple CobraNet
interfaces operating off a common master
clock. See "Synchronization" on page 17 for
more detail.
MCLK_OUT
Master audio
clock output
Out
J3:A4
8*
Low jitter 24.576 MHz master audio clock.
*An external multiplexor controlled by this pin is required for full MCLK_IN and MCLK out
implementation.
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Pinout and Signal Descriptions
4.2.5 Miscellaneous Signals
Signal
Description
Direction
CM-2
Pin #
CS1810xx/
CS4961xx Pin #
HRESET
Reset
In
J1:A18
93
System reset (active low).
10 ns max rise time. 1 ms min assertion time.
Notes
WATCHDOG
Watch Dog
Out
J3:A17
95
Toggles at 750 Hz nominal rate to indicate proper
operation. Period duration in excess of 200 ms
indicates hardware or software failure has occurred
and the interface should be reset. Note that
improper operation can also be indicated by short
pulses (<100 ns).
MUTE
Interface
Ready
Out
J3:A2
92
Asserts (active low) during initialization and when a
fault is detected or connection to the network is lost.
NC
No Connect
-
-
28, 50-53, 7881, 141, 142
4.2.6 Power and Ground Signals
Signal
VCC_+3V
Description
System Digital +3.3 v
CM-2 Pin #
J1:B20, B17, B15,
B13, B11, B9, B7,
B5, B3
CS1810xx/CS4961xx
Pin #
Specification
N/A
3.3 ± 0.3v, 500 mA Typ., 750 mA Max.
J3:B14, B12, B10,
B8, B6, B4, B2
VCC_+5V
J3;B[18:17]
N/A
Backwards Compatibility
VDDD
N/A
10, 24, 54, 66, 83,
98, 119, 130
+1.8 V @ 500mA Typ. for Core Logic
VDDIO
N/A
18, 33, 44, 60, 73,
91, 113, 136
+3.3 V @ 120mA Typ. for I/O Logic
VDDA
N/A
129
Filtered +1.8 V @ 10mA Typ.
AUX_POWER
[3-0]
J3:B[20:19],
A[20:19]
N/A
J1:B19, B16, B14,
B12, B10, B8, B6,
B4, B2
GND
Digital Ground
J3:B16, B15, B13,
B11, B9, B7, B5,
B3, B1
14
13, 21, 27, 36, 47,
57, 63, 69, 76, 86,
94, 101, 116, 122,
126, 133, 139
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Pinout and Signal Descriptions
4.2.7 System Signals
Use these CS1810xx/CS4961xx signals stricktly in the manner described in CM-2
Schematics (Section 9.2 on page 44). Each signal is briefly described below.
Signal
VCXO_CTRL
MCLK_SEL
DBDA, DBCK
TEST
Description
CS1810xx/CS4961xx
Pin #
A Delta-sigma DAC Output for Controlling the On-board VCXO
1
Control Signal for Selecting MCLK Sources
2
I2C Debugger Interface
Used for testing during manufacturing. Keep grounded for normal
operation.
3, 4
9
DATA[15:0]
Data Bus for Flash & Ethernet Controller(s)
29-32, 34, 35, 37, 39-43,
45, 46, 48, 49
ADDR[19:0]
Address Bus for Flash & Ethernet Controller(s)
55, 56, 58, 59, 61, 62, 64,
67, 68, 70-72, 74, 75, 77,
82, 84, 85, 87, 88
WE
Write Enable for Flash and Ethernet Controller(s)
38
CS1
Chip Select for Flash Memory Device
90
CS2
Chip Select for Ethernet Controller(s)
65
OE
Output Enable
89
Wait State Signal from Ethernet Controller(s)
96
IOWAIT
GPIO[2:0]
General-purpose I/O Signals
99, 100, 108
XTI
Reference Clock Input / Crystal Oscillator Input
125
XTO
Crystal Oscillator Output
124
XTAL_OUT
A Buffered Version of XTI
123
FILT2, FILT1
PLL Loop Filter
DAO_MCLK
MCLK Input
HS[3:0]
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8
CS1810xx/CS4961xx Boot Mode Selection
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Pinout and Signal Descriptions
4.3
Characteristics and Specifications
4.3.1 Absolute Maximum Ratings
Parameter
DC power supplies:
Core supply
PLL supply
I/O supply
|VDDA – VDD|
Input current, any pin except supplies
Input voltage on FILT1, FILT2
Input voltage on I/O pins
Storage temperature
Symbol
VDD
VDDA
VDDIO
Min
–0.3
–0.3
–0.3
-
Iin
Vfilt
Vinio
Tstg
Max
2.0
2.0
5.0
0.3
+/- 10
2.0
5.0
150
–65
Unit
V
V
V
V
mA
V
V
°C
Caution: Operation at or beyond these limits may result in permanent damage to the device. Normal operation is
not guaranteed at these extremes.
4.3.2 Recommended Operating Conditions
Parameter
DC power supplies:
Core supply
PLL supply
I/O supply
|VDDA – VDD|
Ambient operating temperature
Symbol
VDD
VDDA
VDDIO
Min
1.71
1.71
3.13
Typ
1.8
1.8
3.3
TA
Max
1.89
1.89
3.46
0.3
-
- CQ
- DQ
0
- 40
Unit
V
V
V
V
°C
+ 70
+ 85
4.3.3 Digital DC Characteristics
(measurements performed under static conditions.)
Parameter
High-level input voltage
Low-level input voltage, except XTI
Low-level input voltage, XTI
Input Hysteresis
High-level output voltage at
IO = –8.0 mAO = –16.0 mA
Low-level output voltage at
IO = 8.0 mAO = –16.0 mA
Input leakage current (all pins without internal pullup resistors except XTI)
Input leakage current (pins with internal pull-up
resistors, XTI)
Symbol
VIH
VIL
VILXTI
Vhys
VOH
Min
2.0
-
Max
0.8
0.6
VDDIO * 0.9
Typ
0.3
-
-
Unit
V
V
V
V
V
VOL
-
-
VDDIO * 0.1
V
IIN
-
-
5
µA
IIN-PU
-
-
50
µA
4.3.4 Power Supply Characteristics
(measurements performed under operating conditions))
Parameter
Power supply current:
Core and I/O operating: VDD
PLL operating: VDDA
With external memory and most ports operating: VDDIO
(Note 1)
Min
Typ
Max
Unit
-
500
10
120
-
mA
mA
mA
NOTES:1. Dependent on application firmware and DSP clock speed.
16
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Synchronization
5.0 Synchronization
Figure 3 shows clock related circuits for the CS1810xx/CS4961xx and board design
(CM-2). This circuitry allows the synchronization modes documented below to be
achieved. Modes are distinguished by different settings of the multiplexors and software
elements.
MCLK_OUT
VCXO
24.576 MHz
DAC
CS1810xx/CS4961xx
AClkConfig
MCLK_IN
SLCK
Sample
Phase
Counter
MCLK_SEL
Phase
Detector
RefClkEnable
RefClkPolarity
FS1
Audio
Clock
Generator
Loop
Filter
Edge
Detect
REFCLK_IN
BeatReceived
Legend:
External
Hardware
Component
(CM2)
Internal
Hardware
Component
(CS1810xx, CS4961xx)
Software
Component
Figure 3. Audio Clock Sub-system
5.1
Synchronization Modes
Clock synchronization mode for conductor and performer roles is independently
selectable via management interface variables syncConductorClock and
syncPerformerClock. The role (conductor or performer) is determined by the network
environment including the conductor priority setting of the device and the other devices on
the network. It is possible to ensure you will never assume the conductor role by selecting
a conductor priority of zero. However, it is not reasonable to assume that by setting a high
conductor priority, you will always assume the conductor role. For more information, refer
to CobraNet Programmer’s Reference Manual.
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Synchronization
The following synchronization modes are further described below:
• "Internal Mode" on page 18
• "External Word Clock Mode" on page 18
• "External Master Clock Mode" on page 18
5.1.1 Internal Mode
All CobraNet clocks are derived from the onboard VCXO. The master clock generated by
the VCXO is available to external circuits via the master clock output.
Conductor—The VCXO is “parked” according to the syncClockTrim setting.
Performer—The VCXO is “steered” to match the clock transmitted by the Conductor.
5.1.2 External Word Clock Mode
All CobraNet clocks are derived from the onboard VCXO. The VCXO is steered from an
external clock supplied to the reference clock input. The clock supplied can be any
integral division of the sample clock in the range of 750Hz to 48kHz.
External synchronization lock range: ±5 µs. This specification indicates drift or wander
between the supplied clock and the generated network clock at the conductor. Absolute
phase difference between the supplied reference clock and generated sample clock is
dependant on network topology.
Conductor—This mode gives a means for synchronizing an entire CobraNet network to
an external clock.
Performer—The interface disregards the fine timing information delivered over the
network from the conductor. Coarse timing information from the conductor is still used;
fine timing information is instead supplied by the reference clock. The external clock
source must be synchronous with the network conductor. This mode is useful in
installations where a house sync source is readily available.
5.1.3 External Master Clock Mode
The VCXO is disabled and MCLK_IN is used as the master clock for the node. This is a
“hard” synchronization mode. The supplied clock is used directly by the CobraNet
interface for all timing. This mode is primarily useful for devices with multiple CobraNet
interfaces sharing a common master audio clock. The supplied clock must be
24.576 MHz. The supplied clock must have a ±37 ppm precision.
Conductor—The entire network is synchronized to the supplied master clock.
Performer—The node will initially lock to the network clock and will “jam sync” via the
supplied master clock. The external clock source must be synchronous with the network
conductor.
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Digital Audio Interface
6.0 Digital Audio Interface
The CS18101x/CS49611x, CS18102x/CS49612x, and CM-2 support four bi-directional
synchronous serial interfaces. The CS18100x & CS49610x support one bi-directional
synchronous serial interface. All interfaces operate in master mode with DAO1_SCLK as
the bit clock and FS1 as the frame clock. A sample period worth of synchronous serial
data includes two (or four) audio channels. CobraNet supports two synchronous serial bit
rates: 48 Khz and 96 KHz. However, 96 kHz sample rate is not available when using
CS18102x/CS49612x with 16X16 channels. Bit rate is selected by the modeRateControl
variable. All synchronous serial interfaces operate from a common clock at the same bit
rate.
FS1
D A O 1 _ D A T A 0 / D A I1 _ D A T A 0
1
2
*D A O 1 _ D A T A 1 / D A I1 _ D A T A 1
3
4
*D A O 1 _ D A T A 2 / D A I1 _ D A T A 2
5
6
*D A O 1 _ D A T A 3 / D A I1 _ D A T A 3
7
8
* N o t p re s e n t in C S 1 8 1 0 0 x o r C S 4 9 6 1 0 x .
Figure 4. Channel Structure for Synchronous Serial Audio at 64FS (One Sample Period) - CS18100x/CS49610x &
CS18101x/CS49611x
FS1
DAO1_DATA0 / DAI1_DATA0
1
2
3
4
DAO1_DATA1 / DAI1_DATA1
5
6
7
8
DAO1_DATA2 / DAI1_DATA2
9
10
11
12
DAO1_DATA3 / DAI1_DATA3
13
14
15
16
Figure 5. Channel Structure for Synchronous Serial Audio at 128FS (One Sample Period) - CS18102x/CS49612x
Default channel ordering is shown above. Note that the first channel always begins after
the rising or falling edge of FS1 (depending on the mode).
DAI1_SCLK period depends on the sample rate selected. Up to 32 significant bits are
received and buffered by the DSP for synchronous inputs. Up to 32 significant bits are
transmitted by the DSP for synchronous outputs. Bit 31 is always the most significant
(sign) bit. A 16-bit audio source must drive to bit periods 31-16 with audio data and bits
15-0 should be actively driven with either a dither signal or zeros. Cirrus Logic
recommends driving unused LS bits to zero.
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Digital Audio Interface
Although data is always transmitted and received with a 32-bit resolution by the
synchronous serial ports, the resolution of the data transferred to/from the Ethernet may
be less. Incoming audio data is truncated to the selected resolution. Unused least
significant bits on outgoing data is zero filled.
6.1
Digital Audio Interface Timing
0 – 5ns
MCLK_OUT
DAO1_SCLK
FS1
0 – 10ns
Figure 6. Timing Relationship between FS512_OUT, DAO1_SCLK and FS1
An DAO1_SCLK edge follows an MCLK_OUT edge by 0.0 to 5.0ns. An FS1 edge follows
a MCLK_OUT edge by 0.0 to 10.0ns.
Note: The DAO1_SCLK and FS1 might be synchronized with the either the falling edge or
the rising edge of MCLK_OUT. Which edge is impossible to predict since it depends
on power up timing.
≥5ns
≥0ns
DAO1_SCLK
DAI1_DATAx
DAO1_DATAx
0 – 12ns
Figure 7. Serial Port Data Timing Overview
Setup times for DAI1_DATAx and FS1 are 5.0 ns with a hold time of 0.0 ns with respect to
the DAI1_SCLK edge. Clock to output times for DAO1_DATAx is 0.0 to 12.0 ns from the
edge of DAO1_SCLK.
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Digital Audio Interface
6.1.1 Normal Mode Data Timing
DAI1_SCLK
FS1
DAI1_DATAx
DAO1_DATAx
23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5
23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
4 3 2
1
0
Unused
23
8 7 6 5 4 3 2
1
0
Unused
23
Figure 8. Audio Data Timing Detail - Normal Mode, 64FS - CS18100x/CS49610x, CS18101x/CS49611x
DAI1_SCLK
FS1
DAI1_DATAx
23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Unused
23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Unused
23
DAO1_DATAx
23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Unused
23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Unused
23
Figure 9. Audio Data Timing Detail - Normal Mode, 128FS - CS18102x/CS49612x
Each audio channel is comprised of 32 bits of data, regardless of audio sample size. The
figure above shows 24-bit audio data.
The MSB is left justified and is aligned with FS1. Data is sampled on the rising edge of
DAI_SCLK and data changes on the falling edge.
6.1.2 I2S Mode Data Timing
DAI1_SCLK
FS1
DAI1_DATAx
DAO1_DATAx
23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5
23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
4 3 2
1
0
Unused
23
8 7 6 5 4 3 2
1
0
Unused
23
Figure 10. Audio Data Timing Detail - I2S Mode, 64FS - CS18100x/CS49610x, CS18101x/CS49611x
DAI1_SCLK
FS1
DAI1_DATAx
23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Unused
23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Unused
23
DAO1_DATAx
23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Unused
23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Unused
23
Figure 11. Audio Data Timing Detail - I2S Mode, 128FS - CS18102x & CS49612x
Each audio channel is comprised of 32 bits of data, regardless of audio sample size. The
figure above shows 24-bit audio data.
The MSB is left justified and arrives one bit period following FS1. Data is sampled on the
rising edge of DAI_SCLK and data changes on the falling edge.
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Digital Audio Interface
6.1.3 Standard Mode Data Timing
DAI1_SCLK
FS1
DAI1_DATAx
DAO1_DATAx
23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8
23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
7 6 5
8 7 6
4 3 2
5 4
3 2
1
0
Unused
23
1
0
Unused
23
Figure 12. Audio Data Timing Detail - Standard Mode, 64FS - CS18100x/CS49610x, CS18101x/CS49611x
DAI1_SCLK
FS1
DAI1_DATAx
23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Unused
23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Unused
23
DAO1_DATAx
23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Unused
23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Unused
23
Figure 13. Audio Data Timing Detail - Standard Mode, 128FS - CS18102x/CS49612x
Each audio channel is comprised of 32 bits of data, regardless of audio sample size. The
figure above shows 24-bit audio data.
The MSB is left justified and is aligned with FS1. Data is sampled on the rising edge of
DAI_SCLK and data changes on the falling edge.
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Host Management Interface (HMI)
7.0 Host Management Interface (HMI)
7.1
Hardware
The host port is 8 bits wide with 4 bits of addressing. Ten of the 16 addressable registers
are implemented. The upper two registers can be used to configure and retrieve the
status on the host port hardware. However, only the first 8 are essential for normal HMI
communications. It is therefore feasible, in most applications, to utilize only the first 3
address bits and tie the most significant bit (A3) low.
Host port hardware supports Intel® (little-endian), Motorola®, and Motorola multiplexed
bus (big-endian) protocols. Standard CobraNet firmware configures the port in the
Motorola, big-endian mode.
The host port memory map is shown in Table 3. Refer also to "HMI Definitions" on
page 33 and "HMI Access Code" on page 34.
Host Address
Register
0
Message A (MS)
1
Message B
2
Message C
3
Message D (LS)
4
Data A (MS)
5
Data B
6
Data C
7
Data D (LS)
8
Control
9
Status
Table 3. Host port memory map
The message and data registers provide separate bi-directional data conduits between
the host processor and the CS1810xx/CS4961xx. A 32-bit word of data is transferred to
the CS1810xx/CS4961xx when the host writes the D message or data register after
presumably previously writing the A, B, and C registers with valid data. Data is transferred
from the CS1810xx/CS4961xx following a read of the D message or data register. Again,
presumably the A, B, and C registers are read previously.
Two additional hardware signals are associated with the host port: HACK and HREQ.
Both are outputs to the host.
HACK may be wired to an interrupt request input on the host. HACK can be made to
assert (logic 0) on specific events as specified by the hackEnable MI variable. HACK is
deasserted (logic 1) by issuance of the Acknowledge Interrupt message (see “Messages”
below).
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Host Management Interface (HMI)
HREQ may be wired to a host interrupt or DMA request input. HREQ is used to signal the
host that data is available (read case, logic 0) or space is available in the host port data
channel (write case, logic 1).
The read and write case are distinguished by the HMI based on the preceding message.
Identify, Goto Translation (read), Goto Packet (read) and Goto Counters cause HREQ to
represent read status. Goto Translation (write) and Goto Packet (write) switch HREQ to
write mode. All other commands have no effect on HREQ operation.
In general, the host can read from the CS1810xx/CS4961xx when HREQ is low and can
write data to CS1810xx/CS4961xx when HREQ is high.
7.2 Host Port Timing - Motorola® Mode
(CL = 20 pF)
Parameter
Symbol
Min
Max
Unit
Address setup before HEN and HDS low
tmas
5
-
ns
Address hold time after HEN and HDS low
tmah
5
-
ns
Delay between HDS then HEN low or HEN then HDS low
tmcdr
0
-
ns
Data valid after HEN and HDS low with HRW high
tmdd
-
19
ns
HEN and HDS low for read
tmrpw
24
-
ns
Data hold time after HEN or HDS high after read
tmdhr
8
-
ns
Data high-Z after HEN or HDS high after read
tmdis
-
18
ns
HEN or HDS high to HEN and HDS low for next read
tmrd
30
-
ns
HEN or HDS high to HEN and HDS low for next write
tmrdtw
30
-
ns
tmrwirqh
-
12
ns
Delay between HDS then HEN low or HEN then HDS low
tmcdw
0
-
ns
Data setup before HEN or HDS high
tmdsu
8
-
ns
HEN and HDS low for write
tmwpw
24
-
ns
HRW setup before HEN and HDS low
tmrwsu
24
-
ns
HRW hold time after HEN or HDS high
tmrwhld
8
-
ns
Data hold after HEN or HDS high
tmdhw
8
-
ns
HEN or HDS high to HEN and HDS low with HRW high for
next read
tmwtrd
30
-
ns
HEN or HDS high to HEN and HDS low for next write
tmwd
30
-
ns
tmrwbsyl
-
12
ns
Read
HR/W rising to HREQ falling
Write
HRW rising to HREQ falling
NOTES:1. The system designer should be aware that the actual maximum speed of the communication port may
be limited by the firmware application. Hardware handshaking on the HREQ pin/bit should be observed
to prevent overflowing the input data buffer.
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Host Management Interface (HMI)
HADDR[3:0]
t m as
t m ah
HDATA[7:0]
HEN
M SP
LSP
t m dd
t m rw su
HRW
t m dhr
t m cdr
t m dis
t m rpw
t m rw hld
t m rdtw
t m rd
HDS
t m rwirqh
HREQ
Figure 14. Host Port Read Cycle Timing - Motorola Mode
H A D D R [3 :0 ]
t m as
H D A T A [7 :0 ]
t m ah
LSP
t m d su
MSP
t m dhw
HEN
t m cdw
t m r w h ld
t m wpw
HRW
t m rw su
t mwd
t m w trd
HDS
t m rw irq l
HREQ
Figure 15. Host Port Write Cycle Timing - Motorola Mode
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Host Management Interface (HMI)
7.3 Host Port Timing - Intel® Mode
(CL = 20 pF)
Parameter
Symbol
Min
Max
Unit
Address setup before HCS and HRD low or HCS and HWR
low
tias
5
-
ns
Address hold time after HCS and HRD low or HCS and HWR
high
tiah
5
-
ns
Delay between HRD then HCS low or HCS then HRD low
ticdr
0
-
ns
Data valid after HCS and HRD low
tidd
-
18
ns
HCS and HRD low for read
tirpw
24
-
ns
Data hold time after HCS or HRD high
tidhr
8
-
ns
Data high-Z after HCS or HRD high
tidis
-
18
ns
HCS or HRD high to HCS and HRD low for next read
tird
30
-
ns
HCS or HRD high to HCS and HWR low for next write
tirdtw
30
-
ns
tirdirqhl
-
12
ns
Delay between HWR then HCS low or HCS then HWR low
ticdw
0
-
ns
Data setup before HCS or HWR high
tidsu
8
-
ns
HCS and HWR low for write
tiwpw
24
-
ns
Data hold after HCS or HWR high
tidhw
8
-
ns
HCS or HWR high to HCS and HRD low for next read
tiwtrd
30
-
ns
HCS or HWR high to HCS and HWR low for next write
tiwd
30
-
ns
tiwrbsyl
-
12
ns
Read
HRD rising to HREQ rising
Write
HWR rising to HREQ falling
NOTES:1. The system designer should be aware that the actual maximum speed of the communication port may
be limited by the firmware application. Hardware handshaking on the HREQ pin/bit should be observed
to prevent overflowing the input data buffer.
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Host Management Interface (HMI)
H A D D R [3 :0 ]
t iah
H D A T A [7 :0 ]
LSP
t ias
t id d
HCS
MSP
t id hr
t icdr
t idis
HW R
t irp w
t ird
t irdtw
HRD
t ird irqh
HREQ
Figure 16. Parallal Control Port - Intel Mode Read Cycle
H A D D R [3:0]
t iah
H DATA[7:0]
LSP
t ias
MSP
t idhw
HCS
t icdw
HRD
t idsu
t iw pw
t iw d
t iw trd
HW R
t iwrbsyl
HREQ
Figure 17. Parallel Control Port - Intel Mode Write Cycle
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Host Management Interface (HMI)
7.4
Protocol and Messages
The message conduit is used to issue commands to the CS1810xx/CS4961xx and
retrieve HMI status. The data conduit is used to transfer data dependent on the HMI state
as determined by commands issued by the host via the message conduit.
7.4.1 Messages
Messages are used to efficiently invoke action in the CS1810xx/CS4961xx. To send a
message, the host optionally writes to the A, B, and C registers. Writing to the D register
transmits the message to the CS1810xx/CS4961xx. A listing of all HMI messages is
shown in Table 4. Refer also to "HMI Definitions" on page 33 and "HMI Access Code" on
page 34.
Message
DRQ Handshake
Mode
A
B
C
D
Translate Address
n/c
Address (MS)
Address
Address (LS)
0xB3
Acknowledge Interrupt
n/c
n/c
n/c
n/c
0xB4
Identify
read
n/c
n/c
7
0xB5
Goto Packet Transmit
Buffer
write
n/c
n/c
6
0xB5
Goto Translation
write
n/c
n/c
5
0xB5
Acknowledge Packet
Receipt
n/c
n/c
n/c
4
0xB5
Transmit Packet
n/c
n/c
n/c
3
0xB5
Goto Counters
read
n/c
n/c
2
0xB5
Goto Packet Receive
Buffer
read
n/c
n/c
1
0xB5
Goto Translation
read
n/c
n/c
0
0xB5
Table 4. HMI messages
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Host Management Interface (HMI)
7.4.1.1. Translate Address
Translate Address does not actually update the address pointers but initiates the
processing required to eventually move them. The host can accomplish other tasks,
including HMI Reads and Writes while the address translation is being processed. A
logical description of Translate Address is given below. A contextual use of the Translate
Address operation is shown in the reference implementations. Refer also to "HMI
Definitions" on page 33 and "HMI Access Code" on page 34.
void TranslateAddress(
long address )
{
int msgack = MSG_D;
MSG_A = ( address & 0xff0000 ) >> 16;
MSG_B = ( address & 0xff00 ) >> 8;
MSG_C = address & 0xff;
MSG_D = CVR_TRANSLATE_ADDRESS;
while( !( ( msgack ^ MSG_D ) & ( 1 << MSG_TOGGLE_BO ) ) );
}
7.4.1.2. Interrupt Acknowledge
Causes HACK to be de-asserted.
void InterruptAck( void )
{
int msgack = MSG_D;
MSG_D = CVR_INTERRUPT_ACK;
while( !( ( msgack ^ MSG_D ) & ( 1 << MSG_TOGGLE_BO ) ) );
}
7.4.1.3. Goto Packet
Moves HMI pointers to bridgeRxPktBuffer (write = 0) or bridgeTxPktBuffer (write = 1).
void GotoPacket(
bool write )
{
int msgack = MSG_D;
MSG_C = write ? MOP_GOTO_PACKET_TRANSMIT : MOP_GOTO_PACKET_RECEIVE;
MSG_D = CVR_MULTIPLEX_OP;
while( !( ( msgack ^ MSG_D ) & ( 1 << MSG_TOGGLE_BO ) ) );
}
7.4.1.4. Goto Translation
Moves HMI data pointers to the results of the most recently completed translate address
operation. The write parameter dictates the operation of the HREQ signal and only needs
to be supplied for applications using hardware data handshaking via this signal.
void GotoTranslation(
bool write = 0 )
{
int msgack = MSG_D;
MSG_C = write ? MOP_GOTO_TRANSLATION_WRITE : MOP_GOTO_TRANSLATION_READ;
MSG_D = CVR_MULTIPLEX_OP;
while( !( ( msgack ^ MSG_D ) & ( 1 << MSG_TOGGLE_BO ) ) );
}
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Host Management Interface (HMI)
7.4.1.5. Packet Received
Sets bridgeRxPkt = bridgeRxReady thus acknowledging receipt of the packet in
bridgeRxPktBuffer.
void PacketReceive( void )
{
int msgack = MSG_D;
MSG_C = MOP_PACKET_RECEIVE;
MSG_D = CVR_MULTIPLEX_OP;
while( !( ( msgack ^ MSG_D ) & ( 1 << MSG_TOGGLE_BO ) ) );
}
7.4.1.6. Packet Transmit
Sets bridgeTxPkt = bridgeTxPktDone+1 thus initiating transmission of the contents of
bridgeTxPktBuffer. Presumably bridgeTxPktBuffer has been previously written with valid
packet data.
void PacketTransmit( void )
{
int msgack = MSG_D;
MSG_C = MOP_PACKET_TRANSMIT;
MSG_D = CVR_MULTIPLEX_OP;
while( !( ( msgack ^ MSG_D ) & ( 1 << MSG_TOGGLE_BO ) ) );
}
7.4.1.7. Goto Counters
Moves HMI data pointers to interrupt status variables (beginning at hackStatus).
void GotoCounters( void )
{
int msgack = MSG_D;
MSG_C = MOP_GOTO_COUNTERS;
MSG_D = CVR_MULTIPLEX_OP;
while( !( ( msgack ^ MSG_D ) & ( 1 << MSG_TOGGLE_BO ) ) );
}
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Host Management Interface (HMI)
7.4.2 Status
HMI status can always be retrieved by reading the message conduit. Status is updated in
a pipelined manner whenever the Message D register is read. Reading the message
conduit gives the current status as of the last time the conduit was read. Bitfields in the
HMI Status Register are outlined in Table 5 below. Refer also to "HMI Definitions" on
page 33 and "HMI Access Code" on page 34.
Status
Bit(s)
Reserved
[31:24]
Region Length
[23:8]
Reserved
[7:5]
Writable Region
4
Translation Complete
3
Packet Transmission Complete
2
Received Packet Available
1
Message Togglebit
0
Table 5. HMI status bits
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Host Management Interface (HMI)
7.4.3 Data
Before accessing data, address setup must be performed. Address setup consists of
issuing a Translate Address request, waiting for the request to complete, then issuing a
Goto Translation.
Pipelining requires that a “garbage read” be performed following an address change. The
second word read contains the data for the address requested. No similar pipelining issue
exists with respect to write operations.
7.4.3.1. Region length
Distance from the original pointer position (as per Translate Address) to the end of the
instantiated region. A value of 0 indicates an invalid pointer.
7.4.3.2. Writable Region
When set, this bit indicates the address pointer is positioned within a writable region. MI
variables may be modified in a writable region by writing data to the data conduit.
7.4.3.3. Translation Complete
When set, this bit indicates that the address translator is available (translation results are
available and a new translation request may be submitted). This bit is cleared when a
Translate Address message is issued and is set when the translation completes.
7.4.3.4. Packet Transmission Complete
This bit is cleared when transmission is initiated by issuance of the Transmit Packet
message. The bit is set when the packet has been transmitted and the transmit buffer is
ready to accept a new packet.
7.4.3.5. Received Packet Available
This bit is set when a packet is received into the packet bridge. It is cleared when the
packet data is read and receipt is acknowledged by issuance of an Acknowledge Packet
Receipt message. Note that Received Packet Available only goes low when there are no
longer any pending received packets for the packet bridge. The packet bridge has the
capacity to queue multiple packets in the receive direction.
7.4.3.6. Message Togglebit
This bit toggles on completion of processing of each message. A safe means for the host
to acknowledge processing of messages is as follows:
void WaitToggle( void )
{
int msgack = MSG_D; /* clean pipeline */
msgack = MSG_D; /* record current state of togglebit */
MSG_D = YOUR_COMMAND_HERE; /* issue command */
/* wait for togglebit to flip */
while( !( ( msgack ^ MSG_D ) & ( 1 << MSG_TOGGLE_BO ) ) );
}
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HMI Reference Code
8.0 HMI Reference Code
The following C code provides examples in using HMI messages, HMI status, and the
HMI memory map.
8.1
HMI Definitions
/*========================================================================
** hmi.h
** CobraNet Host Management Interface example code
** Definitions
**-----------------------------------------------------------------------** $Header$
** Copyright (c) 2004, Peak Audio, a division of Cirrus Logic, Inc.
**========================================================================*/
#define MSG_A 0
#define MSG_B 1
#define MSG_C 2
#define MSG_D 3
#define DATA_A 4
#define DATA_B 5
#define DATA_C 6
#define DATA_D 7
#define CONTROL 8
#define STATUS 9
#define CVR_SET_ADDRESS 0xb2
/* Not availbale on CS1810xx/CS4961xx/CM-2. */
/*CM-1 and Reference Design only. */
#define CVR_TRANSLATE_ADDRESS 0xb3
#define CVR_INTERRUPT_ACK 0xb4
#define CVR_MULTIPLEX_OP 0xb5
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#define
#define
#define
#define
#define
#define
#define
#define
MOP_GOTO_TRANSLATION_READ 0
MOP_GOTO_TRANSLATION_WRITE 5
MOP_GOTO_PACKET_RECEIVE 1
MOP_GOTO_PACKET_TRANSMIT 6
MOP_GOTO_COUNTERS 2
MOP_PACKET_TRANSMIT 3
MOP_PACKET_RECEIPT 4
MOP_IDENTIFY 7
#define
#define
#define
#define
#define
#define
MSG_TOGGLE_BO 0
MSG_RXPACKET_BO 1
MSG_TXPACKET_BO 2
MSG_TRANSLATION_BO 3
MSG_WRITABLE_BO 4
MSG_LENGTH_BO 8
©Copyright 2005 Cirrus Logic, Inc.
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CobraNet Hardware User’s Manual
HMI Reference Code
8.2
HMI Access Code
/*========================================================================
** hmi.c
** CobraNet Host Management Interface example code
** Simple edition
**-----------------------------------------------------------------------** $Header$
** Copyright (c) 2004, Peak Audio, a division of Cirrus Logic, Inc.
**========================================================================*/
#include "hmi.h"
/* variables model HMI state */
long PeekLimit;
long PeekPointer = -1;
long PokeLimit;
long PokePointer = -1;
/* access host port hardware */
#define HMI_BASE 0
unsigned char ReadRegister(
int hmiregister )
{
return *(unsigned char volatile *const) ( hmiregister + HMI_BASE );
}
void WriteRegister(
int hmiregister,
unsigned char value )
{
*(unsigned char volatile *const) ( hmiregister + HMI_BASE ) = value;
}
void SendMessage(
unsigned char message )
{
int msgack = ReadRegister( MSG_D );
/* issue (last byte of) message */
WriteRegister( MSG_D, message );
/* wait for acceptance of message */
while( !( ( msgack ^ ReadRegister( MSG_D ) ) & ( 1 << MSG_TOGGLE_BO ) ) );
}
void SetAddress(
long address )
{
/* translate address */
WriteRegister( MSG_A, ( address & 0xff0000 ) >> 16 );
WriteRegister( MSG_B, ( address & 0xff00 ) >> 8 );
WriteRegister( MSG_C, address & 0xff );
SendMessage( CVR_TRANSLATE_ADDRESS );
/* wait for completion of translate address */
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HMI Reference Code
while( !( ReadRegister( MSG_D ) & ( 1 << MSG_TRANSLATION_BO ) ) );
/* goto translation */
WriteRegister( MSG_C, MOP_GOTO_TRANSLATION_READ );
SendMessage( CVR_MULTIPLEX_OP );
/* "garbage" read clears data pipeline */
ReadRegister( DATA_D );
/* maintain local pointers */
PeekPointer = PokePointer = address;
PeekLimit = PokeLimit = PeekPointer +
ReadRegister( MSG_C ) + ( ReadRegister( MSG_B ) << 8 );
/* read-only region addressed */
if( !( ReadRegister( MSG_A ) & ( 1 << MSG_WRITABLE_BO ) ) ) {
PokeLimit = PokePointer;
}
}
unsigned long Peek(
long address )
{
if( address != PeekPointer ) {
SetAddress( address );
}
if( PeekPointer >= PeekLimit ) {
throw "Peek addressing error!";
}
unsigned long value = ReadRegister( DATA_A ) << 24;
value += ReadRegister( DATA_B ) << 16;
value += ReadRegister( DATA_C ) << 8;
value += ReadRegister( DATA_D );
PeekPointer++; /* maintain local pointer */
return value;
}
void Poke(
long address,
unsigned long value )
{
if( address != PokePointer ) {
SetAddress( address );
}
if( PokePointer >= PokeLimit ) {
throw "Poke addressing error or read-only!";
}
WriteRegister( DATA_A, (unsigned char) ( ( value >> 24 ) & 0xff ) );
WriteRegister( DATA_B, (unsigned char) ( ( value >> 16 ) & 0xff ) );
WriteRegister( DATA_C, (unsigned char) ( ( value >> 8 ) & 0xff ) );
WriteRegister( DATA_D, (unsigned char) ( value & 0xff ) );
/* maintain local pointers */
PokePointer++;
PeekPointer = -1; /* force SetAddress()next Peek() to freshen data */
}
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HMI Reference Code
8.3
CM-1, CM-2 Auto-detection
The following function is useful for systems that support both the CM-1 and CM-2 or
where a CobraNet interface is an optional add-in.
Detect() returns 0 if no CobraNet interface module is detected, 1 for CM-1 and 2 for CM-2.
int Detect( void ) {
/* check for presence of CM-1 */
MSG_B = 0x55; /* write to CM-1 CVR register */
DATA_A = 0xaa; /* write to unused CM-1 register to flip data bus */
if( MSG_B == 0x55 ) { /* read back CVR */
/* redo same detection with different data */
MSG_B = 0x3c;
DATA_A = 0xc3;
if( MSG_B == 0x3c ) {
return 1; /* CM-1 detected */
}
}
/* check for presence of CM-2 */
/* issue identify command */
MSG_C = MOP_IDENTIFY;
MSG_D = CVR_MULTIPLEX_OP;
int msgack = MSG_D; /* clean pipeline */
msgack = MSG_D;
/* wait for togglebit to flip in response to command */
int tm0 = gettimeofday();
while( !( ( MSG_D ^ toggle ) & ( 1 << MSG_TOGGLE_BO ) ) ) {
int tm1 = gettimeofday();
if( ( tm1 - tm0 ) > time_out ) {
return 0; /* command timed out, no CobraNet interface present */
}
}
int garbage = MSG_D; /* clean pipeline */
/* verify identify results */
if( DATA_A == 'C' ) if( DATA_B == 'S' )
if( DATA_C == ( 18101 >> 8 ) ) if( DATA_D == ( 18101&0xff ) {
return 2; /* CM-2 detected */
}
return 0; /* no interface or non-supported interface */
}
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Mechanical Drawings and Schematics
9.0 Mechanical Drawings and Schematics
The section contains detailed drawings of the CM-2 board and CS1810xx/CS4961xx
device package design. The mechanical drawings are arranged as follows:
• "CM-2 Module Assembly Drawing, Top" on page 38
• "General PCB Dimensions" on page 40
• "Example Configuration, Side View" on page 41
• "Faceplate Dimensions" on page 42
• "Connector Detail" on page 43
• "CM-2 RevF Schematic Page 1 of 7" on page 44
• "CM-2 RevF Schematic Page 2 of 7" on page 45
• "CM-2 RevF Schematic Page 3 of 7" on page 46
• "CM-2 RevF Schematic Page 4 of 7" on page 47
• "CM-2 RevF Schematic Page 5 of 7" on page 48
• "CM-2 RevF Schematic Page 6 of 7" on page 49
• "CM-2 RevF Schematic Page 7 of 7" on page 50
• "144-Pin LQFP Package Drawing" on page 51
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Mechanical Drawings and Schematics
CM-2 Mechanical Drawings
NOT TO SCALE
9.1
Figure 18. CM-2 Module Assembly Drawing, Top
38
©Copyright 2005 Cirrus Logic, Inc.
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CobraNet Hardware User’s Manual
Mechanical Drawings and Schematics
Figure 19. CM-2 Module Assembly Drawing, Bottom
DS651UM23
Version 2.3
©Copyright 2005 Cirrus Logic, Inc.
39
©Copyright 2005 Cirrus Logic, Inc.
NOT TO SCALE
2x Mounting holes for front faceplate.
0.3
3.500
General PCB dimensions
2.86
Component Side = J1
Bottom Side = J2
A20
A20
A1
Viewed from component side up.
B20
B1
B20
B1
Component Side = J3
Bottom Side = J4
0.175
0.175
4x 0.16 Hole, 0.3 pads
3.500
40
A1
2x Mounting holes for PCB standoffs
CobraNet Hardware User’s Manual
Mechanical Drawings and Schematics
Figure 20. General PCB Dimensions
DS651UM23
Version 2.3
NOT TO SCALE
0.340
This distance accounts for the thickness of the faceplate
CobraNet Hardware User’s Manual
Mechanical Drawings and Schematics
Figure 21. Example Configuration, Side View
DS651UM23
Version 2.3
©Copyright 2005 Cirrus Logic, Inc.
41
©Copyright 2005 Cirrus Logic, Inc.
2x, Hole Diameter 0.160
1.343
1.333
NOT TO SCALE
0.300
0.431
0.421
0.125 dia, 2x
0.175
0.550
0.680
0.700
Faceplate Dimensions
Faceplate material is 20 guage, 0.037" thick
Chrome plating on faceplate
3.500
0.175
1.000 max, 0.9 typ.
0.340
0.800
0.810
42
1.000
0.490
Note: Mechanical dimensions for the CM-2 and CM-1 Rev F are identical.
There are differences with earlier versions of the CM-1, however. For
reference, earlier versions of the CM-1 dimensions are shown in RED.
0.300
4-40 PEM's, x2
CobraNet Hardware User’s Manual
Mechanical Drawings and Schematics
Figure 22. Faceplate Dimensions
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Version 2.3
0.862
0.500
3.343
CobraNet Hardware User’s Manual
Mechanical Drawings and Schematics
Component
Side Up
1.576
1.925
J3
8x 0.047 Alignment holes
0.208
0.039
NOT TO SCALE
0.157
J1
Connector Detail
Figure 23. Connector Detail
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CobraNet Hardware User’s Manual
Mechanical Drawings and Schematics
9.2
CM-2 Schematics
connector
connector.sch
core
core.sch
HRESET#
HRESET#
HRESET#
HEN#
HRW
HDS#
HADDR[0..3]
HDATA[0..7]
HREQ#
HACK#
HEN#
HRW
HDS#
HADDR[0..3]
HDATA[0..7]
HREQ#
HACK#
HEN#
HRW
HDS#
HADDR[0..3]
HDATA[0..7]
HREQ#
HACK#
WATCHDOG
MUTE#
WATCHDOG
MUTE#
WATCHDOG
MUTE#
UART_TX_OE
UART_TXD
UART_RXD
UART_TX_OE
UART_TXD
UART_RXD
UART_TX_OE
UART_TXD
UART_RXD
MCLK_OUT
MCLK_IN
REFCLK_IN
MCLK_OUT
MCLK_IN
REFCLK_IN
MCLK_OUT
MCLK_IN
REFCLK_IN
FS1
SSI_CLK
SSI_DIN[0..3]
SSI_DOUT[0..3]
FS1
SSI_CLK
SSI_DIN[0..3]
SSI_DOUT[0..3]
FS1
SSI_CLK
SSI_DIN[0..3]
SSI_DOUT[0..3]
GPIO[0..1]
RSVD[1..5]
AUX_POWER[3..0]
RSVD[1..5]
AUX_POWER[0..3]
RSVD[1..5]
AUX_POWER[0..3]
GPIO[0..1] is not used elsewhere.
These pulldowns are used for test points and
to keep these signals at valid levels.
GPIO[0..1]
GPIO0
GPIO1
R1
R2
10K Ohm
GND
This linear regulator is used to assure that the +1.8v rail quickly passes
the 0.5v threshold at powerup, thus minimizing power sequencing issues
and making sure that the DSP does not draw excessive power as the
power rails ramp up. This linear regulator is set with Vout=1.22v, so it
is effectively shut off once the switching regulator comes up. Further
testing and characterization of the DSP is require to determine if this
linear regulator is in fact required.
U9
1
IN
OUT
BYP
2
GND
ADJ
4
C45
0.01 uF
3
5
LTC1761
U1
LTC3406-1.8
1
RUN
SW
Vout/FB
3
L1
VCC_+1.8
2.2 uH
5
C2
C3
2
C1
10 uF, X5R, 6.3 Volts
VIN
GND
4
VCC_+3.3
10 uF, X5R, 6.3 Volts
This is a simple switching regulator. It produces
1.8V at >500 mA at about 90% efficency. A simple low drop
out linear regulator would be a cheaper alternative at the
expense of power. A linear regulator would dissapate
about 0.75 watts max, This switching regulator dissapates
about 0.10 watts max.
Figure 24. CM-2 RevF Schematic Page 1 of 7
44
©Copyright 2005 Cirrus Logic, Inc.
DS651UM23
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VCXO_CTRL
RSVD[1..5]
REFCLK_IN
WATCHDOG
MUTE#
GPIO[0..1]
FS1
SSI_CLK
SSI_DIN[0..3]
SSI_DOUT[0..3]
UART_TX_OE
UART_TXD
UART_RXD
HEN#
HRW
HDS#
HADDR[0..3]
HDATA[0..7]
HREQ#
HACK#
R12
3.3K Ohm
CLK_25
VCXO_CTRL
MCLK_SEL
MCLK_INTERNAL
RSVD[1..5]
REFCLK_IN
WATCHDOG
MUTE#
GPIO[0..1]
FS1
SSI_CLK
SSI_DIN[0..3]
SSI_DOUT[0..3]
UART_TX_OE
UART_TXD
UART_RXD
HEN#
HRW
HDS#
HADDR[0..3]
HDATA[0..7]
HREQ#
HACK#
C19
0.1 uF
CLK_25
AB2
C2
D2
A1
B1
C1
D1
OUT
OUT
VCC
VCC
VCC
C21
0.1 uF
VCC_+3.3
24.576 MHz VCXO
GND
GND
GND
CTRL
CTRL
CTRL
CTRL
U3
FLASH_CS#
MAC_IRQ1
MAC_IRQ0
MAC_CS#
OE#
WE#
IOWAIT
ADDR[0..19]
DATA[0..15]
HRESET_BUF#
VCXO_CTRL
MCLK_SEL
MCLK_INTERNAL
RSVD[1..5]
REFCLK_IN
WATCHDOG
MUTE#
GPIO[0..1]
FS1
SSI_CLK
SSI_DIN[0..3]
SSI_DOUT[0..3]
UART_TX_OE
UART_TXD
UART_RXD
HEN#
HRW
HDS#
HADDR[0..3]
HDATA[0..7]
HREQ#
HACK#
dsp
dsp.sch
HRESET#
5
74LVC32
U10B
AB3
CD3
A4
B4
CD4
VCC_+3.3
FLASH_CS#
MAC_IRQ1
MAC_IRQ0
MAC_CS#
OE#
WE#
IOWAIT
ADDR[0..19]
DATA[0..15]
6
MCLK_IN
DATA[0..15]
ADDR[0..19]
4
HRESET_BUF#
GND
VCXO_OUT
VCXO_OUT
MCLK_SEL
MCLK_IN
VCXO_OUT
FLASH_CS#
OE#
WE#
ADDR[0..19]
DATA[0..15]
HRESET_BUF#
flash
flash.sch
MAC_IRQ1
MAC_CS#
OE#
WE#
IOWAIT
ADDR[0..19]
DATA[0..15]
HRESET_BUF#
macphy2
macphy2.sch
MAC_IRQ0
MAC_CS#
OE#
WE#
IOWAIT
ADDR[0..19]
DATA[0..15]
HRESET_BUF#
macphy1
macphy1.sch
GND
GND
GND
GND
GND
15
1
2
5
11
14
3
6
10
13
LED_BUF[0..7]
AUX_POWER[0..3]
CLK_25
LED_CTRL[0..2]
LED_BUF[0..7]
AUX_POWER[0..3]
CLK_25
G
A/B
1A
2A
3A
4A
1B
2B
3B
4B
VCC_+3.3
3Y
2Y
1Y
4Y
R16
24.9 Ohm, 1%
C22
0.1 uF
VCC_+3.3
U4
74LVC157
12
9
7
24.9 Ohm, 1%
R44
4
LED_BUF[0..7]
CLK_25
AUX_POWER[3..0]
CLK_25
16
VCC
GND
©Copyright 2005 Cirrus Logic, Inc.
8
MCLK_OUT
MCLK_INTERNAL
MCLK_OUT
AUX_POWER[3..0]
LED_CTRL[0..2]
LED_BUF[0..7]
VCC_+3.3
LED_CTRL2
LED_CTRL0
LED_CTRL1
GND
12
13
10
11
14
RCK
OE#
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
CASCADE
VCC_+3.3
SCLR#
SCK
DIN
C15
0.1 uF
VCC_+3.3
16
VCC
GND
DS651UM23
Version 2.3
8
HRESET#
9
15
1
2
3
4
5
6
7
IOWAIT
MUTE#
WATCHDOG
VCXO_CTRL
MCLK_SEL
74LV595
U2
R4
C20
0.1 uF
C18
0.1 uF
C17
0.1 uF
C16
0.1 uF
2
3
4
5
7
8
9
10
6
1
R15
3.3K Ohm
R3
10K Ohm
10K Ohm, 8x Array
RN2
GND
GND
VCC_+3.3
VCC_+3.3
LED Filters go close to the connector.
30.9 Ohm, 1%
R11
30.9 Ohm, 1%
R10
30.9 Ohm, 1%
R9
30.9 Ohm, 1%
R8
30.9 Ohm, 1%
R7
30.9 Ohm, 1%
R6
30.9 Ohm, 1%
R5
30.9 Ohm, 1%
LED_BUF7
LED_BUF6
LED_BUF5
LED_BUF4
LED_BUF3
LED_BUF2
LED_BUF1
LED_BUF0
CobraNet Hardware User’s Manual
Mechanical Drawings and Schematics
LED_BUF[0..7]
Figure 25. CM-2 RevF Schematic Page 2 of 7
45
LED_CTRL[0..2]
ADDR[0..19]
HRESET_BUF#
HRESET_BUF#
ADDR19
ADDR18
ADDR17
ADDR16
ADDR15
ADDR14
ADDR13
ADDR12
ADDR11
ADDR10
ADDR9
ADDR8
ADDR7
ADDR6
ADDR5
ADDR4
ADDR3
ADDR2
ADDR1
10
12
9
16
17
48
1
2
3
4
5
6
7
8
18
19
20
21
22
23
24
25
NC
D15/A-1
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
CE#
WE#
OE#
BYTE#
NC/VPP
NC/WP#
NC/RY/BY#
C23
0.1 uF
VCC_+3.3
RESET#
NC/A19
NC/A18
A17
A16
A15
A14
A13
A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
GND
ADDR[0..19]
VCC
GND
27
©Copyright 2005 Cirrus Logic, Inc.
46
46
37
VCC_+3.3
26
11
28
47
13
14
15
45
43
41
39
36
34
32
30
44
42
40
38
35
33
31
29
DATA7
DATA6
DATA5
DATA4
DATA3
DATA2
DATA1
DATA0
ADDR0
FLASH_CS#
WE#
OE#
GND
VCC_+3.3
VCC_+3.3
FLASH_TSOP
U5
FLASH_CS#
WE#
OE#
DATA[0..15]
DATA[0..15]
CobraNet Hardware User’s Manual
Mechanical Drawings and Schematics
Figure 26. CM-2 RevF Schematic Page 3 of 7
DS651UM23
Version 2.3
8
6
8
1
VCC_+3.3
1
2
7
2
CLK_25
CN12
0.1 uF, 4x Array
CN1
0.1 uF, 4x Array
8
VCC_+3.3
1
C40
22 pF
CLK_25
ADDR[0..19]
DATA[0..15]
IOWAIT
1
ADDR[0..19]
DATA[0..15]
CN3
0.1 uF, 4x Array
CN2
0.1 uF, 4x Array
R55
1 MegOhm
25 MHz
Y1
2
24.9 Ohm, 1%
R45
8
4
7
6
1
3
6
3
2
7
2
5
4
5
4
7
8
VCC_+3.3
1
6
C42
2.2 uF, X7R, 1206
C41
22 pF
UART_TX_OE
UART_TXD
UART_RXD
OE#
WE#
FLASH_CS#
MAC_CS#
HRESET_BUF#
UART_TX_OE
UART_TXD
UART_RXD
FILT2
FILT1
XTAL_OUT
XTO
XTI
UART_TX_OE
UART_TXD
UART_RXD
EXT_A19
EXT_A18
EXT_A17
EXT_A16
EXT_A15
SD_A14/EXT_A13
SD_A13/EXT_A14
SD_A12/EXT_A11
SD_A11/EXT_A10
SD_A10/EXT_A12
SD_A9/EXT_A9
SD_A8/EXT_A8
SD_A7/EXT_A7
SD_A6/EXT_A6
SD_A5/EXT_A5
SD_A4/EXT_A4
SD_A3/EXT_A3
SD_A2/EXT_A2
SD_A1/EXT_A1
SD_A0/EXT_A0
SD_D15/EXT_D7
SD_D14/EXT_D6
SD_D13/EXT_D5
SD_D12/EXT_D4
SD_D11/EXT_D3
SD_D10/EXT_D2
SD_D9/EXT_D1
SD_D8/EXT_D0
SD_D7/EXT_D15
SD_D6/EXT_D14
SD_D5/EXT_D13
SD_D4/EXT_D12
SD_D3/EXT_D11
SD_D2/EXT_D10
SD_D1/EXT_D9
SD_D0/EXT_D8
EXT_OE#
EXT_WE#
EXT_CS1#
EXT_CS2#
IOWAIT
RESET#
C43
1000 pF, COG
R41
5.90K Ohm
127
128
123
124
125
23
25
26
88
87
85
84
82
75
77
55
56
74
58
59
61
62
64
67
68
70
71
72
40
41
42
43
45
46
48
49
29
30
31
32
34
35
37
39
DATA15
DATA14
DATA13
DATA12
DATA11
DATA10
DATA9
DATA8
DATA7
DATA6
DATA5
DATA4
DATA3
DATA2
DATA1
DATA0
ADDR19
ADDR18
ADDR17
ADDR16
ADDR15
ADDR14
ADDR13
ADDR12
ADDR11
ADDR10
ADDR9
ADDR8
ADDR7
ADDR6
ADDR5
ADDR4
ADDR3
ADDR2
ADDR1
ADDR0
89
38
90
65
96
OE#
WE#
FLASH_CS#
MAC_CS#
IOWAIT
93
CN5
0.1 uF, 4x Array
CN4
0.1 uF, 4x Array
HRESET_BUF#
8
1
3
6
3
2
7
2
7
5
4
5
4
6
3
3
4
5
5
VCC_+1.8
VCC_+1.8
VCC_+3.3
3.3K Ohm
VCC_+3.3
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
13
21
27
36
47
57
63
69
76
86
94
101
116
122
133
139
R13
R14
GND
GND
CON4
1
2
3
4
JP1
9
HR/W#
HDS#
HEN#
HACK#
HREQ#
10
10 uF, X5R, 6.3 Volts
C4
HRW
HDS#
HEN#
HACK#
HREQ#
HADDR3
HADDR2
HADDR1
HADDR0
HDATA7
HDATA6
HDATA5
HDATA4
HDATA3
HDATA2
HDATA1
HDATA0
MCLK_INTERNAL
DAO1_LRCLK
SSI_CLK_J
SSI_DOUT3
SSI_DOUT2
SSI_DOUT1
SSI_DOUT0
DAO2_LRCLK
RSVD5
RSVD4
RSVD2
RSVD1
DAO1_LRCLK
SSI_CLK_J
SSI_DIN3
SSI_DIN2
SSI_DIN1
SSI_DIN0
RSVD3
GPIO1
GPIO0
REFCLK_IN
WATCHDOG
MUTE#
MCLK_SEL
MAC_IRQ1
MAC_IRQ0
VCXO_CTRL
105
106
109
110
111
112
114
115
117
118
120
121
8
22
20
15
16
17
19
14
12
5
6
7
11
138
137
131
132
134
135
141
142
108
100
99
97
95
92
2
143
144
1
C24
0.1 uF
C52
0.1 uF
D1
1N4148W
107
103
104
102
140
FB1
CS18101
U6
8
R57
10K Ohm
74LVC32
U10C
3.3K Ohm
DAO2_LRCLK
DAO1_LRCLK
C44
0.1 uF
VCXO_CTRL
VCC_+1.8
RSVD[1..5]
SSI_DIN[0..3]
RSVD[1..5]
G
A/B
1A
2A
3A
4A
1B
2B
3B
4B
VCC_+3.3
4Y
3Y
2Y
1Y
HDATA[0..7]
HADDR[0..3]
Default Boot Mode:
HS3 - Down
HS2 - Down
HS1 - Up
HS0 - Down
R53
RSVD1
SSI_DOUT2
SSI_DOUT1
SSI_DOUT0
SSI_CLK
FS1
FS1
3.3K Ohm
These pullups and pulldowns are used
to set the boot mode of the DSP. The
appropriate resistor is installed to select
the boot mode.
3.3K Ohm
RSVD[1..5]
VCC_+3.3
C53
0.1 uF
VCC_+3.3
U11
74LVC157
12
9
7
4
GPIO[0..1]
SSI_DIN[0..3]
SSI_DOUT[0..3]
SSI_CLK
15
1
2
5
11
14
3
6
10
13
GPIO[0..1]
SSI_DOUT[0..3]
REFCLK_IN
WATCHDOG
MUTE#
MCLK_SEL
MAC_IRQ1
MAC_IRQ0
C5
GND
GND
GND
GND
GND
GND
GND
24.9 Ohm, 1%
R54
MCLK_INTERNAL
HDATA[0..7]
HADDR[0..3]
HRW
HDS#
HEN#
HACK#
HREQ#
R56
10 uF, X5R, 6.3 Volts
FBEAD, 68 Ohm @ 100 MHz
VCXO_CTRL
GPIO2
GPIO1
GPIO0
REFCLK_IN
WATCHDOG_OUT
MUTE#
MCLK_SEL
IRQ1
IRQ2
NC
NC
DAI1_LRCLK
DAI1_SCLK
DAI1_DATA3
DAI1_DATA2
DAI1_DATA1
DAI1_DATA0
DAO2_LRCLK
NC
NC
NC
NC
HS3
DAO1_LRCLK
DAO1_SCLK
DAO1_DATA3
DAO1_DATA2/HS2
DAO1_DATA1/HS1
DAO1_DATA0/HS0
DAO_MCLK
HDATA7
HDATA6
HDATA5
HDATA4
HDATA3
HDATA2
HDATA1
HDATA0
HADDR3
HADDR2
HADDR1
HADDR0
Debug Port
VCC_DSPA
VCC_+3.3
DEBUG_DATA
DEBUG_CLK
GND
16
VCC
GND
8
VCC_+1.8
10
24
54
66
83
98
119
130
VDDD
VDDD
VDDD
VDDD
VDDD
VDDD
VDDD
VDDD
18
33
44
60
91
113
136
73
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
9
TEST
4
3
DBCK
DBDA
NC
NC
NC
NC
NC
NC
NC
NC
NC
28
50
51
52
53
78
79
80
81
GND_A
VDD_A
126
129
©Copyright 2005 Cirrus Logic, Inc.
R42
R46
R48
R50
DS651UM23
Version 2.3
R43
R47
R49
R51
VCC_+1.8
CobraNet Hardware User’s Manual
Mechanical Drawings and Schematics
Figure 27. CM-2 RevF Schematic Page 4 of 7
47
MAC_CS#
OE#
DATA[0..15]
ADDR[0..19]
MAC_CS#
OE#
74LVC32
U10A
DATA[0..15]
ADDR[0..19]
IOWAIT
WE#
MAC_IRQ0
HRESET_BUF#
2
1
3
8
1
DATA0
DATA1
DATA2
DATA3
DATA4
DATA5
DATA6
DATA7
DATA8
DATA9
DATA10
DATA11
DATA12
DATA13
DATA14
DATA15
VCC_+3.3
VCC_+3.3
ADDR2
ADDR3
ADDR1
ADDR4
ADDR0
WE#
MAC_CS#
IOWAIT
MAC_IRQ0
6
7
8
9
10
11
12
13
89
88
87
86
85
84
83
82
93
94
95
96
97
98
1
2
3
4
91
92
100
79
SD0
SD1
SD2
SD3
SD4
SD5
SD6
SD7
SD8
SD9
SD10
SD11
SD12
SD13
SD14
SD15
SA4
SA5
SA6
SA7
SA8
SA9
IOR#
IOW#
AEN
IOWAIT
IO16
CMD
INT
WAKEUP
VCC_+3.3
CN6
0.1 uF, 4x Array
RST
PW_RST#
2
7
14
80
6
3
HRESET_BUF#
4
5
VCC_+3.3
VCC_PHY1 GND
8
VCC_+3.3
10 uF, X5R, 6.3 Volts
2
1
CLK_25
VCC_+3.3
CN7
0.1 uF, 4x Array
VCC_PHY1
10 uF, X5R, 6.3 Volts
VCC_PHY1
DM9000
57
56
43
44
78
37
24
49
50
51
52
53
54
47
38
39
40
41
45
46
29
30
33
34
Keep res close to chip pins.
6.8K Ohm, 1%
R25
MDC
MDIO
CRS
COL
LINK_O
LINK_I
SD
TX_CLK
TXD0
TXD1
TXD2
TXD3
TX_EN
RX_CLK
RXD0
RXD1
RXD2
RXD3
RX_DV
RX_ER
RXI+
RXI-
TXO+
TXO-
U7
U10E
74LVC32
VCC_+3.3
C51
0.1 uF
VCC_+3.3
R20
49.9 Ohm, 1%
VCC_PHY1
R19
49.9 Ohm, 1%
LED_CTRL[0..2]
CN8
0.1 uF, 4x Array
LED_CTRL[0..2]
8
C7
LED_CTRL2
LED_CTRL1
LED_CTRL0
C46
0.01 uF
2
1
C6
5
20
36
55
72
73
90
DVDD
DVDD
DVDD
DVDD
DVDD
DVDD
DVDD
6
7
AGND
AGND
31
32
DGND
DGND
DGND
DGND
DGND
DGND
DGND
DGND
15
23
42
58
63
76
81
99
4
3
27
28
35
AVDD
AVDD
AVDD
6
7
71
70
69
68
FB2
2
3
4
5
7
8
9
10
GND
GND
0.1 uF
C27
6
1
3.3K Ohm, 8x Array
RN7
C25
0.1 uF
GND
GND
0.1 uF
C28
VCC_PHY1
R18
R17
49.9 Ohm, 1%
GND
0.1 uF
C26
12
11
10
9
8
7
H2006A
RXD-
RXD+
TXD-
TXD+
T1B
RXD-
RXD+
TXD-
TXD+
75 Ohm, 1%
13
14
15
16
17
18
S1
S2
FB3
AUX_POWER0
FB4
AUX_POWER1
FB5
AUX_POWER2
FB6
AUX_POWER3
FBEAD, 68 Ohm @ 100 MHz
J5
RJ45
SHIELD
SHIELD
i
h
AUX_POWER[0..3]
Warning: Failure to properly install and
configure the aux. Ethernet signals can result in
very bad things (i.e., fire, smoke, bad hair days).
If power is supplied via the RJ-45 connector then
only the ferrite beads are installed (not the
resistors). If power is not supplied via the RJ-45
then the resistors are installed and the beads are
not.
AUX_POWER[0..3]
Note: See Text Warning
75 Ohm, 1%
1
2
3
4
5
6
7
8
LED_BUF[0..7]
C48
0.01 uF, 2KV
SHIELD
LED_BUF[0..7]
R27
R28
5
TEST5
TEST4
TEST3
TEST2
TEST1
48
19
18
17
16
NC
NC
NC
74
75
77
CLK20MO
59
X2_25M
X1_25M
21
22
CLK_25
R29
R30
R31
R32
4
GPIO3
GPIO2
GPIO1
GPIO0
62
61
60
LINKACT#
DUP#
SPEED#
BGRES
BGGND
26
25
LED_BUF2
L4
3
EEDI
EEDO
EECK
EECS
LED_BUF3
L3
5
64
65
66
67
LED_BUF0
FBEAD, 68 Ohm @ 100 MHz
14
GND
VCC
©Copyright 2005 Cirrus Logic, Inc.
7
LED_BUF1
L2
48
L1
VCC_+3.3
CobraNet Hardware User’s Manual
Mechanical Drawings and Schematics
Figure 28. CM-2 RevF Schematic Page 5 of 7
DS651UM23
Version 2.3
OE#
MAC_CS#
DATA[0..15]
ADDR[0..19]
13
OE#
74LVC32
U10D
DATA[0..15]
ADDR[0..19]
IOWAIT
WE#
MAC_IRQ1
HRESET_BUF#
12
MAC_CS#
11
8
1
DATA0
DATA1
DATA2
DATA3
DATA4
DATA5
DATA6
DATA7
DATA8
DATA9
DATA10
DATA11
DATA12
DATA13
DATA14
DATA15
VCC_+3.3
VCC_+3.3
ADDR2
ADDR3
ADDR1
ADDR4
ADDR0
WE#
MAC_CS#
IOWAIT
MAC_IRQ1
6
7
8
9
10
11
12
13
89
88
87
86
85
84
83
82
93
94
95
96
97
98
1
2
3
4
91
92
100
79
SD0
SD1
SD2
SD3
SD4
SD5
SD6
SD7
SD8
SD9
SD10
SD11
SD12
SD13
SD14
SD15
SA4
SA5
SA6
SA7
SA8
SA9
IOR#
IOW#
AEN
IOWAIT
IO16
CMD
INT
WAKEUP
RST
PW_RST#
2
7
14
80
6
3
HRESET_BUF#
VCC_+3.3
CN9
0.1 uF, 4x Array
10 uF, X5R, 6.3 Volts
8
VCC_PHY2 GND
2
VCC_+3.3
6
1
VCC_+3.3
4
5
C47
0.01 uF
CLK_25
VCC_+3.3
CN10
0.1 uF, 4x Array
VCC_PHY2
VCC_PHY2
10 uF, X5R, 6.3 Volts
C9
DM9000
57
56
43
44
78
37
24
49
50
51
52
53
54
47
38
39
40
41
45
46
29
30
33
34
R52
3.3K Ohm
CN11
0.1 uF, 4x Array
R24
49.9 Ohm, 1%
VCC_PHY2
R23
49.9 Ohm, 1%
VCC_+3.3
The secondary Ethernet MAC and connector are optional.
If it is not required then all parts on this page can be depopulated
(or removed entirely from a new design based on this circuit).
Keep res close to chip pins.
6.8K Ohm, 1%
R26
MDC
MDIO
CRS
COL
LINK_O
LINK_I
SD
TX_CLK
TXD0
TXD1
TXD2
TXD3
TX_EN
RX_CLK
RXD0
RXD1
RXD2
RXD3
RX_DV
RX_ER
RXI+
RXI-
TXO+
TXO-
U8
8
FB7
2
1
C8
DGND
DGND
DGND
DGND
DGND
DGND
DGND
DGND
4
AGND
AGND
6
7
71
70
69
68
4
FBEAD, 68 Ohm @ 100 MHz
2
3
4
5
7
8
9
10
GND
GND
0.1 uF
C30
C29
0.1 uF
6
1
3.3K Ohm, 8x Array
RN8
GND
0.1 uF
C31
GND
GND
0.1 uF
C32
VCC_PHY2
3
2
1
H2006A
RXD-
RXD+
RXD-
RXD+
75 Ohm, 1%
22
23
24
19
21
20
TXD-
TXD+
6
TXD-
TXD+
T1A
5
4
S1
S2
FB8
AUX_POWER0
AUX_POWER1
FB9
AUX_POWER2
FB10
AUX_POWER3
FB11
FBEAD, 68 Ohm @ 100 MHz
J6
RJ45
SHIELD
SHIELD
AUX_POWER[0..3]
Warning: Failure to properly install and
configure the aux. Ethernet signals can result in
very bad things (i.e., fire, smoke, bad hair days).
If power is supplied via the RJ-45 connector then
only the ferrite beads are installed (not the
resistors). If power is not supplied via the RJ-45
then the resistors are installed and the beads are
not.
AUX_POWER[0..3]
Note: See Text Warning
75 Ohm, 1%
1
2
3
4
5
6
7
8
LED_BUF[0..7]
C49
0.01 uF, 2KV
SHIELD
LED_BUF[0..7]
R33
R34
7
27
28
35
AVDD
AVDD
AVDD
5
20
36
55
72
73
90
DVDD
DVDD
DVDD
DVDD
DVDD
DVDD
DVDD
15
23
42
58
63
76
81
99
R35
R36
R37
R38
3
31
32
LED_BUF6
L4
5
TEST5
TEST4
TEST3
TEST2
TEST1
48
19
18
17
16
NC
NC
NC
74
75
77
CLK20MO
59
LED_BUF7
L3
3
GPIO3
GPIO2
GPIO1
GPIO0
62
61
60
LINKACT#
DUP#
SPEED#
BGRES
BGGND
26
25
X2_25M
X1_25M
21
22
CLK_25
R21
LED_BUF4
5
64
65
66
67
©Copyright 2005 Cirrus Logic, Inc.
EEDI
EEDO
EECK
EECS
R22
49.9 Ohm, 1%
LED_BUF5
L2
DS651UM23
Version 2.3
L1
VCC_+3.3
CobraNet Hardware User’s Manual
Mechanical Drawings and Schematics
Figure 29. CM-2 RevF Schematic Page 6 of 7
49
RSVD[1..5]
WATCHDOG
MUTE#
AUX_POWER[0..3]
SSI_CLK
MCLK_IN
MCLK_OUT
FS1
REFCLK_IN
UART_TX_OE
UART_TXD
UART_RXD
SSI_DIN[0..3]
SSI_DOUT[0..3]
HADDR[0..3]
RSVD[1..5]
AUX_POWER[0..3]
SSI_DIN[0..3]
SSI_DOUT[0..3]
HADDR[0..3]
HDATA[0..7]
M1
MOUNTING
RSVD1
RSVD2
RSVD3
RSVD4
RSVD5
WATCHDOG
MUTE#
AUX_POWER0
AUX_POWER1
AUX_POWER2
AUX_POWER3
SSI_CLK
MCLK_IN
MCLK_OUT
FS1
REFCLK_IN
UART_TX_OE
UART_TXD
UART_RXD
SSI_DIN0
SSI_DIN1
SSI_DIN2
SSI_DIN3
SSI_DOUT0
SSI_DOUT1
SSI_DOUT2
SSI_DOUT3
HADDR0
HADDR1
HADDR2
HADDR3
HDATA0
HDATA1
HDATA2
HDATA3
HDATA4
HDATA5
HDATA6
HDATA7
HRESET#
HACK#
HRW
HDS#
HREQ#
HEN#
M3
MOUNTING
SHIELD
R40
0 Ohm
M4
MOUNTING
0.01 uF, 2KV
C50
R39
0 Ohm
M2
MOUNTING
1
1
©Copyright 2005 Cirrus Logic, Inc.
1
50
1
HRESET#
HACK#
HRW
HDS#
HREQ#
HEN#
HDATA[0..7]
Place near the Ethernet connectors.
These two mounting holes are located at the
"back" of the CM-2, near the main interface
connectors.
These two mounting holes are located near
the front panel of the CM-2.
RSVD2
MUTE#
FS1
MCLK_OUT
MCLK_IN
REFCLK_IN
SSI_CLK
SSI_DOUT0
SSI_DOUT1
SSI_DOUT2
SSI_DOUT3
SSI_DIN0
SSI_DIN1
SSI_DIN2
SSI_DIN3
RSVD3
WATCHDOG
RSVD4
AUX_POWER2
AUX_POWER0
UART_RXD
UART_TX_OE
HACK#
HRW
HDS#
HREQ#
HEN#
HADDR0
HADDR1
HADDR2
HDATA0
HDATA1
HDATA2
HDATA3
HDATA4
HDATA5
HDATA6
HRESET#
HDATA7
HADDR3
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
B1
B2
B3
B4
B5
B6
B7
B8
B9
B10
B11
B12
B13
B14
B15
B16
B17
B18
B19
B20
B1
B2
B3
B4
B5
B6
B7
B8
B9
B10
B11
B12
B13
B14
B15
B16
B17
B18
B19
B20
CNM_CONN40
J3
CNM_CONN40
J1
RSVD1
GND
VCC_+3.3
GND
VCC_+3.3
GND
VCC_+3.3
GND
VCC_+3.3
GND
VCC_+3.3
GND
VCC_+3.3
GND
VCC_+3.3
GND
GND
VCC_+5
VCC_+5
AUX_POWER3
AUX_POWER1
GND
VCC_+3.3
GND
VCC_+3.3
GND
VCC_+3.3
GND
VCC_+3.3
GND
VCC_+3.3
GND
VCC_+3.3
GND
VCC_+3.3
GND
VCC_+3.3
GND
VCC_+3.3
UART_TXD
B1
B2
B3
B4
B5
B6
B7
B8
B9
B10
B11
B12
B13
B14
B15
B16
B17
B18
B19
B20
B1
B2
B3
B4
B5
B6
B7
B8
B9
B10
B11
B12
B13
B14
B15
B16
B17
B18
B19
B20
RSVD1
UART_TXD
C35
0.1 uF
C37
0.1 uF
C38
0.1 uF
AC Signal Return Path Caps
C36
0.1 uF
GND
VCC_+3.3
GND
VCC_+3.3
GND
VCC_+3.3
GND
VCC_+3.3
GND
VCC_+3.3
GND
VCC_+3.3
GND
VCC_+3.3
GND
GND
VCC_+5
VCC_+5
AUX_POWER3
AUX_POWER1
GND
VCC_+3.3
GND
VCC_+3.3
GND
VCC_+3.3
GND
VCC_+3.3
GND
VCC_+3.3
GND
VCC_+3.3
GND
VCC_+3.3
GND
VCC_+3.3
GND
VCC_+3.3
C39
0.1 uF
VCC_+5
C10
VCC_+3.3
10 uF, X5R, 6.3 Volts
C12
Power Decoupling Caps
10 uF, X5R, 6.3 Volts
C11
10 uF, X5R, 6.3 Volts
C13
10 uF, X5R, 6.3 Volts
C14
2
3
4
5
7
8
9
10
2
3
4
5
7
8
9
10
2
3
4
5
7
8
9
10
2
3
4
5
7
8
9
10
6
1
6
1
6
1
6
1
10K Ohm, 8x Array
RN6
10K Ohm, 8x Array
RN5
10K Ohm, 8x Array
RN4
10K Ohm, 8x Array
RN3
VCC_+3.3
VCC_+3.3
GND
GND
GND
GND
GND
GND
These pullups/downs are used to assure a valid logic level if a signal is
tri-stated or not connected. In some situations, these may not be required.
HEN#
HREQ#
HDS#
HACK#
UART_TXD
UART_RXD
UART_TX_OE
REFCLK_IN
HDATA3
HDATA2
HDATA1
HDATA0
HADDR0
HADDR1
HADDR2
HDATA4
SSI_CLK
MCLK_IN
FS1
RSVD2
HADDR3
HDATA7
HDATA6
HDATA5
SSI_DIN3
SSI_DIN2
SSI_DIN1
SSI_DIN0
RSVD5
SSI_DOUT3
RSVD3
RSVD4
Note: Pull-ups/downs on SSI_DOUT[0..4] are located on the DSP schematic page.
Note: Similar AC signal return path caps must be included on the motherboard near the connector.
C34
0.1 uF
CNM_CONN40
J4
CNM_CONN40
J2
C33
0.1 uF
VCC_+3.3
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
10 uF, X5R, 6.3 Volts
RSVD2
MUTE#
FS1
MCLK_OUT
MCLK_IN
REFCLK_IN
SSI_CLK
SSI_DOUT0
SSI_DOUT1
SSI_DOUT2
SSI_DOUT3
SSI_DIN0
SSI_DIN1
SSI_DIN2
SSI_DIN3
RSVD3
WATCHDOG
RSVD4
AUX_POWER2
AUX_POWER0
UART_RXD
UART_TX_OE
HACK#
HRW
HDS#
HREQ#
HEN#
HADDR0
HADDR1
HADDR2
HDATA0
HDATA1
HDATA2
HDATA3
HDATA4
HDATA5
HDATA6
HRESET#
HDATA7
HADDR3
CobraNet Hardware User’s Manual
Mechanical Drawings and Schematics
Figure 30. CM-2 RevF Schematic Page 7 of 7
DS651UM23
Version 2.3
CobraNet Hardware User’s Manual
Mechanical Drawings and Schematics
9.3
CS1810xx/CS4961xx Package
E
E1
D D1
Notes:
1. Controlling dimension is millimeter.
2. Dimensioning and tolerancing per ASME
Y14.5M-1994.
e
b
SEATING PLANE
ddd M B
B
L1
θ
A
A1
L
Figure 31. 144-Pin LQFP Package Drawing
MILLIMETERS
INCHES
DIM
A
MIN
NOM
MAX
MIN
NOM
MAX
---
---
1.60
---
---
.063”
A1
0.05
---
0.15
.002”
---
.006”
b
0.17
0.22
0.27
.007”
.009”
.011”
D
22.00 BSC
.866”
D1
20.00 BSC
.787”
E
22.00 BSC
.866”
E1
20.00 BSC
.787”
e
0.50 BSC
.020”
θ
0°
---
7°
0°
---
7°
L
0.45
0.60
0.75
.018”
.024”
.030”
L1
1.00 REF
.039” REF
TOLERANCES OF FORM AND POSITION
ddd
DS651UM23
Version 2.3
0.08
©Copyright 2005 Cirrus Logic, Inc.
.003”
51
CobraNet Hardware User’s Manual
Mechanical Drawings and Schematics
9.4
Temperature Specifications
• Thermal Coefficient (junction-to-ambient): θja - 38° C / Watt
• Ambient Temperature Range: 0-70 deg C
• Junction Temperature Range: 0-125 deg C
52
©Copyright 2005 Cirrus Logic, Inc.
DS651UM23
Version 2.3
CobraNet Hardware User’s Manual
Ordering Information
10.0 Ordering Information
10.1 Device Part Numbers
CS181002-CQ/A1
CS181012-CQ/A1
CS181022-CQ/A1
2x2 Channels
8x8 Channels
16x16 Channels
0°C to +70°C
0°C to +70°C
0°C to +70°C
144-pin LQFP
144-pin LQFP
144-pin LQFP
CS181002-CQZ/A1
CS181012-CQZ/A1
CS181022-CQZ/A1
2x2 Channels
8x8 Channels
16x16 Channels
0°C to +70°C
0°C to +70°C
0°C to +70°C
144-pin LQFP
144-pin LQFP
144-pin LQFP
Lead Free
Lead Free
Lead Free
CS496102-CQZ/A1
CS496112-CQZ/A1
CS496122-CQZ/A1
2x2 Channels + DSP
8x8 Channels + DSP
16x16 Channels + DSP
0°C to +70°C
0°C to +70°C
0°C to +70°C
144-pin LQFP
144-pin LQFP
144-pin LQFP
Lead Free
Lead Free
Lead Free
10.2 Device Part Numbering Scheme
CS1810x 2 — CQZ/A1
Die Revision
Base Part Number
Lead-free Designator:
Z = Lead-free Device Packaging
Channel Count Designator:
0 = 2x2
1 = 8x8
2 = 16x16
(not present if device contains lead)
Package Type:
Q = LQFP (144-pin)
ROM Version
(ROM ID)
Temperature Grade Designator:
C = Commercial (0°C to +70°C)
CS4961x 2 — CQZ/A1
Die Revision
Base Part Number
Lead-free Designator:
Z = Lead-free Device Packaging
Channel Count Designator:
0 = 2x2
1 = 8x8
2 = 16x16
(not present if device contains lead)
Package Type:
Q = LQFP (144-pin)
ROM Version
(ROM ID)
Note:
Temperature Grade Designator:
C = Commercial (0°C to +70°C)
Go to the Cirrus Logic Internet site at http://www.cirrus.com to find contact information for your local sales representative.
Figure 32. Device Part Numbering Explanation
DS651UM23
Version 2.3
©Copyright 2005 Cirrus Logic, Inc.
53
CobraNet Hardware User’s Manual
Ordering Information
Contacting Cirrus Logic Support
For all product questions and inquiries contact a Cirrus Logic Sales Representative.
To find the one nearest to you go to www.cirrus.com
IMPORTANT NOTICE
Cirrus Logic, Inc. and its subsidiaries ("Cirrus") believe that the information contained in this document is accurate and reliable. However, the information
is subject to change without notice and is provided "AS IS" without warranty of any kind (express or implied). Customers are advised to obtain the latest
version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the
terms and conditions of sale supplied at the time of order acknowledgment, including those pertaining to warranty, indemnification, and limitation of liability.
No responsibility is assumed by Cirrus for the use of this information, including use of this information as the basis for manufacture or sale of any items, or
for infringement of patents or other rights of third parties. This document is the property of Cirrus and by furnishing this information, Cirrus grants no license,
express or implied under any patents, mask work rights, copyrights, trademarks, trade secrets or other intellectual property rights. Cirrus owns the copyrights associated with the information contained herein and gives consent for copies to be made of the information only for use within your organization
with respect to Cirrus integrated circuits or other products of Cirrus. This consent does not extend to other copying such as copying for general distribution,
advertising or promotional purposes, or for creating any work for resale.
CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE
PROPERTY OR ENVIRONMENTAL DAMAGE ("CRITICAL APPLICATIONS"). CIRRUS PRODUCTS ARE NOT DESIGNED, AUTHORIZED OR WARRANTED FOR USE IN AIRCRAFT SYSTEMS, MILITARY APPLICATIONS, PRODUCTS SURGICALLY IMPLANTED INTO THE BODY, AUTOMOTIVE
SAFETY OR SECURITY DEVICES, LIFE SUPPORT PRODUCTS OR OTHER CRITICAL APPLICATIONS. INCLUSION OF CIRRUS PRODUCTS IN
SUCH APPLICATIONS IS UNDERSTOOD TO BE FULLY AT THE CUSTOMER'S RISK AND CIRRUS DISCLAIMS AND MAKES NO WARRANTY, EXPRESS, STATUTORY OR IMPLIED, INCLUDING THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR PARTICULAR PURPOSE,
WITH REGARD TO ANY CIRRUS PRODUCT THAT IS USED IN SUCH A MANNER. IF THE CUSTOMER OR CUSTOMER'S CUSTOMER USES OR
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ITS OFFICERS, DIRECTORS, EMPLOYEES, DISTRIBUTORS AND OTHER AGENTS FROM ANY AND ALL LIABILITY, INCLUDING ATTORNEYS'
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Cirrus Logic, Cirrus, and the Cirrus Logic logo designs are trademarks of Cirrus Logic, Inc. All other brand and product names in this document may be
trademarks or service marks of their respective owners.
Motorola is a registered trademark of Motorola, Inc.
Intel is a registered trademark of Intel, Inc.
54
©Copyright 2005 Cirrus Logic, Inc.
DS651UM23
Version 2.3