Fairchild CD4528BC Dual monostable multivibrator Datasheet

Revised August 2000
CD4528BC
Dual Monostable Multivibrator
General Description
Features
The CD4528B is a dual monostable multivibrator. Each
device is retriggerable and resettable. Triggering can occur
from either the rising or falling edge of an input pulse,
resulting in an output pulse over a wide range of widths.
Pulse duration and accuracy are determined by external
timing components Rx and Cx.
■ Wide supply voltage range:
3.0V to 18V
■ Separate reset available
■ Quiescent current = 5.0 nA/package (typ.) at 5.0 VDC
■ Diode protection on all inputs
■ Triggerable from leading or trailing edge pulse
■ Capable of driving two low-power TTL loads or one lowpower Schottky TTL load over the rated temperature
range
Ordering Code:
Order Number
Package Number
Package Description
CD4528BCM
M16A
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow
CD4528BCN
N16E
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Connection Diagram
Truth Table
Inputs
A
B
Q
Q
L
X
X
L
H
X
H
X
L
H
X
X
L
L
H
H
L
↓
H
↑
H
H = HIGH Level
L = LOW Level
↑ = Transition from LOW-to-HIGH
↓ = Transition from HIGH-to-LOW
= One HIGH Level Pulse
= One LOW Level Pulse
X = Irrelevant
Top View
© 2000 Fairchild Semiconductor Corporation
Outputs
Clear
DS005998
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CD4528BC Dual Monostable Multivibrator
October 1987
CD4528BC
Block Diagram
Logic Diagram
(½ of Device Shown)
Note: Externally ground pins 1 and 15 to pin 8.
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2
Recommended Operating
Conditions (Note 2)
(Note 2)
−0.5 VDC to +18 VDC
DC Supply Voltage (VDD)
Input Voltage, All Inputs (VIN)
DC Supply Voltage (VDD)
−0.5 VDC to VDD +0.5 VDC
−65°C to +150°C
Storage Temperature Range (TS)
700 mW
Small Outline
500 mW
Symbol
IDD
VOL
Parameter
Quiescent Device Current
LOW Level Output Voltage
Note 2: VSS = 0V unless otherwise specified.
260°C
DC Electrical Characteristics
(Note 3)
−40°C
Conditions
Min
VIL
VIH
IOL
HIGH Level Output Voltage
LOW Level Input Voltage
HIGH Level Input Voltage
LOW Level Output Current
IIN
+25°C
Min
+85°C
Typ
Max
Min
Max
Units
VDD = 5V
20
0.005
20
150
µA
40
0.010
40
300
µA
VDD = 15V
80
0.015
80
600
µA
VDD = 5V
0.05
0.05
0.05
V
VDD = 10V
0.05
0.05
0.05
V
0.05
V
0.05
0.05
VDD = 5V
4.95
4.95
5.0
4.95
V
VDD = 10V
9.95
9.95
10.0
9.95
V
VDD = 15V
14.95
14.95
15.0
14.95
V
VDD = 5V, VO = 0.5V or 4.5V
1.5
2.25
1.5
1.5
V
VDD = 10V, VO = 1V or 9V
3.0
4.50
3.0
3.0
V
VDD = 15V, VO = 1.5V or 13.5V
4.0
6.75
4.0
4.0
V
VDD = 5V, VO = 0.5V or 4.5V
3.5
3.5
2.75
3.5
V
VDD = 10V, VO = 1V or 9V
7.0
7.0
5.50
7.0
V
VDD = 15V, VO = 1.5V or 13.5V
11.0
11.0
8.25
11.0
V
VDD = 5V, VO = 0.4V
0.52
0.44
0.88
0.36
mA
VDD = 10V, VO = 0.5V
1.3
1.1
2.25
0.9
mA
VDD = 15V, VO = 1.5V
3.6
3.0
8.8
2.4
mA
HIGH Level Output Current
VDD = 5V, VO = 4.6V
−0.2
−0.16
−0.36
−0.12
mA
(Note 4)
VDD = 10V, VO = 9.5V
−0.5
−0.4
−0.9
−0.3
mA
VDD = 15V, VO = 13.5V
−1.4
(Note 4)
IOH
Max
VDD = 10V
VDD = 15V
VOH
−40°C to +85°C
Note 1: “Absolute Maximum Ratings” are those values beyond which the
safety of the device cannot be guaranteed. Except for “Operating Temperature Range”, they are not meant to imply that the devices should be operated at these limits. The table of “Electrical Characteristics” provides
conditions for actual device operation.
Lead Temperature (TL)
(Soldering, 10 seconds)
0V to VDD VDC
Operating Temperature Range (TA)
Power Dissipation (PD)
Dual-In-Line
3V to 15V
Input Voltage (VIN)
Input Current
−1.2
−3.5
−1.0
mA
VDD = 15V, VIN = 0V
−0.3
−10−5
−0.3
−1.0
µA
VDD = 15V, VIN = 15V
0.3
10−5
0.3
1.0
µA
Note 3: VSS = 0V unless otherwise specified.
Note 4: IOH and IOL are tested one output at a time.
3
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CD4528BC
Absolute Maximum Ratings(Note 1)
CD4528BC
AC Electrical Characteristics (Note 5)
TA = 25°C, CL = 50 pF, RL = 200 kΩ, Input tr = tf = 20 ns, unless otherwise specified
Symbol
tr
tf
Parameter
Output Rise Time
Output Fall Time
Typ
Max
tr = (3.0 ns/pF) CL + 30 ns, VDD = 5.0V
Conditions
Min
180
400
Units
ns
tr = (1.5 ns/pF) CL + 15 ns, VDD = 10.0V
90
200
ns
ns
tr = (1.1 ns/pF) CL + 10 ns, VDD = 15.0V
65
160
tf = (1.5 ns/pF) CL + 25 ns, VDD = 5.0V
100
200
ns
tf = (0.75 ns/pF) CL + 12.5 ns, VDD = 10V
50
100
ns
tf = (0.55 ns/pF) CL + 9.5 ns, VDD = 15.0V
35
80
ns
tPLH
Turn-Off, Turn-On Delay
tPLH, tPHL = (1.7 ns/pF) CL + 240 ns, VDD = 5.0V
230
500
ns
tPHL
A or B to Q or Q
tPLH, tPHL = (0.66 ns/pF) CL + 8 ns, VDD = 10.0V
100
250
ns
Cx = 15 pF, Rx = 5.0 kΩ
tPLH, tPHL = (0.5 ns/pF) CL + 65 ns, VDD = 15.0V
65
150
ns
Turn-Off, Turn-On Delay
tPLH, tPHL = (1.7 ns/pF) CL + 620 ns, VDD = 5.0V
230
500
ns
A or B to Q or Q
tPLH, tPHL = (0.66 ns/pF) CL + 257 ns, VDD = 10.0V
100
250
ns
Cx = 100 pF, Rx = 10 kΩ
tPLH, tPHL = (0.5 ns/pF) CL + 185 ns, VDD = 15.0V
65
150
ns
tWL
Minimum Input Pulse Width
VDD = 5.0V
60
150
ns
tWH
A or B
VDD = 10.0V
20
50
ns
Cx = 15 pF, Rx = 5.0 kΩ
VDD = 15V
20
50
ns
Cx = 1000 pF, Rx = 10 kΩ
VDD = 5.0V
60
150
ns
VDD = 10.0V
20
50
ns
VDD = 15.0V
20
50
ns
VDD = 5.0V
550
ns
VDD = 10.0V
350
ns
PWOUT
Output Pulse Width Q or Q
For Cx < 0.01 µF (See Graph
for Appropriate VDD Level)
Cx = 15 pF, Rx = 5.0 kΩ
VDD = 15.0V
For Cx > 0.01 µF Use
VDD = 5.0V
15
29
45
µs
PWout = 0.2 Rx Cx In [VDD − VSS]
VDD = 10.0V
10
37
90
µs
Cx = 10,000 pF, Rx = 10 kΩ
VDD = 15.0V
15
42
95
µs
tPLH
Reset Propagation Delay,
VDD = 5.0V
325
600
ns
tPHL
tPLH, tPHL
VDD = 10.0V
90
225
ns
Cx = 15 pF, Rx = 5.0 kΩ
VDD = 15.0V
60
170
Cx = 1000 pF, Rx = 10 kΩ
VDD = 5.0V
7.0
µs
VDD = 10.0V
6.7
µs
VDD = 15.0V
6.7
µs
Minimum Retrigger Time
VDD = 5.0V
0
ns
Cx = 15 pF, Rx = 5.0 kΩ
VDD = 10.0V
0
ns
VDD = 15.0V
0
ns
VDD = 5.0V
0
ns
VDD = 10.0V
0
ns
VDD = 15.0V
0
Pulse Width Match between Circuits
VDD = 5.0V
6
25
%
in the Same Package
VDD = 10.0V
8
35
%
Cx = 10,000 pF, Rx = 10 kΩ
VDD = 15.0V
8
35
%
tRR
Cx = 1000 pF, Rx = 10 kΩ
300
Note 5: AC parameters are guaranteed by DC correlated testing.
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4
ns
ns
ns
CD4528BC
Pulse Widths
FIGURE 1. Pulse Width vs Cx
FIGURE 2. Normalized Pulse Width vs Temperature
5
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CD4528BC
AC Test Circuits and Waveforms
Duty Cycle = 50%
FIGURE 3. Power Dissipation Test Circuit and Waveforms
*Includes capacitance of probes, wiring, and fixture parasitic.
Note: AC test waveforms for PG1, PG2, and PG3 in Figure 4.
Input Connections
Characteristics
tPLH, tPHL, tr, tf,
CD
A
B
VDD
PG1
VDD
VDD
VSS
PG2
PG3
PG1
PG2
PWout, PWin
tPLH, tPHL, tr, tf,
PWout, PWin
tPLH(R), tPHL(R), PWin
FIGURE 4. AC Test Circuit
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6
CD4528BC
AC Test Circuits and Waveforms
(Continued)
FIGURE 5. AC Test Waveforms
7
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CD4528BC
Physical Dimensions inches (millimeters) unless otherwise noted
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow
Package Number M16A
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8
CD4528BC Dual Monostable Multivibrator
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Package Number N16E
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
2. A critical component in any component of a life support
device or system whose failure to perform can be reasonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the
user.
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