LSI/CSI UL ® LS7215 LS7216 LSI Computer Systems, Inc. 1235 Walt Whitman Road, Melville, NY 11747 (631) 271-0400 FAX (631) 271-0405 A3800 PROGRAMMABLE DIGITAL DELAY TIMER A 0 0 1 1 B 0 1 0 1 MODE One-Shot (OS) Delayed Operate (DO) Delayed Release (DR) Dual Delay (DD) Each input has an internal pull-up resistor of about 500kΩ. One-Shot Mode (OS) A positive transition at the TRIG input causes OUT to switch low without delay and starts the delay timer. At the end of the programmed delay timeout, OUT switches high. If a delay timeout is in progress when a positive transition occurs at the TRIG input, the delay timer will be restarted. A negative transition at the TRIG input has no effect. Delayed Operate Mode (DO) A positive transition at the TRIG input starts the delay timer. At the end of the delay timeout, OUT switches low. A negative transition at the TRIG input causes OUT to switch high without delay. OUT is high when TRIG is low. 7215-072009-1 B 2 19 TRIG V DD (+V) 3 18 WB0 RC/CLOCK 4 17 WB1 RCS/CLKS 5 16 WB2 PSCLS 6 15 WB3 RESET 7 14 WB4 V SS (-V) 8 13 WB5 OUT 9 12 WB6 11 WB7 20 LOAD OD OUT 10 A 1 LOAD B 2 19 TRIG V DD (+V) 3 18 WB0 XTLI/CLOCK 4 17 WB1 XTLO 5 16 WB2 PSCLS 6 15 WB3 RESET 7 14 WB4 V SS (-V) 8 13 WB5 OUT 9 12 WB6 11 WB7 LS7216 TABLE 1. MODE SELECTION 1 LS7215 I/O DESCRIPTION: MODE SELECT Inputs A & B (Pins 1 & 2) The 4 operating modes are selected by Inputs A and B according to Table 1 20 A LSI DESCRIPTION: The LS7215 and LS7216 are CMOS integrated circuits for generating digitally programmable delays. The delay is controlled by 8 binary weighted inputs, WB0 - WB7, in conjunction with an applied clock or oscillator frequency. The programmed time delay manifests itself in the Delay Output (OUT) as a function of the Operating Mode selected by the Mode Select inputs A and B: One-Shot, Delayed Operate, Delayed Release or Dual Delay. The time delay is initiated by a transition at the Trigger Input (TRIG). PIN ASSIGNMENT - TOP VIEW LSI FEATURES: • Programmable delay from microseconds to days • Programmable delay controlled by 8 binary-weighted delay inputs that can be latched from a shared 8-bit bus • On chip oscillator (RC or Crystal) or external clock time base • Selectable prescaler for real time delay generation based on 50Hz/60Hz time base or 32,768Hz watch crystal • Four operating modes • Reset input for delay abort • Low quiescent and operating current • Direct relay drive • +3V to +18V operation (VDD - VSS) • LS7215, LS7216 (DIP); LS7215-S, LS7216-S (SOIC) - See Figure 1 - July 2009 OD OUT 10 FIGURE 1 Delayed Release Mode (DR) A negative transition at the TRIG input starts the delay timer. At the end of the delay timeout, OUT switches high. A postive transition at the TRIG input causes OUT to switch low without delay. OUT is low when TRIG is high. Dual Delay Mode (DD) A positive or negative transition at the TRIG input starts the delay timer. At the end of the delay timeout, OUT switches to the logic state which is the inverse of the TRIG input. If a delay timeout is in progress when a transition occurs at the TRIG input, the delay timer is restarted. TRIGGER Input (TRIG, Pin 14) A transition at the TRIG input causes OUT to switch with or without delay, depending on the selected mode. The TRIG input to OUT transition relation is always opposite in polarity, with the exception of One-Shot mode. (See Mode definitions above.) TRIG input has an internal pulldown resistor of about 500kΩ and is buffered by a Schmitt trigger to provide input hysteresis. LS7215 TIME BASE Input (RC/CLOCK, Pin 4) For LS7215, the basic timing signal is applied at the RC/CLOCK input. The clock can be provided from either an external source or generated by an internal oscillator by connecting an R-C network to this input. The frequency of oscillation is given by ƒ 1/RC . Chip-to-chip oscillation tolerance is ± 5% for a fixed value of RC. The minimum resistance, R MIN = 4,000Ω, VDD = + 3V = 1,200Ω, VDD = +10V = 1,000Ω, VDD = +18V The external clock mode is selected by applying a logic low to the RCS/ CLKS input (Pin 5); the internal oscillator mode is selected by applying a high level to the RCS/CLKS input. VSS (-V, Pin 8) Supply voltage negative terminal or GND. DELAY Output (OUT, Pin 9) Except in One-Shot mode, OUT switches with or without delay (depending on mode) in inverse relation to the logic level of the TRIG input. In One-Shot mode, a timed low level is produced at OUT, in response to a positive transition of the TRIG input. LOAD Input (LOAD, Pin 20) The LOAD input allows the weighting bits, WB0 - WB7, to be latched from a shared bus, such as a MCU IO port. When the LOAD is low, the internal weighting bits dynamically follow the data presented at the WB0 - WB7 inputs. When the LOAD is switched high, the WB0 - WB7 data become latched, freeing up the bus to service other peripheral devices. LOAD input has an internal pull-down resistor to VSS. OPEN DRAIN DELAY Output (ODOUT, Pin 10) The ODOUT is the open drain version of the delay output which enables the chip to directly drive a relay, operating at a voltage higher than the chip supply voltage through a single NPN transistor (see FigLS7216 TIME BASE Input (XTLI/CLOCK, Pin 4) ure 10) . Functionally, the ODOUT is identical to the other delay outFor LS7216, the basic timing clock is applied to the XLTI/CLOCK input put, OUT. from either an external clock source or generated by an internal crystal oscillator by connecting a crystal between XTLI/CLOCK input and the WEIGHTING BIT Inputs (WB7 to WB0, Pins 11 - 18) XTLO output (Pin 5). Inputs WB0 through WB7 are binary weighted delay bits used to program the delay according to the following relations: LS7215 TIME BASE SELECT Input (RCS/CLKS, Pin 5) For LS7215, the external clock operation at Pin 4 is selected by ap- One-Shot Mode: Pulse width = SW plying a logic low to the RCS/CLKS input. The internal oscillator option ƒ with RC timer at Pin 4 is selected by applying a logic high at the RCS/ CLKS input. RCS/CLKS input has an internal pull-down resistor of about All other Modes: Delay = SW + 0.5 500kΩ. ƒ Where: LS7216 TIME BASE Output (XTLO, Pin 5) S = Prescale factor (See Table 2) For LS7216, when a crystal is used for generating the time base oscilla- ƒ = Time base frequency at Pin 4 tion, the crystal is connected between XTLI/CLOCK and XTLO pins. W = WB0 + WB1 + ....... WB7 PRESCALER SELECT Input (PSCLS, Pin 6) The weighting factor, W, is calculated by substituting in the equation The PSCLS input is a 3-state input, which selects one of three prescale above for W, the weighted values for all the WB inputs that are at logic high. The weighted values for the WB inputs are shown in Table 3. factors according to Table 2. Each WB input has an internal pull-down resistor of about 500kΩ. TABLE 2. PRESCALE FACTOR SELECTION TABLE 3. BIT WEIGHTS PSCLS Input S (Prescale Factor) BITS VALUE Logic Level LS7215 LS7216 WB0 1 Float 1 1 WB1 2 VSS 3000 32768 WB2 4 VDD 3600 32768 x 60 WB3 8 WB4 16 Using prescale factors of 3000 and 3600, delays in units of minutes can WB5 32 be produced from 50Hz and 60Hz line sources. Prescale factors of WB6 64 32,768 and 32,768 x 60 can be used to generate accurate delays in WB7 128 units of seconds and minutes, respectively, from a 32kHz watch crystal. TIMER RESET Input (RESET, Pin 7) When RESET input switches high, any timeout in progress is aborted VDD (+V, Pin 3) and OUT switches high without delay. With RESET high, OUT remains Supply voltage positive terminal. high. When RESET switches low with TRIG low in any mode, OUT remains high. When RESET switches low with TRIG high in Delayed Operate and Dual Delay modes, the delay timer is started and OUT switches low at the end of the delay timeout. When RESET switches low with The information included herein is believed to be acTRIG high in Delayed Release mode, OUT switches low without delay. curate and reliable. LSI Computer Systems, Inc. asWhen RESET switches low with TRIG high in One-Shot mode, OUT resumes no responsibilities for inaccuracies, nor for any mains high. RESET input has an internal pull-down resistor of about infringements of patent rights of others which may re500kΩ and is buffered by a Schmitt Trigger to provide input hysteresis. sult from its use. 7215-072009-2 ABSOLUTE MAXIMUM RATINGS: (All voltages referenced to VSS) SYMBOL VALUE DC Supply Voltage VDD +19 Voltage (Any Pin) VIN VSS - 0.3 to VDD + 0.3 Operating Temperature TA -20 to +85 Storage Temperature TSTG -65 to +150 UNIT V V °C °C ELECTRICAL CHARACTERISTICS (Voltages referenced to Vss) Characteristic SYMBOL Supply Voltage VDD Supply Current IDD Input Voltages: Reset, Trigger Low VTL Reset, Trigger High VTH Reset, Trigger Hysteresis All other inputs, Low VIL All other inputs, High VIH Input Currents: PSCLS Low IPL PSCLS High IPH A, B Low IML A, B High All other inputs, Low IMH IIL All other inputs, High IIH Output Current: OUT, ODOUT Sink IOSNK OUT Source IOSRC ODOUT Source 7215-062409-3 3.0 10.0 18.0 Min 3.0 - -20°C Max 18.0 66 252 540 Min 3.0 - +25°C Max 18.0 55 210 450 Min 3.0 - +85°C Max 18.0 44 168 360 3.0 10.0 18.0 3.0 10.0 18.0 3.0 10.0 18.0 3.0 10.0 18.0 3.0 10.0 18.0 2.2 6.1 9.7 0.7 2.2 3.9 1.9 6.5 13.3 0.8 2.3 3.9 1.1 4.5 10.6 - 2.1 6.0 10.5 0.7 2.2 3.9 1.9 6.5 13.3 0.75 2.2 3.8 1.1 4.5 10.6 - 2.0 5.9 11.0 0.7 2.2 3.9 1.9 6.5 13.3 0.7 2.1 3.7 1.1 4.5 10.6 - V V V V V V V V V V V V V V V 3.0 10.0 18.0 3.0 10.0 18.0 3.0 10.0 18.0 3.0 10.0 18.0 - 3.2 31 84 9.8 31 85 6.0 59 157 100 100 33 128 131 - 2.5 24 65 7.5 24 65 5.0 48 128 100 100 27 105 107 - 1.9 18 49 5.8 18.2 49 4.0 38 98 200 200 23 81 82 µA µA µA µA µA µA µA µA µA nA nA µA µA µA 3.0 10.0 18.0 3.0 10.0 18.0 - 13.2 26 30.7 4.1 7.2 8.2 0 - 10.1 19.7 23.6 3.2 5.5 6.3 0 - 7 15 17 2.1 4.1 4.6 0 - mA mA mA mA mA mA mA VDD Unit V µA µA µA Condition with the clock off and all inputs floating. - Input at VSS Input at VDD Input at VSS Input at VDD Input at VSS Input at VDD Vo = +0.5V Vo = VDD - 0.5V In all conditions ELECTRICAL CHARACTERISTICS (Voltages referenced to Vss) (Con’t) Characteristic SYMBOL Switching Characteristics (See Fig. 3) RC Oscillator Frequency fosc External Clock or Crystal Oscillator Frequency fext fext TRIG Set-Up Time A, B Set-Up Time t1 t2 Clock to Out Delay t4 VDD 3.0 10.0 18.0 3.0 10.0 18.0 3.0 10.0 18.0 3.0 10.0 18.0 Unit Min Max Min Max Min Max - 1.8 4.5 8.0 2.6 5.3 5.9 7.2 16.0 15.9 - 1.4 3.4 4.0 2.0 4.0 4.6 5.5 12.8 12 - 1.05 2.6 3.0 1.52 3.0 3.5 4.2 9.7 9.1 MHz MHz MHz MHz MHz MHz MHz MHz MHz 38 0 - 284 98 87 50 0 - 375 130 115 66 0 - 495 172 152 ns ns ns ns ns - Condition For prescale factor S = 1 or 3000 or 3600 S = 32768 or 32768 x 60 CL = 50pF 10 ODOUT +V 500k A 1 MODE REG +V CONTROL LOGIC BUF 9 OUT 500k B 2 8 11-18 EDGE DETECT LATCH TRIG 19 8 500k 500k RESET 7 CLOCK CLOCK/RC/XTLI 4 OSC 8 LATCH/TIMER LATCH MUX PRESCALER XTLO (LS7216) 5 RCS/CLKS (LS7215) (8) 500k 8 20 LOAD 5 500k +V 1M PSCLS 3-STATE DECODER 6 1M 7215-062309-4 WB7-WB0 +V 3 VDD -V 8 VSS t0 Clock t1 TRIG t2 Delayed Operate Mode A, B WB0-WB7 WB0-WB7 (Internal) Data Latched LOAD t4 OUT Programmed Delay Immediate Release Note 1. TRIG input is clocked in by the negative edge of external clock. Note 2. Inputs A, B are sampled only at a TRIG input transition and ignored at all other times. Note 3. OUT is switched by the positive edge of the external clock. FIGURE 3. INPUT/OUTPUT TIMING TRIG F RESET OUT(OS) C OUT(DO) OUT(DR) D OUT(DD) G A B H E A. Turn-on delay in DO and DD modes; Pulse-width in OS mode. B. Turn-off delay in DR and DD modes. C. Pulse-width extended by re-trigger in OS mode. No effect in DO and DD modes because TRIG switches back low before turn-on delay has timed out. D. Turn-off delay in DR mode. E. Turn-on delay in DO and DD modes; pulse-width in OS mode. F. No effect in DO, DR and DD modes because of TRIG’s switching back to opposite levels. G. Time-outs aborted and OUT forces high by RESET. H. After the removal of RESET, OUT switches to the inverse polarity of TRIG immediately (DR) or after the timeout (DO, DD). No effect in OS. FIGURE 4. MODE ILLUSTRATION WITH TRIG, OUT AND RESET 7215-040307-5 +V 470k 3 25pF V DD +V 5 10k ƒ 4 5 CRYSTAL XTLO 4 RCS/CLKS LS7215 LS7216 10M 4 XTLI 25pF 4 RC 0.1µF CLOCK CLOCK LS7216 LS7215 FIGURE 6. MULTI-TIMER WITH SINGLE CRYSTAL TIME-BASE +V V SS 8 ƒ= 1 10 x 10 3 x 0.1 x 10 -6 3 V DD = 1kHz LS7215 1M 4 120VAC CLOCK 200pF V SS FIGURE 5. RC- Oscillator Connection 8 FIGURE 7. DRIVING CLOCK INPUT FROM THE AC LINE +V 20 WB LOAD * * 8 11-18 2 1, 2 3 LOAD 3 V DD WB LOAD * * WB0-WB7 A, B LS7215 19 TRIGGER 4 ƒ TRIG OUT 20 8 11-18 2 1, 2 WB0-WB7 A, B LS7215 9 CLOCK 19 4 TRIG 8 Connect for desired delay and mode FIGURE 8. DELAY EXTENSION BY CASCADING 7215-062309-6 OUT CLOCK V SS * VDD LOAD V SS 8 9 OUT 1 2 TRIGGER IN 19 4 25pF ƒ 25pF 470k A V DD B WB0 TRIG WB1 XTLI 3 WB2 WB3 10M 5 +V S1 +V 6 WB4 XTLO WB5 WB6 PSCLS WB7 7 +V 8 9 OUTPUT 18 1s/1m 17 2s/2m 16 4s/4m 15 8s/8m 14 16s/16m 13 32s/32m 12 64s/64m 11 128s/128m LS7216 s = seconds m = minutes RESET Vss OUT NOTE : Crystal Frequency, ƒ = 32,768Hz Switch: S1 low: Delay increment = 1s; Maximum Delay = 255s S1 high: Delay increment = 1m; Maximum Delay = 255m FIGURE 9. PROGRAMMABLE ACCURATE REAL-TIME DELAY GENERATION +9V +3V 3 +3V VDD 11-18 IO IO 20 ODOUT LOAD 11-18 10 V SS +18V 8 +3V VSS 3 V DD WB0-WB7 +3V LS7215/16 20 ODOUT LOAD V SS 8 FIGURE 10. LATCHING WEIGHTING BITS FROM A MCU (Example showing separate relay and logic supplies) 7215-072009-7 +3V LS7215/16 8 IO MCU VDD WB0-WB7 10 +V 3 1 2 V DD A B WB0 WB1 4 ƒi +V 7 19 9 ƒo WB2 CLOCK WB3 LS7216 WB4 RESET WB5 TRIG WB6 WB7 OUT 18 17 16 15 14 13 12 11 Vss 8 CASE 1. MODE = DO or DR; PRESCALE FACTOR, S = 1 In this setup a frequency division of the input clock, ƒi by a factor of 2 to 257, in increments of 1 can be obtained according to the equation: ƒo = ƒi W+2 where W (weighting factor) = 0 to 255 The ƒo pulse width is non-symmetrical (non-50% duty -cycle) CASE 2. MODE = DD; PRESCALE FACTOR, S = 1 In this setup a frequency division of the input clock, ƒi by a factor of 2 to 512, in increments of 2 can be obtained according to the equation: ƒi ƒo = 2 (W + 1) where W (weighting factor) = 0 to 255 The ƒo pulse widths are symmetrical with 50% duty -cycle EXAMPLES OF CASE 1 and CASE 2 FREQUENCY DIVISIONS WITH W = 2 ƒi ƒo Case 1, Mode = DO; ÷4 ƒo Case 2, Mode = DD; ÷6 FIGURE 11. PROGRAMMABLE FREQUENCY DIVIDER 7215-081806-8