Freescale MC68HC705E5 General release specification Datasheet

Freescale Semiconductor, Inc.
General Release Specification
February 3, 1997
CSIC MCU Design Center
Austin, Texas
For More Information On This Product,
Go to: www.freescale.com
A G R E E M E N T
MC68HC705E5
N O N - D I S C L O S U R E
Freescale Semiconductor, Inc...
R E Q U I R E D
HC705E5GRS/D
REV. 1.0
Freescale Semiconductor, Inc.
Freescale Semiconductor, Inc...
A G R E E M E N T
R E Q U I R E D
General Release Specifiation
N O N - D I S C L O S U R E
Motorola reserves the right to make changes without further notice to
any products herein to improve reliability, function or design. Motorola
does not assume any liability arising out of the application or use of any
product or circuit described herein; neither does it convey any license
under its patent rights nor the rights of others. Motorola products are not
designed, intended, or authorized for use as components in systems
intended for surgical implant into the body, or other applications intended
to support or sustain life, or for any other application in which the failure
of the Motorola product could create a situation where personal injury or
death may occur. Should Buyer purchase or use Motorola products for
any such unintended or unauthorized application, Buyer shall indemnify
and hold Motorola and its officers, employees, subsidiaries, affiliates,
and distributors harmless against all claims, costs, damages, and
expenses, and reasonable attorney fees arising out of, directly or
indirectly, any claim of personal injury or death associated with such
unintended or unauthorized use, even if such claim alleges that Motorola
was negligent regarding the design or manufacture of the part.
 Motorola, Inc., 1997
MC68HC705E5 — Rev. 1.0
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List of Sections
Section 1. General Description . . . . . . . . . . . . . . . . . . . 17
Freescale Semiconductor, Inc...
Section 2. Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Section 3. Central Processing Unit (CPU) . . . . . . . . . . . 29
Section 4. Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Section 5. Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Section 6. Operating Modes . . . . . . . . . . . . . . . . . . . . . 47
Section 7. Input/Output (I/O) Ports . . . . . . . . . . . . . . . . 51
Section 8. Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
A G R E E M E N T
General Release Specification — MC68HC705E5
R E Q U I R E D
Freescale Semiconductor, Inc.
Section 10.Computer Operating
Properly (COP) Watchdog . . . . . . . . . . . 67
Section 11. Motorola Bus (M Bus) Interface . . . . . . . . . 71
Section 12. Synchronous Serial Interface (SSI) . . . . . . 95
Section 13. User EPROM . . . . . . . . . . . . . . . . . . . . . . . . 107
Section 14. Instruction Set . . . . . . . . . . . . . . . . . . . . . . 115
Section 15. Electrical Specifications . . . . . . . . . . . . . . 133
Section 16. Mechanical Data . . . . . . . . . . . . . . . . . . . 143
Section 17. Ordering Information . . . . . . . . . . . . . . . . 145
MC68HC705E5 — Rev. 1.0
General Release Specification
List of Sections
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N O N D I S C L O S U R E
Section 9. Phase-Locked Loop (PLL) Synthesis . . . . . . 61
Freescale Semiconductor, Inc.
N O N D I S C L O S U R E
A G R E E M E N T
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R E Q U I R E D
List of Sections
General Release Specification
MC68HC705E5 — Rev. 1.0
List of Sections
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Section 1. General Description
Freescale Semiconductor, Inc...
1.1
1.2
1.3
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
1.4
Mask Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
1.5
Functional Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
1.5.1
VDD and VSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
1.5.2
IRQ /VPP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
1.5.3
OSC1 and OSC2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
1.5.4
RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
1.5.5
PA0–PA7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
1.5.6
PB0–PB7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
1.5.7
PC0–PC3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
1.5.8
XFC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
1.5.9
VDDSYN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
Section 2. Memory
2.1
2.2
2.3
2.4
2.5
2.6
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
EPROM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
Memory Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
MC68HC705E5 — Rev. 1.0
General Release Specification
Table of Contents
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A G R E E M E N T
Table of Contents
N O N D I S C L O S U R E
General Release Specification — MC68HC705E5
R E Q U I R E D
Freescale Semiconductor, Inc.
Freescale Semiconductor, Inc.
N O N D I S C L O S U R E
A G R E E M E N T
Freescale Semiconductor, Inc...
R E Q U I R E D
Table of Contents
Section 3. Central Processing Unit (CPU)
3.1
3.2
3.3
3.4
3.5
3.6
3.7
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
Accumulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
Index Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
Condition Code Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
Stack Pointer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32
Program Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32
Section 4. Interrupts
4.1
4.2
4.3
4.4
4.5
4.6
4.7
4.8
4.9
4.10
4.11
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
Hardware Controlled Interrupt Sequence . . . . . . . . . . . . . . . . .35
Software Interrupt (SWI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35
External Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36
Timer Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36
Custom Periodic Interrupt (CPI) . . . . . . . . . . . . . . . . . . . . . . . .39
Synchronous Serial Interface Interrupt (SSI) . . . . . . . . . . . . . .40
M-Bus (I2C) Interrupt (M Bus) . . . . . . . . . . . . . . . . . . . . . . . . .40
Operation During Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . .40
Operation During Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . .40
Section 5. Resets
5.1
5.2
5.3
5.4
5.5
5.6
5.6.1
5.6.2
5.6.3
5.6.4
5.7
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41
External Reset (RESET). . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42
Internal Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44
Power-On Reset (POR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44
Computer Operating Properly Reset (COPR). . . . . . . . . . . . . .45
Resetting the COP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45
COP During Wait Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . .45
COP During Stop Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . .45
COP Watchdog Timer Considerations . . . . . . . . . . . . . . . .46
Illegal Address Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46
General Release Specification
MC68HC705E5 — Rev. 1.0
Table of Contents
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Freescale Semiconductor, Inc.
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47
Single-Chip Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48
Self-Check Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48
Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48
Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48
Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49
Data-Retention Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49
Section 7. Input/Output (I/O) Ports
7.1
7.2
7.3
7.4
7.5
7.6
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51
Port A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51
Port B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52
Port C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52
Input/Output Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . .52
Section 8. Timer
8.1
8.2
8.3
8.4
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55
Timer Control and Status Register . . . . . . . . . . . . . . . . . . . . . .57
Timer Counter Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59
Section 9. Phase-Locked Loop (PLL) Synthesis
9.1
9.2
9.3
9.4
9.5
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61
Phase-Locked Loop Control Register. . . . . . . . . . . . . . . . . . . .63
Operation During Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . .65
Noise Immunity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65
MC68HC705E5 — Rev. 1.0
General Release Specification
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A G R E E M E N T
Freescale Semiconductor, Inc...
6.1
6.2
6.3
6.4
6.5
6.5.1
6.5.2
6.5.3
N O N D I S C L O S U R E
Section 6. Operating Modes
R E Q U I R E D
Table of Contents
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N O N D I S C L O S U R E
A G R E E M E N T
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R E Q U I R E D
Table of Contents
Section 10. Computer Operating
Properly (COP) Watchdog
10.1
10.2
10.3
10.4
10.5
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67
System Control and Status Register. . . . . . . . . . . . . . . . . . . . .68
COP During Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .70
COP During Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .70
Section 11. Motorola Bus (M Bus) Interface
11.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71
11.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72
11.3 M-Bus Interface Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73
11.4 M-Bus System Configuration . . . . . . . . . . . . . . . . . . . . . . . . . .73
11.5 M-Bus Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73
11.5.1
Start Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .74
11.5.2
Slave Address Transmission. . . . . . . . . . . . . . . . . . . . . . . .75
11.5.3
Data Transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .75
11.5.4
Repeated Start Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . .76
11.5.5
Stop Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .76
11.5.6
Arbitration Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . .76
11.5.7
Clock Synchronization. . . . . . . . . . . . . . . . . . . . . . . . . . . . .77
11.5.8
Handshaking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .77
11.6 M-Bus Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .78
11.6.1
M-Bus Address Register . . . . . . . . . . . . . . . . . . . . . . . . . . .78
11.6.2
M-Bus Frequency Divider Register . . . . . . . . . . . . . . . . . . .80
11.6.3
M-Bus Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . .82
11.6.4
M-Bus Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . .84
11.6.5
M-Bus Data I/O Register . . . . . . . . . . . . . . . . . . . . . . . . . . .86
11.7 M-Bus Pin Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .88
11.8 Programming Considerations . . . . . . . . . . . . . . . . . . . . . . . . . .88
11.8.1
Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .88
11.8.2
Generation of a Start Signal and the First Byte
of Data Transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .89
11.8.3
Software Responses after Transmission
or Reception of a Byte . . . . . . . . . . . . . . . . . . . . . . . . . .90
11.8.4
Generation of the Stop Signal . . . . . . . . . . . . . . . . . . . . . . .91
General Release Specification
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Section 12. Synchronous Serial Interface (SSI)
Freescale Semiconductor, Inc...
12.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .95
12.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .96
12.3 SSI Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .98
12.3.1
Serial Clock (SCK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .98
12.3.2
Serial Data Input/Output (SDIO) . . . . . . . . . . . . . . . . . . . . .98
12.4 SSI Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .100
12.4.1
SSI Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . .100
12.4.2
SSI Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .103
12.4.3
SSI Data Register (SDR). . . . . . . . . . . . . . . . . . . . . . . . . .104
12.5 SSI During Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .104
12.6 SSI During Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .105
12.7 SSI Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .105
A G R E E M E N T
11.8.5
Generation of a Repeated Start Signal . . . . . . . . . . . . . . . .92
11.8.6
Slave Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .92
11.8.7
Arbitration Lost . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .92
11.9 Operation During Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . .93
11.10 Operation During Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . .93
R E Q U I R E D
Table of Contents
13.1
13.2
13.3
13.4
13.5
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .107
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .107
Bootloader Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .107
Programming Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .112
Mask Option Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .113
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N O N D I S C L O S U R E
Section 13. User EPROM
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N O N D I S C L O S U R E
A G R E E M E N T
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R E Q U I R E D
Table of Contents
Section 14. Instruction Set
14.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .115
14.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .116
14.3 Addressing Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .116
14.3.1
Inherent . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .117
14.3.2
Immediate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .117
14.3.3
Direct . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .117
14.3.4
Extended . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .117
14.3.5
Indexed, No Offset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .118
14.3.6
Indexed, 8-Bit Offset . . . . . . . . . . . . . . . . . . . . . . . . . . . . .118
14.3.7
Indexed,16-Bit Offset. . . . . . . . . . . . . . . . . . . . . . . . . . . . .118
14.3.8
Relative . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .119
14.4 Instruction Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .119
14.4.1
Register/Memory Instructions . . . . . . . . . . . . . . . . . . . . . .120
14.4.2
Read-Modify-Write Instructions . . . . . . . . . . . . . . . . . . . . .121
14.4.3
Jump/Branch Instructions . . . . . . . . . . . . . . . . . . . . . . . . .122
14.4.4
Bit Manipulation Instructions . . . . . . . . . . . . . . . . . . . . . . .124
14.4.5
Control Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .125
14.5 Instruction Set Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . .126
Section 15. Electrical Specifications
15.1
15.2
15.3
15.4
15.5
15.6
15.7
15.8
15.9
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .133
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .133
Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .134
Operating Temperature Range. . . . . . . . . . . . . . . . . . . . . . . .135
Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . .135
DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . .136
Control Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .138
M-Bus Interface Input Signal Timing. . . . . . . . . . . . . . . . . . . .140
M-Bus Interface Output Signal Timing . . . . . . . . . . . . . . . . . .140
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16.1
16.2
16.3
16.4
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .143
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .143
28-Pin Plastic Dual-in-Line Package
(Case 710-02) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .143
28-Pin Small Outline Integrated Circuit Package
(Case 751F-04) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .144
Freescale Semiconductor, Inc...
Section 17. Ordering Information
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .145
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .145
MC Order Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .145
N O N D I S C L O S U R E
17.1
17.2
17.3
A G R E E M E N T
Section 16. Mechanical Data
R E Q U I R E D
Table of Contents
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A G R E E M E N T
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Figure
Title
Page
1-1
1-2
1-3
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
Single-Chip Mode Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . .20
Oscillator Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
2-1
2-2
Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
I/O Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
3-1
3-2
3-3
3-4
3-5
3-6
3-7
Programming Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
Stacking Order . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
Accumulator (A) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
Index Register (X) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
Condition Code Register (CCR) . . . . . . . . . . . . . . . . . . . . . .31
Stack Pointer (SP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32
Program Counter (PC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32
4-1
4-2
4-3
Interrupt Processing Flowchart. . . . . . . . . . . . . . . . . . . . . . .37
STOP/WAIT Flowcharts . . . . . . . . . . . . . . . . . . . . . . . . . . . .38
Custom Periodic Interrupt Control
and Status Register (CPICSR) . . . . . . . . . . . . . . . . . . . .39
5-1
5-2
Reset Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42
RESET and POR Timing Diagram . . . . . . . . . . . . . . . . . . . .43
7-1
Port I/O Circuitry. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53
8-1
8-2
8-3
Timer Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56
Timer Control and Status Register (TCSR) . . . . . . . . . . . . .57
Timer Counter Register (TCR) . . . . . . . . . . . . . . . . . . . . . . .59
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List of Figures
N O N D I S C L O S U R E
General Release Specification — MC68HC705E5
R E Q U I R E D
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Freescale Semiconductor, Inc.
N O N D I S C L O S U R E
A G R E E M E N T
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R E Q U I R E D
List of Figures
Figure
Title
Page
9-1
9-2
PLL Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62
Phase-Locked Loop Control Register (PLLCR) . . . . . . . . . .63
10-1
System Control and Status Register (SCSR) . . . . . . . . . . . .68
11-1
11-2
11-3
11-4
11-5
11-6
11-7
11-8
11-9
M-Bus Transmission Signal Diagram . . . . . . . . . . . . . . . . . .74
Clock Synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . .77
M-Bus Address Register (MADR) . . . . . . . . . . . . . . . . . . . .78
M-Bus Interface Block Diagram . . . . . . . . . . . . . . . . . . . . . .79
M-Bus Frequency Divider Register (MFDR). . . . . . . . . . . . .80
M-Bus Control Register (MCR) . . . . . . . . . . . . . . . . . . . . . .82
M-Bus Status Register (MSR) . . . . . . . . . . . . . . . . . . . . . . .84
M-Bus Data I/O Register (MDR). . . . . . . . . . . . . . . . . . . . . .86
Flowchart of M-Bus Interrupt Routine. . . . . . . . . . . . . . . . . .87
12-1
12-2
12-3
12-4
12-5
12-6
SSI Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .97
Synchronous Serial Interface Timing (CPOL = 1) . . . . . . . .99
Synchronous Serial Interface Timing (CPOL = 0) . . . . . . . .99
SSI Control Register (SCR) . . . . . . . . . . . . . . . . . . . . . . . .100
SSI Status Register (SSR) . . . . . . . . . . . . . . . . . . . . . . . . .103
SSI Data Register (SDR) . . . . . . . . . . . . . . . . . . . . . . . . . .104
13-1
13-2
13-3
13-4
13-5
Programmer Interface to Host . . . . . . . . . . . . . . . . . . . . . .109
MC68HC705E5 Bootloader Flowchart . . . . . . . . . . . . . . . .110
MC68HC705E5 Programming Circuit . . . . . . . . . . . . . . . .111
Programming Register (PROG) . . . . . . . . . . . . . . . . . . . . .112
Mask Option Register (MOR) . . . . . . . . . . . . . . . . . . . . . . .113
15-1
15-2
15-3
15-4
15-5
Maximum Supply Current versus Operating Frequency . .137
Typical Supply Current versus Operating Frequency. . . . .137
External Interrupt Mode Diagram . . . . . . . . . . . . . . . . . . . .138
Power-On Reset and RESET. . . . . . . . . . . . . . . . . . . . . . .139
M-Bus Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . .141
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Table
Title
Page
4-1
Vector Address for Interrupts and Reset . . . . . . . . . . . . . . . .34
5-1
COP Watchdog Timer Recommendations . . . . . . . . . . . . . . .46
6-1
Operating Mode Conditions . . . . . . . . . . . . . . . . . . . . . . . . . .47
7-1
I/O Pin Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53
8-1
RTI Rates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58
9-1
PS1 and PS0 Speed Selects with 32.768-kHz Crystal. . . . . .64
10-1
COP Rates at fosc = 32.768 kHz . . . . . . . . . . . . . . . . . . . . . .69
11-1
M-Bus Clock Prescaler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .81
12-1
Master Mode SCK Frequency Select . . . . . . . . . . . . . . . . . .102
13-1
13-2
13-3
Bootloader Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .108
CPI Rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .113
MOR Read/Write Based on Mode and LATCH Bit . . . . . . . .114
14-1
14-2
14-3
14-4
14-5
Register/Memory Instructions. . . . . . . . . . . . . . . . . . . . . . . .120
Read-Modify-Write Instructions . . . . . . . . . . . . . . . . . . . . . .121
Jump and Branch Instructions . . . . . . . . . . . . . . . . . . . . . . .123
Bit Manipulation Instructions. . . . . . . . . . . . . . . . . . . . . . . . .124
Control Instructions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .125
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List of Tables
N O N D I S C L O S U R E
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Table
14-6
14-7
17-1
Title
Page
Instruction Set Summary . . . . . . . . . . . . . . . . . . . . . . . . . . .126
Opcode Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .132
MC Order Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .145
N O N D I S C L O S U R E
A G R E E M E N T
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R E Q U I R E D
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1.1 Contents
1.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
1.3
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
1.4
Mask Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
1.5
Functional Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
1.5.1
VDD and VSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
1.5.2
IRQ/VPP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
1.5.3
OSC1 and OSC2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
1.5.4
RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
1.5.5
PA0–PA7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
1.5.6
PB0–PB7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
1.5.7
PC0–PC3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
1.5.8
XFC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
1.5.9
VDDSYN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
1.2 Introduction
The MC68HC705E5 is a low-cost introduction to the M68HC05 Family
of microcontrollers (MCUs). The HC05 central processing unit (CPU)
core has been enhanced with a 15-stage multifunctional timer and
programmable phase-locked loop (PLL). The MCU is available in a
28-pin package and has two 8-bit input/output (I/O) ports and one 4-bit
I/O port. The 8-Kbyte memory map consists of user eraseable,
programmable read-only memory (EPROM), random-access memory
(RAM), bootloader ROM, and I/O.
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Section 1. General Description
N O N - D I S C L O S U R E
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1.3 Features
Features of the MC68HC705E5 include:
N O N - D I S C L O S U R E
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A G R E E M E N T
R E Q U I R E D
General Description
•
Low Cost
•
HC05 Core
•
28-Pin Package
•
On-Chip Oscillator (Crystal or Ceramic Resonator)
•
Phase-Locked Loop (PLL) Synthesizer with Programmable Speed
•
Synchronous Serial Interface (SSI) with Interrupts and Most
Significant Bit (MSB) or Least Significant Bit (LSB) First
•
M-Bus (I2C) Communication Port
•
5120 Bytes of User EPROM (Including 16 Bytes of EPROM User
Vectors)
•
384 Bytes of On-Chip RAM
•
15-Stage Multifunctional Timer with Programmable Input
•
Real-Time Interrupt Circuit
•
Computer Operating Properly (COP) Watchdog Timer Mask
Option
•
Custom Periodic Interrupt Circuit
•
20 Bidirectional I/O Lines
•
Single-Chip Mode
•
Bootloader Mode
•
Power-Saving Stop and Wait Modes
•
Edge-Only Sensitive or Edge- and Level-Sensitive Interrupt
Trigger Mask Option
•
STOP Instruction Disable Mask Option
•
System Control and Status Register
•
Illegal Address Reset
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VDD
VSS
COP
SYSTEM
CUSTOM
PERIODIC
INTERRUPT
OSCILLATOR
OSC1
OSCOUT
PLL
SYNTHESIS
CLOCK
SELECT
TPLL
÷2
INTERNAL
PROCESSOR
CLOCK
TIMER
SYSTEM
SSI
SYSTEM
CPU
CONTROL
ALU
IRQ/VPP
M68HC05 CPU
CPU REGISTERS
PA1
PA2
PORT A
RESET
DATA DIRECTION REGISTER
PA0
PA3
PA4
PA5
PA6
ACCUMULATOR
PA7
INDEX REGISTER
PB0
SRAM — 384 BYTES
PB2
PB3/TIPL
PB4/SCK
PB5/SDI/SDO
PB6/SDA
PB7/SCL
BOOT ROM — 240 BYTES
PC0
PORT C
EPROM — 4608 BYTES
PC1
PC2
PC3
Figure 1-1. Block Diagram
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N O N - D I S C L O S U R E
CONDITION CODE REGISTER
PB1
PORT B
PROGRAM COUNTER
DATA DIRECTION REGISTER
STACK POINTER
DATA DIRECTION
REGISTER
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VDDSYN
XFC
I2C
SYSTEM
A G R E E M E N T
OSC2
R E Q U I R E D
General Description
Features
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R E Q U I R E D
General Description
1.4 Mask Options
The M68HC705E5 has these four mask options which are handled with
five EPROM bits (MOR).
1. STOP instruction (enable/disable)
2. IRQ (edge-sensitive only or edge- and level-sensitive)
3. COP watchdog timer (enable/disable)
ROM versions of this device will have these options programmed by the
factory. Refer to 13.5 Mask Option Register for additional information.
NOTE:
A line over a signal name indicates an active low signal. For example,
RESET is active low.
1.5 Functional Pin Description
Figure 1-2 shows the single-chip mode pinout for the MC68HC705E5.
Refer to the following subsections for a description of the pins.
N O N - D I S C L O S U R E
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A G R E E M E N T
4. CPI Rate (1 second, 0.5 second, or 0.25 second)
IRQ
1
28
XFC
RESET
2
27
VDDSYN
OSC1
3
26
PA0
OSC2
4
25
PA1
PB7/SCL
5
24
PA2
PB6/SDA
6
23
PA3
PB5/SDIO
7
22
PA4
PB4/SCK
8
21
PA5
PB3/TIPL
9
20
PA6
PB2
10
19
PA7
PB1
11
18
PC0
PB0
12
17
PC1
VDD
13
16
PC2
VSS
14
15
PC3
Figure 1-2. Single-Chip Mode Pinout
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1.5.2 IRQ/VPP
This pin is used to supply the EPROM with the required programming
voltage. In addition, the mask interrupt request has a programmable
option that provides two different choices of interrupt triggering
sensitivity. The options are:
1. Negative edge-sensitive triggering only
2. Both negative edge-sensitive and level-sensitive triggering
The MCU completes the current instruction before it responds to the
interrupt request. When IRQ/VPP goes low for at least one tILIH, a logic
1 is latched internally to signify an interrupt has been requested. When
the MCU completes its current instruction, the interrupt latch is tested. If
the interrupt latch contains a logic 1, and the interrupt mask bit (I bit) in
the condition code register is clear, the MCU then begins the interrupt
sequence.
If the option is selected to include level-sensitive triggering, the IRQ input
requires an external resistor to VDD for wired-OR operation.
The IRQ/VPP pin contains an internal Schmitt trigger as part of its input
to improve noise immunity. Refer to Section 4. Interrupts for more
detail.
NOTE:
The voltage on the IRQ pin affects the mode of operation. For additional
information, see Section 6. Operating Modes.
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A G R E E M E N T
Power is supplied to the microcontroller using these two pins. VDD is the
positive supply and VSS is ground.
N O N - D I S C L O S U R E
1.5.1 VDD and VSS
R E Q U I R E D
General Description
Functional Pin Description
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1.5.3 OSC1 and OSC2
These pins provide control input for an on-chip clock oscillator circuit
which can optionally drive a PLL clock. A crystal, a ceramic resonator, or
an external signal connects to these pins providing a system clock. The
oscillator frequency is two times the internal bus rate if the PLL is not
used.
Crystal
Figure 1-3 (a) shows the recommended circuit for using a crystal. The
crystal and components should be mounted as close as possible to
the input pins to minimize output distortion and startup stabilization
time.
Ceramic Resonator
A ceramic resonator may be used in place of the crystal in
cost-sensitive applications. Figure 1-3 (a) shows the recommended
circuit for using a ceramic resonator. The manufacturer of the
particular ceramic resonator being considered should be consulted
for specific information.
External Clock
An external clock should be applied to the OSC1 input with the OSC2
pin not connected (refer to Figure 1-3 (b)). This setup can be used if
the user does not wish to run the CPU with a 32.768-kHz crystal or
the PLL frequencies are not suitable for the application.
N O N - D I S C L O S U R E
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A G R E E M E N T
R E Q U I R E D
General Description
MCU
OSC1
MCU
OSC2
OSC1
OSC2
330 kΩ
20 MΩ
10 pF
UNCONNECTED
< EXTERNAL CLOCK
32.768 kHz
33 pF
(a) Crystal/Ceramic Resonator
Oscillator Connections
(b) External Clock Source
Connections
Figure 1-3. Oscillator Connections
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1.5.5 PA0–PA7
These eight I/O lines comprise port A. The state of any pin is software
programmable and all port A lines are configured as input during
power-on or reset. See 7.6 Input/Output Programming for additional
information.
1.5.6 PB0–PB7
These eight I/O lines comprise port B. The state of any pin is software
programmable and all port B lines are configured as input during
power-on or reset. PB7 (SCL) and PB6 (SDA) can be configured as an
M-bus interface. (Refer to Section 11. Motorola Bus (M Bus) Interface
for M-bus pin configurations). PB3–PB5 (TIPL, SCK, and SDIO) can be
configured as a synchronous serial interface (SSI). Refer to Section 12.
Synchronous Serial Interface (SSI) and to 7.6 Input/Output
Programming for additional information.
1.5.7 PC0–PC3
These four I/O lines comprise port C. The state of any pin is software
programmable and all port C lines are configured as input during
power-on or reset. 7.6 Input/Output Programming for additional
information.
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A G R E E M E N T
This active low pin is used to reset the MCU to a known startup state by
pulling RESET low. The RESET pin contains an internal Schmitt trigger
as part of its input to improve noise immunity. See Section 5. Resets for
additional information.
N O N - D I S C L O S U R E
1.5.4 RESET
R E Q U I R E D
General Description
Functional Pin Description
Freescale Semiconductor, Inc.
1.5.8 XFC
This pin provides a means for connecting an external filter capacitor to
the synthesizer PLL filter. For additional information concerning this
capacitor, see Section 9. Phase-Locked Loop (PLL) Synthesis.
1.5.9 VDDSYN
This pin provides a separate power connection to the PLL synthesizer
which should be at the same potential as VDD.
NOTE:
Any unused inputs and I/O ports should be tied to an appropriate logic
level (either VDD or VSS). Although the I/O ports of the MC68HC705E5
do not require termination, it is recommended to reduce the possibility of
static damage.
N O N - D I S C L O S U R E
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A G R E E M E N T
R E Q U I R E D
General Description
General Release Specification
MC68HC705E5 — Rev. 1.0
General Description
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2.1 Contents
2.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
2.3
EPROM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
2.4
RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
2.5
Memory Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
2.6
Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
2.2 Introduction
The MC68HC705E5 has an 8-Kbyte memory map, consisting of user
erasable, programmable read-only memory (EPROM), user random
access memory (RAM), bootloader ROM, control registers, and
input/output (I/O). Refer to Figure 2-1 for the memory map and Figure
2-2 for the register map.
2.3 EPROM
The user EPROM consists of 5120 bytes of EPROM from $0B00 to
$1EFF and 16 bytes of user vectors from $1FF0 to $1FFF.
The bootloader ROM and vectors are located from $1F01 to $1FEF.
All of the user vectors, $1FF2 through $1FFF, are dedicated to reset and
interrupt vectors. Location $1F00 is the mask option register (MOR).
2.4 RAM
The user RAM, including the stack area, consists of 384 bytes located
from $0080 to $01FF. The stack begins at address $00FF. The stack
pointer can access 64 bytes of RAM from $00FF to $00C0. Using the
stack area for data storage or temporary work locations requires care to
prevent it from being overwritten due to stacking from an interrupt or
subroutine call.
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Memory
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Section 2. Memory
N O N - D I S C L O S U R E
General Release Specification — MC68HC705E5
R E Q U I R E D
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Freescale Semiconductor, Inc.
2.5 Memory Map
$0000
$001F
$0020
$007F
$0080
$00BF
$00C0
$00FF
$0100
$01FF
$0200
I/O
32 BYTES
PORT A DATA REGISTER
$00
PORT B DATA REGISTER
$01
UNUSED
96 BYTES
PORT C DATA REGISTER
$02
UNUSED
$03
RAM
128 BYTES
PORT A DATA DIRECTION REGISTER
$04
PORT B DATA DIRECTION REGISTER
$05
PORT C DATA DIRECTION REGISTER
$06
PLL CONTROL REGISTER
$07
TIMER CONTROL & STATUS REGISTER
$08
TIMER COUNTER REGISTER
$09
STACK
64 BYTES
RAM
256 BYTES
UNUSED
2304 BYTES
$0AFF
$0B00
USER EPROM
5120 BYTES
SSI REGISTERS
$0A-$0C
UNUSED
$0D-$10
EEPROM PROGRAMMING REGISTER
$11
CPI CONTROL & STATUS REGISTER
$12
SCSR REGISTER
$13
$18
MBUS (I2
C) M BUS
REGISTERS
$1EFF
$1F00 MASK OPTION REGISTER
$1F01
BOOT ROM
240 BYTES
$1FEF
$1FF0
EPROM USER VECTORS
16 BYTES
$1FFF
N O N - D I S C L O S U R E
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A G R E E M E N T
R E Q U I R E D
Memory
$1C
$1D
UNUSED
$1E
$1F
TEST REGISTER
UNUSED
$1FF0
UNUSED
$1FF1
M BUS VECTOR (HIGH BYTE)
$1FF2
M BUS VECTOR (LOW BYTE)
$1FF3
SSI VECTOR (HIGH BYTE)
$1FF4
SSI VECTOR (LOW BYTE)
$1FF5
CPI VECTOR (HIGH BYTE)
$1FF6
CPI VECTOR (LOW BYTE)
$1FF7
TIMER VECTOR (HIGH BYTE)
$1FF8
TIMER VECTOR (LOW BYTE)
$1FF9
IRQ VECTOR (HIGH BYTE)
$1FFA
IRQ VECTOR (LOW BYTE)
$1FFB
SWI VECTOR (HIGH BYTE)
$1FFC
SWI VECTOR (LOW BYTE)
$1FFD
RESET VECTOR (HIGH BYTE)
$1FFE
RESET VECTOR (LOW BYTE)
$1FFF
Figure 2-1. Memory Map
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Memory
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Register
Bit 7
6
5
4
3
2
1
Bit 0
0
0
0
0
0
BCS
0
BWC
PLLON
VCOTST
PS1
PS0
TOF
RTIF
TOFE
RTIE
TOFA
RTIFA
RT1
RT0
$0000
Port A Data Register
$0001
Port B Data Register
$0002
Port C Data Register
$0003
Unimplemented
$0004
Port A Data Direction Register
$0005
Port B Data Direction Register
$0006
Port C Data Direction Register
$0007
PLL Control Register
$0008
Timer Control and Status Register.
$0009
Timer Counter Register
$000A
SSI Control Register
SIE
SE
LSBF
MSTR
CPOL
SDIR
SR1
SR0
$000B
SSI Status Register
SF
DCOL
0
0
0
0
0
TIPL
$000C
SSI Data Register
D7
D6
D5
D4
D3
D2
D1
D0
$000D
Unimplemented
$000E
Unimplemented
$000F
Unimplemented
$0010
Unimplemented
$0011
Programming Register
—
—
—
—
—
LATCH
0
EPGM
$0012
CPI Control and Status Register
—
CPIF
—
CPIE
—
—
—
—
$0013
System Control and Status Register
0
0
0
STOPR
ILADR
COPR
CRS1
CRS0
$0014
Unimplemented
$0015
Unimplemented
$0016
Unimplemented
$0017
Unimplemented
= Unimplemented
Figure 2-2. I/O Registers
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Addr.
N O N - D I S C L O S U R E
2.6 Register Summary
R E Q U I R E D
Memory
Register Summary
Freescale Semiconductor, Inc.
Addr.
Register
Bit 7
6
5
4
3
2
1
$0018
M-Bus Address Register
MAD7
MAD6
MAD5
MAD4
MAD3
MAD2
MAD1
$0019
M Bus Frequency Divider Register
FD4
FD3
FD2
FD1
FD0
$001A
M Bus Control Register
MEN
MIEN
MSTA
MTX
TXAK
MMUX
$001B
M Bus Status Register
MCF
MAAS
MBB
MAL
SRW
MIF
MXAK
$001C
M Bus Data I/O Register
MD7
MD6
MD5
MD4
MD3
MD2
MD1
MD0
$001D
Unimplemented
$001E
Unimplemented
$001F
Reserved
R
R
R
R
R
R
R
R
= Unimplemented
R
Bit 0
= Reserved
Figure 2-2. I/O Registers (Continued)
N O N - D I S C L O S U R E
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A G R E E M E N T
R E Q U I R E D
Memory
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Memory
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3.1 Contents
3.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
3.3
Accumulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
3.4
Index Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
3.5
Condition Code Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
3.6
Stack Pointer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32
3.7
Program Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32
3.2 Introduction
The MCU contains five registers as shown in Figure 3-1. The interrupt
stacking order is shown in Figure 3-2.
7
0
A
ACCUMULATOR
7
0
X
INDEX REGISTER
12
0
PC
12
0
PROGRAM COUNTER
7
0
0
0
0
1
0
1
SP
STACK POINTER
CCR
H
I
N
Z
C
CONDITION CODE REGISTER
Figure 3-1. Programming Model
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A G R E E M E N T
Section 3. Central Processing Unit (CPU)
N O N - D I S C L O S U R E
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A G R E E M E N T
R E Q U I R E D
Central Processing Unit (CPU)
7
0
1
1
R
E
T
U
R
N
INCREASING
MEMORY
ADDRESSES
1
STACK
CONDITION CODE REGISTER
I
N
T
E
R
R
U
P
T
ACCUMULATOR
INDEX REGISTER
PCH
PCL
DECREASING
MEMORY
ADDRESSES
UNSTACK
NOTE: Since the stack pointer decrements during pushes, the PCL is stacked
first, followed by PCH, etc. Pulling from the stack is in the reverse
Figure 3-2. Stacking Order
3.3 Accumulator
The accumulator is a general-purpose 8-bit register used to hold
operands and results of arithmetic calculations or data manipulations.
Bit 7
6
5
4
3
2
1
Bit 0
A
Figure 3-3. Accumulator (A)
3.4 Index Register
The index register is an 8-bit register used for the indexed addressing
value to create an effective address. The index register may also be
used as a temporary storage area.
Bit 7
6
5
4
3
2
1
Bit 0
X
Figure 3-4. Index Register (X)
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Bit 4
3
2
1
Bit 0
H
I
N
Z
C
Figure 3-5. Condition Code Register (CCR)
Half Carry (H)
This bit is set during ADD and ADC operations to indicate that a carry
occurred between bits 3 and 4.
Interrupt (I)
When this bit is set, the timer and external interrupt are masked
(disabled). If an interrupt occurs while this bit is set, the interrupt is
latched and processed as soon as the I bit is cleared.
Negative (N)
When set, this bit indicates that the result of the last arithmetic, logical,
or data manipulation was negative.
Zero (Z)
When set, this bit indicates that the result of the last arithmetic, logical,
or data manipulation was zero.
Carry/Borrow (C)
When set, this bit indicates that a carry or borrow out of the arithmetic
logical unit (ALU) occurred during the last arithmetic operation. This
bit also is affected during bit test and branch instructions and during
shifts and rotates.
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The CCR is a 5-bit register in which the H, N, Z, and C bits are used to
indicate the results of the instruction just executed, and the I bit is used
to enable interrupts. These bits can be tested individually by a program,
and specific actions can be taken as a result of their state. Each bit is
explained in the following paragraphs.
N O N - D I S C L O S U R E
3.5 Condition Code Register
R E Q U I R E D
Central Processing Unit (CPU)
Condition Code Register
Freescale Semiconductor, Inc.
3.6 Stack Pointer
The stack pointer contains the address of the next free location on the
stack. During an MCU reset or the reset stack pointer (RSP) instruction,
the stack pointer is set to location $00FF. The stack pointer then is
decremented as data is pushed onto the stack and incremented as data
is pulled from the stack.
When accessing memory, the seven most significant bits (MSB) are
permanently set to 0000011. These seven bits are appended to the six
least significant register bits to produce an address within the range of
$00FF to $00C0. Subroutines and interrupts may use up to 64 (decimal)
locations. If 64 locations are exceeded, the stack pointer wraps around
and loses the previously stored information. A subroutine call occupies
two locations on the stack; an interrupt uses five locations.
N O N - D I S C L O S U R E
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A G R E E M E N T
R E Q U I R E D
Central Processing Unit (CPU)
Bit
12
11
10
9
8
7
0
0
0
0
0
1
6
5
4
3
2
1
Bit
0
SP
Figure 3-6. Stack Pointer (SP)
3.7 Program Counter
The program counter is a 13-bit register that contains the address of the
next byte to be fetched.
Bit
12
11
10
9
8
7
6
5
4
3
2
1
Bit
0
PC
Figure 3-7. Program Counter (PC)
NOTE:
The HC05 CPU core is capable of addressing 16-bit locations. For this
implementation, however, the addressing registers are limited to an
8-Kbyte memory map.
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4.1 Contents
4.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
4.3
Hardware Controlled Interrupt Sequence . . . . . . . . . . . . . . . . .35
4.4
Software Interrupt (SWI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35
4.5
External Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36
4.6
Timer Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36
4.7
Custom Periodic Interrupt (CPI) . . . . . . . . . . . . . . . . . . . . . . . .39
4.8
Synchronous Serial Interface Interrupt (SSI) . . . . . . . . . . . . . .40
4.9
M-Bus (I2C) Interrupt (M Bus). . . . . . . . . . . . . . . . . . . . . . . . . .40
4.10
Operation During Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . .40
4.11
Operation During Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . .40
4.2 Introduction
The MCU can be interrupted six different ways: the five maskable
hardware interrupts (IRQ, timer, CPI, SSI, and M bus) and the
nonmaskable software interrupt instruction (SWI).
Interrupts cause the processor to save register contents on the stack
and to set the interrupt mask (I bit) to prevent additional interrupts. The
RTI instruction causes the register contents to be recovered from the
stack and normal processing to resume.
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A G R E E M E N T
Section 4. Interrupts
N O N - D I S C L O S U R E
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A G R E E M E N T
R E Q U I R E D
Interrupts
Unlike RESET, hardware interrupts do not cause the current instruction
execution to be halted, but are considered pending until the current
instruction is complete. The current instruction is the one already fetched
and being operated on.
When the current instruction is complete, the processor checks all
pending hardware interrupts. If interrupts are not masked (CCR I bit
clear) and the corresponding interrupt enable bit is set, the processor
proceeds with interrupt processing; otherwise, the next instruction is
fetched and executed.
If both an external interrupt and a timer interrupt are pending at the end
of an instruction execution, the external interrupt is serviced first. The
SWI is executed the same as any other instruction, regardless of the I-bit
state.
Table 4-1. Vector Address for Interrupts and Reset
Register
Flag
Name
CPU
Interrupt
Vector
Address
N/A
N/A
Reset
RESET
$1FFE–$1FFF
N/A
N/A
Software
SWI
$1FFC–$1FFD
N/A
N/A
External Interrupt
IRQ
$1FFA–$1FFB
TCSR
TOF
Timer Overflow
TIMER
$1FF8–$1FF9
N/A
RTIF
Real-Time Interrupt
TIMER
$1FF8–$1FF9
CPICSR
CPIF
Custom Periodic Interrupt
CPI
$1FF6–$1FF7
SSR
SF
Synchronous Serial Interrupt
SSI
$1FF4–$1FF5
MSR
MIF
M-Bus Interrupt
M Bus
$1FF2–$1FF3
Interrupts
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Interrupts
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1. RESET — A low input on the RESET input pin causes the program
to vector to its starting address which is specified by the contents
of memory locations $1FFE and $1FFF. The I bit in the condition
code register is also set. Much of the MCU is configured to a
known state during this type of reset as described in Section 5.
Resets.
2. STOP — The STOP instruction causes the oscillator to be turned
off and the processor to “sleep” until an external interrupt (IRQ) or
reset occurs.
3. WAIT — The WAIT instruction causes all processor clocks to stop,
but leaves the timer clock running. This “rest” state of the
processor can be cleared by reset, an external interrupt (IRQ), or
timer interrupt. There are no special wait vectors for these
individual interrupts.
4.4 Software Interrupt (SWI)
The SWI is an executable instruction and a nonmaskable interrupt. It is
executed regardless of the state of the I bit in the CCR. If the I bit is zero
(interrupts enabled), SWI executes after interrupts which were pending
when the SWI was fetched but before interrupts generated after the SWI
was fetched. The interrupt service routine address is specified by the
contents of memory locations $1FFC and $1FFD.
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The following three functions (RESET, STOP, and WAIT) are not in the
strictest sense an interrupt; however, they are acted upon in a similar
manner. See Figure 4-1 and Figure 4-2. A discussion is provided below.
N O N - D I S C L O S U R E
4.3 Hardware Controlled Interrupt Sequence
R E Q U I R E D
Interrupts
Hardware Controlled Interrupt Sequence
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A G R E E M E N T
R E Q U I R E D
Interrupts
4.5 External Interrupt
If the I bit of the condition code reister (CCR) is set, all maskable
interrupts (internal and external) are disabled. Clearing the I bit enables
interrupts. The interrupt request is latched immediately following the
falling edge of IRQ. It is then synchronized internally and serviced by the
interrupt service routine located at the address specified by the contents
of $1FFA and $1FFB.
Either a level-sensitive and edge-sensitive trigger or an
edge-sensitive-only trigger is available as a mask option.
NOTE:
The internal interrupt latch is cleared in the first part of the interrupt
service routine; therefore, one external interrupt pulse could be latched
and serviced as soon as the I bit is cleared.
4.6 Timer Interrupt
Two different timer interrupt flags cause a timer interrupt whenever they
are set and enabled. The interrupt flags and enable bits are located in
the timer control and status register (TCSR). Either of these interrupts
will vector to the same interrupt service routine, located at the address
specified by the contents of memory location $1FF8 and $1FF9. For
additional information, refer to 8.3 Timer Control and Status Register.
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Y
IS
I BIT
SET?
N
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IRQ
EXTERNAL
INTERRUPT?
Y
CLEAR IRQ
REQUEST
LATCH.
N
TIMER
INTERNAL
INTERRUPT?
Y
STACK
PC, X, A, CC
N
CPI
INTERNAL
INTERRUPT?
Y
SET
I BIT.
N
LOAD PC FROM:
SWI: $1FFC–$1FFD
IRQ:
$1FFA–$1FFB
TIMER: $1FF8–$1FF9
CPI:
$1FF6–$1FF7
SSI:
$1FF4–$1FF5
M BUS: $1FF2–$1FF3
FETCH NEXT
INSTRUCTION.
N
SWI
INSTRUCTION
?
Y
N
RTI
INSTRUCTION
?
Y
RESTORE RESISTERS
FROM STACK
CC, A, X, PC.
N
EXECUTE
INSTRUCTION.
Figure 4-1. Interrupt Processing Flowchart
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N O N - D I S C L O S U R E
FROM
RESET
A G R E E M E N T
R E Q U I R E D
Interrupts
Timer Interrupt
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A G R E E M E N T
R E Q U I R E D
Interrupts
N
N
STOP
WAIT
STOP OSCILLATOR
AND ALL CLOCKS.
CLEAR I BIT.
OSCILLATOR ACTIVE.
TIMER CLOCK ACTIVE.
PROCESSOR CLOCKS
STOPPED.
RESET?
RESET?
Y
Y
EXTERNAL
INTERRUPT
(IRQ)?
Y
N
EXTERNAL
INTERRUPT
(IRQ)?
Y
TURN ON OSCILLATOR.
WAIT FOR TIME
DELAY TO STABILIZE.
N
TIMER
INTERNAL
Y
INTERRUPT?
N
Y
RESTART
PROCESSOR CLOCK.
CPI, SSI, OR M-BUS
INTERNAL
INTERRUPT?
N
Y
1. FETCH RESET
VECTOR OR
2. SERVICE
INTERRUPT
A. STACK
B. SET I BIT
C. VECTOR TO
INTERRUPT
ROUTINE
1. FETCH RESET
VECTOR OR
2. SERVICE
INTERRUPT
A. STACK
B. SET I BIT
C. VECTOR TO
INTERRUPT
ROUTINE
Figure 4-2. STOP/WAIT Flowcharts
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The custom periodic interrupt is mask programmable to a 0.25 second,
0.5 second, or 1 second interrupt. The interrupt is generated from the
32-kHz OSC1 input by a 15-bit counter. This interrupt is under the
control of the custom periodic interrupt control and status register
located at $12.
Address
$0012
Bit 7
6
5
4
3
2
1
Bit 0
0
CPIF
0
CPIE
0
0
0
0
0
0
0
0
0
0
0
0
Read:
Write:
Reset:
Figure 4-3. Custom Periodic Interrupt Control
and Status Register (CPICSR)
CPIF — Custom Periodic Interrupt Flag
CPIF is a clearable, read-only status bit and is set when the 15-bit
counter changes from $7FFF to $0000. A CPU interrupt request will
be generated if CPIE is set. Clearing the CPIF is done by writing a
zero to it. Writing a one to CPIF has no effect on the bit’s value. Reset
clears CPIF.
CPIE — Custom Periodic Interrupt Enable
When this bit is cleared, the CPI interrupts are disabled. When this bit
is set, the CPU interrupt request is generated when the CPIF bit is set.
Reset clears this bit.
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The CPI flag and enable bits are located in the CPI control and status
register (CPICSR). A CPI interrupt will vector to the interrupt service
routine located at the address specified by the contents of memory
location $1FF6 and $1FF7.
N O N - D I S C L O S U R E
4.7 Custom Periodic Interrupt (CPI)
R E Q U I R E D
Interrupts
Custom Periodic Interrupt (CPI)
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R E Q U I R E D
Interrupts
4.8 Synchronous Serial Interface Interrupt (SSI)
The SSI flag and enable bits are located in the SSI control (SCR) and
status (SSR) registers. An SSI interrupt will vector to the interrupt service
routine located at the address specified by the contents of memory
locations $1FF4 and $1FF5. For additional information, refer to 12.4 SSI
Registers.
4.9 M-Bus (I2C) Interrupt (M Bus)
The MIF flag and enable bits are located in the M-bus status (MSR) and
control (MCR) registers. An M-bus interrupt will vector to the interrupt
service routine located at the address specified by the contents of
memory locations $1FF2 and $1FF3. For further information, refer to
11.6 M-Bus Registers.
4.10 Operation During Stop Mode
The timer system is cleared and the CPI counter is halted when going
into stop mode. When stop mode is exited by an external interrupt or an
external RESET, the internal oscillator will resume, followed by a
4064-cycle internal processor oscillator stabilization delay. The timer
system counter is then cleared and operation resumes. The CPI will
continue counting once the oscillator resumes and does not wait for the
oscillator to stabilize.
4.11 Operation During Wait Mode
The CPU clock halts during wait mode, but the timer and CPI remain
active. A timer interrupt or custom periodic interrupt, SSI, and M bus will
cause the processor to exit wait mode if the interrupts are enabled.
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5.1 Contents
5.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41
5.3
External Reset (RESET). . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42
5.4
Internal Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44
5.5
Power-On Reset (POR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44
5.6
Computer Operating Properly Reset (COPR). . . . . . . . . . . . . .45
5.6.1
Resetting the COP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45
5.6.2
COP During Wait Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . .45
5.6.3
COP During Stop Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . .45
5.6.4
COP Watchdog Timer Considerations . . . . . . . . . . . . . . . .46
5.7
Illegal Address Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46
5.2 Introduction
The MCU can be reset from five sources: one external input and four
internal restart conditions. The RESET pin is an input with a Schmitt
trigger as shown in Figure 5-1. All the internal peripheral modules will be
reset by the internal reset signal (RST). Refer to Figure 5-2 for reset
timing detail.
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Section 5. Resets
N O N - D I S C L O S U R E
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Resets
5.3 External Reset (RESET)
The RESET pin is the only external source of a reset. This pin is
connected to a Schmitt trigger input gate to provide an upper and lower
threshold voltage separated by a minimum amount of hysteresis. This
external reset occurs whenever the RESET pin is pulled below the lower
threshold and remains in reset until the RESET pin rises above the
upper threshold. This active-low input will generate the RST signal and
reset the CPU and peripherals. The only reset sources that can alter the
MCU’s operating mode are termination of the external reset input or the
internal computer operating properly (COP) watchdog reset.
NOTE:
Activation of the RST signal is generally referred to as a reset of the
device, unless otherwise specified.
TO IRQ
LOGIC
IRQ/VTST
D
LATCH
MODE
SELECT
RESET
R
(PULSE WIDTH = 3xE-CLK)
PH2
OSC
DATA
ADDRESS
CLOCKED
ONE-SHOT
COP WATCHDOG
(COPR)
CPU
VDD
S
D
LATCH
POWER-ON RESET
(POR)
ADDRESS
ILLEGAL ADDRESS
(ILLADDR)
STOPEN
DISABLED STOP
INSTRUCTION
RST
TO OTHER
PERIPHERALS
PH2
Figure 5-1. Reset Block Diagram
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NEW
PCH
1FFE
4064 tCYC
NEW
PCL
1FFF
tCYC
VDD THRESHOLD (1 TO 2 V TYPICAL)
NEW PC
OP
CODE
NEW PC
3
tRL
1FFE
1FFE
1FFE
PCH
1FFE
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Figure 5-2. RESET and POR Timing Diagram
NOTES:
1. Internal timing signal and bus information are not available externally.
2. OSC1 line is not meant to represent frequency. It is only used to represent time.
3. The next rising edge of the internal processor clock following the rising edge of RESET initiates the reset sequence.
RESET
INTERNAL
DATA
BUS1
INTERNAL
ADDRESS
BUS1
INTERNAL
PROCESSOR
CLOCK1
OSC12
VDD
tVDDR
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OP
CODE
NEW PC
R E Q U I R E D
PCL
1FFF
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External Reset (RESET)
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R E Q U I R E D
Resets
A G R E E M E N T
5.5 Power-On Reset (POR)
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5.4 Internal Resets
N O N - D I S C L O S U R E
The RESET pin can also act as an open-drain output. It will be pulled to
a low state by an internal pulldown that is activated by any reset source.
This RESET pulldown device will be asserted only by three to four cycles
of the internal clock, PH2 (PH2 period = E clock period), or as long as an
internal reset source is asserted. When the external RESET pin is
asserted, the pulldown device will be turned on for the three to four
internal clock cycles only.
The four internally generated resets are the initial power-on reset
function, the COP watchdog timer reset, the illegal address detector, and
the disabled STOP instruction. The only reset sources that can alter the
MCU’s operating mode are termination of the external RESET input or
the internal COP watchdog timer. The other internal resets will not have
any effect on the mode of operation when their reset state ends. All
internal resets will also assert (pull to logic 0) the external RESET pin for
the duration of the reset or three to four internal clock cycles, whichever
is longer.
The internal POR is generated on power-up to allow the clock oscillator
to stabilize. The POR is strictly for power turn-on conditions and is not
able to detect a drop in the power supply voltage (brown-out). There is
an oscillator stabilization delay of 4064 internal processor clock cycles
after the oscillator becomes active.
The POR will generate the RST signal which will reset the CPU. If any
other reset function is active at the end of the 4064-cycle delay, the RST
signal will remain in the reset condition until the other reset condition(s)
end.
POR will activate the RESET pin pulldown device connected to the pin.
VDD must drop below VPOR for the internal POR circuit to detect the next
rise of VDD.
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The COP reset function is enabled or disabled by a mask option and is
verified during production testing.
The COP watchdog reset will activate the internal pulldown device
connected to the RESET pin.
5.6.1 Resetting the COP
Preventing a COP reset is done by writing a logic 0 to the COPF bit. This
action will reset the counter and begin the timeout period again. The
COPF bit is bit 0 of address $1FF0. A read of address $1FF0 will return
user data programmed at that location.
5.6.2 COP During Wait Mode
The COP will continue to operate normally during wait mode. The
software should pull the device out of wait mode periodically and reset
the COP by writing to the COPF bit to prevent a COP reset.
5.6.3 COP During Stop Mode
When the stop enable mask option is selected, stop mode disables the
oscillator circuit and thereby turns the clock off for the entire device. The
COP counter will be reset when stop mode is entered. If a reset is used
to exit stop mode, the COP counter will be held in reset during the 4064
cycles of startup delay. If any operable interrupt is used to exit stop
mode, the COP counter will not be reset during the 4064-cycle startup
delay and will have that many cycles already counted when control is
returned to the program.
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The MCU contains a watchdog timer that automatically times out if not
reset (cleared) within a specific time by a program reset sequence. If the
COP watchdog timer is allowed to timeout, an internal reset is generated
to reset the MCU. Regardless of an internal or external reset, the MCU
comes out of a COP reset according to the standard rules of mode
selection.
N O N - D I S C L O S U R E
5.6 Computer Operating Properly Reset (COPR)
R E Q U I R E D
Resets
Computer Operating Properly Reset (COPR)
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Resets
5.6.4 COP Watchdog Timer Considerations
If enabled by a mask option, the COP watchdog timer is active in all
modes of operation (disabled in test and self-check modes). If the COP
watchdog timer is selected by a mask option, any execution of the STOP
instruction (either intentional or inadvertent due to the CPU being
disturbed) will cause the oscillator to halt and prevent the COP watchdog
timer from timing out. Therefore, it is recommended that the STOP
instruction should be disabled if the COP watchdog timer is enabled.
If the COP watchdog timer is selected by a mask option, the COP will
reset the MCU when it times out. Therefore, it is recommended that the
COP watchdog should be disabled for a system that must have
intentional uses of the wait mode for periods longer than the COP
timeout period.
The recommended interactions and considerations for the COP
watchdog timer, STOP instruction, and WAIT instruction are
summarized in Figure 5-1.
Table 5-1. COP Watchdog Timer Recommendations
IF the Following Conditions Exist:
THEN the COP Watchdog
Timer Should Be:
STOP Instruction
Wait Time
Converted to Reset
WAIT Time
Less Than
COP Time-Out
Enable or Disable COP
by Mask Option
Converted to Reset
WAIT Time
More Than
COP Time-Out
Disable COP by Mask Option
Acts as STOP
Any Length
WAIT Time
Disable COP by Mask Option
5.7 Illegal Address Reset
When an opcode fetch occurs from an address which is not implemented
in the RAM ($0080–$01FF) or ROM ($0F00–$1FFF), the part is reset
automatically.
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6.1 Contents
6.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47
6.3
Single-Chip Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48
6.4
Self-Check Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48
6.5
Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48
6.5.1
Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48
6.5.2
Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49
6.5.3
Data-Retention Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49
6.2 Introduction
The MCU has two modes of operation: single-chip mode and self-check
mode. This section describes these modes as well as the two low-power
modes: stop mode and wait mode.
Refer to Table 6-1 for the conditions required to go into each of the
operating modes.
Table 6-1. Operating Mode Conditions
RESET
IRQ
PB1
Mode
VSS – VDD
VSS – VDD
Single-Chip
VTST
VDD
Self-Check
VTST = 2 x VDD
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Operating Modes
6.3 Single-Chip Mode
In single-chip mode, the address and data buses are not available
externally, but there are two 8-bit input/output (I/O) ports and one 4-bit
I/O port. This mode allows the MCU to function as a self-contained
microcontroller, with maximum use of the pins for on-chip peripheral
functions. All address and data activity occurs within the MCU.
Single-chip mode is entered on the rising edge of RESET if the IRQ pin
is within normal operating range.
Refer to Figure 1-2 for the single-chip user mode pinout diagram.
6.4 Self-Check Mode
The self-check mode provides an internal check to determine if the
device is functional.
6.5 Low-Power Modes
The following subsections provide a description of the low-power modes.
6.5.1 Stop Mode
The STOP instruction places the MCU in its lowest power-consumption
mode. In stop mode, the internal oscillator is turned off, halting all
internal processing, including timer (and COP watchdog timer)
operation.
During stop mode, the I bit in the CCR is cleared to enable external
interrupts. All other registers, including the bits in the TCSR, and
memory remain unaltered. All input/output lines remain unchanged. The
processor can be brought out of stop mode only by an external interrupt
or RESET.
The STOP instruction can be disabled by a mask option. When disabled,
the STOP instruction causes a chip reset.
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The WAIT instruction places the MCU in a low power-consumption
mode, but the wait mode consumes more power than the stop mode. All
CPU action is suspended, but the timer, CPI, COP, SSI, and M bus
remain active. An interrupt from the timer, SSI, or M bus can cause the
MCU to exit the wait mode.
During the wait mode, the I bit in the CCR is cleared to enable interrupts.
All other registers, memory, and input/output lines remain in their
previous state. The timer, SSI, and/or IIC modules may be enabled to
allow a periodic exit from the wait mode.
Refer to Figure 4-2 and to 4.11 Operation During Wait Mode for
additional information.
6.5.3 Data-Retention Mode
The contents of RAM and CPU registers are retained at supply voltages
as low as 2.0 Vdc. This is called the data-retention mode where the data
is held, but the device is not guaranteed to operate. RESET must be held
low during data-retention mode.
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6.5.2 Wait Mode
N O N - D I S C L O S U R E
Refer to Figure 4-2 and to 4.10 Operation During Stop Mode for
additional information.
R E Q U I R E D
Operating Modes
Low-Power Modes
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Operating Modes
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7.1 Contents
7.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51
7.3
Port A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51
7.4
Port B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52
7.5
Port C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52
7.6
Input/Output Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . .52
7.2 Introduction
In single-chip mode, 20 lines are arranged as two 8-bit input/output (I/O)
ports and one 4-bit I/O port. These ports are programmable as either
inputs or outputs under software control of the data direction registers.
To avoid a glitch on the output pins, write data to the I/O port data
register before writing a one to the corresponding data direction register
(DDR).
7.3 Port A
Port A is an 8-bit bidirectional port which does not share any of its pins
with other subsystems. The port A data register is at $0000 and the DDR
is at $0004. Reset does not affect the data registers, but clears the data
direction registers, thereby returning the ports to inputs. Writing a one to
a DDR bit sets the corresponding port bit to output mode.
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A G R E E M E N T
Section 7. Input/Output (I/O) Ports
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R E Q U I R E D
Input/Output (I/O) Ports
7.4 Port B
Port B is an 8-bit bidirectional port which does share some of its pins with
other subsystems. The address of the port B data register is $0001 and
the DDR is at address $0005. Reset does not affect the data registers,
but clears the data direction registers, thereby returning the ports to
inputs. Writing a one to a DDR bit sets the corresponding port bit to
output mode. Refer to Section 11. Motorola Bus (M Bus) Interface and
Section 12. Synchronous Serial Interface (SSI) for descriptions of
port B behavior while either module is enabled.
7.5 Port C
Port C is a 4-bit bidirectional port which does not share any of its pins
with other subsystems. The port C data register is at $0002 and the DDR
is at $0006. Reset does not affect the data registers, but clears the data
direction registers, thereby returning the ports to inputs. Writing a one to
a DDR bit sets the corresponding port bit to output mode.
7.6 Input/Output Programming
Ports A, B, and C may be programmed as inputs or outputs under
software control. The direction of the pins is determined by the state of
the corresponding bit in the port DDR with each port having an
associated DDR. Any port A, port B, or port C pin is configured as an
output if its corresponding DDR bit is set to a logic 1. A pin is configured
as an input if its corresponding DDR bit is cleared to a logic 0.
At power-on or reset, all DDRs are cleared, which configures all port A,
B, and C pins as inputs. The data direction registers are capable of being
written to or read from by the processor. During the programmed output
state, a read of the data register actually reads the value of the output
data latch and not the I/O pin. See Table 7-1 and Figure 7-1.
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R/W
DDR
I/O Pin Function
0
0
The I/O pin is in input mode. Data is written into the output
data latch.
0
1
Data is written into the output data latch and output of
the I/O pin.
1
0
The state of the I/O pin is read.
1
1
The I/O pin is in an output mode. The output data latch
is read.
DATA DIRECTION
REGISTER BIT
INTERNAL
HC05
CONNECTIONS
LATCHED OUTPUT
DATA BIT
OUTPUT
I/O
PIN
A G R E E M E N T
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Table 7-1. I/O Pin Functions
R E Q U I R E D
Input/Output (I/O) Ports
Input/Output Programming
INPUT
I/O
Figure 7-1. Port I/O Circuitry
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N O N - D I S C L O S U R E
INPUT
REGISTER
BIT
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Input/Output (I/O) Ports
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8.1 Contents
8.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55
8.3
Timer Control and Status Register . . . . . . . . . . . . . . . . . . . . . .57
8.4
Timer Counter Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59
8.2 Introduction
The timer for this device is a 15-stage multifunctional ripple counter. The
features include timer overflow, power-on reset (POR), and real-time
interrupt.
As seen in Figure 8-1, the timer is driven by the output of the clock select
circuit (as determined by the value of BCS in the PLLCR) and then a
fixed divide-by-four prescaler. This signal drives an 8-bit ripple counter.
The value of this 8-bit ripple counter can be read by the CPU at any time
by accessing the timer counter register (TCR) at address $09. A timer
overflow function is implemented on the last stage of this counter, giving
a possible interrupt at the rate of fop/1024. Two additional stages
produce the POR function at fop/4064.
This circuit is followed by two more stages, with the resulting clock
(fop/16,384) driving the real-time interrupt circuit. The RTI circuit consists
of three divider stages with a one-of-four selector. The RTI rate selector
bit and the RTI and TOF enable bits and flags are located in the timer
control and status register at location $0008.
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Section 8. Timer
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R E Q U I R E D
Timer
MC68HC05E4 INTERNAL BUS
8
8
$09 TCR
TIMER COUNTER REGISTER (TCR)
INTERNAL
PROCESSOR
CLOCK
fop
fop/22
TCR
÷4
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fop/210
7-BIT COUNTER
POR
TCBP
RTI SELECT CIRCUIT
OVERFLOW
DETECT
CIRCUIT
$08 TCSR
TIMER CONTROL & STATUS REGISTER
N O N - D I S C L O S U R E
TCSR
TOF
RTIF
TOFE
RTIE
TOFA RTIFA
RT1
RT0
INTERRUPT CIRCUIT
TO INTERRUPT
LOGIC
Figure 8-1. Timer Block Diagram
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Address:
$0008
Bit 7
6
5
4
3
2
1
Bit 0
TOF
RTIF
TOFE
RTIE
TOFA
RTIFA
RT1
RT0
0
0
0
0
0
0
1
1
Read:
Write:
Reset:
Figure 8-2. Timer Control and Status Register (TCSR)
TOF — Timer Over Flow
TOF is a clearable, read-only status bit and is set when the 8-bit ripple
counter rolls over from $FF to $00. A CPU interrupt request will be
generated if TOFE is set. Clearing the TOF is done by writing a logic 1
to TOFA. This is a read-only bit. Reset also clears TOF.
RTIF — Real-Time Interrupt Flag
The real-time interrupt circuit consists of a 3-stage divider and a
one-of-four selector. The clock frequency that drives the RTI circuit is
fop/213 (or fop/8192) with three additional divider stages giving a
maximum interrupt period of four seconds at a crystal frequency of
32.768 kHz. RTIF is a clearable, read-only status bit and is set when
the output of the chosen (one-of-four selection) stage goes active. A
CPU interrupt request will be generated if RTIE is set. Clearing the
RTIF is done by writing a logic 1 to RTIFA. Reset also clears RTIF.
TOFE — Timer Overflow Enable
When this bit is set, a CPU interrupt request is generated when the
TOF bit is set. Reset clears this bit.
MC68HC705E5 — Rev. 1.0
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Timer
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A G R E E M E N T
The timer control and status register (TCSR) contains the timer interrupt
flag, the timer interrupt enable bits, and the real-time interrupt rate select
bits. Figure 8-2 shows the value of each bit in the TCSR when coming
out of reset.
N O N - D I S C L O S U R E
8.3 Timer Control and Status Register
R E Q U I R E D
Timer
Timer Control and Status Register
Freescale Semiconductor, Inc.
R E Q U I R E D
Timer
RTIE — Real-Time Interrupt Enable
When this bit is set, a CPU interrupt request is generated when the
RTIF bit is set. Reset clears this bit.
TOFA — Timer Over Flow Flag Acknowledge
When a one is written to this bit location, the TOF flag bit is cleared.
This bit always reads as a zero.
RTIFA — Real-Time Interrupt Flag Acknowledge
N O N - D I S C L O S U R E
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A G R E E M E N T
When a one is written to this bit location, the RTIF flag bit is cleared.
This bit always reads as a zero.
RT1–RT0 — Real-Time Interrupt Rate Select
These two bits select one of four taps from the real-time interrupt
circuit.Table 8-1 shows the available interrupt rates with several fop
values. Reset sets RT0 and RT1, selecting the lowest periodic rate
and therefore the maximum time in which to alter these bits if
necessary. Care should be taken when altering RT0 and RT1 if the
time-out period is imminent or uncertain. If the selected tap is
modified during a cycle in which the counter is switching, an RTIF
could be missed or an additional one could be generated.
Table 8-1. RTI Rates
RT1 Rates at fop Frequency Specified
RT1–RT0
16.384 kHz
524 kHz
1.049 MHz
2.097 MHz
4.194 MHz
fop
00
1s
31.3 ms
15.6 ms
7.8 ms
3.9 ms
214 ÷ fop
01
2s
62.5 ms
31.3 ms
15.6 ms
7.8 ms
215 ÷ fop
10
4s
125 ms
62.5 ms
31.3 ms
15.6 ms
216 ÷ fop
11
8s
250 ms
125.1 ms
62.5 ms
31.3 ms
217 ÷ fop
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MC68HC705E5 — Rev. 1.0
Timer
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Address:
$0009
Bit 7
6
5
4
3
2
1
Bit 0
0
0
0
0
0
0
1
1
Read:
Write:
Reset:
= Unimplemented
Figure 8-3. Timer Counter Register (TCR)
The power-on cycle clears the entire counter chain and begins clocking
the counter. After 4064 cycles, the power-on reset circuit is released,
which again clears the counter chain and allows the device to come out
of reset. At this point, if RESET is not asserted, the timer will start
counting up from zero and normal device operation will begin. When
RESET is asserted any time during operation other than POR, the
counter chain will be cleared.
MC68HC705E5 — Rev. 1.0
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Timer
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A G R E E M E N T
The timer counter register (TCR) is a read-only register which contains
the current value of the 8-bit ripple counter at the beginning of the timer
chain. This counter is clocked at fop divided by four and can be used for
various functions including a software input capture. Extended time
periods can be attained using the TOF function to increment a temporary
RAM storage location, thereby simulating a 16-bit (or more) counter.
N O N - D I S C L O S U R E
8.4 Timer Counter Register
R E Q U I R E D
Timer
Timer Counter Register
Freescale Semiconductor, Inc.
N O N - D I S C L O S U R E
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A G R E E M E N T
R E Q U I R E D
Timer
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MC68HC705E5 — Rev. 1.0
Timer
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9.1 Contents
9.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61
9.3
Phase-Locked Loop Control Register. . . . . . . . . . . . . . . . . . . .63
9.4
Operation During Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . .65
9.5
Noise Immunity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65
9.2 Introduction
The PLL consists of a variable bandwidth loop filter, a voltage-controlled
oscillator (VCO), a feedback frequency divider, and a digital phase
detector. The PLL requires an external loop filter capacitor (typically
0.1 µF) connected between XFC and VDDSYN. This capacitor should be
located as close to the chip as possible to minimize noise. VDDSYN is the
supply source for the PLL and should be bypassed to minimize noise.
The VDDSYN bypass cap should be as close as possible to the chip.
The phase detector compares the frequency and phase of the feedback
frequency (tFB) and the crystal oscillator reference frequency (tREF) and
generates the output, PCOMP, as shown in Figure 9-1. The output
waveform is then integrated and amplified. The resultant DC voltage is
applied to the voltage controlled oscillator. The output of the VCO is
divided by a variable frequency divider of 256, 128, 64, or 32 to provide
the feedback frequency for the phase detector.
MC68HC705E5 — Rev. 1.0
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Phase-Locked Loop (PLL) Synthesis
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A G R E E M E N T
Section 9. Phase-Locked Loop (PLL) Synthesis
N O N - D I S C L O S U R E
General Release Specification — MC68HC705E5
R E Q U I R E D
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N O N - D I S C L O S U R E
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A G R E E M E N T
R E Q U I R E D
Phase-Locked Loop (PLL) Synthesis
VDDSYN
0.1 µF
tREF
OSC1
CRYSTAL
OSCILLATOR
0.1 µF
XFC
PCOMP
PHASE
DETECT
LOOP FILTER
OSC1
VCO
PLLOUT
CLOCK
SELECT
÷2
TO CLOCK
GENERATION
CIRCUITRY
BCS
tFB
FREQUENCY
DIVIDER
PS1
PS0
Figure 9-1. PLL Circuit
To change PLL frequencies, follow the procedure outlined here:
1. Clear BCS to enable the low-frequency bus rate.
2. Clear PLLON to disable the PLL and select high bandwidth.
3. Select the speed using PS1 and PS0.
4. Set PLLON to enable the PLL.
5. Wait a time of 90% tPLLS for the PLL frequency to stabilize and
select manual low bandwidth, wait another 10% tPLLS.
6. Set BCS to switch to the high-frequency bus rate
The user cannot switch among the high speeds with the BCS bit set.
Following the procedure above will prevent possible bursts of
high-frequency operation during the re-configuration of the PLL.
Whenever the PLL is first enabled, the wide bandwidth mode should be
used. This enables the PLL frequency to ramp up quickly. When the
output frequency is near the desired frequency, the filter is switched to
the narrow bandwidth mode to make the final frequency more stable.
General Release Specification
MC68HC705E5 — Rev. 1.0
Phase-Locked Loop (PLL) Synthesis
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9.3 Phase-Locked Loop Control Register
This read/write register contains the control bits which select the PLL
frequency and enable/disable the synthesizer.
Address:
$0007
Bit 7
6
5
4
3
2
1
Bit 0
0
BCS
0
BWC
PLLON
VCOTST
PS1
PS0
0
0
0
0
1
1
0
1
Read:
R E Q U I R E D
Phase-Locked Loop (PLL) Synthesis
Phase-Locked Loop Control Register
Figure 9-2. Phase-Locked Loop Control Register (PLLCR)
BCS — Bus Clock Select
When this bit is set, the output of the PLL is used to generate the
internal processor clock. When clear, the internal bus clock is driven
by the crystal (OSC1 ÷ 2). Once BCS has been changed, it may take
up to 1.5 OSC1 cycles + 1.5 PLLOUT cycles to make the transition.
During the transition, the clock select output will be held low and all
CPU and timer activity will cease until the transition is complete.
Before setting BCS, allow at least a time of tPLLS after PLLON is set.
This bit cannot be set unless the PLLON bit is already set on a
previous instruction. Reset clears this bit.
BWC — Bandwidth Control
This bit selects high bandwidth control when set and low bandwidth
control when clear. The low bandwidth driver is always enabled, so
this bit determines whether the high bandwidth driver is on or off.
When the PLL is turned on, the BWC bit should be set to a logic 1 for
a time of 90% tPLLS to allow the PLL time to acquire a frequency close
to the desired frequency. The BWC bit should then be cleared and
software should delay for a time 10% tPLLS to allow the PLL time to
make the final adjustments. The PLL clock cannot be used (BCS bit
set). Although it is NOT prohibited in hardware, the BCS bit should not
be set unless the BWC bit is cleared and the proper delay times have
been followed. The PLL will generate a lower jitter clock when the
BWC bit is cleared. Reset clears this bit.
MC68HC705E5 — Rev. 1.0
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Phase-Locked Loop (PLL) Synthesis
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A G R E E M E N T
Reset:
N O N - D I S C L O S U R E
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Write:
Freescale Semiconductor, Inc.
PLLON — PLL On
This bit activates the synthesizer circuit without connecting it to the
control circuit. This allows the synthesizer to stabilize before it can
drive the CPU clocks. When this bit is cleared, the PLL is shut off and
the BCS bit cannot be set. (Setting the BCS bit would engage the
disabled PLL onto the bus.) Reset sets this bit.
NOTE:
PLLON cannot be cleared unless the BCS bit has been cleared on a
previous write to the register.
VCOTST — VCO Test
This bit is used to isolate the loop filter from the VCO to facilitate
testing. When cleared only in test or self-check modes, the low
bandwidth mode of the PLL filter is disabled. When set, the loop filter
operates as indicated by the value of the BWC bit. Reset sets this bit.
NOTE:
This bit is intended for use by Motorola to test and characterize the PLL.
This bit cannot be cleared in user mode.
PS1–PS0 — PLL Synthesizer Speed Select
These two bits select one-of-four taps from the PLL to drive the CPU
clocks. These bits are used in conjunction with PLLON and BCS bits
in the PLL control register. These bits should not be written if BCS in
the PLLCR is at a logic high. Reset clears PS1 and sets PS0,
choosing a bus clock frequency of 1.049 MHz.
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A G R E E M E N T
R E Q U I R E D
Phase-Locked Loop (PLL) Synthesis
Table 9-1. PS1 and PS0 Speed Selects with 32.768-kHz Crystal
CPU Bus Clock Frequency (fop)
PS1–PS0
0 0
524 kHz
0 1
1.049 MHz
Reset Condition
1 0
2.097 MHz
See Note Below
1 1
4.194 MHz
See Note Below
NOTE:
For the standard MC68HC705E5, the 4.194-MHz bus clock frequency should never be selected, and the 2.097-MHz bus clock frequency should not be selected
when running the part below V
= 4.5 V.
DD
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MC68HC705E5 — Rev. 1.0
Phase-Locked Loop (PLL) Synthesis
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9.4 Operation During Stop Mode
The PLL is switched to low-frequency bus rate and is temporarily turned
off when STOP is executed. Coming out of stop mode with an external
IRQ, the PLL is turned on with the same configuration it had before going
into STOP, with the exception of BCS which is reset. Otherwise, the PLL
control register is in the reset condition.
R E Q U I R E D
Phase-Locked Loop (PLL) Synthesis
Operation During Stop Mode
1. The application environment should be designed so that the MCU
is not near signal traces which switch often, such as a clock signal.
2. The oscillator circuit for the MCU should be placed as close as
possible to the OSC1 and OSC2 pins on the MCU.
3. All power pins should be filtered (to minimize noise on these
signals) by using bypass capacitors placed as close as possible to
the MCU.
See the application note Designing for Electromagnetic Compatibility
(EMC) with HCMOS Microcontrollers available through the Motorola
Literature Distribution Center, Motorola document number AN1050/D.
MC68HC705E5 — Rev. 1.0
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Phase-Locked Loop (PLL) Synthesis
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A G R E E M E N T
The MCU should be insulated as much as possible from noise in the
system. We recommend the following steps be taken to help prevent
problems due to noise injection.
N O N - D I S C L O S U R E
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9.5 Noise Immunity
Freescale Semiconductor, Inc.
N O N - D I S C L O S U R E
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A G R E E M E N T
R E Q U I R E D
Phase-Locked Loop (PLL) Synthesis
General Release Specification
MC68HC705E5 — Rev. 1.0
Phase-Locked Loop (PLL) Synthesis
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10.1 Contents
10.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67
10.3
System Control and Status Register. . . . . . . . . . . . . . . . . . . . .68
10.4
COP During Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .70
10.5
COP During Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .70
10.2 Introduction
The COP watchdog system is a mask-programmable feature which will
generate a system reset if not serviced within the specified COP timeout
period. The COP counter chain is derived from an output of the CPI
circuit. This input signal is divided to give the COP reset rate selected by
the first write to the system control and status register (SCSR) located at
address $13.
A COP reset is done by writing a logic 0 to bit zero of address $1FF0.
This will reset the COP counter chain and begin the timeout countdown
again. The COP counter chain is also cleared when the MCU is in reset
or stop mode.
MC68HC705E5 — Rev. 1.0
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Computer Operating Properly (COP) Watchdog
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A G R E E M E N T
Section 10. Computer Operating Properly (COP)
Watchdog
N O N - D I S C L O S U R E
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A G R E E M E N T
R E Q U I R E D
Computer Operating Properly (COP) Watchdog
10.3 System Control and Status Register
The SCSR is a read/write register containing the control flags for the
COP rate, COP inhibit, and IRQ level and status flags indicating the
cause of the last reset. Figure 10-1 shows the value of each bit in the
SCSR when coming out of reset.
Address:
$0013
Bit 7
6
5
4
3
2
1
Bit 0
0
0
0
STOPR
ILADR
COPR
CRS1
CRS0
0
0
0
R
R
R
0
0
Read:
Write:
Reset:
R = Determined by cause of previous reset
Figure 10-1. System Control and Status Register (SCSR)
NOTE:
The debounce time for the IRQ input must be shorter than the COP
timeout period.
STOPR — Illegal STOP Instruction Reset
STOPR is a read-only status bit. This bit is set by the execution of a
STOP instruction when the STOP instruction option is disabled. This
bit is cleared by POR, external reset, or COP reset.
1 = Last reset was the execution of a disabled STOP instruction.
0 = Last reset was not the execution of a disabled STOP
instruction.
ILADR — Illegal Address Reset
ILADR is a read-only status bit. This bit is set by an ILADR reset, but
is cleared by POR, external reset, or COP reset.
1 = Last reset was an ILADR reset.
0 = Last reset was not an ILADR reset.
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NOTE:
The COP watchdog reset is a mask option. Therefore, a COP reset will
only occur when this option is enabled. This option cannot be disabled
by software.
CRS1 and CRS0 — COP Rate Select
The value of these two bits determines the COP timeout rate. These
bits can be written only on the first write to this register after reset. If
these bits are never written to, the COP reset rate will be set at one
second. The COP counter chain is cleared when these bits are
written.
NOTE:
Although these bits default to zero, the user should write to these bits to
prevent subsequent writes from changing the COP rate.
A bit set/clear for any bit in this register is executed as a
read-modify-write of this register. If used as the first write to this register,
further writes to CRS1 and CRS0 would not be valid, and the default
value would be set.
Table 10-1. COP Rates at fosc = 32.768 kHz
CRS1
CRS0
Minimum COP Rate
0
0
1 second
0
1
2 seconds
1
0
4 seconds
1
1
8 seconds
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Computer Operating Properly (COP) Watchdog
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A G R E E M E N T
COPR is a read-only status bit. This bit is set by a COP reset, but is
cleared by POR, external reset, or illegal address reset.
1 = Last reset was a COP reset.
0 = Last reset was not a COP reset.
N O N - D I S C L O S U R E
COPR — COP Reset
R E Q U I R E D
Computer Operating Properly (COP) Watchdog
System Control and Status Register
Freescale Semiconductor, Inc.
10.4 COP During Wait Mode
The CPU clock halts during wait mode, but the oscillator and the COP
system are still active. The software should exit wait mode to service the
COP system before the COP timeout period.
10.5 COP During Stop Mode
Prior to entry into stop mode, the COP should be cleared. This allows for
proper stop recovery and eliminates a possible COP time-out during
stop mode recovery, if the COP was about to time out prior to the STOP
instruction. If enabled, stop mode turns off the oscillator and, therefore,
will stop the COP.
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A G R E E M E N T
R E Q U I R E D
Computer Operating Properly (COP) Watchdog
General Release Specification
MC68HC705E5 — Rev. 1.0
Computer Operating Properly (COP) Watchdog
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11.1 Contents
11.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72
11.3
M-Bus Interface Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73
11.4
M-Bus System Configuration . . . . . . . . . . . . . . . . . . . . . . . . . .73
11.5 M-Bus Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73
11.5.1
Start Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .74
11.5.2
Slave Address Transmission. . . . . . . . . . . . . . . . . . . . . . . .75
11.5.3
Data Transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .75
11.5.4
Repeated Start Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . .76
11.5.5
Stop Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .76
11.5.6
Arbitration Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . .76
11.5.7
Clock Synchronization. . . . . . . . . . . . . . . . . . . . . . . . . . . . .77
11.5.8
Handshaking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .77
11.6 M-Bus Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .78
11.6.1
M-Bus Address Register . . . . . . . . . . . . . . . . . . . . . . . . . . .78
11.6.2
M-Bus Frequency Divider Register . . . . . . . . . . . . . . . . . . .80
11.6.3
M-Bus Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . .82
11.6.4
M-Bus Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . .84
11.6.5
M-Bus Data I/O Register . . . . . . . . . . . . . . . . . . . . . . . . . . .86
11.7
M-Bus Pin Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .88
11.8 Programming Considerations . . . . . . . . . . . . . . . . . . . . . . . . . .88
11.8.1
Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .88
11.8.2
Generation of a Start Signal and the First Byte
of Data Transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .89
11.8.3
Software Responses after Transmission
or Reception of a Byte . . . . . . . . . . . . . . . . . . . . . . . . . .90
11.8.4
Generation of the Stop Signal . . . . . . . . . . . . . . . . . . . . . . .91
11.8.5
Generation of a Repeated Start Signal . . . . . . . . . . . . . . . .92
MC68HC705E5 — Rev. 1.0
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Motorola Bus (M Bus) Interface
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A G R E E M E N T
Section 11. Motorola Bus (M Bus) Interface
N O N - D I S C L O S U R E
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A G R E E M E N T
R E Q U I R E D
Motorola Bus (M Bus) Interface
11.8.6
11.8.7
11.9
Slave Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .92
Arbitration Lost . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .92
Operation During Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . .93
11.10 Operation During Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . .93
11.2 Introduction
Motorola bus (M bus) is a 2-wire, bidirectional serial bus which provides
a simple, efficient way for data exchange between devices. It is fully
compatible to I2C bus standards and is similar to the MC68HC05T10.
This bus is suitable for applications that require frequent
communications over a short distance between a number of devices. It
also provides a flexibility that allows additional devices to be connected
to the bus. The maximum data rate is limited to 100 Kbits and the
maximum communication distance and number of devices that can be
connected is limited by the maximum bus capacitance of 400 pF.
The M-bus system is a true multimaster bus including collision detection
and arbitration to prevent data corruption if two or more masters intend
to control the bus simultaneously. This feature provides the capability for
complex applications with multiprocessor control. It may also be used for
rapid testing and alignment of end products by way of external
connections to an assembly-line computer.
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MC68HC705E5 — Rev. 1.0
Motorola Bus (M Bus) Interface
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•
Fully Compatible with I2C Bus Standard
•
Multimaster Operation
•
Software Programmable for 1of 32 Different Serial Clock
Frequencies
•
Software Selectable Acknowledge Bit
•
Interrupt Driven Byte-by-Byte Data Transfer
•
Arbitration Lost Driven Interrupt with Automatic Mode Switching
from Master to Slave
•
Calling Address Identification Interrupt
•
Generate/Detect the Start or Stop Signal
•
Repeated Start Signal Generation
•
Generate/Recognize the Acknowledge Bit
•
Bus Busy Detection
11.4 M-Bus System Configuration
The M-bus system uses a serial data line (SDA) and a serial clock line
(SCL) for data transfer. All devices connected to it must have open-drain
or open-collector outputs and the logical AND function is performed on
both lines by two pullup resistors.
11.5 M-Bus Protocol
Normally, a standard communication is composed of four parts: start
signal, slave address transmission, data transfer, and stop signal. These
are described briefly in the following subsections and illustrated in
Figure 11-1.
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A G R E E M E N T
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Features of the M-bus interface include:
N O N - D I S C L O S U R E
11.3 M-Bus Interface Features
R E Q U I R E D
Motorola Bus (M Bus) Interface
M-Bus Interface Features
Freescale Semiconductor, Inc.
N O N - D I S C L O S U R E
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A G R E E M E N T
R E Q U I R E D
Motorola Bus (M Bus) Interface
11.5.1 Start Signal
When the bus is free (for example, no master device is engaging the bus
and both SCL and SDA lines are at logical high), a master may initiate
communication by sending a start signal. As shown in Figure 11-1, a
start signal is defined as a high-to-low transition of SDA while SCL is
high. This signal denotes the beginning of new data transfer (each data
transfer may contain several bytes of data) and wakes up all slaves.
MSB
SCL
1
1
0
0
0
0
1
LSB
MSB
1
1
LSB
1
0
0
0
0
ACKNOWLEDGE BIT
1
1
NO ACKNOWLEDGE
SDA
START SIGNAL
STOP SIGNAL
MSB
SCL
1
1
0
0
0
0
1
LSB
MSB
1
1
LSB
1
0
0
0
0
1
ACKNOWLEDGE BIT
1
NO ACKNOWLEDGE
SDA
START SIGNAL
REPEATED START SIGNAL
STOP SIGNAL
Figure 11-1. M-Bus Transmission Signal Diagram
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Only the slave with a matched address will respond by sending back an
acknowledge bit. This acknowledge bit is accomplished by pulling SDA
low on the ninth clock cycle. (See Figure 11-1.)
11.5.3 Data Transfer
Once a successful slave addressing is achieved, the data transfer can
proceed byte by byte in the direction specified by the R/W bit sent by the
calling master.
Each data byte is eight bits long. Data can be changed only when SCL
is low and must be held stable while SCL is high as shown in Figure
11-1. The MSB is transmitted first and each byte has to be followed by
an acknowledge bit. The acknowledge bit is signalled by the receiving
device by pulling the SDA low on the ninth clock cycle. Therefore, one
complete data byte transfer needs nine clock cycles.
If the slave receiver does not acknowledge the master, the SDA line
should be left high by the slave. The master can then generate a stop
signal to abort the data transfer or a start signal (repeated start) to
commence a new transfer.
If the master receiver does not acknowledge the slave transmitter after
a byte has been transmitted, it means an “end of data” to the slave. The
slave should now release the SDA line for the master to generate a stop
or start signal.
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Immediately after the start signal, the first byte of data transfer is the
slave address transmitted by the master. This data is a 7-bit calling
address followed by a R/W bit. The R/W bit tells the slave the desired
direction of data transfer.
N O N - D I S C L O S U R E
11.5.2 Slave Address Transmission
R E Q U I R E D
Motorola Bus (M Bus) Interface
M-Bus Protocol
Freescale Semiconductor, Inc.
R E Q U I R E D
Motorola Bus (M Bus) Interface
11.5.4 Repeated Start Signal
As shown in Figure 11-1, a repeated start signal is used to generate a
start signal without first generating a stop signal to terminate the
communication. This is used by the master to communicate with another
slave or with the same slave in a different mode (transmit/receive mode)
without releasing the bus.
N O N - D I S C L O S U R E
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A G R E E M E N T
11.5.5 Stop Signal
The master can terminate the communication by generating a stop
signal to free the bus. However, the master may generate a start signal
followed by a calling command without first generating a stop signal.
This is called repeat start. A stop signal is defined as a low-to-high
transition of SDA while SCL is at logical high. (See Figure 11-1.)
11.5.6 Arbitration Procedure
This interface circuit is a true multimaster system which allows more
than one master to be connected to it. If two or more masters try to
control the bus at the same time, a clock synchronization procedure
determines the bus clock, for which the low period is equal to the longest
clock low period and the high is equal to the shortest one among the
masters. A data arbitration procedure determines the priority. The
masters will lose arbitration if they transmit a logic 1 while another
transmits logic 0. The losing masters will immediately switch over to
slave receive mode and stop its data and clock outputs. In this case, the
transition from master to slave mode will not generate a stop condition;
however, a software bit will be set by hardware to indicate loss of
arbitration.
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11.5.8 Handshaking
The clock synchronization mechanism can be used as a handshake in
data transfer. Slave devices may hold the SCL low after completion of
one byte. In such cases, the device will halt the bus clock and force the
master clock into a wait state until the slave releases the SCL line.
START COUNTING HIGH PERIOD
WAIT
SCL1
SCL2
SCL
INTERNAL COUNTER RESET
Figure 11-2. Clock Synchronization
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A G R E E M E N T
Since wired-AND logic is performed on the SCL line, a high-to-low
transition will affect the devices connected to the bus. The devices start
counting their low period and once a device's clock has gone low, it will
hold the SCL line low until the clock high state is reached. However, the
change of low to high in this device clock may not change the state of
the SCL line if another device clock is still within its low period.
Therefore, the synchronized clock SCL will be held low by the device
with the longest low period. Devices with shorter low periods enter a high
wait state during this time. (See Figure 11-2.) When all devices
concerned have counted off their low period, the synchronized SCL line
will be released and go high. There will then be no difference between
the device clocks and the state of the SCL line and all devices will start
counting their high periods. The first device to complete its high period
will again pull the SCL line low.
N O N - D I S C L O S U R E
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11.5.7 Clock Synchronization
R E Q U I R E D
Motorola Bus (M Bus) Interface
M-Bus Protocol
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A G R E E M E N T
R E Q U I R E D
Motorola Bus (M Bus) Interface
11.6 M-Bus Registers
Five different registers are used in the M-bus interface. The internal
configuration of these registers is discussed in the following paragraphs.
NOTE:
The register addresses show only the low-order address bits (for
example ABL3–ABL0). The registers can be placed anywhere in the
device memory map by generating an appropriate module select signal
in the map logic.
A block diagram of the M-bus system is shown in Figure 11-3.
11.6.1 M-Bus Address Register
Address:
$0018
Bit 7
6
5
4
3
2
1
MAD7
MAD6
MAD5
MAD4
MAD3
MAD2
MAD1
0
0
0
0
0
0
0
Bit 0
Read:
Write:
Reset:
—
= Unimplemented
Figure 11-3. M-Bus Address Register (MADR)
Bit 1–Bit 7
Each of these bits contains its own specific slave address. This
register is cleared upon reset.
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M
S
T
A
M
T
X
T
X
A
K
SDA CONTROL
M
C
F
M
A
A
S
M
B
B
M
A
L
S
R
W
M
I
F
R
X
A
K
TRANSMITTER
CONTROL
TRANSMITTER
SHIFT REGISTER
FREQUENCY DIVIDER
REGISTER
A G R E E M E N T
Figure 11-4. M-Bus Interface Block Diagram
START, STOP GENERATOR &
TIMING SYNC
M-BUS CLOCK GENERATOR
SYNC LOGIC
M-BUS INTERRUPT
START, STOP DETECTOR &
ARBITRATION
SCL CONTROL
M
I
E
N
STATUS REGISTER
N O N - D I S C L O S U R E
SDA
SCL
INTERRUPT
M
E
N
CONTROL REGISTER
DATA BUS
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R E Q U I R E D
RECEIVER
CONTROL
RECEIVER
SHIFT REGISTER
ADDRESS
COMPARATOR
ADDRESS
REGISTER
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Motorola Bus (M Bus) Interface
M-Bus Registers
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R E Q U I R E D
Motorola Bus (M Bus) Interface
11.6.2 M-Bus Frequency Divider Register
Address:
Bit 7
A G R E E M E N T
6
5
4
3
2
1
Bit 0
FD4
FD3
FD2
FD1
FD0
0
0
0
0
0
Read:
Write:
Reset:
—
—
—
= Unimplemented
Figure 11-5. M-Bus Frequency Divider Register (MFDR)
Bit 0–Bit 4
These bits are used for clock rate selection. The serial bit clock
frequency is equal to the CPU clock divided by the divider shown in
Table 11-1. This register is cleared upon reset.
For a 4-MHz external crystal operation (2-MHz internal operating
frequency), the serial bit clock frequency of the M-bus ranges from
460 Hz to 90,909 Hz.
N O N - D I S C L O S U R E
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$0019
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FD4, FD3, FD2, FD1, FD0
Divider
00000
22
10000
352
00001
24
10001
384
00010
28
10010
448
00011
34
10011
544
00100
44
10100
704
00101
48
10101
768
00110
56
10110
896
00111
68
10111
1088
01000
88
11000
1408
01001
96
11001
1536
01010
112
11010
1792
01011
136
11011
2176
01100
176
11100
2816
01101
192
11101
3072
01110
224
11110
3584
01111
272
11111
4352
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A G R E E M E N T
Divider
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FD4, FD3, FD2, FD1, FD0
N O N - D I S C L O S U R E
Table 11-1. M-Bus Clock Prescaler
R E Q U I R E D
Motorola Bus (M Bus) Interface
M-Bus Registers
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N O N - D I S C L O S U R E
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A G R E E M E N T
R E Q U I R E D
Motorola Bus (M Bus) Interface
11.6.3 M-Bus Control Register
The M-bus control register (MCR) provides five control bits and is
cleared upon reset.
Address:
$001A
Bit 7
6
5
4
3
2
MEN
MIEN
MSTA
MTX
TXAK
MMUX
0
0
0
0
0
0
1
Bit 0
—
—
Read:
Write:
Reset:
= Unimplemented
Figure 11-6. M-Bus Control Register (MCR)
MEN — M-Bus Enable Bit
If MEN is set, the M-bus interface system is enabled. If MEN is
cleared, the interface is reset and disabled. The MEN bit must be set
first before any bits of MCR are set.
MIEN — M-Bus Interrupt Enable Bit
If MIEN is set, an interrupt occurs provided the MIF flag in the status
register is set and the I bit in the condition code register is cleared. If
MIEN is cleared, the M-bus interrupt is disabled.
MSTA — Master/Slave Mode Select Bit
Upon reset, this bit is cleared. When this bit is changed from a logic 0
to a logic 1, a start signal is generated on the bus, and master mode
is selected. When this bit is changed from a logic 1 to a logic 0, a stop
signal is generated and the operating mode changes from master to
slave.
In master mode, a bit clear immediately followed by a bit set
generates a repeated start signal (see Figure 11-1) without
generating a stop signal.
1 = Master
0 = Slave
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MTX — Transmit/Receiver Mode Select Bit
This bit selects the direction of master and slave transfers. When
addressed as a slave, this bit should be set by software according to
the SRW bit in the status register. In master mode, this bit should be
set according to the type of transfer required. Hence, for address
cycles this bit will always be high.
1 = Transmit
0 = Receive
R E Q U I R E D
Motorola Bus (M Bus) Interface
M-Bus Registers
MMUX — M-Bus Multiplexer
This bit is used to enable PB7 and PB6 to be under the control of the
M-bus circuit. When set, both PB7 and PB6 become open-collector
outputs or inputs when enabled by the M-bus control. When cleared
PB7 and PB6 are under control of the port DDR logic. This bit can be
set or cleared independent of the MEN bit. Caution should be used if
PB7 and PB6 are used as general-purpose I/O.
1 = M-bus control
0 = POR condition, port B DDR control
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A G R E E M E N T
If TXAK is cleared, an acknowledge signal will be sent out to the bus
at the ninth clock bit after receiving one byte of data. When TXAK is
set, there will be no acknowledge signal response (for example,
acknowledge bit = 1).
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TXAK — Transmit Acknowledge Enable Bit
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R E Q U I R E D
Motorola Bus (M Bus) Interface
11.6.4 M-Bus Status Register
This status register is software readable only with exception of bit 1
(MIF) and bit 4 (MAL) which are software clearable. All bits are cleared
upon reset except bit 7 (MCF) and bit 0 (RXAK).
Address:
N O N - D I S C L O S U R E
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A G R E E M E N T
Read:
$001B
Bit 7
6
5
4
MCF
MAAS
MBB
MAL
Write:
Reset:
3
2
1
Bit 0
SRW
MIF
RXAK
MAL CLR
1
0
0
0
MIF CLR
—
0
0
1
= Unimplemented
Figure 11-7. M-Bus Status Register (MSR)
MCF — Data Transferring Bit
While one byte of data is being transferred, this bit is cleared. It is set
by the falling edge of the ninth clock of a byte transfer.
1 = Transfer complete
0 = Transfer in progress
MAAS — Addressed as a Slave Bit
When its own specific address (MADR) is matched with the calling
address, this bit is set. The CPU is interrupted provided MIEN is set.
Then CPU needs to check the SRW bit and set its TX/RX mode
accordingly.
1 = Addressed as a slave
0 = Not addressed
Writing to the M-bus control register clears this bit.
MBB — Bus Busy Bit
This bit indicates the status of the bus. When a start signal is
detected, the MBB is set. If a stop signal is detected, it is cleared.
1 = Bus busy
0 = Bus idle
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SRW — R/W Command Bit
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When MAAS is set, the R/W command bit of the calling address (sent
from master) is latched into the R/W command bit (SRW). Checking
this bit, the CPU can select the slave transmit/receive mode
according to the command of master.
1 = Slave transmit, master reading from slave
0 = Slave receive, master writing to slave
MIF — M-Bus Interrupt Bit
MIF is set when an interrupt is pending. This will cause an M-bus
interrupt request provided MIEN is set. This bit is set when one of the
following events occurs:
– Transmission of one byte is completed. The bit is set at the
falling edge of the ninth clock.
– Reception of a calling address which matches its own specific
address in slave receive mode.
– Arbitration is lost.
This bit must be cleared by writing a logic 0 to it.
RXAK — Receive Acknowledge Bit
If RXAK is low, it indicates an acknowledge signal has been received
after the completion of an 8-bit data transmission on the bus. If RXAK
is high, it means no acknowledge signal is detected at the ninth clock.
1 = No acknowledge received
0 = Acknowledge received
RXAK is set upon reset.
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MAL is set by hardware when the arbitration procedure is lost during
a master transmission. This bit must be cleared by software.
N O N - D I S C L O S U R E
MAL — Arbitration Lost Bit
R E Q U I R E D
Motorola Bus (M Bus) Interface
M-Bus Registers
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R E Q U I R E D
Motorola Bus (M Bus) Interface
11.6.5 M-Bus Data I/O Register
Address:
$001C
Bit 7
6
5
4
3
2
1
Bit 0
MD7
MD6
MD5
MD4
MD3
MD2
MD1
MD0
Read:
Reset:
Unaffected by Reset
Figure 11-8. M-Bus Data I/O Register (MDR)
In master transmit mode, data written to this register is sent (MSB first)
to the bus automatically. In master receive mode, reading from this
register initiates reception of the next byte of data. This is accomplished
by holding the SCL clock line low until a read of this register occurs.
Once the data is read, the device releases the SCL line to allow the
transmitting device to transmit the next byte. In slave mode, the same
function is available after it is addressed.
N O N - D I S C L O S U R E
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A G R E E M E N T
Write:
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R E Q U I R E D
Motorola Bus (M Bus) Interface
M-Bus Registers
CLEAR MIF
RX
TX/RX
Y
LAST BYTE
TRANSMITTED
N
Y
LAST BYTE
TO BE READ
ARBITRATION
LOST
N
CLEAR MAL
Y
Freescale Semiconductor, Inc...
Y
N
N
RXAK=0
N
MAAS = 1
Y
SET TXAK = 1
RX
TX/RX
Y (READ)
N
WRITE NEXT
BYTE TO MDR
N
Y
LAST 2nd BYTE
TO BE READ
N
MAAS = 1
TX
SRW = 1
GENERATE
STOP SIGNAL
READ MDR
AND STORE
N (WRITE)
SET
TX MODE
GENERATE
STOP SIGNAL
Y
WRITE
TO MDR
N
TX NEXT
BYTE
SET
RX MODE
READ DATA FROM
MDR AND STORE
ACK FROM
RECEIVER
DUMMY READ
FROM MDR
SWITCH TO
RX MODE
DUMMY READ
FROM MDR
RTI
Figure 11-9. Flowchart of M-Bus Interrupt Routine
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A G R E E M E N T
TX
MASTER
MODE
N O N - D I S C L O S U R E
Y
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R E Q U I R E D
Motorola Bus (M Bus) Interface
11.7 M-Bus Pin Configuration
When the M-bus interface is enabled with the MEN bit and the MMUX bit
in the M-bus control register (MCR), the port B data direction register bits
6 and 7 relinquish control to the M-bus control register bits. Enabling the
M-bus does not alter the state of the port B DDR bits.
Programming considerations are discussed in the following subsections.
11.8.1 Initialization
Initialization is accomplished using the following steps:
1. Update frequency divider register (MFDR) to select an SCL
frequency.
2. Update M-bus address register (MADR) to define its own slave
address.
3. Set MEN bit of the M-bus control register (MCR) to enable the
M-bus interface system and set the MMUX bit to allow M-bus
control of the PB7 and PB6 pins.
N O N - D I S C L O S U R E
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A G R E E M E N T
11.8 Programming Considerations
4. Modify the M-bus control register (MCR) bits to select
master/slave mode, transmit/receive mode, interrupt enable, or
not.
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After completion of the initialization procedure, serial data can be
transmitted by selecting the master transmitter mode. If the device is
connected to a multimaster bus system, the state of the M-bus busy bit
(MBB) must be tested to check whether the serial bus is free. If the bus
is free (MBB = 0), the start condition and the first byte (the slave address)
can be sent.
Freescale Semiconductor, Inc...
An example of a program which generates the start signal and transmits
the first byte of data (slave address) is shown here. (The MMUX bit must
be set to allow control of PB7 and PB6 pins.)
CHFALG
TXSTART
SEI
BRSET
BSET
BSET
LDA
STA
DISABLE INTERRUPT
CHECK THE MBB BIT OF THE
STATUS REGISTER. IF IT IS
SET, WAIT UNTIL IT IS CLEAR
SET TRANSMIT MODE
SET MASTER MODE
i.e., GENERATE START CONDITION
GET THE CALLING ADDRESS
TRANSMIT THE CALLING
ADDRESS
ENABLE INTERRUPT
N O N - D I S C L O S U R E
CLI
;
5,MSR,CHFLAG;
;
;
4,MCR
;
5,MCR
;
;
#CALLING
;
MDR
;
;
;
A G R E E M E N T
11.8.2 Generation of a Start Signal and the First Byte of Data Transfer
R E Q U I R E D
Motorola Bus (M Bus) Interface
Programming Considerations
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11.8.3 Software Responses after Transmission or Reception of a Byte
Transmission or reception of a byte will set the data transferring bit
(MCF) to a logic 1, which indicates one byte of communication is
finished. Also, the M-bus interrupt bit (MIF) is set to generate an M-bus
interrupt if the interrupt function is enabled during initialization. Software
must clear the MIF bit in the interrupt routine first. The MCF bit will be
cleared by reading from the M-bus data I/O register (MDR) in receive
mode or writing to MDR in transmit mode. Software may serve the M-bus
I/O in the main program by monitoring the MIF bit if the interrupt function
is disabled.
The following is an example of a software response by a master
transmitter in the interrupt routine. See Figure 11-9.
ISR
BCLR
BRCLR
1,MSR
5,MCR,SLAVE
BRCLR
4,MCR,RECEIVE
BRSET
0,MSR,END
TRANSMIT LDA
STA
DATABUF
MDR
;
;
;
;
;
;
;
;
;
;
CLEAR THE MIF FLAG
CHECK THE MSTA FLAG,
BRANCH IF SLAVE MODE
CHECK THE MODE FLAG,
BRANCH IF IN RECEIVE MODE
CHECK ACK FROM RECEIVER
IF NO ACK, END OF
TRANSMISSION
GET THE NEXT BYTE OF DATA
TRANSMIT THE DATA
N O N - D I S C L O S U R E
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A G R E E M E N T
R E Q U I R E D
Motorola Bus (M Bus) Interface
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The following is an example showing how a stop condition is generated
by a master transmitter.
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MASTX
END
EMASTX
BRSET
LDA
0,MSR,END
TXCNT
BEQ
END
LDA
STA
DEC
BRA
BCLR
RTI
DATABUF
MDR
TXCNT
EMASTX
5,MCR
;
;
;
;
;
;
;
;
;
;
;
IF NO ACK, BRANCH TO END
GET VALUE FROM THE
TRANSMITTING COUNTER
IF NO MORE DATA, BRANCH TO
END
GET NEXT BYTE OF DATA
TRANSMIT THE DATA
DECREASE THE TXCNT
EXIT
GENERATE A STOP CONDITION
RETURN FROM INTERRUPT
If a master receiver wants to terminate a data transfer, it must inform the
slave transmitter by not acknowledging the last byte of data. This can be
done by setting the transmit acknowledge bit (TXAK) before reading the
second to the last byte of data. Before reading the last byte of data, a
stop signal must be generated first.
The following is an example showing how a stop signal is generated by
a master receiver.
MASR
RXCNT
ENMASR
RXCNT
; LAST BYTE TO BE READ
LAMAR
DEC
BEQ
LDA
DECA
BNE
BSET
NXMAR
3,MCR
;
;
;
;
ENMASR
BRA
BCLR
NXMAR
5,MCR
LDA
STA
RTI
MDR
RXBUF
NXMAR
CHECK LAST 2ND BYTE TO BE READ
NOT LAST ONE OR LAST SECOND
LAST SECOND, DISABLE ACK
TRANSMITTING
; LAST ONE, GENERATE 'STOP'
; SIGNAL
; READ DATA AND STORE
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A data transfer ends with a stop signal generated by the master device.
A master transmitter can simply generate a stop signal after all the data
has been transmitted.
N O N - D I S C L O S U R E
11.8.4 Generation of the Stop Signal
R E Q U I R E D
Motorola Bus (M Bus) Interface
Programming Considerations
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A G R E E M E N T
R E Q U I R E D
Motorola Bus (M Bus) Interface
11.8.5 Generation of a Repeated Start Signal
If at the end of data transfer the master still wants to communicate on the
bus, it can generate another start signal followed by another slave
address without first generating a stop signal. A program example is
shown here.
RESTART
BCLR
BSET
5,MCR
5,MCR
LDA
STA
#CALLING
MDR
;
;
;
;
;
;
ANOTHER START (RESTART) IS
GENERATED BY THESE TWO
CONSEQUENCE INSTRUCTION
GET THE CALLING ADDRESS
TRANSMIT THE CALLING
ADDRESS
11.8.6 Slave Mode
In the slave service routine, the master addressed as slave bit (MAAS)
should be tested to see if a calling of its own address has just been
received. If MAAS is set, software should set the transmit/receive mode
select bit (MTX bit of MCR) according to the R/W command bit (SRW).
Writing to the MCR clears the MAAS automatically. A data transfer may
then be initiated by writing information to MDR or dummy reading from
MDR.
In the slave transmitter routine, the received acknowledge bit (RXAK)
must be tested before transmitting the next byte of data. If RXAK is set,
indicating an end of the data signal from the master receiver, then RXAK
must switch from transmitter mode to receiver mode by software. A
dummy read must follow to release the SCL line so that the master can
generate a stop signal.
11.8.7 Arbitration Lost
If more than one master wants to engage the bus simultaneously, only
one master wins and the others lose arbitration. The arbitration loss
devices immediately switch to slave receive mode by hardware. Their
data output to the SDA line is stopped, but the internal transmitting clock
still runs until the end of the current byte transmission. An interrupt
occurs when this dummy byte transmission is accomplished with
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1. The hardware will inhibit the transmission.
2. The MSTA bit will switch from one to zero without generating a
stop condition.
3. Interrupt to CPU will be generated.
In consideration of these cases, the slave service routine should test the
MAL first, and software should clear the MAL bit if it is set.
11.9 Operation During Wait Mode
During wait mode the M-bus block is idle. If in slave mode, the M-bus
block will wake up on receiving a valid start condition. If the interrupt is
enabled, the CPU will come out of wait mode after the end of a byte
transmission.
11.10 Operation During Stop Mode
N O N - D I S C L O S U R E
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4. MAL will be set to indicate that the attempt to engage the bus has
failed.
In stop mode, the whole block is disabled.
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MAL = 1 and MSTA = 0. If one master attempts to start transmission
while the bus is being engaged by another master:
R E Q U I R E D
Motorola Bus (M Bus) Interface
Operation During Wait Mode
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R E Q U I R E D
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Section 12. Synchronous Serial Interface (SSI)
12.1 Contents
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .96
12.3 SSI Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .98
12.3.1
Serial Clock (SCK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .98
12.3.2
Serial Data Input/Output (SDIO) . . . . . . . . . . . . . . . . . . . . .98
12.4 SSI Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .100
12.4.1
SSI Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . .100
12.4.2
SSI Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .103
12.4.3
SSI Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .104
SSI During Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .104
12.6
SSI During Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .105
12.7
SSI Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .105
N O N - D I S C L O S U R E
12.5
A G R E E M E N T
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12.2
R E Q U I R E D
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A G R E E M E N T
R E Q U I R E D
Synchronous Serial Interface (SSI)
12.2 Introduction
This synchronous serial I/O module is also used on the MC68HC05X1.
The module is similar to the SIOP used on the MC68HC05P7 and the
MC68HC705P9 and the SPI used on the MC68HC05L5.
The SSI is a two-wire master/slave system including serial clock (SCK)
and serial data input output (SDIO). Data is transferred eight bits at a
time. An interrupt may be generated at the completion of each transfer,
and a software programmable option determines whether the SSI
transfers data most significant bit (MSB) or least significant bit (LSB)
first. When operating as a master device, the serial clock speed is
selectable between four rates; as a slave device, the clock speed may
be chosen over a wide range. Refer to Figure 12-1.
In master mode, transmission is initiated by a write to the SSI data
register (SDR). A transfer cannot be initiated in slave mode; however,
the external master will initiate the transfer. The programmer must
choose between master or slave mode before the SSI is enabled. It is up
to the programmer to ensure that only one master exists in the system
at any one time. All devices in the system must operate with the same
clock polarity and data rates. Slaves should always be disabled before
the master is disabled. Likewise, the master should always be enabled
before the slaves are enabled.
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INTERNAL BUS
DATA BUS
CONTROLS/ADDRESS BUS
INTERRUPT CIRCUIT
TO INTERRUPT LOGIC
0 0 0 0 0
SSI DATA REGISTER
HFF
SDIO
LSBF
SR
MSTR
CPOL
SE
SSI CONTROL REGISTER
START
SSI STATUS REGISTER
SF
DCOL
SE
PB3/TIPL
CLOCK GENERATOR
SCK
MSTR
&
Figure 12-1. SSI Block Diagram
N O N - D I S C L O S U R E
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CONTROL LOGIC
A G R E E M E N T
R E Q U I R E D
Synchronous Serial Interface (SSI)
Introduction
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12.3 SSI Signals
The following sections describe the SSI signals.
12.3.1 Serial Clock (SCK)
In master mode (MSTR = 1), the SCK pin is an output with a selectable
frequency of:
fop divided by 16 (SR1:SR0 = 00),
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Synchronous Serial Interface (SSI)
fop divided by 8 (SR1:SR0 = 01),
fop divided by 4 (SR1:SR0 = 10), or
fop divided by 2 (SR1:SR0 = 11).
This pin will be high (CPOL = 1) or low (CPOL = 0) between
transmissions.
In slave mode (MSTR = 0), the SCK pin is an input and the clock must
be supplied by an external master with a maximum frequency of fop
divided by 2. There is no minimum SCK frequency. This pin should be
driven high (CPOL = 1) or low (CPOL = 0) between transmissions by the
external master and must be stable before the SSI is first enabled
(SE = 1).
NOTE:
Data is always captured with the SDIO pin on the rising edge of SCK.
Data is always shifted out and presented at the SDIO pin on the falling
edge of SCK.
12.3.2 Serial Data Input/Output (SDIO)
This pin receives and transmits data to or from the SSI module as
described in the following paragraphs.
SDIO as an Output Pin
Prior to enabling the SSI (SE = 0), the SDIO pin will be three-stated.
The SDIO pin will be active when the SSI is enabled (SE = 1), the
serial direction (SDIR = 1) bit is set, and MSTR = 1. The state of the
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If (CPOL = 0), the first data bit will be driven out to the SDIO pin before
the first rising edge of SCK. Subsequent falling edges of SCK will shift
the remaining data bits out.
SDIO as an Input Pin
The SDIO pin will accept data once the SSI is enabled and the SDIR
bit = 0. Valid data must be present at least 100 ns before the rising
edge of the clock and remain valid for 100 ns after the edge. See
Figure 12-2 and Figure 12-3.
SCK
SDIO
BIT 1
BIT 2
BIT 3
BIT 7
BIT 8
SE
Figure 12-2. Synchronous Serial Interface Timing (CPOL = 1)
SCK
SDIO
BIT 1
BIT 2
BIT 3
BIT 7
BIT 8
SE
Figure 12-3. Synchronous Serial Interface Timing (CPOL = 0)
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If (CPOL = 1), the first falling edge of SCK will shift the first data bit
out to the SDIO pin. Subsequent falling edges of SCK will shift the
remaining data bits out.
N O N - D I S C L O S U R E
pin will depend on the value of the CPOL bit. Data can be sent or
received in either MSB first format (LSBF = 0) or LSB first format
(LSBF = 1).
R E Q U I R E D
Synchronous Serial Interface (SSI)
SSI Signals
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A G R E E M E N T
R E Q U I R E D
Synchronous Serial Interface (SSI)
12.4 SSI Registers
The SSI registers are described in the following subsections.
12.4.1 SSI Control Register
This register is located at address $000A. A reset clears all of these bits,
except bit 3 which is set. Writes to this register during a transfer should
be avoided, with the exception of clearing the SE bit to disable the SSI.
In addition, the clock polarity, rate, data format, and master/slave
selection should not be changed while the SSI is enabled (SE = 1) or
being enabled. Always disable the SSI, by clearing the SE bit, before
altering control bits within the SCR.
Address:
$000A
Bit 7
6
5
4
3
2
1
Bit 0
SIE
SE
LSBF
MSTR
CPOL
SDIR
SR1
SR0
0
0
0
0
1
0
0
0
Read:
Write:
Reset:
Figure 12-4. SSI Control Register (SCR)
SIE — SSI Interrupt Enable
This bit determines whether an interrupt request should be generated
when a transfer is complete. Reset clears this bit.
1 = An interrupt request will be made if the CPU is in the run or wait
mode of operation and the status flag bit SF is set.
0 = No interrupt requests will be made by the SSI.
SE — SSI Enable
When this bit is set, it enables the SSI and SCK pins. When this bit is
cleared, any transmission in progress is aborted and the SCK and
SDIO are three-stated. The SE bit is readable and writable any time.
Clearing SE while a data transfer is occurring will abort the
transmission and reset the bit counter. Reset clears this bit.
1 = Enable the SSI module.
0 = Disable the SSI module.
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MSTR — Master Mode
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Reset clears this bit and configures the SSI for slave operation. MSTR
may be set at any time regardless of the state of SE.
1 = SSI is configured for master mode. The transmission is initiated
by a write to the data register and the SCK pin becomes an
output providing a synchronous data clock at a rate determined
by the SR bit.
0 = SSI is configured to slave mode. Any transmission in progress
is aborted. Transfers are initiated by an external master which
should supply the clock signal to the SCK pin.
CPOL — Clock Polarity
The clock polarity bit controls the state of the SCK pin between
transmissions.
1 = SCK will be high between transmissions.
0 = SCK will be low between transmissions.
In both cases, the data is latched on the rising edge of SCK for serial
input and is valid on the rising edge of SCK for serial output. Reset
sets this bit.
SDIR — Serial Data Direction
When the SE bit = 1, SDIR functions as the output driver enable bit
for the SDIO pin with SSI in master or in slave mode. This bit has no
effect on the SDIO pin when the SSI is disabled (SE = 0). This bit is
cleared by reset.
1 = Enable the output driver of the SDIO pin.
0 = Disable the output driver of the SDIO pin.
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The LSBF bit determines the format of the data transfer. The two
formats are least significant bit (LSB) or most significant bit (MSB)
transferred or received first. Reset clears this bit, initializing the SSI to
MSB first order.
1 = Data will be sent and received in an LSB first format.
0 = Data will be sent and received in an MSB first format.
N O N - D I S C L O S U R E
LSBF — Least Significant Bit First
R E Q U I R E D
Synchronous Serial Interface (SSI)
SSI Registers
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SR1 and SR0 — SSI Clock Rate Select
These bits determine the frequency of SCK when in master mode
(MSTR = 1). They have no effect in slave mode (MSTR = 0).
Table 12-1. Master Mode SCK Frequency Select
SR1
SR0
SCK Frequency
0
0
fop ÷ 16
0
1
fop ÷ 8
1
0
fop ÷ 4
1
1
fop ÷ 2
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12.4.2 SSI Status Register
The SSI status register (SSR) is located at address $000B and contains
three bits.
Address:
$000B
Bit 7
6
Read:
5
4
3
2
1
Bit 0
0
0
0
0
0
TIPL
0
0
1
0
0
0
DCOL
SF
R E Q U I R E D
Synchronous Serial Interface (SSI)
SSI Registers
0
0
= Unimplemened
Figure 12-5. SSI Status Register (SSR)
SF — SSI Flag
This bit is set upon occurrence of the last rising clock edge and
indicates that a data transfer has taken place. It has no effect on any
further transmissions and can be ignored without problem. However,
SF must be cleared before a master can initiate a transfer. SF is
cleared by reading the SSR with SF set followed by a read or write of
the serial data register. If it is cleared before the last edge of the next
byte, it will be set again. Reset clears this bit.
DCOL — Data Collision
This is a read-only status bit which indicates that an invalid access to
the data register has been made. This can occur any time after the
first falling edge of SCK and before SF is set. DCOL is cleared by
reading the status register with SF set followed by a read or write of
the data register. If the last part of the clearing sequence is done after
another transmission has been started, DCOL will be set again. Reset
also clears this bit.
TIPL
The state of the PB3 pin is latched and placed into this bit on the
eighth rising SCK clock during a shift operation. This is the case
regardless of the state of MSTR and CPOL in the SSI control register.
Reset clears this bit.
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Reset:
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Write:
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R E Q U I R E D
Synchronous Serial Interface (SSI)
12.4.3 SSI Data Register
This register is located at address $000C and is both the transmit and
receive data register. This system is not double buffered but writes to
this register during transfers are masked and will not destroy the
previous contents. The SDR can be read at any time but if a transfer is
in progress the results may be ambiguous. This register should only be
written to when the SSI is enabled (SE = 1).
N O N - D I S C L O S U R E
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A G R E E M E N T
Address:
$000C
Bit 7
6
5
4
3
2
1
Bit 0
Read:
Write:
Reset:
Reset Results Unknown
Figure 12-6. SSI Data Register (SDR)
12.5 SSI During Stop Mode
In stop mode, the SSI halts operation. The SDIO and SCK pins will
maintain their states.
If the SSI was nearing completion of a transfer when stop mode is
entered, it might be possible for the SSI to generate an interrupt request
and cause the processor to immediately exit stop mode. To prevent this
occurrence, the programmer should ensure that all transfers are
complete before entering stop mode.
If the SSI is configured to slave mode, then further care should be taken
in entering stop mode. In slave mode, the SCK pin will still accept a clock
from an external master, allowing potentially unwanted transfers to take
place and power consumption to be increased. Note that the SSI will not
generate interrupt requests in this situation. However, on exiting stop
mode through some other means, the SF flag may be found to be set. If,
at this point, SIE is also set, an interrupt request will be generated.
NOTE:
To avoid these potential problems, it is safer to disable the SSI
completely (SE = 0) before entering stop mode.
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The CPU clock halts during wait mode, but the SSI remains active. If
interrupts are enabled, an SSI interrupt will cause the processor to exit
wait mode.
12.7 SSI Pin Configuration
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When the SSI is enabled via the SE bit of the SCR ($0A), the port B data
direction register bits 3–5 relinquish control to the SSI as directed by the
combination of the SE, MSTR, and SDIR bits. The states of the port B
DDR bits are not altered by the SSI.
A G R E E M E N T
12.6 SSI During Wait Mode
R E Q U I R E D
Synchronous Serial Interface (SSI)
SSI During Wait Mode
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A G R E E M E N T
R E Q U I R E D
Synchronous Serial Interface (SSI)
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13.1 Contents
13.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .107
13.3
Bootloader Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .107
13.4
Programming Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .112
13.5
Mask Option Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .113
13.2 Introduction
The user EPROM consists of 5120 bytes of EPROM from $0B00 to
$1EFF and 16 bytes of user vectors from $1FF0 to $1FFF.
The bootloader ROM and vectors are located from $1F01 to $1FEF.
All of the user vectors, $1FF2 through $1FFF, are dedicated to reset and
interrupt vectors. Location $1F00 is the mask option register (MOR).
13.3 Bootloader Mode
Bootloader mode is entered upon the rising edge of RESET if the IRQ is
at VTST and the PB1 pin is at logic 1. The bootloader code resides in the
ROM from $1F01 to $1FEF. This program handles copying of user code
from an external EPROM into the on-chip EPROM. The bootload
function does not have to be done from an external EPROM, but it may
be done from a host.
The user code must be a one-to-one correspondence with the internal
EPROM addresses.
NOTE:
The MCU designer must disable the COP hardware in bootloader mode.
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Section 13. User EPROM
N O N - D I S C L O S U R E
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A G R E E M E N T
R E Q U I R E D
User EPROM
Three pins are used to select various bootloader functions: PB0, PB3,
and PB4. PB0 is normally a SYNC pin, which is used to synchronize the
MCU to an off-chip source driving EPROM data into the MCU. If an
external EPROM is used, this pin must be connected to VSS. PB4 and
PB3 are used to select a programming mode. Two other pins, PC2 and
PC3, are used to drive the PROG LED and the VERF LED, respectively.
The programming modes along with gate and drain stress are shown in
Table 13-1.
Table 13-1. Bootloader Functions
PB0
PB4
PB3
Mode
SYNC
1
1
Program/Verify
SYNC
1
0
Verify Only
SYNC
0
0
Factory Test
0
0
1
Factory Test
1
0
1
Factory Test
The bootloader uses an external 12-bit counter to address the memory
device containing the code to be copied. This counter requires a clock
and a reset function. The 12-bit counter can address up to 4 Kbytes of
memory, which means that a port pin has to be used to address the extra
memory space.
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DATA OUT
CLK (OUT)
SYNC (IN)
HOST READ DATA
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(a) Dump EPROM Interface to a Host
DATA READ
CLK (OUT)
SYNC (IN)
DATA IN
(b) Program/Verify Interface to a Host
N O N - D I S C L O S U R E
Figure 13-1. Programmer Interface to Host
A G R E E M E N T
PORT A
R E Q U I R E D
User EPROM
Bootloader Mode
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R E Q U I R E D
User EPROM
BOOT
YES
NO
PB2 = 0
JUMP TO RAM
DDRC <-%00001111
PORTC <-%00001111
DDRB <-%00100000
PORTB <-%00000000
MAYPRG
PB4 = 1
PUT RAMSUB IN RAM
NO
YES
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A G R E E M E N T
PB3 = 1
YES
NO
YES
DUMP EPROM
PRG/VERF
BUMP COUNT TO $B00
PB0 = 1
NO
PB4 = 1
YES
GATE STRESS
GET BYTE FROM PORT A
PROGRAM BYTE
JSR NXTADR
NO
DRAIN STRESS
DDRA = OUTPUT
NO
END ADDR
($1FFF)
BUMP COUNT TO $B00
YES
WAIT
VERIFY
GET BYTE START @ $B00
CHANGE INSTRUCTION
FROM STA TO EOR
PUT BYTE ON PORT A
YES
INC COUNT TO $B00
START ADDR <- $B00
END ADDRESS
($1FFF)
GET BYTE FROM PORT A
JSR RAMSUB
NO
YES
PB0=1
(SYNC)
NO
NO
COMPARE
YES
JSR NXTADR
WAIT
END ADDRESS
($1FFF)
NO
YES
VERF LED ON
WAIT
Figure 13-2. MC68HC705E5 Bootloader Flowchart
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2764
1
IRQ/VPP
OSC1
OSC2
PA2
13
D2
A2
D3
A3
15
PA3
16 D4
17
D5
18
D6
19 D7
PA4
10 µΩ
15 pF 15 pF
PA5
PA6
VDD
Freescale Semiconductor, Inc...
A0
PA1
11 D0
12 D1
PA0
10.24 MHz
PA7
VDD
VDD2
PB1
20
VDD2
VSS2
RESET
22
VSS
PB5
PD5
VDD
VDD
PB2
PROG
2
VDD
CE
OE
A1
A4
A5
10
9
8
7
6
5
4
A6
A7 3
25
A8
24
A9
21
A10
23
A11
VDD
9
Q1
7
Q2
6
Q3
5
Q4
3
Q5
2
Q6
4
Q7
13
Q8
12
Q9
14
Q10
15
Q11
1 Q12
16
8
RST
A12
11
14
CLK
10
PC0
PC2
390 Ω
MC14040B
27 28
PC1
VERF
VDD
PC3
390 Ω
14
PB3
PB0 (SYNC)
PB4
VDD
VDD
2
3
MC74HC02
1
4
5
6
8
9
10
13
11
12
7
All resistors are 10 kΩ unless specified otherwise.
Figure 13-3. MC68HC705E5 Programming Circuit
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A G R E E M E N T
VDD
N O N - D I S C L O S U R E
VPP
R E Q U I R E D
User EPROM
Bootloader Mode
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A G R E E M E N T
R E Q U I R E D
User EPROM
13.4 Programming Register
This register is used to program the EPROM array. Only the LATCH and
EPGM bits are available in user mode. To program a byte of EPROM,
set LATCH, write data to the desired address, then set EPGM for tEPGM.
Address:
$0011
Bit 7
6
5
4
3
2
1
Bit 0
—
—
—
—
—
LATCH
0
EPGM
0
0
0
0
1
0
0
0
Read:
Write:
Reset:
Figure 13-4. Programming Register (PROG)
LATCH — EPROM Latch Control
READ: Any time
WRITE: Any time
0 = EPROM address and data bus configured for normal reads
1 = EPROM address and data bus configured for programming.
Causes address and data bus to be latched when a write to
EPROM is done. EPROM cannot be read if LATCH = 1.
EPGM — EPROM Program Control
READ: Any time
WRITE: Cleared any time, set only if LATCH = 1
0 = Programming power switched off the EPROM array
1 = Programming power switched on to the EPROM array. If
LATCH = 0, then EPGM is cleared automatically. EPGM
cannot be set if LATCH is not set. LATCH and EPGM cannot
both be set on the same write.
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13.5 Mask Option Register
The MOR contains programmable EPROM bits to control mask options.
The MOR register is latched upon reset going away.
Address:
$1F00
Bit 7
6
5
4
3
2
1
Bit 0
—
—
—
STOPEN
CPI1
CPI0
IRQ
COP
0
0
0
0
1
0
0
0
R E Q U I R E D
User EPROM
Mask Option Register
Reset:
Figure 13-5. Mask Option Register (MOR)
STOPEN — STOP Enable
When set, STOP is enabled.
CPI1, CPI0 — CPI Rate bits
READ: Any time
WRITE: In special modes, writing these bits activates the function
without having to program it and can be written many times.
In user mode, writing has no effect. These bits must be
programmed. Refer to Table 13-2.
Table 13-2. CPI Rate
CPI1
CPI0
Interrupt Rate
0
X
1 Second CPI Rate
1
0
0.5 Second CPI Rate
1
1
0.25 Second CPI Rate
IRQ — IRQ sensitivity
1 = This bit selects the edge and level sensitive IRQ.
0 = This bit selects the edge-only sensitive IRQ (EPROM erased
state).
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Write::
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Read:
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In test mode, reading and writing the MOR is done according to
Table 13-3.
Table 13-3. MOR Read/Write Based on Mode and LATCH Bit
Latch
Test
Read
Write
0
0
E
N
1
0
N
PE
0
1
E
R
1
1
R
PE
PE = Program EPROM Byte
R = Register Latch
N = Nothing
E = EPROM Byte
COP — COP Enable
When set, this bit enables the COP watchdog timer.
When clear, the COP is disabled.
1 = The COP is enabled.
0 = The COP is disabled (EPROM erased state).
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A G R E E M E N T
R E Q U I R E D
User EPROM
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Section 14. Instruction Set
14.1 Contents
14.3 Addressing Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .116
14.3.1
Inherent . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .117
14.3.2
Immediate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .117
14.3.3
Direct . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .117
14.3.4
Extended . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .117
14.3.5
Indexed, No Offset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .118
14.3.6
Indexed, 8-Bit Offset . . . . . . . . . . . . . . . . . . . . . . . . . . . . .118
14.3.7
Indexed,16-Bit Offset. . . . . . . . . . . . . . . . . . . . . . . . . . . . .118
14.3.8
Relative . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .119
14.4 Instruction Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .119
14.4.1
Register/Memory Instructions . . . . . . . . . . . . . . . . . . . . . .120
14.4.2
Read-Modify-Write Instructions . . . . . . . . . . . . . . . . . . . . .121
14.4.3
Jump/Branch Instructions . . . . . . . . . . . . . . . . . . . . . . . . .122
14.4.4
Bit Manipulation Instructions . . . . . . . . . . . . . . . . . . . . . . .124
14.4.5
Control Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .125
14.5
Instruction Set Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . .126
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A G R E E M E N T
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .116
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14.2
R E Q U I R E D
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14.2 Introduction
The MCU instruction set has 62 instructions and uses eight addressing
modes. The instructions include all those of the M146805 CMOS Family
plus one more: the unsigned multiply (MUL) instruction. The MUL
instruction allows unsigned multiplication of the contents of the
accumulator (A) and the index register (X). The high-order product is
stored in the index register, and the low-order product is stored in the
accumulator.
14.3 Addressing Modes
The CPU uses eight addressing modes for flexibility in accessing data.
The addressing modes provide eight different ways for the CPU to find
the data required to execute an instruction. The eight addressing modes
are:
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R E Q U I R E D
Instruction Set
•
Inherent
•
Immediate
•
Direct
•
Extended
•
Indexed, no offset
•
Indexed, 8-bit offset
•
Indexed, 16-bit offset
•
Relative
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14.3.1 Inherent
Inherent instructions are those that have no operand, such as return
from interrupt (RTI) and stop (STOP). Some of the inherent instructions
act on data in the CPU registers, such as set carry flag (SEC) and
increment accumulator (INCA). Inherent instructions require no operand
address and are one byte long.
R E Q U I R E D
Instruction Set
Addressing Modes
14.3.3 Direct
Direct instructions can access any of the first 256 memory locations with
two bytes. The first byte is the opcode, and the second is the low byte of
the operand address. In direct addressing, the CPU automatically uses
$00 as the high byte of the operand address.
14.3.4 Extended
Extended instructions use three bytes and can access any address in
memory. The first byte is the opcode; the second and third bytes are the
high and low bytes of the operand address.
When using the Motorola assembler, the programmer does not need to
specify whether an instruction is direct or extended. The assembler
automatically selects the shortest form of the instruction.
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Immediate instructions are those that contain a value to be used in an
operation with the value in the accumulator or index register. Immediate
instructions require no operand address and are two bytes long. The
opcode is the first byte, and the immediate data value is the second byte.
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14.3.2 Immediate
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A G R E E M E N T
R E Q U I R E D
Instruction Set
14.3.5 Indexed, No Offset
Indexed instructions with no offset are 1-byte instructions that can
access data with variable addresses within the first 256 memory
locations. The index register contains the low byte of the effective
address of the operand. The CPU automatically uses $00 as the high
byte, so these instructions can address locations $0000–$00FF.
Indexed, no offset instructions are often used to move a pointer through
a table or to hold the address of a frequently used RAM or I/O location.
14.3.6 Indexed, 8-Bit Offset
Indexed, 8-bit offset instructions are 2-byte instructions that can access
data with variable addresses within the first 511 memory locations. The
CPU adds the unsigned byte in the index register to the unsigned byte
following the opcode. The sum is the effective address of the operand.
These instructions can access locations $0000–$01FE.
Indexed 8-bit offset instructions are useful for selecting the kth element
in an n-element table. The table can begin anywhere within the first 256
memory locations and could extend as far as location 510 ($01FE). The
k value is typically in the index register, and the address of the beginning
of the table is in the byte following the opcode.
14.3.7 Indexed,16-Bit Offset
Indexed, 16-bit offset instructions are 3-byte instructions that can access
data with variable addresses at any location in memory. The CPU adds
the unsigned byte in the index register to the two unsigned bytes
following the opcode. The sum is the effective address of the operand.
The first byte after the opcode is the high byte of the 16-bit offset; the
second byte is the low byte of the offset.
Indexed, 16-bit offset instructions are useful for selecting the kth element
in an n-element table anywhere in memory.
As with direct and extended addressing, the Motorola assembler
determines the shortest form of indexed addressing.
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When using the Motorola assembler, the programmer does not need to
calculate the offset, because the assembler determines the proper offset
and verifies that it is within the span of the branch.
14.4 Instruction Types
The MCU instructions fall into the following five categories:
•
Register/Memory Instructions
•
Read-Modify-Write Instructions
•
Jump/Branch Instructions
•
Bit Manipulation Instructions
•
Control Instructions
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Relative addressing is only for branch instructions. If the branch
condition is true, the CPU finds the effective branch destination by
adding the signed byte following the opcode to the contents of the
program counter. If the branch condition is not true, the CPU goes to the
next instruction. The offset is a signed, two’s complement byte that gives
a branching range of –128 to +127 bytes from the address of the next
location after the branch instruction.
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A G R E E M E N T
14.3.8 Relative
R E Q U I R E D
Instruction Set
Instruction Types
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R E Q U I R E D
Instruction Set
14.4.1 Register/Memory Instructions
These instructions operate on CPU registers and memory locations.
Most of them use two operands. One operand is in either the
accumulator or the index register. The CPU finds the other operand in
memory.
Table 14-1. Register/Memory Instructions
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A G R E E M E N T
Instruction
Mnemonic
Add Memory Byte and Carry Bit to Accumulator
ADC
Add Memory Byte to Accumulator
ADD
AND Memory Byte with Accumulator
AND
Bit Test Accumulator
BIT
Compare Accumulator
CMP
Compare Index Register with Memory Byte
CPX
EXCLUSIVE OR Accumulator with Memory Byte
EOR
Load Accumulator with Memory Byte
LDA
Load Index Register with Memory Byte
LDX
Multiply
MUL
OR Accumulator with Memory Byte
ORA
Subtract Memory Byte and Carry Bit from Accumulator
SBC
Store Accumulator in Memory
STA
Store Index Register in Memory
STX
Subtract Memory Byte from Accumulator
SUB
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14.4.2 Read-Modify-Write Instructions
These instructions read a memory location or a register, modify its
contents, and write the modified value back to the memory location or to
the register.
Do not use read-modify-write operations on write-only registers.
Table 14-2. Read-Modify-Write Instructions
Mnemonic
Arithmetic Shift Left (Same as LSL)
ASL
Arithmetic Shift Right
ASR
Bit Clear
BCLR(1)
Bit Set
BSET(1)
Clear Register
CLR
Complement (One’s Complement)
COM
Decrement
DEC
Increment
INC
Logical Shift Left (Same as ASL)
LSL
Logical Shift Right
LSR
Negate (Two’s Complement)
NEG
Rotate Left through Carry Bit
ROL
Rotate Right through Carry Bit
ROR
Test for Negative or Zero
TST(2)
1. Unlike other read-modify-write instructions, BCLR and
BSET use only direct addressing.
2. TST is an exception to the read-modify-write sequence because it does not write a replacement value.
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A G R E E M E N T
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Instruction
N O N - D I S C L O S U R E
NOTE:
R E Q U I R E D
Instruction Set
Instruction Types
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14.4.3 Jump/Branch Instructions
Jump instructions allow the CPU to interrupt the normal sequence of the
program counter. The unconditional jump instruction (JMP) and the
jump-to-subroutine instruction (JSR) have no register operand. Branch
instructions allow the CPU to interrupt the normal sequence of the
program counter when a test condition is met. If the test condition is not
met, the branch is not performed.
The BRCLR and BRSET instructions cause a branch based on the state
of any readable bit in the first 256 memory locations. These 3-byte
instructions use a combination of direct addressing and relative
addressing. The direct address of the byte to be tested is in the byte
following the opcode. The third byte is the signed offset byte. The CPU
finds the effective branch destination by adding the third byte to the
program counter if the specified bit tests true. The bit to be tested and its
condition (set or clear) is part of the opcode. The span of branching is
from –128 to +127 from the address of the next location after the branch
instruction. The CPU also transfers the tested bit to the carry/borrow bit
of the condition code register.
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A G R E E M E N T
R E Q U I R E D
Instruction Set
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Mnemonic
Branch if Carry Bit Clear
BCC
Branch if Carry Bit Set
BCS
Branch if Equal
BEQ
Branch if Half-Carry Bit Clear
BHCC
Branch if Half-Carry Bit Set
BHCS
Branch if Higher
BHI
Branch if Higher or Same
BHS
Branch if IRQ Pin High
BIH
Branch if IRQ Pin Low
BIL
Branch if Lower
BLO
Branch if Lower or Same
BLS
Branch if Interrupt Mask Clear
BMC
Branch if Minus
BMI
Branch if Interrupt Mask Set
BMS
Branch if Not Equal
BNE
Branch if Plus
BPL
Branch Always
BRA
Branch if Bit Clear
Branch Never
Branch if Bit Set
BRCLR
BRN
BRSET
Branch to Subroutine
BSR
Unconditional Jump
JMP
Jump to Subroutine
JSR
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A G R E E M E N T
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Instruction
N O N - D I S C L O S U R E
Table 14-3. Jump and Branch Instructions
R E Q U I R E D
Instruction Set
Instruction Types
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R E Q U I R E D
Instruction Set
14.4.4 Bit Manipulation Instructions
The CPU can set or clear any writable bit in the first 256 bytes of
memory, which includes I/O registers and on-chip RAM locations. The
CPU can also test and branch based on the state of any bit in any of the
first 256 memory locations.
Table 14-4. Bit Manipulation Instructions
A G R E E M E N T
Instruction
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Bit Clear
Mnemonic
BCLR
Branch if Bit Clear
BRCLR
Branch if Bit Set
BRSET
BSET
N O N - D I S C L O S U R E
Bit Set
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Table 14-5. Control Instructions
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Instruction
Mnemonic
Clear Carry Bit
CLC
Clear Interrupt Mask
CLI
No Operation
NOP
Reset Stack Pointer
RSP
Return from Interrupt
RTI
Return from Subroutine
RTS
Set Carry Bit
SEC
Set Interrupt Mask
SEI
Stop Oscillator and Enable IRQ Pin
STOP
Software Interrupt
SWI
Transfer Accumulator to Index Register
TAX
Transfer Index Register to Accumulator
TXA
Stop CPU Clock and Enable Interrupts
WAIT
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A G R E E M E N T
These instructions act on CPU registers and control CPU operation
during program execution.
N O N - D I S C L O S U R E
14.4.5 Control Instructions
R E Q U I R E D
Instruction Set
Instruction Types
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14.5 Instruction Set Summary
ADC #opr
ADC opr
ADC opr
ADC opr,X
ADC opr,X
ADC ,X
ADD #opr
ADD opr
ADD opr
ADD opr,X
ADD opr,X
ADD ,X
AND #opr
AND opr
AND opr
AND opr,X
AND opr,X
AND ,X
ASL opr
ASLA
ASLX
ASL opr,X
ASL ,X
↕
IMM
DIR
EXT
IX2
IX1
IX
ii
A9
2
B9 dd 3
C9 hh ll 4
D9 ee ff 5
E9 ff
4
F9
3
↕
IMM
DIR
EXT
IX2
IX1
IX
AB ii
2
BB dd 3
CB hh ll 4
DB ee ff 5
EB ff
4
FB
3
↕ —
IMM
DIR
EXT
IX2
IX1
IX
ii
A4
2
B4 dd 3
C4 hh ll 4
D4 ee ff 5
E4 ff
4
F4
3
38
48
58
68
78
dd
↕
DIR
INH
INH
IX1
IX
DIR
INH
INH
IX1
IX
37
47
57
67
77
dd
REL
Effect on
CCR
Description
H I N Z C
A ← (A) + (M) + (C)
Add with Carry
A ← (A) + (M)
Add without Carry
Arithmetic Shift Left (Same as LSL)
C
BCC rel
Branch if Carry Bit Clear
↕
↕
— — ↕
0
b7
Arithmetic Shift Right
↕ —
A ← (A) ∧ (M)
Logical AND
ASR opr
ASRA
ASRX
ASR opr,X
ASR ,X
↕ —
— — ↕
↕
↕
↕
b0
C
b7
— — ↕
↕
↕
b0
PC ← (PC) + 2 + rel ? C = 0
Mn ← 0
— — — — —
ff
ff
Cycles
Operation
Opcode
Source
Form
Operand
Table 14-6. Instruction Set Summary
Address
Mode
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A G R E E M E N T
R E Q U I R E D
Instruction Set
5
3
3
6
5
5
3
3
6
5
24
rr
3
DIR (b0)
DIR (b1)
DIR (b2)
DIR (b3)
— — — — —
DIR (b4)
DIR (b5)
DIR (b6)
DIR (b7)
11
13
15
17
19
1B
1D
1F
dd
dd
dd
dd
dd
dd
dd
dd
5
5
5
5
5
5
5
5
— — — — —
25
rr
3
BCLR n opr
Clear Bit n
BCS rel
Branch if Carry Bit Set (Same as BLO)
BEQ rel
Branch if Equal
PC ← (PC) + 2 + rel ? Z = 1
— — — — —
REL
27
rr
3
BHCC rel
Branch if Half-Carry Bit Clear
PC ← (PC) + 2 + rel ? H = 0
— — — — —
REL
28
rr
3
BHCS rel
Branch if Half-Carry Bit Set
BHI rel
Branch if Higher
BHS rel
Branch if Higher or Same
PC ← (PC) + 2 + rel ? C = 1
REL
PC ← (PC) + 2 + rel ? H = 1
— — — — —
REL
29
rr
3
PC ← (PC) + 2 + rel ? C ∨ Z = 0
— — — — —
REL
22
rr
3
PC ← (PC) + 2 + rel ? C = 0
— — — — —
REL
24
rr
3
General Release Specification
MC68HC705E5 — Rev. 1.0
Instruction Set
For More Information On This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
Operand
Cycles
Branch if IRQ Pin High
PC ← (PC) + 2 + rel ? IRQ = 1
— — — — —
REL
2F
rr
3
BIL rel
Branch if IRQ Pin Low
PC ← (PC) + 2 + rel ? IRQ = 0
— — — — —
REL
2E
rr
3
A5
B5
C5
D5
E5
F5
ii
dd
hh ll
ee ff
ff
2
3
4
5
4
3
Freescale Semiconductor, Inc...
Operation
BIT #opr
BIT opr
BIT opr
BIT opr,X
BIT opr,X
BIT ,X
Bit Test Accumulator with Memory Byte
Description
(A) ∧ (M)
— — — — —
REL
25
rr
3
REL
23
rr
3
— — — — —
REL
2C
rr
3
— — — — —
REL
2B
rr
3
— — — — —
REL
2D
rr
3
— — — — —
REL
26
rr
3
— — — — —
REL
2A
rr
3
— — — — —
REL
20
rr
3
DIR (b0)
DIR (b1)
DIR (b2)
DIR (b3)
— — — — ↕
DIR (b4)
DIR (b5)
DIR (b6)
DIR (b7)
01
03
05
07
09
0B
0D
0F
dd rr
dd rr
dd rr
dd rr
dd rr
dd rr
dd rr
dd rr
5
5
5
5
5
5
5
5
— — — — —
BMC rel
Branch if Interrupt Mask Clear
PC ← (PC) + 2 + rel ? I = 0
BMI rel
Branch if Minus
PC ← (PC) + 2 + rel ? N = 1
BMS rel
Branch if Interrupt Mask Set
PC ← (PC) + 2 + rel ? I = 1
BNE rel
Branch if Not Equal
PC ← (PC) + 2 + rel ? Z = 0
BPL rel
Branch if Plus
PC ← (PC) + 2 + rel ? N = 0
BRA rel
Branch Always
PC ← (PC) + 2 + rel ? 1 = 1
BRSET n opr rel Branch if Bit n Set
BSET n opr
Set Bit n
↕ —
— — — — —
Branch if Lower or Same
Branch Never
— — ↕
IMM
DIR
EXT
IX2
IX1
IX
PC ← (PC) + 2 + rel ? C = 1
Branch if Lower (Same as BCS)
BRN rel
H I N Z C
PC ← (PC) + 2 + rel ? C ∨ Z = 1
BLO rel
BLS rel
BRCLR n opr rel Branch if Bit n Clear
Effect on
CCR
PC ← (PC) + 2 + rel ? Mn = 0
PC ← (PC) + 2 + rel ? 1 = 0
21
rr
3
PC ← (PC) + 2 + rel ? Mn = 1
DIR (b0)
DIR (b1)
DIR (b2)
DIR (b3)
— — — — ↕
DIR (b4)
DIR (b5)
DIR (b6)
DIR (b7)
REL
00
02
04
06
08
0A
0C
0E
dd rr
dd rr
dd rr
dd rr
dd rr
dd rr
dd rr
dd rr
5
5
5
5
5
5
5
5
Mn ← 1
DIR (b0)
DIR (b1)
DIR (b2)
DIR (b3)
— — — — —
DIR (b4)
DIR (b5)
DIR (b6)
DIR (b7)
10
12
14
16
18
1A
1C
1E
dd
dd
dd
dd
dd
dd
dd
dd
5
5
5
5
5
5
5
5
PC ← (PC) + 2; push (PCL)
SP ← (SP) – 1; push (PCH)
SP ← (SP) – 1
PC ← (PC) + rel
— — — — —
REL
AD
rr
6
BSR rel
Branch to Subroutine
CLC
Clear Carry Bit
C←0
— — — — 0
INH
98
2
CLI
Clear Interrupt Mask
I←0
— 0 — — —
INH
9A
2
MC68HC705E5 — Rev. 1.0
General Release Specification
Instruction Set
For More Information On This Product,
Go to: www.freescale.com
A G R E E M E N T
Opcode
BIH rel
Source
Form
N O N - D I S C L O S U R E
Address
Mode
Table 14-6. Instruction Set Summary (Continued)
R E Q U I R E D
Instruction Set
Instruction Set Summary
Freescale Semiconductor, Inc.
CLR opr
CLRA
CLRX
CLR opr,X
CLR ,X
CMP #opr
CMP opr
CMP opr
CMP opr,X
CMP opr,X
CMP ,X
COM opr
COMA
COMX
COM opr,X
COM ,X
CPX #opr
CPX opr
CPX opr
CPX opr,X
CPX opr,X
CPX ,X
DEC opr
DECA
DECX
DEC opr,X
DEC ,X
EOR #opr
EOR opr
EOR opr
EOR opr,X
EOR opr,X
EOR ,X
INC opr
INCA
INCX
INC opr,X
INC ,X
JMP opr
JMP opr
JMP opr,X
JMP opr,X
JMP ,X
DIR
INH
INH
IX1
IX
3F
4F
5F
6F
7F
dd
↕
IMM
DIR
EXT
IX2
IX1
IX
ii
A1
2
B1 dd 3
C1 hh ll 4
D1 ee ff 5
E1 ff
4
F1
3
1
DIR
INH
INH
IX1
IX
33
43
53
63
73
↕
IMM
DIR
EXT
IX2
IX1
IX
ii
A3
2
B3 dd 3
C3 hh ll 4
D3 ee ff 5
E3 ff
4
F3
3
↕ —
DIR
INH
INH
IX1
IX
3A
4A
5A
6A
7A
↕ —
IMM
DIR
EXT
IX2
IX1
IX
ii
A8
2
B8 dd 3
C8 hh ll 4
D8 ee ff 5
E8 ff
4
F8
3
↕ —
DIR
INH
INH
IX1
IX
3C
4C
5C
6C
7C
DIR
EXT
IX2
IX1
IX
BC dd 2
CC hh ll 3
DC ee ff 4
EC ff
3
FC
2
Effect on
CCR
Description
H I N Z C
M ← $00
A ← $00
X ← $00
M ← $00
M ← $00
Clear Byte
Compare Accumulator with Memory Byte
Complement Byte (One’s Complement)
Compare Index Register with Memory Byte
EXCLUSIVE OR Accumulator with Memory
Byte
Unconditional Jump
M ← (M) = $FF – (M)
A ← (A) = $FF – (A)
X ← (X) = $FF – (X)
M ← (M) = $FF – (M)
M ← (M) = $FF – (M)
(X) – (M)
M ← (M) – 1
A ← (A) – 1
X ← (X) – 1
M ← (M) – 1
M ← (M) – 1
Decrement Byte
Increment Byte
(A) – (M)
A ← (A) ⊕ (M)
M ← (M) + 1
A ← (A) + 1
X ← (X) + 1
M ← (M) + 1
M ← (M) + 1
PC ← Jump Address
— — 0 1 —
— — ↕
— — ↕
— — ↕
— — ↕
— — ↕
— — ↕
↕
↕
↕
— — — — —
General Release Specification
ff
dd
ff
dd
ff
dd
ff
Cycles
Operation
Operand
Source
Form
Opcode
Table 14-6. Instruction Set Summary (Continued)
Address
Mode
N O N - D I S C L O S U R E
Freescale Semiconductor, Inc...
A G R E E M E N T
R E Q U I R E D
Instruction Set
5
3
3
6
5
5
3
3
6
5
5
3
3
6
5
5
3
3
6
5
MC68HC705E5 — Rev. 1.0
Instruction Set
For More Information On This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
LSL opr
LSLA
LSLX
LSL opr,X
LSL ,X
PC ← (PC) + n (n = 1, 2, or 3)
Push (PCL); SP ← (SP) – 1
Push (PCH); SP ← (SP) – 1
PC ← Effective Address
Jump to Subroutine
A ← (M)
Load Accumulator with Memory Byte
X ← (M)
Load Index Register with Memory Byte
Logical Shift Left (Same as ASL)
↕ —
IMM
DIR
EXT
IX2
IX1
IX
AE ii
2
BE dd 3
CE hh ll 4
DE ee ff 5
EE ff
4
FE
3
38
48
58
68
78
dd
↕
DIR
INH
INH
IX1
IX
0
DIR
INH
INH
IX1
IX
34
44
54
64
74
dd
MUL
Unsigned Multiply
0
C
b7
INH
42
Negate Byte (Two’s Complement)
NOP
No Operation
↕
— — 0
↕
↕
b0
X : A ← (X) × (A)
NEG opr
NEGA
NEGX
NEG opr,X
NEG ,X
— — ↕
b0
M ← –(M) = $00 – (M)
A ← –(A) = $00 – (A)
X ← –(X) = $00 – (X)
M ← –(M) = $00 – (M)
M ← –(M) = $00 – (M)
0 — — — 0
— — ↕
↕
↕
— — — — —
A ← (A) ∨ (M)
Logical OR Accumulator with Memory
Rotate Byte Left through Carry Bit
— — ↕
C
— — ↕
b7
b0
MC68HC705E5 — Rev. 1.0
DIR
INH
INH
IX1
IX
30
40
50
60
70
INH
9D
ff
ff
5
3
3
6
5
5
3
3
6
5
11
dd
ff
5
3
3
6
5
2
↕ —
IMM
DIR
EXT
IX2
IX1
IX
AA
BA
CA
DA
EA
FA
ii
dd
hh ll
ee ff
ff
39
49
59
69
79
dd
↕
DIR
INH
INH
IX1
IX
↕
Cycles
↕ —
ii
A6
2
B6 dd 3
C6 hh ll 4
D6 ee ff 5
E6 ff
4
F6
3
— — ↕
C
b7
Logical Shift Right
ROL opr
ROLA
ROLX
ROL opr,X
ROL ,X
— — ↕
IMM
DIR
EXT
IX2
IX1
IX
H I N Z C
LSR opr
LSRA
LSRX
LSR opr,X
LSR ,X
ORA #opr
ORA opr
ORA opr
ORA opr,X
ORA opr,X
ORA ,X
BD dd 5
CD hh ll 6
DD ee ff 7
ED ff
6
FD
5
Description
ff
2
3
4
5
4
3
5
3
3
6
5
General Release Specification
Instruction Set
For More Information On This Product,
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A G R E E M E N T
LDX #opr
LDX opr
LDX opr
LDX opr,X
LDX opr,X
LDX ,X
— — — — —
DIR
EXT
IX2
IX1
IX
Effect on
CCR
N O N - D I S C L O S U R E
LDA #opr
LDA opr
LDA opr
LDA opr,X
LDA opr,X
LDA ,X
Opcode
Freescale Semiconductor, Inc...
JSR opr
JSR opr
JSR opr,X
JSR opr,X
JSR ,X
Operation
Address
Mode
Source
Form
Operand
Table 14-6. Instruction Set Summary (Continued)
R E Q U I R E D
Instruction Set
Instruction Set Summary
Freescale Semiconductor, Inc.
N O N - D I S C L O S U R E
DIR
INH
INH
IX1
IX
36
46
56
66
76
dd
— — — — —
INH
9C
2
↕
↕
INH
80
9
— — — — —
INH
81
6
— — ↕
↕
IMM
DIR
EXT
IX2
IX1
IX
ii
A2
2
B2 dd 3
C2 hh ll 4
D2 ee ff 5
E2 ff
4
F2
3
Effect on
CCR
Description
H I N Z C
ROR opr
RORA
RORX
ROR opr,X
ROR ,X
Rotate Byte Right through Carry Bit
RSP
Reset Stack Pointer
SP ← $00FF
RTI
Return from Interrupt
SP ← (SP) + 1; Pull (CCR)
SP ← (SP) + 1; Pull (A)
SP ← (SP) + 1; Pull (X)
SP ← (SP) + 1; Pull (PCH)
SP ← (SP) + 1; Pull (PCL)
RTS
Return from Subroutine
SP ← (SP) + 1; Pull (PCH)
SP ← (SP) + 1; Pull (PCL)
C
b7
— — ↕
↕
↕
b0
↕
↕
↕
SBC #opr
SBC opr
SBC opr
SBC opr,X
SBC opr,X
SBC ,X
Subtract Memory Byte and Carry Bit from
Accumulator
SEC
Set Carry Bit
C←1
— — — — 1
INH
99
SEI
Set Interrupt Mask
I←1
— 1 — — —
INH
9B
STA opr
STA opr
STA opr,X
STA opr,X
STA ,X
Store Accumulator in Memory
STOP
Stop Oscillator and Enable IRQ Pin
STX opr
STX opr
STX opr,X
STX opr,X
STX ,X
SUB #opr
SUB opr
SUB opr
SUB opr,X
SUB opr,X
SUB ,X
Store Index Register In Memory
Subtract Memory Byte from Accumulator
SWI
Software Interrupt
TAX
Transfer Accumulator to Index Register
A ← (A) – (M) – (C)
M ← (A)
↕
↕ —
DIR
EXT
IX2
IX1
IX
B7
C7
D7
E7
F7
— 0 — — —
INH
8E
— — ↕
ff
Cycles
Operation
Operand
Source
Form
Opcode
Table 14-6. Instruction Set Summary (Continued)
Address
Mode
Freescale Semiconductor, Inc...
A G R E E M E N T
R E Q U I R E D
Instruction Set
5
3
3
6
5
2
2
dd
hh ll
ee ff
ff
4
5
6
5
4
2
dd
hh ll
ee ff
ff
↕ —
DIR
EXT
IX2
IX1
IX
BF
CF
DF
EF
FF
↕
↕
IMM
DIR
EXT
IX2
IX1
IX
ii
A0
2
B0 dd 3
C0 hh ll 4
D0 ee ff 5
E0 ff
4
F0
3
PC ← (PC) + 1; Push (PCL)
SP ← (SP) – 1; Push (PCH)
SP ← (SP) – 1; Push (X)
SP ← (SP) – 1; Push (A)
— 1 — — —
SP ← (SP) – 1; Push (CCR)
SP ← (SP) – 1; I ← 1
PCH ← Interrupt Vector High Byte
PCL ← Interrupt Vector Low Byte
INH
83
10
INH
97
2
M ← (X)
A ← (A) – (M)
X ← (A)
— — ↕
— — ↕
— — — — —
General Release Specification
4
5
6
5
4
MC68HC705E5 — Rev. 1.0
Instruction Set
For More Information On This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
TXA
Transfer Index Register to Accumulator
— — — — —
INH
9F
2
— 0 — — —
INH
8F
2
— — ↕
(M) – $00
A ← (X)
Stop CPU Clock and Enable Interrupts
Accumulator
Carry/borrow flag
Condition code register
Direct address of operand
Direct address of operand and relative offset of branch instruction
Direct addressing mode
High and low bytes of offset in indexed, 16-bit offset addressing
Extended addressing mode
Offset byte in indexed, 8-bit offset addressing
Half-carry flag
High and low bytes of operand address in extended addressing
Interrupt mask
Immediate operand byte
Immediate addressing mode
Inherent addressing mode
Indexed, no offset addressing mode
Indexed, 8-bit offset addressing mode
Indexed, 16-bit offset addressing mode
Memory location
Negative flag
Any bit
opr
PC
PCH
PCL
REL
rel
rr
SP
X
Z
#
∧
∨
⊕
()
–( )
←
?
:
↕
—
↕ —
ff
4
3
3
5
4
Operand (one or two bytes)
Program counter
Program counter high byte
Program counter low byte
Relative addressing mode
Relative program counter offset byte
Relative program counter offset byte
Stack pointer
Index register
Zero flag
Immediate value
Logical AND
Logical OR
Logical EXCLUSIVE OR
Contents of
Negation (two’s complement)
Loaded with
If
Concatenated with
Set or cleared
Not affected
MC68HC705E5 — Rev. 1.0
General Release Specification
Instruction Set
For More Information On This Product,
Go to: www.freescale.com
A G R E E M E N T
dd
Cycles
3D
4D
5D
6D
7D
Description
N O N - D I S C L O S U R E
Test Memory Byte for Negative or Zero
A
C
CCR
dd
dd rr
DIR
ee ff
EXT
ff
H
hh ll
I
ii
IMM
INH
IX
IX1
IX2
M
N
n
DIR
INH
INH
IX1
IX
Effect on
CCR
H I N Z C
TST opr
TSTA
TSTX
TST opr,X
TST ,X
WAIT
Operand
Operation
Opcode
Freescale Semiconductor, Inc...
Source
Form
Address
Mode
Table 14-6. Instruction Set Summary (Continued)
R E Q U I R E D
Instruction Set
Instruction Set Summary
General Release Specification
Instruction Set
For More Information On This Product,
Go to: www.freescale.com
F
E
D
C
B
A
9
8
7
6
5
4
3
2
1
0
MSB
LSB
1
DIR
2
REL
Branch
3
DIR
4
5
INH
6
IX1
Read-Modify-Write
INH
7
IX
INH = Inherent
IMM = Immediate
DIR = Direct
EXT = Extended
REL = Relative
IX = Indexed, No Offset
IX1 = Indexed, 8-Bit Offset
IX2 = Indexed, 16-Bit Offset
1
1
1
1
1
1
1
2
2
2
2
2
2
2
2
2
EOR
IMM 2
2
ADC
IMM 2
2
ORA
IMM 2
2
ADD
IMM 2
2
2
SUB
IMM 2
2
CMP
IMM 2
2
SBC
IMM 2
2
CPX
IMM 2
2
AND
IMM 2
2
BIT
IMM 2
2
LDA
IMM 2
A
IMM
MSB
0
LSB
0
5
SUB
IX2 2
5
CMP
IX2 2
5
SBC
IX2 2
5
CPX
IX2 2
5
AND
IX2 2
5
BIT
IX2 2
5
LDA
IX2 2
6
STA
IX2 2
5
EOR
IX2 2
5
ADC
IX2 2
5
ORA
IX2 2
5
ADD
IX2 2
4
JMP
IX2 2
7
JSR
IX2 2
5
LDX
IX2 2
6
STX
IX2 2
D
IX2
4
SUB
IX1 1
4
CMP
IX1 1
4
SBC
IX1 1
4
CPX
IX1 1
4
AND
IX1 1
4
BIT
IX1 1
4
LDA
IX1 1
5
STA
IX1 1
4
EOR
IX1 1
4
ADC
IX1 1
4
ORA
IX1 1
4
ADD
IX1 1
3
JMP
IX1 1
6
JSR
IX1 1
4
LDX
IX1 1
5
STX
IX1 1
E
IX1
MSB of Opcode in Hexadecimal
4
SUB
EXT 3
4
CMP
EXT 3
4
SBC
EXT 3
4
CPX
EXT 3
4
AND
EXT 3
4
BIT
EXT 3
4
LDA
EXT 3
5
STA
EXT 3
4
EOR
EXT 3
4
ADC
EXT 3
4
ORA
EXT 3
4
ADD
EXT 3
3
JMP
EXT 3
6
JSR
EXT 3
4
LDX
EXT 3
5
STX
EXT 3
C
EXT
Register/Memory
3
SUB
DIR 3
3
CMP
DIR 3
3
SBC
DIR 3
3
CPX
DIR 3
3
AND
DIR 3
3
BIT
DIR 3
3
LDA
DIR 3
4
STA
DIR 3
3
EOR
DIR 3
3
ADC
DIR 3
3
ORA
DIR 3
3
ADD
DIR 3
2
JMP
DIR 3
5
JSR
DIR 3
3
LDX
DIR 3
4
STX
DIR 3
B
DIR
5 Number of Cycles
BRSET0 Opcode Mnemonic
3
DIR Number of Bytes/Addressing Mode
2
6
BSR
REL 2
2
LDX
2
IMM 2
2
TAX
INH
2
CLC
INH 2
2
SEC
INH 2
2
CLI
INH 2
2
SEI
INH 2
2
RSP
INH
2
NOP
INH 2
9
2
STOP
INH
2
2
TXA
WAIT
INH 1
INH
10
SWI
INH
9
RTI
INH
6
RTS
INH
8
INH
Control
INH
LSB of Opcode in Hexadecimal
5
5
3
5
3
3
6
5
BRSET0
BRA
BSET0
NEG
NEGA
NEGX
NEG
NEG
3
DIR 2
DIR 2
REL 2
DIR 1
INH 1
INH 2
IX1 1
IX 1
5
5
3
BRCLR0
BRN
BCLR0
3
1
DIR 2
DIR 2
REL
5
11
5
3
BRSET1
MUL
BHI
BSET1
3
1
DIR 2
INH
DIR 2
REL
5
5
3
5
3
3
6
5
BRCLR1
BLS
BCLR1
COM
COMA
COMX
COM
COM
3
DIR 2
DIR 2
REL 2
DIR 1
INH 1
INH 2
IX1 1
IX 1
5
5
3
5
3
3
6
5
BRSET2
BCC
BSET2
LSR
LSRA
LSRX
LSR
LSR
3
DIR 2
DIR 2
REL 2
DIR 1
INH 1
INH 2
IX1 1
IX
5
5
3
BRCLR2
BCLR2 BCS/BLO
3
DIR 2
DIR 2
REL
5
5
3
5
3
3
6
5
BRSET3
BNE
BSET3
ROR
RORA
RORX
ROR
ROR
3
DIR 2
DIR 2
REL 2
DIR 1
INH 1
INH 2
IX1 1
IX
5
5
3
5
3
3
6
5
BRCLR3
BEQ
BCLR3
ASR
ASRA
ASRX
ASR
ASR
3
DIR 2
DIR 2
REL 2
DIR 1
INH 1
INH 2
IX1 1
IX
5
5
3
5
3
3
6
5
BRSET4
BHCC
BSET4
ASL/LSL ASLA/LSLA ASLX/LSLX ASL/LSL ASL/LSL
3
DIR 2
DIR 2
REL 2
DIR 1
INH 1
INH 2
IX1 1
IX
5
5
3
5
3
3
6
5
BRCLR4
BHCS
BCLR4
ROL
ROLA
ROLX
ROL
ROL
3
DIR 2
DIR 2
REL 2
DIR 1
INH 1
INH 2
IX1 1
IX
5
5
3
5
3
3
6
5
BRSET5
BPL
BSET5
DEC
DECA
DECX
DEC
DEC
3
DIR 2
DIR 2
REL 2
DIR 1
INH 1
INH 2
IX1 1
IX
5
5
3
BRCLR5
BMI
BCLR5
3
DIR 2
DIR 2
REL
5
5
3
5
3
3
6
5
BRSET6
BMC
BSET6
INC
INCA
INCX
INC
INC
3
DIR 2
DIR 2
REL 2
DIR 1
INH 1
INH 2
IX1 1
IX
5
5
3
4
3
3
5
4
BRCLR6
BMS
BCLR6
TST
TSTA
TSTX
TST
TST
3
DIR 2
DIR 2
REL 2
DIR 1
INH 1
INH 2
IX1 1
IX
5
5
3
BRSET7
BIL
BSET7
3
1
DIR 2
DIR 2
REL
5
5
3
5
3
3
6
5
BRCLR7
BIH
BCLR7
CLR
CLRA
CLRX
CLR
CLR
3
DIR 2
DIR 2
REL 2
DIR 1
INH 1
INH 2
IX1 1
IX 1
0
DIR
Bit Manipulation
Table 14-7. Opcode Map
STX
LDX
JSR
JMP
ADD
ORA
ADC
EOR
STA
LDA
BIT
AND
CPX
SBC
CMP
SUB
F
IX
IX
IX
4
IX
3
IX
5
IX
2
IX
3
IX
3
IX
3
IX
3
IX
4
IX
3
IX
3
IX
3
IX
3
IX
3
IX
3
3
F
E
D
C
B
A
9
8
7
6
5
4
3
2
1
0
MSB
LSB
nc...
N O N - D I S C LFreescale
O S U R E Semiconductor,
A G R E E M E IN
T
R E Q U I R E D
Freescale Semiconductor, Inc.
Instruction Set
MC68HC705E5 — Rev. 1.0
Freescale Semiconductor, Inc...
15.1 Contents
15.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .133
15.3
Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .134
15.4
Operating Temperature Range. . . . . . . . . . . . . . . . . . . . . . . .135
15.5
Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . .135
15.6
DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . .136
15.7
Control Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .138
15.8
M-Bus Interface Input Signal Timing. . . . . . . . . . . . . . . . . . . .140
15.9
M-Bus Interface Output Signal Timing . . . . . . . . . . . . . . . . . .140
15.2 Introduction
This section contains the electrical and timing specifications.
MC68HC705E5 — Rev. 1.0
General Release Specification
Electrical Specifications
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A G R E E M E N T
Section 15. Electrical Specifications
N O N - D I S C L O S U R E
General Release Specification — MC68HC705E5
R E Q U I R E D
Freescale Semiconductor, Inc.
Freescale Semiconductor, Inc.
15.3 Maximum Ratings
Maximum ratings are the extreme limits to which the MCU can be
exposed without permanently damaging it.
The MCU contains circuitry to protect the inputs against damage from
high static voltages; however, do not apply voltages higher than those
shown in the table below. Keep VIN and VOUT within the range
VSS ≤ (VIN or VOUT) ≤ VDD. Connect unused inputs to the appropriate
voltage level, either VSS or VDD.
N O N - D I S C L O S U R E
Freescale Semiconductor, Inc...
A G R E E M E N T
R E Q U I R E D
Electrical Specifications
Rating
Symbol
Value
Unit
Supply Voltage
VDD
–0.3 to +7.0
V
Input Voltage
VIN
VSS –0.3 to
VDD +0.3
V
Bootloader Mode (IRQ Pin Only)
VIN
VSS –0.3 to
2 x VDD +0.3
V
I
25
mA
TSTG
–65 to +150
°C
Current Drain Per Pin Excluding VDD and VSS
Storage Temperature Range
NOTE:
This device is not guaranteed to operate properly at the maximum
ratings. Refer to 15.6 DC Electrical Characteristics for guaranteed
operating conditions.
General Release Specification
MC68HC705E5 — Rev. 1.0
Electrical Specifications
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Operating Temperature Range
MC68HC(7)05E5DW (Standard)
MC68HC(7)05E5P
Symbol
Value
Unit
TA
TL to TH
0 to +70
0 to +70
°C
Freescale Semiconductor, Inc...
15.5 Thermal Characteristics
Characteristic
Symbol
Value
Unit
Thermal Resistance
Plastic DIP
SOIC
θJA
60
60
°C/W
I/O Pin Power Dissipation
PI/O
User Determined
W
Power Dissipation(1)
PD
PD = (IDD x VDD) + PI/O =
K/(TJ + 273 °C)
W
Constant(2)
K
PD x (TA + 273 °C)
+ PD2 x θJA
W/°C
Average Junction Temperature
TJ
TA + (PD x θJA)
°C
TJM
125
°C
Maximum Junction Temperature
NOTES:
1. Power dissipation is a function of temperature.
2. K is a constant unique to the device. K can be determined for a known TA and
measured PD. With this value of K, PD and TJ can be determined for any value of TA.
MC68HC705E5 — Rev. 1.0
General Release Specification
Electrical Specifications
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A G R E E M E N T
Characteristic
N O N - D I S C L O S U R E
15.4 Operating Temperature Range
R E Q U I R E D
Electrical Specifications
Operating Temperature Range
Freescale Semiconductor, Inc.
N O N - D I S C L O S U R E
Freescale Semiconductor, Inc...
A G R E E M E N T
R E Q U I R E D
Electrical Specifications
15.6 DC Electrical Characteristics
Characteristic
Symbol
Min
Typ
Max
Unit
VOL
VOH
—
VDD –0.1
—
—
0.1
—
V
Output High Voltage
(ILOAD –0.8 mA) PA0–PA7, PB0–PB7, PC0–PC3
VOH
VDD –0.8
—
—
V
Output Low Voltage
(ILOAD = 1.6 mA) PA0–PA7, PB0–PB7, PC0–PC3
VOL
—
—
0.4
V
Input High Voltage
PA0–PA7, PB0–PB7, PC0–PC3, IRQ, RESET, OSC1
VIH
0.7 x VDD
—
VDD
V
Input Low Voltage
PA0–PA7, PB0–PB7, PC0–PC3, IRQ, RESET, OSC1
VIL
VSS
—
0.3 x VDD
V
EPROM Programming Voltage
VIN
14.5
—
15.5
V
XFC Wide Bandwidth
Source
Sink
IOH
IOL
–50
50
–100
100
—
—
µA
XFC Narrow Bandwidth
Source
Sink
IOH
IOL
–1
1
–2
2
—
—
µA
—
—
120
2.5
400
3.5
µA
mA
—
—
50
0.7
150
1
µA
mA
—
10
50
µA
Output Voltage
ILOAD = 10.0 µA
ILOAD = –10.0 µA
Supply Current (see Notes)
Run
(fosc = 32.768 kHz, fop = 16.384 kHz)
(fosc = 4.2 MHz, fop = 2.1 MHz)
Wait
(fosc = 32.768 kHz, fop = 16.384 kHz)
(fosc = 4.2 MHz, fop = 2.1 MHz)
Stop (PLL Off)
25 oC
IDD
I/O Ports Hi-Z Leakage Current
PA0–PA7, PB0–PB7, PC0–PC3
IOZ
—
—
10
µA
Input Current
RESET, IRQ, OSC1
IIN
—
—
1
µA
COUT
CINT
—
—
—
—
12
8
pF
Capacitance
Ports as Input or Output
RESET, IRQ
NOTES:
1. VDD = 5.0 Vdc ± 10%, VSS = 0 Vdc, TA = 0 °C to +70 °C, unless otherwise noted
2. Typical values at midpoint of voltage range, 25 °C only
3. Wait IDD: Only timer and CPI systems active
4. Run (Operating) IDD, wait IDD: Measured using external square wave clock source; all inputs 0.2 V from rail;
no dc loads; less than 50 pF on all outputs; CL = 20 pF on OSC2
5. Wait, stop IDD: All ports configured as inputs; VIL = 0.2; VIH = VDD –0.2 V
6. Stop IDD measured with OSC1 = VSS
7. Wait IDD affected linearly by the OSC2 capacitance
General Release Specification
MC68HC705E5 — Rev. 1.0
Electrical Specifications
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Freescale Semiconductor, Inc.
3.5
VDD = 5.0 V
TA = –0 °C to 70 °C
3.0
SUPPLY CURRENT (mA)
R E Q U I R E D
Electrical Specifications
DC Electrical Characteristics
2.5
2.0
D
NID
RU
1.5
1.0
WAIT
I DD
0.277
0.798
0.537
1.058
1.319
1.579
1.840
2.100
OPERATING FREQUENCY (MHz)
Figure 15-1. Maximum Supply Current
versus Operating Frequency
2.5
VDD = 5.0 V
TA = –0 °C to 70 °C
SUPPLY CURRENT (mA)
2.0
A G R E E M E N T
0
0.016
1.5
D
NID
RU
1.0
WAIT
0.5
I DD
0
0.016
0.277
0.537
0.798
1.058
1.579
1.319
1.840
2.100
OPERATING FREQUENCY (MHz)
Figure 15-2. Typical Supply Current
versus Operating Frequency
MC68HC705E5 — Rev. 1.0
General Release Specification
Electrical Specifications
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N O N - D I S C L O S U R E
Freescale Semiconductor, Inc...
0.5
Freescale Semiconductor, Inc.
N O N - D I S C L O S U R E
Freescale Semiconductor, Inc...
A G R E E M E N T
R E Q U I R E D
Electrical Specifications
15.7 Control Timing
Characteristic
Symbol
Min
Max
Unit
Frequency of Operation
Crystal Option
External Clock Option
fOSC
—
dc
32.768
4.2
kHz
MHz
Internal Operating Frequency
Crystal (fOSC ÷ 2)
External Clock (fOSC ÷ 2)
fOP
—
dc
16.384
2.1
kHz
MHz
Cycle Time
tcyc
480
—
ns
tEPGM
—
10
ms
RESET Pulse Width
tRL
1.5
—
tcyc
Interrupt Pulse Width Low (Edge-Triggered)
tILIH
125
—
ns
Interrupt Pulse Period
tILIL
see Note 2
—
tcyc
tOH, tOL
90
—
ns
tPLLS
50
—
ms
EPROM Byte Programming Time
OSC1 Pulse Width
PLL Startup Stabilization Time
NOTES:
1. VDD = 5.0 Vdc ± 10%, VSS = 0 Vdc, TA = 0 oC to +70 oC, unless otherwise noted
2. The minimum period, tILI, should not be less than the number of cycle times it takes to execute the
interrupt service routine plus 19 tcyc.
IRQ
tILIH
tILIH
IRQ1
tILIH
.
.
.
NORMALLY USED
WITH WIRE-ORed
CONNECTION
IRQn
IRQ
(MCU)
Figure 15-3. External Interrupt Mode Diagram
General Release Specification
MC68HC705E5 — Rev. 1.0
Electrical Specifications
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NEW
PCH
1FFE
4064 tCYC
NEW
PCL
1FFF
tCYC
NEW PC
VDD THRESHOLD (1 TO 2 V TYPICAL)
OP
CODE
NEW PC
3
tRL
1FFE
1FFE
1FFE
PCH
1FFE
MC68HC705E5 — Rev. 1.0
Electrical Specifications
For More Information On This Product,
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General Release Specification
N O N - D I S C L O S U R E
A G R E E M E N T
Figure 15-4. Power-On Reset and RESET
NOTES:
1. Internal timing signal and bus information are not available externally.
2. OSC1 line is not meant to represent frequency. It is only used to represent time.
3. The next rising edge of the internal processor clock following the rising edge of RESET initiates the reset sequence.
RESET
INTERNAL
DATA
BUS1
INTERNAL
ADDRESS
BUS1
INTERNAL
PROCESSOR
CLOCK1
OSC12
VDD
tVDDR
Freescale Semiconductor, Inc...
NEW PC
OP
CODE
NEW PC
R E Q U I R E D
PCL
1FFF
Freescale Semiconductor, Inc.
Electrical Specifications
Control Timing
Freescale Semiconductor, Inc.
N O N - D I S C L O S U R E
Freescale Semiconductor, Inc...
A G R E E M E N T
R E Q U I R E D
Electrical Specifications
15.8 M-Bus Interface Input Signal Timing
Characteristic
Symbol
Min
Max
Unit
tHD.STA
2
—
tcyc
Clock Low Period
tLOW
4.7
—
tcyc
Clock High Period
tHIGH
4
—
tcyc
SDA/SCL Rise Time
tR
—
1.0
ms
SDA/SCL Fall Time
tF
—
300
ns
Data Setup Time
tSU.DAT
250
—
ns
Data Hold Time
tHD.DAT
0
—
tcyc
Start Condition Setup Time (For Repeated Start Condition Only)
tSU.STA
2
—
tcyc
Stop Condition Setup Time
tSU.STO
2
—
tcyc
Start Condition Hold Time
NOTE: VDD = 5.0 Vdc ± 10%, VSS = 0 Vdc, TA = –40 oC to +85 oC, unless otherwise noted
15.9 M-Bus Interface Output Signal Timing
Characteristic
Symbol
Min
Max
Unit
tHD.STA
12
—
tcyc
Clock Low Period
tLOW
11
—
tcyc
Clock High Period
tHIGH
11
—
tcyc
SDA/SCL Rise Time
tR
—
1.0
ms
SDA/SCL Fall Time
tF
—
300
ns
Data Setup Time
tSU.DAT
tLow–tcyc
—
ns
Data Hold Time
tHD.DAT
0
—
tcyc
Start Condition Setup Time (For Repeated Start Condition Only)
tSU.STA
10
—
tcyc
Stop Condition Setup Time
tSU.STO
12
—
tcyc
Start Condition Hold Time
NOTE: VDD = 5.0 Vdc ± 10%, VSS = 0 Vdc, TA = –40 oC to +85 oC, unless otherwise noted
General Release Specification
MC68HC705E5 — Rev. 1.0
Electrical Specifications
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Freescale Semiconductor, Inc.
SDA
SCL
tLOW
Freescale Semiconductor, Inc...
tHD.DAT
tHIGH
tHD.STA
tSU.STO
tSU.DAT
N O N - D I S C L O S U R E
A G R E E M E N T
Figure 15-5. M-Bus Interface Timing
R E Q U I R E D
Electrical Specifications
M-Bus Interface Output Signal Timing
MC68HC705E5 — Rev. 1.0
General Release Specification
Electrical Specifications
For More Information On This Product,
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Freescale Semiconductor, Inc.
N O N - D I S C L O S U R E
Freescale Semiconductor, Inc...
A G R E E M E N T
R E Q U I R E D
Electrical Specifications
General Release Specification
MC68HC705E5 — Rev. 1.0
Electrical Specifications
For More Information On This Product,
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Freescale Semiconductor, Inc...
16.1 Contents
16.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .143
16.3
28-Pin Plastic Dual-in-Line Package
(Case 710-02) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .143
16.4
28-Pin Small Outline Integrated Circuit Package
(Case 751F-04) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .144
16.2 Introduction
This section describes the dimensions of the plastic dual in-line package
(PDIP) and small outline integrated circuit (SOIC) MCU packages.
16.3 28-Pin Plastic Dual-in-Line Package (Case 710-02)
28
! ! ! #! %% !
$" ! ! ! ! ! !
! ! # ! "
15
B
1
14
A
L
C
N
H
G
F
D
K
M
J
MC68HC705E5 — Rev. 1.0
°
°
°
°
General Release Specification
Mechanical Data
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A G R E E M E N T
Section 16. Mechanical Data
N O N - D I S C L O S U R E
General Release Specification — MC68HC705E5
R E Q U I R E D
Freescale Semiconductor, Inc.
Freescale Semiconductor, Inc.
R E Q U I R E D
Mechanical Data
16.4 28-Pin Small Outline Integrated Circuit Package (Case 751F-04)
-A28
! ! % ! !
! " !" $" !" ! "
!" #
!" !! $ ! $" !
!
15
14X
-B1
P
14
28X D
!
M
C
-T26X
-T-
G
K
F
J
°
°
°
°
N O N - D I S C L O S U R E
Freescale Semiconductor, Inc...
A G R E E M E N T
R X 45°
General Release Specification
MC68HC705E5 — Rev. 1.0
Mechanical Data
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Freescale Semiconductor, Inc...
17.1 Contents
17.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .145
17.3
MC Order Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .145
17.2 Introduction
This section contains ordering information.
17.3 MC Order Numbers
Table 17-1 shows the MC order numbers for the available package
types.
Table 17-1. MC Order Numbers
Package Type
Operating
Temperature
Range
MC Order Number
28-Pin Plastic Dual In-Line Package (PDIP)
0 °C to 70°C
MC68HC705E5P
28-Pin Small Outline Integrated Circuit
Package (SOIC)
0 °C to 70°C
MC68HC705E5DW
MC68HC705E5 — Rev. 1.0
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Ordering Information
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A G R E E M E N T
Section 17. Ordering Information
N O N - D I S C L O S U R E
General Release Specification — MC68HC705E5
R E Q U I R E D
Freescale Semiconductor, Inc.
Freescale Semiconductor, Inc.
N O N - D I S C L O S U R E
Freescale Semiconductor, Inc...
A G R E E M E N T
R E Q U I R E D
Ordering Information
General Release Specification
MC68HC705E5 — Rev. 1.0
Ordering Information
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Home Page:
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email:
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and its officers, employees, subsidiaries, affiliates, and distributors harmless against all
claims, costs, damages, and expenses, and reasonable attorney fees arising out of,
directly or indirectly, any claim of personal injury or death associated with such
unintended or unauthorized use, even if such claim alleges that Freescale
Semiconductor was negligent regarding the design or manufacture of the part.
© Motorola, Inc., 1997
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