Cypress CY7C1383FV25-100BGI 18-mbit (512k x 36/1m x 18) flow-through sram Datasheet

CY7C1381DV25, CY7C1381FV25
CY7C1383DV25, CY7C1383FV25
18-Mbit (512K x 36/1M x 18) Flow-Through SRAM
Functional Description [1]
Features
• Supports 133 MHz bus operations
• 512K x 36/1M x 18 common IO
• 2.5V core power supply (VDD)
• 2.5V IO supply (VDDQ)
• Fast clock-to-output times, 6.5 ns (133 MHz version)
• Provides high-performance 2-1-1-1 access rate
• User selectable burst counter supporting Intel® Pentium®
interleaved or linear burst sequences
• Separate processor and controller address strobes
• Synchronous self timed write
• Asynchronous output enable
• CY7C1381DV25/CY7C1383DV25 available in
JEDEC-standard Pb-free 100-pin TQFP, Pb-free and non
Pb-free 165-ball FBGA package.
CY7C1381FV25/CY7C1383FV25 available in Pb-free and
non Pb-free 119-ball BGA package
• IEEE 1149.1 JTAG-Compatible Boundary Scan
• ZZ sleep mode option
The
CY7C1381DV25/CY7C1383DV25/CY7C1381FV25/
CY7C1383FV25 is a 2.5V, 512K x 36 and 1M x 18
synchronous flow through SRAMs, designed to interface with
high-speed microprocessors with minimum glue logic.
Maximum access delay from clock rise is 6.5 ns (133 MHz
version). A 2-bit on-chip counter captures the first address in
a burst and increments the address automatically for the rest
of the burst access. All synchronous inputs are gated by
registers controlled by a positive edge triggered clock input
(CLK). The synchronous inputs include all addresses, all data
inputs, address pipelining chip enable (CE1), depth expansion
chip enables (CE2 and CE3 [2]), burst control inputs (ADSC,
ADSP, and ADV), write enables (BWx, and BWE), and global
write (GW). Asynchronous inputs include the output enable
(OE) and the ZZ pin.
CY7C1381DV25/CY7C1383DV25/CY7C1381FV25/
The
CY7C1383FV25 allows interleaved or linear burst sequences,
selected by the MODE input pin. A HIGH selects an
interleaved burst sequence, while a LOW selects a linear burst
sequence. Burst accesses can be initiated with the processor
address strobe (ADSP) or the cache controller address strobe
(ADSC) inputs. Address advancement is controlled by the
address advancement (ADV) input.
Addresses and chip enables are registered at rising edge of
clock when either address strobe processor (ADSP) or
address strobe controller (ADSC) are active. Subsequent
burst addresses can be internally generated as controlled by
the advance pin (ADV).
The
CY7C1381DV25/CY7C1383DV25/CY7C1381FV25/
CY7C1383FV25 operates from a +2.5V core power supply
while all outputs also operate with a +2.5 supply. All inputs and
outputs are JEDEC-standard and JESD8-5-compatible.
Selection Guide
133 MHz
100 MHz
Unit
Maximum Access Time
6.5
8.5
ns
Maximum Operating Current
210
175
mA
Maximum CMOS Standby Current
70
70
mA
Notes
1. For best practices or recommendations, please refer to the Cypress application note AN1064, SRAM System Design Guidelines on www.cypress.com.
2. CE3, CE2 are for TQFP and 165 FBGA package only. 119 BGA is offered only in 1 chip enable.
Cypress Semiconductor Corporation
Document #: 38-05547 Rev. *E
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised Feburary 14, 2007
[+] Feedback
CY7C1381DV25, CY7C1381FV25
CY7C1383DV25, CY7C1383FV25
Logic Block Diagram – CY7C1381DV25/CY7C1381FV25 [3] (512K x 36)
ADDRESS
REGISTER
A0, A1, A
A [1:0]
MODE
BURST Q1
COUNTER
AND LOGIC
Q0
CLR
ADV
CLK
ADSC
ADSP
DQ D , DQP D
DQ D , DQP D
BW D
BYTE
BYTE
WRITE REGISTER
WRITE REGISTER
DQ C , DQP C
DQ C , DQP C
BW C
WRITE REGISTER
WRITE REGISTER
DQ B , DQP B
MEMORY
ARRAY
DQ B , DQP B
BW B
SENSE
AMPS
OUTPUT
BUFFERS
DQs
DQP A
DQP B
DQP C
WRITE REGISTER
DQP D
WRITE REGISTER
DQ A , DQP
DQ A , DQP
BW A
BYTE
A
WRITE REGISTER
BYTE
BWE
WRITE REGISTER
INPUT
REGISTERS
GW
ENABLE
REGISTER
CE1
CE2
CE3
OE
SLEEP
Logic Block Diagram – CY7C1383DV25/CY7C1383FV25 [3] (1M x 18)
A0,A1,A
ADDRESS
REGISTER
A[1:0]
MODE
BURST Q1
COUNTER AND
ADV
Q0
DQ B ,DQP B
BW B
DQ A ,DQP A
BW A
DQ B ,DQP B
WRITE DRIVER
MEMORY
ARRAY
SENSE
AMPS
OUTPUT
BUFFERS
DQs
DQP A
DQP B
DQ A ,DQP A
WRITE DRIVER
BWE
GW
CE 1
CE 2
CE 3
ENABLE
INPUT
REGISTERS
OE
SLEEP
CONTROL
Note
3. CY7C1381FV25 and CY7C1383FV25 have only 1 chip enable (CE1).
Document #: 38-05547 Rev. *E
Page 2 of 28
[+] Feedback
CY7C1381DV25, CY7C1381FV25
CY7C1383DV25, CY7C1383FV25
Pin Configurations
NC
NC
NC
CY7C1383DV25
(1 Mbit x 18)
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
Document #: 38-05547 Rev. *E
A
NC
NC
VDDQ
VSSQ
NC
DQPA
DQA
DQA
VSSQ
VDDQ
DQA
DQA
VSS
NC
VDD
ZZ
DQA
DQA
VDDQ
VSSQ
DQA
DQA
NC
NC
VSSQ
VDDQ
NC
NC
NC
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
VDDQ
VSSQ
NC
NC
DQB
DQB
VSSQ
VDDQ
DQB
DQB
NC
VDD
NC
VSS
DQB
DQB
VDDQ
VSSQ
DQB
DQB
DQPB
NC
VSSQ
VDDQ
NC
NC
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
MODE
A
A
A
A
A1
A0
NC
NC
VSS
VDD
DQPB
DQB
DQB
VDDQ
VSSQ
DQB
DQB
DQB
DQB
VSSQ
VDDQ
DQB
DQB
VSS
NC
VDD
ZZ
DQA
DQA
VDDQ
VSSQ
DQA
DQA
DQA
DQA
VSSQ
VDDQ
DQA
DQA
DQPA
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
CY7C1381DV25
(512K x 36)
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
MODE
A
A
A
A
A1
A0
NC
NC
VSS
VDD
DQPC
DQC
DQC
VDDQ
VSSQ
DQC
DQC
DQC
DQC
VSSQ
VDDQ
DQC
DQC
NC
VDD
NC
VSS
DQD
DQD
VDDQ
VSSQ
DQD
DQD
DQD
DQD
VSSQ
VDDQ
DQD
DQD
DQPD
A
A
CE1
CE2
NC
NC
BWB
BWA
CE3
VDD
VSS
CLK
GW
BWE
OE
ADSC
ADSP
ADV
A
A
A
A
CE1
CE2
BWD
BWC
BWB
BWA
CE3
VDD
VSS
CLK
GW
BWE
OE
ADSC
ADSP
ADV
A
A
100-pin TQFP Pinout (3 Chip Enable)
Page 3 of 28
[+] Feedback
CY7C1381DV25, CY7C1381FV25
CY7C1383DV25, CY7C1383FV25
Pin Configurations (continued)
119-Ball BGA Pinout
CY7C1381FV25 (512K x 36)
A
1
VDDQ
2
A
3
A
B
C
NC/288M
NC/144M
A
A
A
A
D
E
DQC
DQC
DQPC
DQC
VSS
VSS
F
VDDQ
DQC
VSS
G
H
J
K
DQC
DQC
VDDQ
DQD
DQC
DQC
VDD
DQD
BWC
VSS
NC
VSS
ADV
NC
L
DQD
DQD
M
VDDQ
DQD
BWD
VSS
N
DQD
DQD
VSS
4
ADSP
5
A
6
A
7
VDDQ
ADSC
VDD
A
A
A
A
NC/576M
NC/1G
NC
CE1
VSS
VSS
DQPB
DQB
DQB
DQB
OE
VSS
DQB
VDDQ
BWB
VSS
NC
VSS
DQB
DQB
VDD
DQA
DQB
DQB
VDDQ
DQA
BWA
VSS
DQA
DQA
DQA
VDDQ
VSS
DQA
DQA
GW
VDD
CLK
BWE
A1
P
DQD
DQPD
VSS
A0
VSS
DQPA
DQA
R
NC
A
MODE
VDD
NC
A
NC
T
U
NC
VDDQ
NC/72M
TMS
A
TDI
A
TCK
A
TDO
NC/36M
NC
ZZ
VDDQ
CY7C1383FV25 (1M x 18)
1
2
3
4
5
6
7
A
VDDQ
A
A
ADSP
A
A
VDDQ
B
NC/288M
A
A
A
NC/144M
A
A
A
A
A
NC/576M
C
ADSC
VDD
D
DQB
NC
VSS
NC
VSS
DQPA
NC
E
NC
DQB
VSS
CE1
VSS
NC
DQA
F
VDDQ
NC
VSS
DQA
VDDQ
NC
DQB
VDDQ
DQB
NC
VDD
BWB
VSS
NC
OE
ADV
VSS
G
H
J
NC
VSS
NC
DQA
VDD
DQA
NC
VDDQ
K
NC
DQB
VSS
CLK
NC
DQA
L
M
DQB
VDDQ
NC
DQB
NC
VSS
NC
DQA
NC
NC
VDDQ
N
DQB
NC
VSS
BWE
A1
BWA
VSS
VSS
DQA
NC
P
NC
DQPB
VSS
A0
VSS
NC
DQA
R
T
U
NC
NC/72M
VDDQ
A
A
TMS
MODE
A
TDI
VDD
NC/36M
TCK
NC
A
TDO
A
A
NC
NC
ZZ
VDDQ
Document #: 38-05547 Rev. *E
GW
VDD
NC
VSS
NC/1G
Page 4 of 28
[+] Feedback
CY7C1381DV25, CY7C1381FV25
CY7C1383DV25, CY7C1383FV25
Pin Configurations (continued)
165-Ball FBGA Pinout (3 Chip Enable)
CY7C1381DV25 (512K x 36)
2
3
4
5
6
7
8
9
10
11
A
B
C
D
E
F
G
H
J
K
L
M
N
P
NC/288M
1
A
CE1
BWC
BWB
CE3
BWE
ADSC
ADV
A
NC
NC/144M
A
CE2
BWD
BWA
CLK
GW
OE
ADSP
A
NC/576M
DQPC
DQC
NC
DQC
VDDQ
VDDQ
VSS
VDD
VSS
VSS
VSS
VSS
VSS
VSS
VDD
VDDQ
VSS
VDDQ
NC/1G
DQB
DQPB
DQB
DQC
DQC
VDDQ
VDD
VSS
VSS
VSS
VDD
VDDQ
DQB
DQB
DQC
DQC
VDDQ
VDD
VSS
VSS
VSS
VDD
VDDQ
DQB
DQB
DQC
NC
DQD
DQC
NC
DQD
VDDQ
NC
VDDQ
VDD
VDD
VDD
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VDD
VDD
VDD
VDDQ
NC
VDDQ
DQB
NC
DQA
DQB
ZZ
DQA
DQD
DQD
VDDQ
VDD
VSS
VSS
VSS
VDD
VDDQ
DQA
DQA
DQD
DQD
VDDQ
VDD
VSS
VSS
VSS
VDD
VDDQ
DQA
DQA
DQD
DQPD
DQD
NC
VDDQ
VDDQ
VDD
VSS
VSS
NC
VSS
VDD
VSS
VDDQ
VDDQ
DQA
NC
DQA
DQPA
NC
NC/72M
A
A
TDI
A
A1
VSS
NC
TDO
A
A
A
A
R
MODE
NC/36M
A
A
TMS
A0
TCK
A
A
A
A
9
10
11
CY7C1383DV25 (1Mx 18)
1
2
3
4
A
B
C
D
E
F
G
H
J
K
L
M
N
P
NC/288M
A
CE1
BWB
NC/144M
A
CE2
NC
NC
NC
NC
DQB
VDDQ
VDDQ
VSS
VDD
NC
DQB
VDDQ
NC
NC
VSS
DQB
DQB
DQB
NC
NC
DQB
R
6
7
8
NC
CE3
BWE
ADSC
ADV
A
BWA
CLK
GW
OE
ADSP
A
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VDD
VDDQ
VDDQ
NC/1G
NC
DQPA
DQA
VDD
VSS
VSS
VSS
VDD
VDDQ
NC
DQA
VDDQ
VDDQ
NC
VDDQ
VDD
VSS
VSS
VSS
VSS
VSS
VDD
VDD
VDD
VDDQ
VDDQ
NC
VDDQ
NC
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VDD
VDD
VDD
VDD
NC
NC
DQA
DQA
DQA
ZZ
NC
NC
VDDQ
VDD
VSS
VSS
VSS
VDD
VDDQ
DQA
NC
DQB
NC
VDDQ
VDD
VSS
VSS
VSS
VDD
VDDQ
DQA
NC
DQB
DQPB
NC
NC
VDDQ
VDDQ
VDD
VSS
VSS
NC
VSS
A
VSS
NC
VDD
VSS
VDDQ
VDDQ
DQA
NC
NC
NC
NC
NC/72M
A
A
TDI
A1
TDO
A
A
A
A
MODE
NC/36M
A
A
TMS
A0
TCK
A
A
A
A
Document #: 38-05547 Rev. *E
5
A
NC/576M
Page 5 of 28
[+] Feedback
CY7C1381DV25, CY7C1381FV25
CY7C1383DV25, CY7C1383FV25
Pin Definitions
Name
IO
Description
A0, A1, A
InputSynchronous
Address inputs used to select one of the address locations. Sampled at the rising edge
of the CLK if ADSP or ADSC is active LOW, and CE1, CE2, and CE3 [2] are sampled active.
A[1:0] feed the 2-bit counter.
BWA, BWB
BWC, BWD
InputSynchronous
Byte write select inputs, active LOW. Qualified with BWE to conduct byte writes to the
SRAM. Sampled on the rising edge of CLK.
GW
InputSynchronous
Global write enable input, active LOW. When asserted LOW on the rising edge of CLK, a
global write is conducted (all bytes are written, regardless of the values on BW[A:D] and BWE).
CLK
InputClock
Clock input. Used to capture all synchronous inputs to the device. Also used to increment
the burst counter when ADV is asserted LOW, during a burst operation.
CE1
InputSynchronous
Chip enable 1 input, active LOW. Sampled on the rising edge of CLK. Used in conjunction
with CE2 and CE3 [2] to select or deselect the device. ADSP is ignored if CE1 is HIGH. CE1
is sampled only when a new external address is loaded.
CE2
InputSynchronous
Chip enable 2 input, active HIGH. Sampled on the rising edge of CLK. Used in conjunction
with CE1 and CE3 [2] to select or deselect the device. CE2 is sampled only when a new
external address is loaded.
CE3 [2]
InputSynchronous
Chip enable 3 input, active LOW. Sampled on the rising edge of CLK. Used in conjunction
with CE1 and CE2 to select or deselect the device. CE3 is sampled only when a new external
address is loaded.
OE
InputAsynchronous
Output enable, asynchronous input, active LOW. Controls the direction of the IO pins.
When LOW, the IO pins behave as outputs. When deasserted HIGH, IO pins are tri-stated,
and act as input data pins. OE is masked during the first clock of a read cycle when emerging
from a deselected state.
ADV
InputSynchronous
Advance input signal. Sampled on the rising edge of CLK. When asserted, it automatically
increments the address in a burst cycle.
ADSP
InputSynchronous
Address strobe from processor, sampled on the rising edge of CLK, active LOW. When
asserted LOW, addresses presented to the device are captured in the address registers.
A[1:0] are also loaded into the burst counter. When ADSP and ADSC are both asserted, only
ADSP is recognized. ASDP is ignored when CE1 is deasserted HIGH.
ADSC
InputSynchronous
Address strobe from controller, sampled on the rising edge of CLK, active LOW. When
asserted LOW, addresses presented to the device are captured in the address registers.
A[1:0] are also loaded into the burst counter. When ADSP and ADSC are both asserted, only
ADSP is recognized.
BWE
InputSynchronous
Byte write enable input, active LOW. Sampled on the rising edge of CLK. This signal must
be asserted LOW to conduct a byte write.
ZZ
InputAsynchronous
ZZ sleep input. This active HIGH input places the device in a non-time critical sleep
condition with data integrity preserved. For normal operation, this pin has to be LOW or left
floating. ZZ pin has an internal pull down.
DQs
IOSynchronous
Bidirectional data IO lines. As inputs, they feed into an on-chip data register that is triggered
by the rising edge of CLK. As outputs, they deliver the data contained in the memory location
specified by the addresses presented during the previous clock rise of the read cycle. The
direction of the pins is controlled by OE. When OE is asserted LOW, the pins behave as
outputs. When HIGH, DQs and DQPX are placed in a tri-state condition.The outputs are
automatically tri-stated during the data portion of a write sequence, during the first clock
when emerging from a deselected state, and when the device is deselected, regardless of
the state of OE.
DQPX
IOSynchronous
Bidirectional data parity IO lines. Functionally, these signals are identical to DQs. During
write sequences, DQPX is controlled by BWX correspondingly.
Document #: 38-05547 Rev. *E
Page 6 of 28
[+] Feedback
CY7C1381DV25, CY7C1381FV25
CY7C1383DV25, CY7C1383FV25
Pin Definitions (continued)
Name
MODE
VDD
VDDQ
VSS
VSSQ
IO
Description
Input-Static
Selects burst order. When tied to GND selects linear burst sequence. When tied to VDD or
left floating selects interleaved burst sequence. This is a strap pin and must remain static
during device operation. Mode pin has an internal pull up.
Power Supply
Power supply inputs to the core of the device.
IO Power Supply Power supply for the IO circuitry.
Ground
IO Ground
Ground for the core of the device.
Ground for the IO circuitry.
TDO
JTAG serial output Serial data-out to the JTAG circuit. Delivers data on the negative edge of TCK. If the JTAG
Synchronous
feature is not used, this pin can be left unconnected. This pin is not available on TQFP
packages.
TDI
JTAG serial input Serial data-in to the JTAG circuit. Sampled on the rising edge of TCK. If the JTAG feature
Synchronous
is not used, this pin can be left floating or connected to VDD through a pull up resistor. This
pin is not available on TQFP packages.
TMS
JTAG serial input Serial data-in to the JTAG circuit. Sampled on the rising edge of TCK. If the JTAG feature
Synchronous
is not used, this pin can be disconnected or connected to VDD. This pin is not available on
TQFP packages.
TCK
NC, NC/(36M,
72M, 144M,
288M, 576M,
1G)
VSS/DNU
JTAGClock
-
Ground/DNU
Clock input to the JTAG circuitry. If the JTAG feature is not used, this pin must be
connected to VSS. This pin is not available on TQFP packages.
No Connects. Not internally connected to the die. 36M, 72M, 144M, 288M, 576M, and 1G
are address expansion pins and are not internally connected to the die.
This pin can be connected to ground or can be left floating.
Functional Overview
All synchronous inputs pass through input registers controlled
by the rising edge of the clock. Maximum access delay from
the clock rise (t CDV) is 6.5 ns (133 MHz device).
The
CY7C1381DV25/CY7C1383DV25/CY7C1381FV25/
CY7C1383FV25 supports secondary cache in systems using
a linear or interleaved burst sequence. The interleaved burst
order supports Pentium® and i486™ processors. The linear
burst sequence is suited for processors that use a linear burst
sequence. The burst order is user selectable, and is
determined by sampling the MODE input. Accesses can be
initiated with either the processor address strobe (ADSP) or
the controller address strobe (ADSC). Address advancement
through the burst sequence is controlled by the ADV input. A
two-bit on-chip wraparound burst counter captures the first
address in a burst sequence and automatically increments the
address for the rest of the burst access.
Byte write operations are qualified with the byte write enable
(BWE) and byte write select (BWX) inputs. A global write
enable (GW) overrides all byte write inputs and writes data to
all four bytes. All writes are simplified with on-chip
synchronous self timed write circuitry.
Three synchronous chip selects (CE1, CE2, CE3 [2]) and an
asynchronous output enable (OE) provide for easy bank
Document #: 38-05547 Rev. *E
selection and output tri-state control. ADSP is ignored if CE1
is HIGH.
Single Read Accesses
A single read access is initiated when the following conditions
are satisfied at clock rise: (1) CE1, CE2, and CE3 [2] are all
asserted active, and (2) ADSP or ADSC is asserted LOW (if
the access is initiated by ADSC, the write inputs must be
deserted during this first cycle). The address presented to the
address inputs is latched into the address register and the
burst counter and/or control logic, and presented to the
memory core. If the OE input is asserted LOW, the requested
data will be available at the data outputs with a maximum to
tCDV after clock rise. ADSP is ignored if CE1 is HIGH.
Single Write Accesses Initiated by ADSP
This access is initiated when the following conditions are
satisfied at clock rise: (1) CE1, CE2, CE3 [2] are all asserted
active, and (2) ADSP is asserted LOW. The addresses
presented are loaded into the address register and the burst
inputs (GW, BWE, and BWX) are ignored during this first clock
cycle. If the write inputs are asserted active (see Truth Table
for Read/Write [4, 9] on page 10 for appropriate states that
indicate a write) on the next clock rise, the appropriate data will
be latched and written into the device. Byte writes are allowed.
All IOs are tri-stated during a byte write. As this is a common
IO device, the asynchronous OE input signal must be deserted
Page 7 of 28
[+] Feedback
CY7C1381DV25, CY7C1381FV25
CY7C1383DV25, CY7C1383FV25
and the IOs must be tri-stated prior to the presentation of data
to DQs. As a safety precaution, the data lines are tri-stated
once a write cycle is detected, regardless of the state of OE.
Single Write Accesses Initiated by ADSC
This write access is initiated when the following conditions are
satisfied at clock rise: (1) CE1, CE2, and CE3 [2] are all
asserted active, (2) ADSC is asserted LOW, (3) ADSP is
deserted HIGH, and (4) the write input signals (GW, BWE, and
BWX) indicate a write access. ADSC is ignored if ADSP is
active LOW.
The addresses presented are loaded into the address register
and the burst counter, the control logic, or both, and delivered
to the memory core. The information presented to DQX will be
written into the specified address location. Byte writes are
allowed. All IOs are tri-stated when a write is detected, even a
byte write. Since this is a common IO device, the
asynchronous OE input signal must be deasserted and the IOs
must be tri-stated prior to the presentation of data to DQs. As
a safety precaution, the data lines are tri-stated once a write
cycle is detected, regardless of the state of OE.
Burst Sequences
The
CY7C1381DV25/CY7C1383DV25/CY7C1381FV25/
CY7C1383FV25 provides an on-chip two-bit wraparound burst
counter inside the SRAM. The burst counter is fed by A[1:0],
and can follow either a linear or interleaved burst order. The
burst order is determined by the state of the MODE input. A
LOW on MODE will select a linear burst sequence. A HIGH on
MODE will select an interleaved burst order. Leaving MODE
unconnected will cause the device to default to a interleaved
burst sequence.
Sleep Mode
The ZZ input pin is an asynchronous input. Asserting ZZ
places the SRAM in a power conservation sleep mode. Two
clock cycles are required to enter into or exit from this sleep
mode. While in this mode, data integrity is guaranteed.
Accesses pending when entering the sleep mode are not
considered valid nor is the completion of the operation
guaranteed. The device must be deselected prior to entering
the sleep mode. CE1, CE2, CE3 [2], ADSP, and ADSC must
remain inactive for the duration of tZZREC after the ZZ input
returns LOW.
Interleaved Burst Address Table
(MODE = Floating or VDD)
First
Address
A1: A0
Second
Address
A1: A0
Third
Address
A1: A0
Fourth
Address
A1: A0
00
01
10
11
01
00
11
10
10
11
00
01
11
10
01
00
Linear Burst Address Table (MODE = GND)
First
Address
A1: A0
Second
Address
A1: A0
Third
Address
A1: A0
Fourth
Address
A1: A0
00
01
10
11
01
10
11
00
10
11
00
01
11
00
01
10
ZZ Mode Electrical Characteristics
Parameter
Description
Test Conditions
IDDZZ
Sleep mode standby current
ZZ > VDD – 0.2V
tZZS
Device operation to ZZ
ZZ > VDD – 0.2V
tZZREC
ZZ recovery time
ZZ < 0.2V
tZZI
ZZ active to sleep current
This parameter is sampled
tRZZI
ZZ Inactive to exit sleep current
This parameter is sampled
Document #: 38-05547 Rev. *E
Min.
Max.
Unit
80
mA
2tCYC
ns
2tCYC
ns
2tCYC
0
ns
ns
Page 8 of 28
[+] Feedback
CY7C1381DV25, CY7C1381FV25
CY7C1383DV25, CY7C1383FV25
Truth Table [4, 5, 6, 7, 8]
Cycle Description
Address
Used
CE1 CE2 CE3 ZZ
ADSP
ADSC
ADV WRITE
OE
CLK
DQ
Deselected Cycle, Power
Down
None
H
X
X
L
X
L
X
X
X
L-H Tri-State
Deselected Cycle, Power
Down
None
L
L
X
L
L
X
X
X
X
L-H Tri-State
Deselected Cycle, Power
Down
None
L
X
H
L
L
X
X
X
X
L-H Tri-State
Deselected Cycle, Power
Down
None
L
L
X
L
H
L
X
X
X
L-H Tri-State
Deselected Cycle, Power
Down
None
X
X
X
L
H
L
X
X
X
L-H Tri-State
Sleep Mode, Power Down
None
X
X
X
H
X
X
X
X
X
X
Tri-State
Read Cycle, Begin Burst
Read Cycle, Begin Burst
Write Cycle, Begin Burst
Read Cycle, Begin Burst
Read Cycle, Begin Burst
Read Cycle, Continue Burst
Read Cycle, Continue Burst
Read Cycle, Continue Burst
External
External
External
External
External
Next
Next
Next
L
L
L
L
L
X
X
H
H
H
H
H
H
X
X
X
L
L
L
L
L
X
X
X
L
L
L
L
L
L
L
L
L
L
H
H
H
H
H
X
X
X
L
L
L
H
H
H
X
X
X
X
X
L
L
L
X
X
L
H
H
H
H
H
L
H
X
L
H
L
H
L
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
Q
Tri-State
D
Q
Tri-State
Q
Tri-State
Q
Read Cycle, Continue Burst
Next
H
X
X
L
X
H
L
H
H
L-H Tri-State
Write Cycle, Continue Burst
Next
X
X
X
L
H
H
L
L
X
L-H D
Write Cycle, Continue Burst
Next
H
X
X
L
X
H
L
L
X
L-H D
Read Cycle, Suspend Burst
Current
X
X
X
L
H
H
H
H
L
L-H Q
Read Cycle, Suspend Burst
Current
X
X
X
L
H
H
H
H
H
L-H Tri-State
Read Cycle, Suspend Burst
Current
H
X
X
L
X
H
H
H
L
L-H Q
Read Cycle, Suspend Burst
Current
H
X
X
L
X
H
H
H
H
L-H Tri-State
Write Cycle, Suspend Burst
Current
X
X
X
L
H
H
H
L
X
L-H D
Write Cycle, Suspend Burst
Current
H
X
X
L
X
H
H
L
X
L-H D
Notes
4. X = Don't Care, H = Logic HIGH, L = Logic LOW.
5. WRITE = L when any one or more byte write enable signals, and BWE = L or GW = L. WRITE = H when all byte write enable signals, BWE, GW = H.
6. The DQ pins are controlled by the current cycle and the OE signal. OE is asynchronous and is not sampled with the clock.
7. The SRAM always initiates a read cycle when ADSP is asserted, regardless of the state of GW, BWE, or BWX. Writes may occur only on subsequent clocks after
the ADSP or with the assertion of ADSC. As a result, OE must be driven HIGH prior to the start of the write cycle to allow the outputs to tri-state. OE is a don't
care for the remainder of the write cycle.
8. OE is asynchronous and is not sampled with the clock rise. It is masked internally during write cycles. During a read cycle all data bits are tri-state when OE is
inactive or when the device is deselected, and all data bits behave as output when OE is active (LOW).
Document #: 38-05547 Rev. *E
Page 9 of 28
[+] Feedback
CY7C1381DV25, CY7C1381FV25
CY7C1383DV25, CY7C1383FV25
Truth Table for Read/Write [4, 9]
Function (CY7C1381DV25/CY7C1381FV25)
GW
BWE
BWD
BWC
BWB
BWA
Read
H
H
X
X
X
X
Read
H
L
H
H
H
H
Write Byte A (DQA, DQPA)
H
L
H
H
H
L
Write Byte B (DQB, DQPB)
H
L
H
H
L
H
Write Bytes A, B (DQA, DQB, DQPA, DQPB)
H
L
H
H
L
L
Write Byte C (DQC, DQPC)
H
L
H
L
H
H
Write Bytes C, A (DQC, DQA, DQPC, DQPA)
H
L
H
L
H
L
Write Bytes C, B (DQC, DQB, DQPC, DQPB)
H
L
H
L
L
H
Write Bytes C, B, A (DQC, DQB, DQA, DQPC,
DQPB, DQPA)
H
L
H
L
L
L
Write Byte D (DQD, DQPD)
H
L
L
H
H
H
Write Bytes D, A (DQD, DQA, DQPD, DQPA)
H
L
L
H
H
L
Write Bytes D, B (DQD, DQA, DQPD, DQPA)
H
L
L
H
L
H
Write Bytes D, B, A (DQD, DQB, DQA, DQPD,
DQPB, DQPA)
H
L
L
H
L
L
Write Bytes D, B (DQD, DQB, DQPD, DQPB)
H
L
L
L
H
H
Write Bytes D, B, A (DQD, DQC, DQA, DQPD,
DQPC, DQPA)
H
L
L
L
H
L
Write Bytes D, C, A (DQD, DQB, DQA, DQPD,
DQPB, DQPA)
H
L
L
L
L
H
Write All Bytes
H
L
L
L
L
L
Write All Bytes
L
X
X
X
X
X
Truth Table for Read/Write [4, 9]
Function (CY7C1383DV25/CY7C1383FV25)
GW
BWE
BWB
BWA
Read
H
H
X
X
Read
H
L
H
H
Write Byte A – (DQA and DQPA)
H
L
H
L
Write Byte B – (DQB and DQPB)
H
L
L
H
Write All Bytes
H
L
L
L
Write All Bytes
L
X
X
X
Note
9. Table only lists a partial listing of the byte write combinations. Any combination of BWX is valid. Appropriate write will be done based on which byte write is active.
Document #: 38-05547 Rev. *E
Page 10 of 28
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CY7C1381DV25, CY7C1381FV25
CY7C1383DV25, CY7C1383FV25
IEEE 1149.1 Serial Boundary Scan (JTAG)
Test Data-In (TDI)
The CY7C1381DV25/CY7C1383DV25 incorporates a serial
boundary scan test access port (TAP). This part is fully
compliant with 1149.1. The TAP operates using
JEDEC-standard 3.3V or 2.5V IO logic levels.
The CY7C1381DV25/CY7C1383DV25 contains a TAP
controller, instruction register, boundary scan register, bypass
register, and ID register.
The TDI ball is used to serially input information into the
registers and can be connected to the input of any of the
registers. The register between TDI and TDO is chosen by the
instruction that is loaded into the TAP instruction register. For
information on loading the instruction register, see TAP
Controller State Diagram. TDI is internally pulled up and can
be unconnected if the TAP is unused in an application. TDI is
connected to the most significant bit (MSB) of any register.
(See TAP Controller Block Diagram).
Disabling the JTAG Feature
It is possible to operate the SRAM without using the JTAG
feature. To disable the TAP controller, TCK must be tied LOW
(VSS) to prevent clocking of the device. TDI and TMS are
internally pulled up and may be unconnected. They may
alternately be connected to VDD through a pull up resistor.
TDO may be left unconnected. Upon power up, the device will
come up in a reset state, which will not interfere with the
operation of the device.
Test Data-Out (TDO)
The TDO output ball is used to serially clock data out from the
registers. The output is active depending upon the current
state of the TAP state machine. The output changes on the
falling edge of TCK. TDO is connected to the least significant
bit (LSB) of any register. (See TAP Controller State Diagram.)
TAP Controller Block Diagram
TAP Controller State Diagram
1
0
TEST-LOGIC
RESET
Bypass Register
0
0
RUN-TEST/
IDLE
2 1 0
1
SELECT
DR-SCAN
1
SELECT
IR-SCAN
0
1
1
CAPTURE-DR
Selection
Circuitry
0
CAPTURE-IR
S
election
Circuitr
TDO
y
Identification Register
x . . . . . 2 1 0
SHIFT-IR
1
Instruction Register
31 30 29 . . . 2 1 0
0
SHIFT-DR
0
Boundary Scan Register
1
EXIT1-DR
1
EXIT1-IR
0
1
TCK
0
PAUSE-DR
0
PAUSE-IR
1
0
TMS
TAP CONTROLLER
1
EXIT2-DR
0
EXIT2-IR
Performing a TAP Reset
1
1
UPDATE-DR
UPDATE-IR
1
TDI
0
0
0
1
0
1
0
The 0 or 1 next to each state represents the value of TMS at
the rising edge of TCK.
Test Access Port (TAP)
Test Clock (TCK)
The test clock is used only with the TAP controller. All inputs
are captured on the rising edge of TCK. All outputs are driven
from the falling edge of TCK.
Test MODE SELECT (TMS)
The TMS input is used to give commands to the TAP controller
and is sampled on the rising edge of TCK. This pin may be left
unconnected if the TAP is not used. The ball is pulled up
internally, resulting in a logic HIGH level.
Document #: 38-05547 Rev. *E
A Reset is performed by forcing TMS HIGH (VDD) for five rising
edges of TCK. This Reset does not affect the operation of the
SRAM and may be performed while the SRAM is operating. At
power up, the TAP is reset internally to ensure that TDO
comes up in a High-Z state.
TAP Registers
Registers are connected between the TDI and TDO balls and
allow data to be scanned in and out of the SRAM test circuitry.
Only one register can be selected at a time through the
instruction registers. Data is serially loaded into the TDI ball on
the rising edge of TCK. Data is output on the TDO ball on the
falling edge of TCK.
Instruction Register
Three-bit instructions can be serially loaded into the instruction
register. This register is loaded when it is placed between the
TDI and TDO balls as shown in the TAP Controller Block
Diagram. Upon power up, the instruction register is loaded
with the IDCODE instruction. It is also loaded with the IDCODE
instruction if the controller is placed in a reset state as
described in the previous section.
Page 11 of 28
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CY7C1381DV25, CY7C1381FV25
CY7C1383DV25, CY7C1383FV25
When the TAP controller is in the Capture-IR state, the two
least significant bits are loaded with a binary ‘01’ pattern to
allow for fault isolation of the board level serial test data path.
Bypass Register
To save time when serially shifting data through registers, it is
sometimes advantageous to skip certain chips. The bypass
register is a single-bit register that can be placed between the
TDI and TDO balls. This allows data to be shifted through the
SRAM with minimal delay. The bypass register is set LOW
(VSS) when the BYPASS instruction is executed.
Boundary Scan Register
The boundary scan register is connected to all the input and
bidirectional balls on the SRAM.
The boundary scan register is loaded with the contents of the
RAM IO ring when the TAP controller is in the Capture-DR
state and is then placed between the TDI and TDO balls when
the controller is moved to the Shift-DR state. The EXTEST,
SAMPLE/PRELOAD, and SAMPLE Z instructions can be used
to capture the contents of the input and output ring.
The boundary scan order tables show the order in which the
bits are connected. Each bit corresponds to one of the bumps
on the SRAM package. The MSB of the register is connected
to TDI, and the LSB is connected to TDO.
(ID) Register
The ID register is loaded with a vendor specific 32-bit code
during the Capture-DR state when the IDCODE command is
loaded in the instruction register. The IDCODE is hardwired
into the SRAM and can be shifted out when the TAP controller
is in the Shift-DR state. The ID register has a vendor code and
other information described in the Identification Register
Definitions on page 14.
TAP Instruction Set
Overview
Eight different instructions are possible with the three bit
instruction register. All combinations are listed in Identification
Codes on page 15. Three of these instructions are listed as
RESERVED and must not be used. The other five instructions
are described in detail below.
Instructions are loaded into the TAP controller during the
Shift-IR state, when the instruction register is placed between
TDI and TDO. During this state, instructions are shifted
through the instruction register through the TDI and TDO balls.
To execute the instruction once it is shifted in, the TAP
controller needs to be moved into the Update-IR state.
EXTEST
The EXTEST instruction enables the preloaded data to be
driven out through the system output pins. This instruction also
selects the boundary scan register to be connected for serial
access between the TDI and TDO in the Shift-DR controller
state.
IDCODE
The IDCODE instruction causes a vendor specific 32-bit code
to be loaded into the instruction register. It also places the
instruction register between the TDI and TDO balls and allows
Document #: 38-05547 Rev. *E
the IDCODE to be shifted out of the device when the TAP
controller enters the Shift-DR state.
The IDCODE instruction is loaded into the instruction register
upon power up or whenever the TAP controller is given a test
logic reset state.
SAMPLE Z
The SAMPLE Z instruction causes the boundary scan register
to be connected between the TDI and TDO balls when the TAP
controller is in a Shift-DR state. The SAMPLE Z command
places all SRAM outputs into a High-Z state.
SAMPLE/PRELOAD
SAMPLE/PRELOAD is a 1149.1 mandatory instruction. When
the SAMPLE/PRELOAD instructions are loaded into the
instruction register and the TAP controller is in the Capture-DR
state, a snapshot of data on the inputs and output pins is
captured in the boundary scan register.
The user must be aware that the TAP controller clock can only
operate at a frequency up to 20 MHz, while the SRAM clock
operates more than an order of magnitude faster. Because
there is a large difference in the clock frequencies, it is
possible that during the Capture-DR state, an input or output
will undergo a transition. The TAP may then try to capture a
signal while in transition (metastable state). This will not harm
the device, but there is no guarantee as to the value that will
be captured. Repeatable results may not be possible.
To guarantee that the boundary scan register will capture the
correct value of a signal, the SRAM signal must be stabilized
long enough to meet the TAP controller's capture setup plus
hold times (tCS and tCH). The SRAM clock input might not be
captured correctly if there is no way in a design to stop (or
slow) the clock during a SAMPLE/PRELOAD instruction. If this
is an issue, it is still possible to capture all other signals and
simply ignore the value of the CK and CK captured in the
boundary scan register.
Once the data is captured, it is possible to shift out the data by
putting the TAP into the Shift-DR state. This places the
boundary scan register between the TDI and TDO pins.
PRELOAD allows an initial data pattern to be placed at the
latched parallel outputs of the boundary scan register cells
prior to the selection of another boundary scan test operation.
The shifting of data for the SAMPLE and PRELOAD phases
can occur concurrently when required; that is, while data
captured is shifted out, the preloaded data is shifted in.
BYPASS
When the BYPASS instruction is loaded in the instruction
register and the TAP is placed in a Shift-DR state, the bypass
register is placed between the TDI and TDO balls. The
advantage of the BYPASS instruction is that it shortens the
boundary scan path when multiple devices are connected
together on a board.
EXTEST Output Bus Tri-State
IEEE Standard 1149.1 mandates that the TAP controller be
able to put the output bus into a tri-state mode.
The boundary scan register has a special bit located at bit #85
(for 119-BGA package) or bit #89 (for 165-fBGA package).
When this scan cell, called the “extest output bus tri-state,” is
latched into the preload register during the Update-DR state in
Page 12 of 28
[+] Feedback
CY7C1381DV25, CY7C1381FV25
CY7C1383DV25, CY7C1383FV25
the TAP controller, it will directly control the state of the output
(Q-bus) pins, when the EXTEST is entered as the current
instruction. When HIGH, it will enable the output buffers to
drive the output bus. When LOW, this bit will place the output
bus into a High-Z condition.
register. When the EXTEST instruction is entered, this bit will
directly control the output Q-bus pins. Note that this bit is
preset HIGH to enable the output when the device is powered
up, and also when the TAP controller is in the Test-Logic-Reset
state.
This bit can be set by entering the SAMPLE/PRELOAD or
EXTEST command, and then shifting the desired bit into that
cell, during the Shift-DR state. During Update-DR, the value
loaded into that shift-register cell will latch into the preload
Reserved
These instructions are not implemented but are reserved for
future use. Do not use these instructions.
TAP Timing
1
2
3
Test Clock
(TCK)
t
t TH
t TMSS
t TMSH
t TDIS
t TDIH
TL
4
5
6
t CYC
Test Mode Select
(TMS)
Test Data-In
(TDI)
t TDOV
t TDOX
Test Data-Out
(TDO)
DON’T CARE
UNDEFINED
TAP AC Switching Characteristics
Over the Operating Range [10, 11]
Parameter
Description
Min.
Max.
Unit
Clock
tTCYC
TCK Clock Cycle Time
tTF
TCK Clock Frequency
tTH
TCK Clock HIGH time
20
ns
tTL
TCK Clock LOW time
20
ns
50
ns
20
MHz
Output Times
tTDOV
TCK Clock LOW to TDO Valid
tTDOX
TCK Clock LOW to TDO Invalid
0
ns
tTMSS
TMS Setup to TCK Clock Rise
5
ns
tTDIS
TDI Setup to TCK Clock Rise
5
ns
tCS
Capture Setup to TCK Rise
5
ns
tTMSH
TMS Hold after TCK Clock Rise
5
ns
tTDIH
TDI Hold after Clock Rise
5
ns
tCH
Capture Hold after Clock Rise
5
ns
10
ns
Setup Times
Hold Times
Notes
10. tCS and tCH refer to the setup and hold time requirements of latching data from the boundary scan register.
11. Test conditions are specified using the load in TAP AC test conditions. tR/tF = 1 ns.
Document #: 38-05547 Rev. *E
Page 13 of 28
[+] Feedback
CY7C1381DV25, CY7C1381FV25
CY7C1383DV25, CY7C1383FV25
2.5V TAP AC Test Conditions
2.5V TAP AC Output Load Equivalent
1.25V
Input pulse levels .................................................VSS to 2.5V
Input rise and fall time..................................................... 1 ns
50Ω
Input timing reference levels .........................................1.25V
Output reference levels.................................................1.25V
TDO
Test load termination supply voltage.............................1.25V
Z O= 50 Ω
20pF
TAP DC Electrical Characteristics And Operating Conditions
(0°C < TA < +70°C; VDD = 2.5V ±0.125V unless otherwise noted) [12]
Parameter
Description
Test Conditions
Min.
Max.
Unit
VOH1
Output HIGH Voltage
IOH = –1.0 mA, VDDQ = 2.5V
2.0
V
VOH2
Output HIGH Voltage
IOH = –100 µA, VDDQ = 2.5V
2.1
V
VOL1
Output LOW Voltage
IOL = 8.0 mA, VDDQ = 2.5V
0.4
V
VOL2
Output LOW Voltage
IOL = 100 µA
0.2
V
VDDQ = 2.5V
VIH
Input HIGH Voltage
VDDQ = 2.5V
1.7
VDD + 0.3
V
VIL
Input LOW Voltage
VDDQ = 2.5V
–0.3
0.7
V
IX
Input Load Current
–5
5
µA
GND < VIN < VDDQ
Identification Register Definitions
Instruction Field
CY7C1381DV25/
CY7C1381FV25
(512K x 36)
CY7C1383DV25/
CY7C1383FV25
(1 Mbit x 18)
000
000
Revision Number (31:29)
Device Depth (28:24)
Device Width (23:18) 119-BGA
Description
Describes the version number
01011
01011
101001
101001
Defines the memory type and architecture
Reserved for internal use.
Device Width (23:18) 165-FBGA
000001
000001
Defines the memory type and architecture
Cypress Device ID (17:12)
100101
010101
Defines the width and density
00000110100
00000110100
1
1
Cypress JEDEC ID Code (11:1)
ID Register Presence Indicator (0)
Allows unique identification of SRAM vendor
Indicates the presence of an ID register
Scan Register Sizes
Register Name
Bit Size (x36)
Bit Size (x18)
Instruction Bypass
3
3
Bypass
1
1
ID
32
32
Boundary Scan Order (119-ball BGA package)
85
85
Boundary Scan Order (165-ball FBGA package)
89
89
Note
12. All voltages referenced to VSS (GND).
Document #: 38-05547 Rev. *E
Page 14 of 28
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CY7C1381DV25, CY7C1381FV25
CY7C1383DV25, CY7C1383FV25
Identification Codes
Instruction
Code
Description
EXTEST
000
Captures IO ring contents. Places the boundary scan register between TDI and TDO.
Forces all SRAM outputs to High-Z state.
IDCODE
001
Loads the ID register with the vendor ID code and places the register between TDI and
TDO. This operation does not affect SRAM operations.
SAMPLE Z
010
Captures IO ring contents. Places the boundary scan register between TDI and TDO.
Forces all SRAM output drivers to a High-Z state.
RESERVED
011
Do Not Use. This instruction is reserved for future use.
SAMPLE/PRELOAD
100
Captures IO ring contents. Places the boundary scan register between TDI and TDO.
Does not affect SRAM operation.
RESERVED
101
Do Not Use. This instruction is reserved for future use.
RESERVED
110
Do Not Use. This instruction is reserved for future use.
BYPASS
111
Places the bypass register between TDI and TDO. This operation does not affect SRAM
operations.
119-Ball BGA Boundary Scan Order [13, 14]
Bit #
Ball ID
Bit #
Ball ID
Bit #
Ball ID
Bit #
Ball ID
1
23
F6
45
G4
67
L1
2
H4
T4
24
E7
46
A4
68
M2
3
T5
25
D7
47
G3
69
N1
4
T6
26
H7
48
C3
70
P1
5
R5
27
G6
49
B2
71
K1
6
L5
28
E6
50
B3
72
L2
7
R6
29
D6
51
A3
73
8
U6
30
C7
52
C2
74
N2
P2
9
R7
31
B7
53
A2
75
R3
10
T7
32
C6
54
B1
76
T1
11
P6
33
A6
55
C1
77
R1
12
N7
34
C5
56
D2
78
T2
13
M6
35
B5
57
E1
79
L3
14
L7
36
G5
58
F2
80
R2
15
K6
37
B6
59
G1
81
T3
16
P7
38
D4
60
H2
82
L4
17
N6
39
B4
61
D1
83
N4
18
L6
40
F4
62
E2
84
P4
19
K7
41
M4
63
G2
85
Internal
20
J5
42
A5
64
H1
21
H6
43
K4
65
J3
22
G7
44
E4
66
2K
Notes
13. Balls that are NC (No Connect) are preset LOW.
14. Bit #85 is preset HIGH.
Document #: 38-05547 Rev. *E
Page 15 of 28
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CY7C1381DV25, CY7C1381FV25
CY7C1383DV25, CY7C1383FV25
165-Ball BGA Boundary Scan Order [13, 15]
Bit #
Ball ID
Bit #
Ball ID
Bit #
Ball ID
1
N6
31
D10
61
G1
2
N7
32
C11
62
D2
3
N10
33
A11
63
E2
4
P11
34
B11
64
F2
5
P8
35
A10
65
G2
6
R8
36
B10
66
H1
7
R9
37
A9
67
H3
8
P9
38
B9
68
J1
9
P10
39
C10
69
K1
10
R10
40
A8
70
L1
11
R11
41
B8
71
M1
12
H11
42
A7
72
J2
13
N11
43
B7
73
K2
14
M11
44
B6
74
L2
15
L11
45
A6
75
M2
16
K11
46
B5
76
N1
17
J11
47
A5
77
N2
18
M10
48
A4
78
P1
19
L10
49
B4
79
R1
20
K10
50
B3
80
R2
21
J10
51
A3
81
P3
22
H9
52
A2
82
R3
23
H10
53
B2
83
P2
24
G11
54
C2
84
R4
25
F11
55
B1
85
P4
26
E11
56
A1
86
N5
27
D11
57
C1
87
P6
28
G10
58
D1
88
R6
29
F10
59
E1
89
Internal
30
E10
60
F1
Note
15. Bit #89 is preset HIGH.
Document #: 38-05547 Rev. *E
Page 16 of 28
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CY7C1383DV25, CY7C1383FV25
Maximum Ratings
DC Input Voltage ................................... –0.5V to VDD + 0.5V
Exceeding the maximum ratings may impair the useful life of
the device. For user guidelines, not tested.
Storage Temperature ................................. –65°C to +150°C
Ambient Temperature with
Power Applied............................................. –55°C to +125°C
Current into Outputs (LOW) ........................................ 20 mA
Static Discharge Voltage.......................................... > 2001V
(per MIL-STD-883, Method 3015)
Latch-up Current ................................................... > 200 mA
Operating Range
Supply Voltage on VDD Relative to GND ....... –0.3V to +3.6V
Supply Voltage on VDDQ Relative to GND ...... –0.3V to +VDD
DC Voltage Applied to Outputs
in Tri-State........................................... –0.5V to VDDQ + 0.5V
Range
Ambient Temperature
Commercial
Industrial
VDD
VDDQ
2.5V ± 5% 2.5V – 5%
to VDD
0°C to +70°C
–40°C to +85°C
Electrical Characteristics
Over the Operating Range [16, 17]
Parameter
Description
Test Conditions
VDD
Power Supply Voltage
VDDQ
IO Supply Voltage
for 2.5V IO
VOH
Output HIGH Voltage
for 2.5V IO, IOH = –1.0 mA
VOL
Output LOW Voltage
for 2.5V IO, IOL = 1.0 mA
VIH
Input HIGH Voltage [16] for 2.5V IO
[16]
VIL
Input LOW Voltage
IX
Input Leakage Current
except ZZ and MODE
Min.
Max.
Unit
2.375
2.625
V
2.375
VDD
2.0
for 2.5V IO
GND ≤ VI ≤ VDDQ
0.4
V
1.7
VDD + 0.3V
V
–0.3
0.7
V
–5
5
µA
Input = VDD
Input Current of ZZ
µA
–30
Input Current of MODE Input = VSS
5
Input = VSS
V
V
Input = VDD
µA
µA
–5
30
µA
5
µA
IOZ
Output Leakage Current GND ≤ VI ≤ VDD, Output Disabled
IDD
VDD Operating Supply
Current
VDD = Max., IOUT = 0 mA,
f = fMAX = 1/tCYC
7.5-ns cycle, 133 MHz
210
mA
10-ns cycle, 100 MHz
175
mA
Automatic CE
Power Down
Current—TTL Inputs
Max. VDD, Device Deselected,
VIN ≥ VIH or VIN ≤ VIL, f = fMAX,
inputs switching
7.5-ns cycle, 133 MHz
140
mA
10-ns cycle, 100 MHz
120
ISB1
–5
ISB2
Automatic CE
Max. VDD, Device Deselected,
Power Down
VIN ≥ VDD – 0.3V or VIN ≤ 0.3V,
Current—CMOS Inputs f = 0, inputs static
All speeds
70
ISB3
Max. VDD, Device Deselected,
Automatic CE
Power Down
VIN ≥ VDDQ – 0.3V or VIN ≤ 0.3V,
Current—CMOS Inputs f = fMAX, inputs switching
7.5-ns cycle, 133 MHz
130
mA
10-ns cycle, 100 MHz
110
mA
All speeds
80
mA
ISB4
Automatic CE
Power Down
Current—TTL Inputs
Max. VDD, Device Deselected,
VIN ≥ VDD – 0.3V or VIN ≤ 0.3V,
f = 0, inputs static
mA
Notes
16. Overshoot: VIH(AC) < VDD +1.5V (Pulse width less than tCYC/2), undershoot: VIL(AC) > –2V (Pulse width less than tCYC/2).
17. Tpower up: assumes a linear ramp from 0V to VDD(min.) within 200 ms. During this time VIH < VDD and VDDQ < VDD.
Document #: 38-05547 Rev. *E
Page 17 of 28
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CY7C1381DV25, CY7C1381FV25
CY7C1383DV25, CY7C1383FV25
Capacitance [18]
Parameter
Description
Test Conditions
100 TQFP
Package
119 BGA
Package
165 FBGA
Package
Unit
Input Capacitance
TA = 25°C, f = 1 MHz,
Clock Input Capacitance VDD/VDDQ= 2.5V
5
8
9
pF
CCLK
5
8
9
pF
CIO
Input/Output Capacitance
5
8
9
pF
100 TQFP
Package
119 BGA
Package
165 FBGA
Package
Unit
28.66
23.8
20.7
°C/W
4.08
6.2
4.0
°C/W
CIN
Thermal Resistance [18]
Parameter
Description
ΘJA
Thermal Resistance
(Junction to Ambient)
ΘJC
Thermal Resistance
(Junction to Case)
Test Conditions
Test conditions follow
standard test methods and
procedures for measuring
thermal impedance, in
accordance with
EIA/JESD51.
AC Test Loads and Waveforms
2.5V IO Test Load
R = 1667Ω
2.5V
OUTPUT
OUTPUT
RL = 50Ω
Z0 = 50Ω
VT = 1.25V
(a)
ALL INPUT PULSES
VDDQ
GND
5 pF
INCLUDING
JIG AND
SCOPE
R = 1538Ω
(b)
10%
90%
10%
90%
≤ 1 ns
≤ 1 ns
(c)
Note
18. Tested initially and after any design or process change that may affect these parameters.
Document #: 38-05547 Rev. *E
Page 18 of 28
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CY7C1383DV25, CY7C1383FV25
Switching Characteristics
Over the Operating Range [19, 20]
Parameter
tPOWER
Description
VDD(Typical) to the first Access [21]
133 MHz
Min.
Max.
100 MHz
Min.
Max.
Unit
1
1
ms
Clock
tCYC
Clock Cycle Time
7.5
10
ns
tCH
Clock HIGH
2.1
2.5
ns
tCL
Clock LOW
2.1
2.5
ns
Output Times
tCDV
Data Output Valid After CLK Rise
tDOH
Data Output Hold After CLK Rise
[22, 23, 24]
tCLZ
Clock to Low-Z
tCHZ
Clock to High-Z [22, 23, 24]
tOEV
OE LOW to Output Valid
6.5
2.0
2.0
2.0
0
8.5
0
3.2
[22, 23, 24]
tOELZ
OE LOW to Output Low-Z
tOEHZ
OE HIGH to Output High-Z [22, 23, 24]
ns
2.0
4.0
0
ns
5.0
ns
3.8
ns
5.0
ns
0
4.0
ns
ns
Setup Times
tAS
Address Setup Before CLK Rise
1.5
1.5
ns
tADS
ADSP, ADSC Setup Before CLK Rise
1.5
1.5
ns
tADVS
ADV Setup Before CLK Rise
1.5
1.5
ns
tWES
GW, BWE, BW[A:D] Setup Before CLK Rise
1.5
1.5
ns
tDS
Data Input Setup Before CLK Rise
1.5
1.5
ns
tCES
Chip Enable Setup
1.5
1.5
ns
Hold Times
tAH
Address Hold After CLK Rise
0.5
0.5
ns
tADH
ADSP, ADSC Hold After CLK Rise
0.5
0.5
ns
tWEH
GW, BWE, BW[A:D] Hold After CLK Rise
0.5
0.5
ns
tADVH
ADV Hold After CLK Rise
0.5
0.5
ns
tDH
Data Input Hold After CLK Rise
0.5
0.5
ns
tCEH
Chip Enable Hold After CLK Rise
0.5
0.5
ns
Notes
19. Timing reference level is 1.25V.
20. Test conditions shown in (a) of AC Test Loads unless otherwise noted.
21. This part has a voltage regulator internally; tPOWER is the time that the power needs to be supplied above VDD(minimum) initially, before a read or write operation
can be initiated.
22. tCHZ, tCLZ,tOELZ, and tOEHZ are specified with AC test conditions shown in part (b) of AC Test Loads. Transition is measured ± 200 mV from steady-state voltage.
23. At any given voltage and temperature, tOEHZ is less than tOELZ and tCHZ is less than tCLZ to eliminate bus contention between SRAMs when sharing the same
data bus. These specifications do not imply a bus contention condition, but reflect parameters guaranteed over worst case user conditions. Device is designed
to achieve High-Z prior to Low-Z under the same system conditions.
24. This parameter is sampled and not 100% tested.
Document #: 38-05547 Rev. *E
Page 19 of 28
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CY7C1383DV25, CY7C1383FV25
Timing Diagrams
Read Cycle Timing [25]
tCYC
CLK
t
t ADS
CH
t CL
tADH
ADSP
t ADS
tADH
ADSC
t AS
tAH
A1
ADDRESS
A2
t
GW, BWE,BW
WES
t
WEH
X
t CES
Deselect Cycle
t CEH
CE
t
ADVS
t
ADVH
ADV
ADV suspends burst
OE
t OEV
t OEHZ
t CLZ
Data Out (Q)
High-Z
Q(A1)
t CDV
t OELZ
t CHZ
t DOH
Q(A2)
Q(A2 + 1)
Q(A2 + 2)
t CDV
Q(A2 + 3)
Q(A2)
Q(A2 + 1)
Q(A2 + 2)
Burst wraps around
to its initial state
Single READ
BURST
READ
DON’T CARE
UNDEFINED
Note
25. On this diagram, when CE is LOW: CE1 is LOW, CE2 is HIGH and CE3 is LOW. When CE is HIGH: CE1 is HIGH or CE2 is LOW or CE3 is HIGH.
Document #: 38-05547 Rev. *E
Page 20 of 28
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CY7C1383DV25, CY7C1383FV25
Timing Diagrams (continued)
Write Cycle Timing [25, 26]
t CYC
CLK
t
t ADS
CH
t
CL
tADH
ADSP
t ADS
ADSC extends burst
tADH
t ADS
tADH
ADSC
t AS
tAH
A1
ADDRESS
A2
A3
Byte write signals are ignored for first cycle when
ADSP initiates burst
t WES tWEH
BWE,
BW X
t
WES
t
WEH
GW
t CES
tCEH
CE
t ADVS tADVH
ADV
ADV suspends burst
OE
t
Data in (D)
High-Z
t
DS
t
DH
D(A1)
D(A2)
D(A2 + 1)
D(A2 + 1)
D(A2 + 2)
D(A2 + 3)
D(A3)
D(A3 + 1)
D(A3 + 2)
OEHZ
Data Out (Q)
BURST READ
Single WRITE
BURST WRITE
DON’T CARE
Extended BURST WRITE
UNDEFINED
Note
26. Full width write can be initiated by either GW LOW, or by GW HIGH, BWE LOW and BWX LOW.
Document #: 38-05547 Rev. *E
Page 21 of 28
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CY7C1383DV25, CY7C1383FV25
Timing Diagrams (continued)
Read/Write Cycle Timing [25, 27, 28]
tCYC
CLK
t
t ADS
CH
t
CL
tADH
ADSP
ADSC
t AS
A1
ADDRESS
tAH
A2
A3
A4
t
BWE, BW
WES
t
A5
A6
D(A5)
D(A6)
WEH
X
t CES
tCEH
CE
ADV
OE
t DS
Data In (D)
Data Out (Q)
High-Z
t
OEHZ
Q(A1)
tDH
t OELZ
D(A3)
tCDV
Q(A4)
Q(A2)
Back-to-Back READs
Single WRITE
Q(A4+1)
Q(A4+2)
BURST READ
DON’T CARE
Q(A4+3)
Back-to-Back
WRITEs
UNDEFINED
Notes
27. The data bus (Q) remains in high-Z following a write cycle, unless a new read access is initiated by ADSP or ADSC.
28. GW is HIGH.
Document #: 38-05547 Rev. *E
Page 22 of 28
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CY7C1383DV25, CY7C1383FV25
Timing Diagrams (continued)
ZZ Mode Timing [29, 30]
CLK
t ZZ
ZZ
I
t ZZREC
t ZZI
SUPPLY
I
t RZZI
DDZZ
ALL INPUTS
(except ZZ)
Outputs (Q)
DESELECT or READ Only
High-Z
DON’T CARE
Notes
29. Device must be deselected when entering ZZ sleep mode. See Cycle Descriptions table for all possible signal conditions to deselect the device.
30. DQs are in high-Z when exiting ZZ sleep mode.
Document #: 38-05547 Rev. *E
Page 23 of 28
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CY7C1383DV25, CY7C1383FV25
Ordering Information
Not all of the speed, package, and temperature ranges are available. Please contact your local sales representative or visit
www.cypress.com for actual products offered.
Speed
(MHz)
133
Ordering Code
CY7C1381DV25-133AXC
Package
Diagram
Part and Package Type
51-85050 100-Pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Pb-Free
Operating
Range
Commercial
CY7C1383DV25-133AXC
CY7C1381FV25-133BGC
51-85115 119-ball Ball Grid Array (14 x 22 x 2.4 mm)
CY7C1383FV25-133BGC
CY7C1381FV25-133BGXC 51-85115 119-ball Ball Grid Array (14 x 22 x 2.4 mm) Pb-Free
CY7C1383FV25-133BGXC
CY7C1381DV25-133BZC
51-85180 165-ball Fine-Pitch Ball Grid Array (13 x 15 x 1.4 mm)
CY7C1383DV25-133BZC
CY7C1381DV25-133BZXC 51-85180 165-ball Fine-Pitch Ball Grid Array (13 x 15 x 1.4 mm) Pb-Free
CY7C1383DV25-133BZXC
CY7C1381DV25-133AXI
51-85050 100-Pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Pb-Free
lndustrial
CY7C1383DV25-133AXI
CY7C1381FV25-133BGI
51-85115 119-ball Ball Grid Array (14 x 22 x 2.4 mm)
CY7C1383FV25-133BGI
CY7C1381FV25-133BGXI
51-85115 119-ball Ball Grid Array (14 x 22 x 2.4 mm) Pb-Free
CY7C1383FV25-133BGXI
CY7C1381DV25-133BZI
51-85180 165-ball Fine-Pitch Ball Grid Array (13 x 15 x 1.4 mm)
CY7C1383DV25-133BZI
CY7C1381DV25-133BZXI
51-85180 165-ball Fine-Pitch Ball Grid Array (13 x 15 x 1.4 mm) Pb-Free
CY7C1383DV25-133BZXI
100
CY7C1381DV25-100AXC
51-85050 100-Pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Pb-Free
Commercial
CY7C1383DV25-100AXC
CY7C1381FV25-100BGC
51-85115 119-ball Ball Grid Array (14 x 22 x 2.4 mm)
CY7C1383FV25-100BGC
CY7C1381FV25-100BGXC 51-85115 119-ball Ball Grid Array (14 x 22 x 2.4 mm) Pb-Free
CY7C1383FV25-100BGXC
CY7C1381DV25-100BZC
51-85180 165-ball Fine-Pitch Ball Grid Array (13 x 15 x 1.4 mm)
CY7C1383DV25-100BZC
CY7C1381DV25-100BZXC 51-85180 165-ball Fine-Pitch Ball Grid Array (13 x 15 x 1.4 mm) Pb-Free
CY7C1383DV25-100BZXC
CY7C1381DV25-100AXI
51-85050 100-Pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Pb-Free
lndustrial
CY7C1383DV25-100AXI
CY7C1381FV25-100BGI
51-85115 119-ball Ball Grid Array (14 x 22 x 2.4 mm)
CY7C1383FV25-100BGI
CY7C1381FV25-100BGXI
51-85115 119-ball Ball Grid Array (14 x 22 x 2.4 mm) Pb-Free
CY7C1383FV25-100BGXI
CY7C1381DV25-100BZI
51-85180 165-ball Fine-Pitch Ball Grid Array (13 x 15 x 1.4 mm)
CY7C1383DV25-100BZI
CY7C1381DV25-100BZXI
51-85180 165-ball Fine-Pitch Ball Grid Array (13 x 15 x 1.4 mm) Pb-Free
CY7C1383DV25-100BZXI
Document #: 38-05547 Rev. *E
Page 24 of 28
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Package Diagrams
Figure 1. 100-Pin Thin Plastic Quad Flat pack (14 x 20 x 1.4 mm) (51-85050)
16.00±0.20
1.40±0.05
14.00±0.10
100
81
80
1
20.00±0.10
22.00±0.20
0.30±0.08
0.65
TYP.
30
12°±1°
(8X)
SEE DETAIL
A
51
31
50
0.20 MAX.
0.10
1.60 MAX.
R 0.08 MIN.
0.20 MAX.
0° MIN.
SEATING PLANE
STAND-OFF
0.05 MIN.
0.15 MAX.
0.25
NOTE:
1. JEDEC STD REF MS-026
GAUGE PLANE
0°-7°
R 0.08 MIN.
0.20 MAX.
2. BODY LENGTH DIMENSION DOES NOT INCLUDE MOLD PROTRUSION/END FLASH
MOLD PROTRUSION/END FLASH SHALL NOT EXCEED 0.0098 in (0.25 mm) PER SIDE
BODY LENGTH DIMENSIONS ARE MAX PLASTIC BODY SIZE INCLUDING MOLD MISMATCH
3. DIMENSIONS IN MILLIMETERS
0.60±0.15
0.20 MIN.
51-85050-*B
1.00 REF.
DETAIL
Document #: 38-05547 Rev. *E
A
Page 25 of 28
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CY7C1383DV25, CY7C1383FV25
Package Diagrams (continued)
Figure 2. 119-Ball BGA (14 x 22 x 2.4 mm) (51-85115)
51-85115-*B
Document #: 38-05547 Rev. *E
Page 26 of 28
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CY7C1383DV25, CY7C1383FV25
Package Diagrams (continued)
Figure 3. 165-Ball FBGA (13 x 15 x 1.4 mm) (51-85180)
165 FBGA 13 x 15 x 1.40 MM BB165D/BW165D
BOTTOM VIEW
PIN 1 CORNER
BOTTOM VIEW
TOP VIEW
PIN 1 CORNER
TOP VIEW
Ø0.05 M C
Ø0.25 MØ0.05
CAB MC
PIN 1 CORNER
Ø0.25 M C A B
Ø0.50 -0.06
(165X)
PIN 1 CORNER
1
2
1
+0.14
4
2
5
3
6
4
7
5
8
6
9
7
10
11
8
9
11
10
11
10
9
11
8
10
7
9
6
8
5
7
Ø0.50 -0.06 (165X)
4
6
3 +0.14
2
5
4
1
3
2
1A
B
A
C
B
C
B
D
C
D
C
E
D
F
1.00
A
1.00
B
F
E
G
F
G
F
H
G
H
G
J
H
K
J
L
K
M
L
N
M
P
N
P
N
R
P
R
P
7.00
7.00
14.00
D
E
14.00
15.00±0.10
E
15.00±0.10
15.00±0.10
A
15.00±0.10
3
J
H
K
J
L
K
M
L
N
M
R
R
A
A
A
1.00
5.00
A
1.00
5.00
10.00
10.00
B
B
13.00±0.10
B
13.00±0.10
B
13.00±0.10
13.00±0.10
SEATING PLANE
NOTES :
NOTES
:
SOLDER
PAD TYPE
: NON-SOLDER MASK DEFINED (NSMD)
PACKAGE
WEIGHT
SOLDER
PAD: 0.475g
TYPE : NON-SOLDER MASK DEFINED (NSMD)
JEDEC REFERENCE
: MO-216
/ DESIGN 4.6C
PACKAGE WEIGHT
: 0.475g
PACKAGE
CODE
: BB0AC : MO-216 / DESIGN 4.6C
JEDEC
REFERENCE
PACKAGE CODE : BB0AC
51-85180-*A
0.35±0.06
C
0.35±0.06
0.36
0.36
SEATING PLANE
C
0.15 C
1.40 MAX.
1.40 MAX.
0.15(4X)
0.15 C
0.53±0.05
0.53±0.05
0.25
C
0.25 C
0.15(4X)
51-85180-*A
Intel and Pentium are registered trademarks, and i486 is a trademark of Intel Corporation. All product and company names
mentioned in this document are the trademarks of their respective holders.
Document #: 38-05547 Rev. *E
Page 27 of 28
© Cypress Semiconductor Corporation, 2006-2007. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for
the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended
to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
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CY7C1381DV25, CY7C1381FV25
CY7C1383DV25, CY7C1383FV25
Document History Page
Document Title: CY7C1381DV25/CY7C1383DV25/CY7C1381FV25/CY7C1383FV25, 18-Mbit (512K x 36/1M x 18)
Flow-Through SRAM
Document Number: 38-05547
REV.
ECN NO.
Issue Date
Orig. of
Change
Description of Change
**
254518
See ECN
RKF
New data sheet
*A
288531
See ECN
SYT
Edited description under “IEEE 1149.1 Serial Boundary Scan (JTAG)” for
non-compliance with 1149.1
Removed 117Mhz Speed Bin
Added Pb-free information for 100-Pin TQFP, 119 BGA and 165 FBGA
Packages
Added comment of ‘Pb-free BG packages availability’ below the Ordering
Information
*B
326078
See ECN
PCI
Address expansion pins/balls in the pinouts for all packages are modified as
per JEDEC standard
Added description on EXTEST Output Bus Tri-State
Changed description on the Tap Instruction Set Overview and Extest
Changed Device Width (23:18) for 119-BGA from 000001 to 101001
Added separate row for 165 -FBGA Device Width (23:18)
Changed ΘJA and ΘJC for TQFP Package from 31 and 6 °C/W to 28.66 and
4.08 °C/W respectively
Changed ΘJA and ΘJc or BGA Package from 45 and 7 °C/W to 23.8 and 6.2
°C/W respectively
Changed ΘJA and ΘJc for FBGA Package from 46 and 3 °C/W to 20.7 and
4.0 °C/W respectively
Modified VOL, VOH test conditions
Removed comment of ‘Pb-free BG packages availability’ below the Ordering
Information
Updated Ordering Information Table
*C
416321
See ECN
NXR
Changed address of Cypress Semiconductor Corporation on Page# 1 from
“3901 North First Street” to “198 Champion Court”
Changed the description of IX from Input Load Current to Input Leakage
Current on page# 17
Changed the IX current values of MODE on page # 18 from –5 µA and 30 µA
to –30 µA and 5 µA
Changed the IX current values of ZZ on page # 18 from –30 µA and 5 µA
to –5 µA and 30 µA
Changed VIH < VDD to VIH < VDDon page # 18
Replaced Package Name column with Package Diagram in the Ordering
Information table
*D
475009
See ECN
VKN
Converted from Preliminary to Final.
Added the Maximum Rating for Supply Voltage on VDDQ Relative to GND
Changed tTH, tTL from 25 ns to 20 ns and tTDOV from 5 ns to 10 ns in TAP
AC Switching Characteristics table.
Updated the Ordering Information table.
*E
793579
See ECN
VKN
Added Part numbers CY7C1381FV25 and CY7C1383FV25
Added footnote# 3 regarding Chip Enable
Updated Ordering Information table
Document #: 38-05547 Rev. *E
Page 28 of 28
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