ON Semiconductort MC74VHC540 Octal Bus Buffer Inverting The MC74VHC540 is an advanced high speed CMOS inverting octal bus buffer fabricated with silicon gate CMOS technology. It achieves high speed operation similar to equivalent Bipolar Schottky TTL while maintaining CMOS low power dissipation. The MC74VHC540 features inputs and outputs on opposite sides of the package and two AND--ed active-- low output enables. When either OE1 or OE2 are high, the terminal outputs are in the high impedance state. The internal circuit is composed of three stages, including a buffer output which provides high noise immunity and stable output. The inputs tolerate voltages up to 7V, allowing the interface of 5V systems to 3V systems. • High Speed: tPD = 3.7ns (Typ) at VCC = 5V • Low Power Dissipation: ICC = 4μA (Max) at TA = 25°C • High Noise Immunity: VNIH = VNIL = 28% VCC • Power Down Protection Provided on Inputs • Balanced Propagation Delays • Designed for 2V to 5.5V Operating Range • Low Noise: VOLP = 1.2V (Max) • Pin and Function Compatible with Other Standard Logic Families • Latchup Performance Exceeds 300mA • ESD Performance: HBM > 2000V; Machine Model > 200V • Chip Complexity: 124 FETs or 31 Equivalent Gates • DW SUFFIX 20--LEAD SOIC WIDE PACKAGE CASE 751D--05 DT SUFFIX 20--LEAD TSSOP PACKAGE CASE 948E--02 M SUFFIX 20--LEAD SOIC EIAJ PACKAGE CASE 967--01 ORDERING INFORMATION SOIC WIDE MC74VHCXXXDW TSSOP MC74VHCXXXDT SOIC EIAJ MC74VHCXXXM PIN ASSIGNMENT These devices are available in Pb--free package(s). Specifications herein apply to both standard and Pb--free devices. Please see our website at www.onsemi.com for specific Pb--free orderable part numbers, or contact your local ON Semiconductor sales office or representative. OE1 1 20 VCC A1 2 19 OE2 A2 3 18 Y1 A3 4 17 Y2 A4 5 16 Y3 A5 6 15 Y4 A6 7 14 Y5 A7 8 13 Y6 A8 9 12 Y7 10 11 Y8 GND FUNCTION TABLE Inputs © Semiconductor Components Industries, LLC, 2006 March, 2006 -- Rev. 3 1 OE1 OE2 A L L H X L L X H L H X X Output Y H L Z Z Publication Order Number: MC74VHC540/D LOGIC DIAGRAM A1 A2 A3 DATA INPUTS A4 A5 A6 A7 A8 OUTPUT ENABLES OE1 OE2 2 18 3 17 4 16 5 15 6 14 7 13 8 12 9 11 Y1 Y2 Y3 Y4 INVERTING OUTPUTS Y5 Y6 Y7 Y8 1 19 http://onsemi.com 2 MAXIMUM RATINGS* Symbol Value Unit VCC DC Supply Voltage Parameter – 0.5 to + 7.0 V Vin DC Input Voltage – 0.5 to + 7.0 V Vout DC Output Voltage – 0.5 to VCC + 0.5 V IIK Input Diode Current -- 20 mA IOK Output Diode Current ± 20 mA Iout DC Output Current, per Pin ± 25 mA ICC DC Supply Current, VCC and GND Pins ± 75 mA PD Power Dissipation in Still Air, 500 450 mW Tstg Storage Temperature – 65 to + 150 _C SOIC Packages† TSSOP Package† This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high--impedance circuit. For proper operation, Vin and Vout should be constrained to the range GND ≤ (Vin or Vout) ≤ VCC. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or V CC ). Unused outputs must be left open. * Absolute maximum continuous ratings are those values beyond which damage to the device may occur. Exposure to these conditions or conditions beyond those indicated may adversely affect device reliability. Functional operation under absolute--maximum--rated conditions is not implied. †Derating — SOIC Packages: – 7 mW/_C from 65_ to 125_C TSSOP Package: -- 6.1 mW/_C from 65_ to 125_C RECOMMENDED OPERATING CONDITIONS Symbol Parameter VCC DC Supply Voltage Vin DC Input Voltage Vout DC Output Voltage TA Operating Temperature, All Package Types tr, tf Input Rise and Fall Time (Figure 1) VCC = 3.3V ±0.3V VCC =5.0V ±0.5V Min Max Unit 2.0 5.5 V 0 5.5 V 0 VCC V -- 40 + 85 _C 0 0 100 20 ns/V DC ELECTRICAL CHARACTERISTICS VCC V Symbol Parameter Test Conditions VIH Minimum High--Level Input Voltage 2.0 3.0 to 5.5 VIL Maximum Low--Level Input Voltage 2.0 3.0 to 5.5 VOH Minimum High--Level Output Voltage Vin = VIH or VIL IOH = -- 50μA Vin = VIH or VIL IOH = -- 4mA IOH = -- 8mA VOL Maximum Low--Level Output Voltage Vin = VIH or VIL IOL = 50μA TA = 25°C Min Min 1.9 2.9 4.4 3.0 4.5 2.58 3.94 3.0 4.5 http://onsemi.com Max 1.50 VCC x 0.7 0.50 VCC x 0.3 2.0 3.0 4.5 3 Max 1.50 VCC x 0.7 2.0 3.0 4.5 Vin = VIH or VIL IOL = 4mA IOL = 8mA Typ TA = -- 40 to 85°C 2.0 3.0 4.5 Unit V 0.50 VCC x 0.3 V V 1.9 2.9 4.4 2.48 3.80 0.0 0.0 0.0 0.1 0.1 0.1 0.1 0.1 0.1 0.36 0.36 0.44 0.44 V DC ELECTRICAL CHARACTERISTICS VCC V TA = 25°C Max Unit Iin Maximum Input Leakage Current Vin = 5.5V or GND 0 to 5.5 ± 0.1 ± 1.0 μA IOZ Maximum Three--State Leakage Current Vin = VIL or VIH Vout = VCC or GND 5.5 ± 0.25 ± 2.5 μA ICC Maximum Quiescent Supply Current Vin = VCC or GND 5.5 4.0 40.0 μA Symbol Parameter Test Conditions Min Typ TA = -- 40 to 85°C Max Min AC ELECTRICAL CHARACTERISTICS (Input tr = tf = 3.0ns) TA = 25°C Typ Max Min Max Unit CL = 15pF CL = 50pF 4.8 7.3 7.0 10.5 1.0 1.0 8.5 12.0 ns VCC = 5.0 ± 0.5V CL = 15pF CL = 50pF 3.7 5.2 5.0 7.0 1.0 1.0 6.0 8.0 Output Enable TIme, OEn to Y (Figures 2 and 4) VCC = 3.3 ± 0.3V RL = 1kΩ CL = 15pF CL = 50pF 6.8 9.3 10.5 14.0 1.0 1.0 12.5 16.0 VCC = 5.0 ± 0.5V RL = 1kΩ CL = 15pF CL = 50pF 4.7 6.2 7.2 9.2 1.0 1.0 8.5 10.5 Output Disable Time, OEn to Y (Figures 2 and 4) VCC = 3.3 ± 0.3V RL = 1kΩ CL = 50pF 11.2 15.4 1.0 17.5 VCC = 5.0 ± 0.5V RL = 1kΩ CL = 50pF 6.0 8.8 1.0 10.0 Output to Output Skew VCC = 3.3 ± 0.3V (Note 1) CL = 50pF 1.5 ns VCC = 5.0 ± 0.5V (Note 1) CL = 50pF 1.0 ns Symbol Parameter tPLH, tPHL Maximum Propagation Delay, A to Y (Figures 1 and 3) VCC = 3.3 ± 0.3V tPZL, tPZH tPLZ, tPHZ tOSLH, tOSHL Test Conditions Min TA = -- 40 to 85°C Cin Maximum Input Capacitance 4 Cout Maximum Three--State Output Capacitance (Output in High Impedance State) 6 10 10 ns ns pF pF Typical @ 25°C, VCC = 5.0V 17 CPD Power Dissipation Capacitance (Note 2) pF 1. Parameter guaranteed by design. tOSLH = |tPLHm -- tPLHn|, tOSHL = |tPHLm -- tPHLn|. 2. CPD is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load. Average operating current can be obtained by the equation: ICC(OPR) = CPD ¯ VCC ¯ fin + ICC/8 (per bit). CPD is used to determine the no--load dynamic power consumption; PD = CPD ¯ VCC2 ¯ fin + ICC ¯ VCC. NOISE CHARACTERISTICS (Input tr = tf = 3.0ns, CL = 50pF, VCC = 5.0V) TA = 25°C Parameter Symbol Typ Max Unit VOLP Quiet Output Maximum Dynamic VOL 0.9 1.2 V VOLV Quiet Output Minimum Dynamic VOL -- 0.9 -- 1.2 V VIHD Minimum High Level Dynamic Input Voltage 3.5 V VILD Maximum Low Level Dynamic Input Voltage 1.5 V http://onsemi.com 4 SWITCHING WAVEFORMS VCC VCC A OE1 or OE2 50% 50% 50% tPZL tPLH tPHL GND tPLZ HIGH IMPEDANCE GND 50% VCC Y VOL +0.3V Y tPZH 50% VCC tPHZ 50% VCC Y Figure 1. VOH --0.3V HIGH IMPEDANCE Figure 2. TEST CIRCUITS TEST POINT TEST POINT OUTPUT DEVICE UNDER TEST OUTPUT DEVICE UNDER TEST CL* *Includes all probe and jig capacitance 1kΩ CL* CONNECT TO VCC WHEN TESTING tPLZ AND tPZL. CONNECT TO GND WHEN TESTING tPHZ AND tPZH. *Includes all probe and jig capacitance Figure 3. Figure 4. INPUT EQUIVALENT CIRCUIT INPUT http://onsemi.com 5 OUTLINE DIMENSIONS DW SUFFIX SOIC CASE 751D--05 ISSUE F A 20 θ X 45 _ E h 1 10 20X B B 0.25 M T A S B S A L H M 10X 0.25 NOTES: 1. DIMENSIONS ARE IN MILLIMETERS. 2. INTERPRET DIMENSIONS AND TOLERANCES PER ASME Y14.5M, 1994. 3. DIMENSIONS D AND E DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 PER SIDE. 5. DIMENSION B DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE PROTRUSION SHALL BE 0.13 TOTAL IN EXCESS OF B DIMENSION AT MAXIMUM MATERIAL CONDITION. 11 B M D 18X e A1 SEATING PLANE C T http://onsemi.com 6 DIM A A1 B C D E e H h L θ MILLIMETERS MIN MAX 2.35 2.65 0.10 0.25 0.35 0.49 0.23 0.32 12.65 12.95 7.40 7.60 1.27 BSC 10.05 10.55 0.25 0.75 0.50 0.90 0_ 7_ OUTLINE DIMENSIONS DT SUFFIX TSSOP CASE 948E--02 ISSUE A 20X 0.15 (0.006) T U 2X L K REF 0.10 (0.004) S L/2 20 M T U S V S K K1 11 J J1 B --U-- PIN 1 IDENT SECTION N--N 1 10 0.25 (0.010) N 0.15 (0.006) T U S M A --V-- NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH OR GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25 (0.010) PER SIDE. 5. DIMENSION K DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE K DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 7. DIMENSION A AND B ARE TO BE DETERMINED AT DATUM PLANE --W--. N F DETAIL E --W-- C D G H DETAIL E 0.100 (0.004) --T-- SEATING PLANE http://onsemi.com 7 DIM A B C D F G H J J1 K K1 L M MILLIMETERS MIN MAX 6.40 6.60 4.30 4.50 -----1.20 0.05 0.15 0.50 0.75 0.65 BSC 0.27 0.37 0.09 0.20 0.09 0.16 0.19 0.30 0.19 0.25 6.40 BSC 0_ 8_ INCHES MIN MAX 0.252 0.260 0.169 0.177 -----0.047 0.002 0.006 0.020 0.030 0.026 BSC 0.011 0.015 0.004 0.008 0.004 0.006 0.007 0.012 0.007 0.010 0.252 BSC 0_ 8_ OUTLINE DIMENSIONS M SUFFIX SOIC EIAJ CASE 967--01 ISSUE O 20 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS D AND E DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS AND ARE MEASURED AT THE PARTING LINE. MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 5. THE LEAD WIDTH DIMENSION (b) DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE LEAD WIDTH DIMENSION AT MAXIMUM MATERIAL CONDITION. DAMBAR CANNOT BE LOCATED ON THE LOWER RADIUS OR THE FOOT. MINIMUM SPACE BETWEEN PROTRUSIONS AND ADJACENT LEAD TO BE 0.46 ( 0.018). LE 11 Q1 E HE 1 M_ L 10 DETAIL P Z D e VIEW P A A1 b 0.13 (0.005) c M 0.10 (0.004) DIM A A1 b c D E e HE L LE M Q1 Z MILLIMETERS MIN MAX -----2.05 0.05 0.20 0.35 0.50 0.18 0.27 12.35 12.80 5.10 5.45 1.27 BSC 7.40 8.20 0.50 0.85 1.10 1.50 10 _ 0_ 0.70 0.90 -----0.81 INCHES MIN MAX -----0.081 0.002 0.008 0.014 0.020 0.007 0.011 0.486 0.504 0.201 0.215 0.050 BSC 0.291 0.323 0.020 0.033 0.043 0.059 10 _ 0_ 0.028 0.035 -----0.032 ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. 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