IDT IDT709279L15G High-speed 32/16k x 16 synchronous dual-port static ram Datasheet

HIGH-SPEED 32/16K x 16
SYNCHRONOUS
DUAL-PORT STATIC RAM
Features
◆
◆
◆
◆
◆
True Dual-Ported memory cells which allow simultaneous
access of the same memory location
High-speed clock to data access
– Commercial: 6.5/7.5/9/12/15ns (max.)
– Industrial: 12ns (max.)
Low-power operation
– IDT709279/69S
Active: 950mW (typ.)
Standby: 5mW (typ.)
– IDT709279/69L
Active: 950mW (typ.)
Standby: 1mW (typ.)
Flow-Through or Pipelined output mode on either port via
the FT/PIPE pin
Counter enable and reset features
◆
◆
◆
◆
◆
◆
IDT709279/69S/L
Dual chip enables allow for depth expansion without
additional logic
Full synchronous operation on both ports
– 4ns setup to clock and 1ns hold on all control, data, and
address inputs
– Data input, address, and control registers
– Fast 6.5ns clock to data out in the Pipelined output mode
– Self-timed write allows fast cycle time
– 10ns cycle time, 100MHz operation in Pipelined output mode
Separate upper-byte and lower-byte controls for
multiplexed bus and bus matching compatibility
TTL- compatible, single 5V (±10%) power supply
Industrial temperature range (–40°C to +85°C) is
available for selected speeds
Available in a 100-pin Thin Quad Flatpack (TQFP) package
Functional Block Diagram
R/WR
UBR
R/WL
UBL
CE0L
CE1L
1
0
0/1
CE0R
CE1R
1
0
0/1
LBR
OER
LBL
OEL
FT/PIPEL
0/1
1b 0b b a 1a 0a
I/O8LI/O15L
0a 1a
a b 0b 1b
0/1
FT/PIPER
I/O8R-I/O15R
I/O
Control
,
,
I/O
Control
I/O0L-I/O7L
I/O0R-I/O7R
A14R(1)
A14L(1)
A0L
CLKL
ADSL
CNTENL
CNTRSTL
Counter/
Address
Reg.
MEMORY
ARRAY
Counter/
Address
Reg.
A0R
CLKR
ADSR
CNTENR
CNTRSTR
3243 drw 01
NOTE:
1. A14 X is a NC for IDT709269.
JUNE 2004
1
©2004 Integrated Device Technology, Inc.
DSC-3243/13
IDT709279/69S/L
High-Speed 32/16K x 16 Synchronous Dual-Port Static RAM
Description
Preliminary
Industrial and Commercial Temperature Ranges
The IDT709279/69 is a high-speed 32/16K x 16 bit synchronous
Dual-Port RAM. The memory array utilizes Dual-Port memory cells to
allow simultaneous access of any address from both ports. Registers on
control, data, and address inputs provide minimal setup and hold times.
The timing latitude provided by this approach allows systems to be
designed with very short cycle times.
With an input data register, the IDT709279/69 has been optimized for
applications having unidirectional or bidirectional data flow in bursts. An
automatic power down feature, controlled by CE0 and CE1, permits the
on-chip circuitry of each port to enter a very low standby power mode.
Fabricated using IDT’s CMOS high-performance technology, these
devices typically operate on only 950mW of power.
A8L
A7L
A6L
A5L
A4L
A 3L
A2L
A1L
A0L
CNTENL
CLK L
ADSL
GND
ADSR
CLKR
CNTENR
A0R
A1R
A 2R
A3R
A4R
A 5R
A6R
A7R
A8R
Pin Configurations(2,3,4)
01/15/04
Index
A9L
A10L
A 11L
A12L
A13L
4
72
5
71
6
70
7
69
8
68
9
67
10
IDT709279/69PF
PN100-1(5)
11
12
13
100-Pin TQFP
Top View(6)
14
66
65
64
63
62
15
61
16
60
17
59
18
58
19
57
20
56
21
55
22
54
23
53
24
52
51
25
26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
A9R
A10R
A11R
A12R
A13R
A14R(1)
NC
NC
NC
LBR
UB R
CE0R
CE 1R
,
CNTRSTR
GND
R/WR
OER
FT/PIPER
GND
I/O15R
I/O14R
I/O13R
I/O12R
I/O11R
I/O10R
I/O9L
I/O8L
VCC
I/O7 L
I/O6L
I/O5L
I/O4L
I/O3L
I/O2L
GND
I/OIL
I/O0L
GND
I/O0R
I/O1R
I/O2R
I/O3R
I/O4R
I/O5R
I/O6R
VCC
I/O7R
I/O8R
I/O9R
NC
A14L(1)
NC
NC
NC
LBL
UBL
CE0L
CE1L
CNTRSTL
VCC
R/WL
OE L
FT/PIPEL
GND
I/O15L
I/O14L
I/O13L
I/O12L
I/O11L
I/O10L
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76
1
75
2
74
3
73
3243 drw 02
NOTES:
1. A14X is a NC for IDT709269.
2. All VCC pins must be connected to power supply.
3. All GND pins must be connected to ground supply.
4. Package body is approximately 14mm x 14mm x 1.4mm
5. This package code is used to reference the package diagram.
6. This text does not indicate orientation of the actual part-marking.
2
6.42
IDT709279/69S/L
High-Speed 32/16K x 16 Synchronous Dual-Port Static RAM
Preliminary
Industrial and Commercial Temperature Ranges
Pin Names
Left Port
Right Port
Names
CE0L, CE1L
CE0R, CE1R
Chip Enables (3)
R/WL
R/WR
Read/Write Enable
OEL
OER
Output Enable
A0L - A14L(1)
A0R - A14R(1)
Address
I/O0L - I/O15L
I/O0R - I/O15R
Data Input/Output
CLKL
CLKR
Clock
UBL
UBR
Upper Byte Select(2)
LBL
LBR
Lower Byte Select(2)
ADSL
ADSR
Address Strobe
CNTENL
CNTENR
Counter Enable
CNTRSTL
CNTRSTR
Counter Reset
FT/PIPEL
FT/PIPER
Flow-Through/Pipeline
VSS
Power
GND
Ground
NOTES:
1. A14x is a NC for IDT709269.
2. LB and UB are single buffered regardless of state of FT/PIPE.
3. CEo and CE1 are single buffered when FT/PIPE = VIL,
CEo and CE 1 are double buffered when FT/PIPE = VIH,
i.e. the signals take two cycles to deselect.
3243 tbl 01
Truth Table I—Read/Write and Enable Control(1,2,3)
OE
CLK
CE0
CE1
UB
LB
R/W
Upper Byte
I/O8-15
Lower Byte
I/O0-7
X
↑
H
X
X
X
X
High-Z
High-Z
Deselected—Power Down
X
↑
X
L
X
X
X
High-Z
High-Z
Deselected—Power Down
X
↑
L
H
H
H
X
High-Z
High-Z
Both Bytes Deselected
X
↑
L
H
L
H
L
DIN
High-Z
Write to Upper Byte Only
X
↑
L
H
H
L
L
High-Z
DIN
Write to Lower Byte Only
X
↑
L
H
L
L
L
DIN
DIN
Write to Both Bytes
L
↑
L
H
L
H
H
DOUT
High-Z
Read Upper Byte Only
L
↑
L
H
H
L
H
High-Z
DOUT
Read Lower Byte Only
L
↑
L
H
L
L
H
DOUT
DOUT
Read Both Bytes
H
X
L
H
L
L
X
High-Z
High-Z
Outputs Disabled
Mode
3243 tbl 02
NOTES:
1. "H" = VIH, "L" = VIL, "X" = Don't Care.
2. ADS, CNTEN, CNTRST = X.
3. OE is an asynchronous input signal.
6.42
3
IDT709279/69S/L
High-Speed 32/16K x 16 Synchronous Dual-Port Static RAM
Preliminary
Industrial and Commercial Temperature Ranges
Truth Table II—Address Counter Control(1,2)
External
Address
Previous
Internal
Address
Internal
Address
Used
CLK
An
X
An
↑
↑
ADS
MODE
CNTEN
CNTRST
I/O(3)
X
H
DI/O (n)
H
DI/O(n+1)
Counter Enabled—Internal Address generation
External Address Blocked—Counter disabled (An + 1 reused)
L(4)
H
L
(5)
X
An
An + 1
X
An + 1
An + 1
↑
H
H
H
DI/O(n+1)
X
X
A0
↑
X
X
L(4)
DI/O(0)
External Address Used
Counter Reset to Address 0
3243 tbl 03
NOTES:
1. "H" = VIH, "L" = VIL, "X" = Don't Care.
2. CE0, LB, UB, and OE = VIL; CE 1 and R/W = VIH.
3. Outputs configured in Flow-Through Output mode: if outputs are in Pipelined mode the data out will be delayed by one cycle.
4. ADS is independent of all other signals including CE0, CE1, UB and LB.
5. The address counter advances if CNTEN = VIL on the rising edge of CLK, regardless of all other signals including CE0, CE1, UB and LB.
Recommended DC Operating
Recommended Operating
(1)
Conditions
Temperature and Supply Voltage
Grade
Commercial
Industrial
Symbol
Ambient
Temperature
GND
VCC
0OC to +70OC
0V
5.0V + 10%
-40OC to +85OC
0V
5.0V + 10%
NOTES:
1. This is the parameter TA. This is the "instant on" case temperature.
3243 tbl 04
Parameter
VCC
Supply Voltage
GND
Ground
VIH
Input High Voltage
Typ.
Max.
Unit
4.5
5.0
5.5
V
0
0
0
V
2.2
____
(2)
Input Low Voltage
VIL
Min.
-0.5
____
(1)
6.0
0.8
Capacitance(1)
Absolute Maximum Ratings(1)
Commercial
& Industrial
Unit
Terminal Voltage
with Respect
to GND
-0.5 to +7.0
V
TBIAS
TemperatureUnder Bias
-55 to +125
o
C
TSTG
Storage Temperature
-65 to +150
o
C
TJN
Junction Temperature
+150
o
C
IOUT
DC Output Current
V TERM
(2)
Rating
(TA = +25°C, f = 1.0MHz)
Symbol
CIN
Parameter
Input Capacitance
(2)
COUT
50
V
3243 tbl 05
NOTES:
1. VTERM must not exceed VCC + 10%.
2. VIL > -1.5V for pulse width less than 10ns.
Symbol
V
Output Capacitance
Conditions(2)
Max.
Unit
VIN = 0V
9
pF
V OUT = 0V
10
pF
3243 tbl 07
NOTES:
1. These parameters are determined by device characterization, but are not
production tested.
2. COUT also references CI/O.
mA
3243 tbl 06
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may
cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any other conditions above those
indicated in the operational sections of this specification is not implied. Exposure
to absolute maximum rating conditions for extended periods may affect
reliability.
2. VTERM must not exceed VCC + 10% for more than 25% of the cycle time or 10ns
maximum, and is limited to < 20mA for the period of VTERM > VCC + 10%.
3. Ambient Temperature Under Bias. No AC Conditions. Chip Deselect.
4
6.42
IDT709279/69S/L
High-Speed 32/16K x 16 Synchronous Dual-Port Static RAM
Preliminary
Industrial and Commercial Temperature Ranges
DC Electrical Characteristics Over the Operating
Temperature Supply Voltage Range (VCC = 5.0V ± 10%)
709279/69S/L
Symbol
Parameter
Test Conditions
(1)
Min.
Max.
Unit
|ILI|
Input Leakage Current
VCC = 5.5V, VIN = 0V to VCC
___
10
µA
|ILO|
Output Leakage Current
CE0 = VIH or CE1 = VIL, VOUT = 0V to VCC
___
10
µA
VOL
Output Low Voltage
IOL = +4mA
___
0.4
V
VOH
Output High Voltage
IOH = -4mA
2.4
___
V
3243 tbl 08
NOTE:
1. At VCC < 2.0V input leakages are undefined.
DC Electrical Characteristics Over the Operating
Temperature and Supply Voltage Range(6) (VCC = 5V ± 10%)
709279/69X6
Com'l Only
Symbol
ICC
ISB1
ISB2
ISB3
ISB4
Parameter
Dynamic Operating
Current
(Both Ports Active)
Standby Current
(Both Ports - TTL
Level Inputs)
Standby Current
(One Port - TTL
Level Inputs)
Full Standby Current
(Both Ports CMOS Level Inputs)
Full Standby Current
(One Port CMOS Level Inputs)
Test Condition
Version
709279/69X7
Com'l Only
709279/69X9
Com'l Only
Typ.(4)
Max.
Typ. (4)
Max.
Typ. (4)
Max.
Unit
mA
COM'L
S
L
270
270
585
525
250
250
490
440
210
210
390
350
IND
S
L
____
____
____
____
____
____
____
____
____
____
____
____
COM'L
S
L
80
80
205
175
65
65
170
145
50
50
135
115
IND
S
L
____
____
____
____
____
____
____
____
____
____
____
____
CE"A" = VIL and
CE"B" = VIH(3)
Active Port Outputs
Disabled, f=fMAX(1)
COM'L
S
L
180
180
405
360
160
160
340
295
140
140
270
240
IND
S
L
____
____
____
____
____
____
____
____
____
____
____
____
Both Ports CER and
CEL > VCC - 0.2V
VIN > VCC - 0.2V or
VIN < 0.2V, f = 0(2)
COM'L
S
L
1.0
0.2
15
5
1.0
0.2
15
5
1.0
0.2
15
5
IND
S
L
____
____
____
____
____
____
____
____
____
____
____
____
CE"A" < 0.2V and
CE"B" > V CC - 0.2V(5)
VIN > VCC - 0.2V or
VIN < 0.2V, Active Port Outputs
Disabled, f = fMAX(1)
COM'L
S
L
170
170
395
340
150
150
330
290
130
130
245
225
IND
S
L
____
____
____
____
____
____
____
____
____
____
____
____
CEL and CER= VIL
Outputs Disabled
f = fMAX(1)
CEL = CER = VIH
f = fMAX(1)
mA
mA
mA
mA
3243 tbl 09
NOTES:
1. At f = f MAX, address and control lines (except Output Enable) are cycling at the maximum frequency clock cycle of 1/tCYC, using "AC TEST CONDITIONS" at input
levels of GND to 3V.
2. f = 0 means no address, clock, or control lines change. Applies only to input at CMOS level standby.
3. Port "A" may be either left or right port. Port "B" is the opposite from port "A".
4. VCC = 5V, TA = 25°C for Typ, and are not production tested. I CC DC(f=0) = 150mA (Typ).
5. CE X = VIL means CE0X = VIL and CE1X = VIH
CE X = VIH means CE0X = VIH or CE1X = V IL
CE X < 0.2V means CE0X < 0.2V and CE1X > VCC - 0.2V
CE X > VCC - 0.2V means CE0X > VCC - 0.2V or CE1X < 0.2V
"X" represents "L" for left port or "R" for right port.
6. 'X' in part numbers indicate power rating (S or L).
6.42
5
IDT709279/69S/L
High-Speed 32/16K x 16 Synchronous Dual-Port Static RAM
Preliminary
Industrial and Commercial Temperature Ranges
DC Electrical Characteristics Over the Operating
Temperature and Supply Voltage Range(6) (VCC = 5V ± 10%)
709279/69X12
Com'l
& Ind
Symbol
ICC
ISB1
ISB2
ISB3
ISB4
Parameter
Dynamic Operating
Current
(Both Ports Active)
Standby Current
(Both Ports - TTL
Level Inputs)
Standby Current
(One Port - TTL
Level Inputs)
Full Standby Current
(Both Ports CMOS Level Inputs)
Full Standby Current
(One Port CMOS Level Inputs)
Test Condition
Version
709279/69X15
Com'l Only
Typ. (4)
Max.
Typ. (4)
Max.
Unit
mA
COM'L
S
L
200
200
345
305
190
190
325
285
IND
S
L
200
200
380
340
____
____
____
____
COM'L
S
L
50
50
110
90
50
50
110
90
IND
S
L
50
50
125
105
____
____
____
____
CE"A" = VIL and
CE"B" = VIH(3)
Active Port Outputs
Disabled, f=fMAX(1)
COM'L
S
L
130
130
230
200
120
120
220
190
IND
S
L
130
130
245
215
____
____
____
____
Both Ports CER and
CEL > VCC - 0.2V
VIN > VCC - 0.2V or
VIN < 0.2V, f = 0(2)
COM'L
S
L
1.0
0.2
15
5
1.0
0.2
15
5
IND
S
L
1.0
0.2
15
5
____
____
____
____
COM'L
S
L
120
120
205
185
110
110
195
175
IND
S
L
120
120
220
200
____
____
____
____
CEL and CER= VIL
Outputs Disabled f = fMAX(1)
CEL = CER = VIH
f = fMAX(1)
CE"A" < 0.2V and
CE"B" > VCC - 0.2V(5)
VIN > VCC - 0.2V or
VIN < 0.2V, Active Port Outputs
Disabled, f = fMAX(1)
mA
mA
mA
mA
3243 tbl 09a
NOTES:
1. At f = fMAX, address and control lines (except Output Enable) are cycling at the maximum frequency clock cycle of 1/tCYC, using "AC TEST CONDITIONS" at input
levels of GND to 3V.
2. f = 0 means no address, clock, or control lines change. Applies only to input at CMOS level standby.
3. Port "A" may be either left or right port. Port "B" is the opposite from port "A".
4. VCC = 5V, TA = 25°C for Typ, and are not production tested. ICC DC(f=0) = 150mA (Typ).
5. CEX = VIL means CE0X = VIL and CE1X = VIH
CEX = VIH means CE0X = VIH or CE1X = V IL
CEX < 0.2V means CE0X < 0.2V and CE1X > VCC - 0.2V
CEX > VCC - 0.2V means CE0X > VCC - 0.2V or CE1X < 0.2V
"X" represents "L" for left port or "R" for right port.
6. 'X' in part numbers indicate power rating (S or L).
6
6.42
IDT709279/69S/L
High-Speed 32/16K x 16 Synchronous Dual-Port Static RAM
Preliminary
Industrial and Commercial Temperature Ranges
AC Test Conditions
GND to 3.0V
Input Pulse Levels
3ns Max.
Input Rise/Fall Times
Input Timing Reference Levels
1.5V
Output Reference Levels
1.5V
Figures 1,2 and 3
Output Load
3243 tbl 10
5V
5V
893Ω
893Ω
DATAOUT
DATAOUT
30pF
347Ω
3243 drw 04
3243 drw 05
Figure 1. AC Output Test load.
8
7
5pF*
347Ω
Figure 2. Output Test Load
(For tCKLZ, t CKHZ, tOLZ , and tOHZ ).
*Including scope and jig.
- 10pF is the I/O capacitance
of this device, and 30pF is the
AC Test Load Capacitance
6
tCD1,
tCD2
(Typical, ns)
5
4
3
2
1
0
-1
20 40 60 80 100 120 140 160 180 200
Capacitance (pF)
3243 drw 06
Figure 3. Typical Output Derating (Lumped Capacitive Load).
6.42
7
,
IDT709279/69S/L
High-Speed 32/16K x 16 Synchronous Dual-Port Static RAM
Preliminary
Industrial and Commercial Temperature Ranges
AC Electrical Characteristics Over the Operating Temperature Range
(Read and Write Cycle Timing)(3,4) (VCC = 5V ± 10%, TA = 0°C to +70°C)
709279/69X6
Com'l Only
Symbol
Parameter
(2)
709279/69X7
Com'l Only
709279/69X9
Com'l Only
709279/69X12
Com'l
& Ind
709279/69X15
Com'l Only
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
Unit
19
____
22
____
25
____
30
____
35
____
ns
10
____
12
____
15
____
20
____
25
____
ns
tCYC1
Clock Cycle Time (Flow-Through)
tCYC2
Clock Cycle Time (Pipelined)(2)
tCH1
Clock High Time (Flow-Through)(2)
6.5
____
7.5
____
12
____
12
____
12
____
ns
tCL1
(2)
tCH2
Clock Low Time (Flow-Through)
6.5
____
7.5
____
12
____
12
____
12
____
ns
(2)
4
____
5
____
6
____
8
____
10
____
ns
(2)
4
____
5
____
6
____
8
____
10
____
ns
Clock High Time (Pipelined)
tCL2
Clock Low Time (Pipelined)
tR
Clock Rise Time
____
3
____
3
____
3
____
3
____
3
ns
tF
Clock Fall Time
____
3
____
3
____
3
____
3
____
3
ns
tSA
Address Setup Time
3.5
____
4
____
4
____
4
____
4
____
ns
tHA
Address Hold Time
0
____
0
____
1
____
1
____
1
____
ns
tSC
Chip Enable Setup Time
3.5
____
4
____
4
____
4
____
4
____
ns
tHC
Chip Enable Hold Time
0
____
0
____
1
____
1
____
1
____
ns
tSW
R/W Setup Time
3.5
____
4
____
4
____
4
____
4
____
ns
tHW
R/W Hold Time
0
____
0
____
1
____
1
____
1
____
ns
tSD
Input Data Setup Time
3.5
____
4
____
4
____
4
____
4
____
ns
tHD
Input Data Hold Time
0
____
0
____
1
____
1
____
1
____
ns
tSAD
ADS Setup Time
3.5
____
4
____
4
____
4
____
4
____
ns
tHAD
ADS Hold Time
0
____
0
____
1
____
1
____
1
____
ns
tSCN
CNTEN Setup Time
3.5
____
4
____
4
____
4
____
4
____
ns
tHCN
CNTEN Hold Time
0
____
0
____
1
____
1
____
1
____
ns
CNTRST Setup Time
3.5
____
4
____
4
____
4
____
4
____
ns
tHRST
CNTRST Hold Time
0
____
0
____
1
____
1
____
1
____
ns
tOE
Output Enable to Data Valid
____
6.5
____
7.5
____
9
____
12
____
15
ns
2
____
2
____
2
____
2
____
2
____
ns
tSRST
tOLZ
tOHZ
(1)
Output Enable to Output Low-Z
(1)
Output Enable to Output High-Z
tCD1
Clock to Data Valid (Flow-Through)
tCD2
Clock to Data Valid (Pipelined)(2)
tDC
Data Output Hold After Clock High
tCKHZ
tCKLZ
(2)
1
7
1
7
1
7
1
7
1
7
ns
____
15
____
18
____
20
____
25
____
30
ns
____
6.5
____
7.5
____
9
____
12
____
15
ns
2
____
2
____
2
____
2
____
2
____
ns
(1)
2
9
2
9
2
9
2
9
2
9
ns
(1)
2
____
2
____
2
____
2
____
2
____
ns
ns
Clock High to Output High-Z
Clock High to Output Low-Z
Port-to-Port Delay
tCWDD
Write Port Clock High to Read Data Delay
____
24
____
28
____
35
____
40
____
50
tCCS
Clock-to-Clock Setup Time
____
9
____
10
____
15
____
15
____
20
ns
3243 tbl 11
NOTES:
1. Transition is measured 0mV from Low or High-impedance voltage with the Output Test Load (Figure 2). This parameter is guaranteed by device characterization, but is not production tested.
2. The Pipelined output parameters (tCYC2, tCD2) apply to either or both left and right ports when FT/PIPE = V IH. Flow-through parameters (tCYC1, tCD1) apply when
FT/PIPE = VIL for that port.
3. All input signals are synchronous with respect to the clock except for the asynchronous Output Enable (OE) and FT/PIPE. FT/PIPE should be treated as a DC
signal, i.e. steady state during operation.
4. 'X' in part number indicates power rating (S or L).
8
6.42
IDT709279/69S/L
High-Speed 32/16K x 16 Synchronous Dual-Port Static RAM
Preliminary
Industrial and Commercial Temperature Ranges
Timing Waveform of Read Cycle for Flow-Through Output
(FT/PIPE"X" = VIL)(3,7)
tCYC1
tCH1
tCL1
CLK
CE0
tSC
tSC
tHC
CE1
tSB
tHB
UB, LB
tHB
tSB
R/W
tSW
tHW
tSA
tHA
(5)
ADDRESS
An
An + 1
An + 2
tCKHZ (1)
Qn
DATAOUT
tCKLZ
An + 3
tDC
tCD1
OE
tHC
(4)
Qn + 1
(1)
tOHZ
Qn + 2
(1)
tOLZ
tDC
(1)
(2)
tOE
3243 drw 07
Timing Waveform of Read Cycle for Pipelined Output (FT/PIPE"X" = VIH)(3,7)
tCYC2
tCH2
tCL2
CLK
CE0
tSC
tSC
tHC
tHC
(4)
CE1
UB, LB
R/W
(5)
ADDRESS
tSB
tSB
tHB
tHB
(6)
tSW
tHW
tSA
tHA
An
An + 1
(1 Latency)
An + 2
tDC
tCD2
DATAOUT
Qn
tCKLZ
An + 3
Qn + 1
(1)
tOHZ
Qn + 2
(1)
tOLZ
(6)
(1)
(2)
OE
tOE
3243 drw 08
NOTES:
1. Transition is measured 0mV from Low or High-impedance voltage with the Output Test Load (Figure 2).
2. OE is asynchronously controlled; all other inputs are synchronous to the rising clock edge.
3. ADS = VIL, CNTEN and CNTRST = VIH.
4. The output is disabled (High-Impedance state) by CE0 = V IH, CE1 = VIL, UB = VIH, or LB = V IH following the next rising edge of the clock. Refer to Truth Table 1.
5. Addresses do not have to be accessed sequentially since ADS = VIL constantly loads the address on the rising edge of the CLK; numbers
are for reference use only.
6. If UB or LB was HIGH, then the Upper Byte and/or Lower Byte of DATAOUT for Qn + 2 would be disabled (High-Impedance state).
7. "x" denotes Left or Right port. The diagram is with respect to that port.
6.42
9
IDT709279/69S/L
High-Speed 32/16K x 16 Synchronous Dual-Port Static RAM
Preliminary
Industrial and Commercial Temperature Ranges
Timing Waveform of a Bank Select Pipelined Read(1,2)
tCH2
tCYC2
tCL2
CLK
tSA
A0
ADDRESS(B1)
CE0(B1)
tHA
tSC tHC
tSC tHC
tCD2
tCKHZ
tCD2
Q3
Q1
tDC
tDC
tSA
(3)
tCD2
Q0
DATAOUT(B1)
ADDRESS(B2)
A6
A5
A4
A3
A2
A1
tCKLZ
(3)
tCKHZ (3)
tHA
A0
A6
A5
A4
A3
A2
A1
tSC tHC
CE0(B2)
tSC tHC
tCKHZ (3)
tCD2
DATAOUT(B2)
tCKLZ
tCD2
Q2
(3)
Q4
tCKLZ (3)
3243 drw 09
Timing Waveform of a Bank Select Flow-Through Read(6)
tCH1
tCYC1
tCL1
CLK
tSA
ADDRESS(B1)
CE0(B1)
tHA
A0
tSC
tHC
tSC
tCD1
tCKHZ
tCD1
D3
tCKLZ
(1)
D5
tCKHZ (1)
tCKLZ
(1)
tHA
A0
tSC
tCD1
tDC
A1
A6
A5
A4
A3
A2
tSC
CE0(B2)
(1)
D1
tDC
ADDRESS(B2)
tHC
tCD1
D0
DATAOUT(B1)
tSA
A6
A5
A4
A3
A2
A1
tHC
tHC
tCD1
DATAOUT(B2)
tCKLZ
(1)
tCKHZ
(1)
tCD1
D2
tCKLZ
(1)
tCKHZ
(1)
D4
3243 drw 09a
NOTES:
1. B1 Represents Bank #1; B2 Represents Bank #2. Each Bank consists of one IDT709279/69 for this waveform, and are setup for depth expansion in this
example. ADDRESS(B1) = ADDRESS(B2) in this situation.
2. UB, LB, OE, and ADS = VIL; CE1(B1) , CE1(B2) , R/W, CNTEN, and CNTRST = VIH.
3. Transition is measured 0mV from Low or High-impedance voltage with the Output Test Load (Figure 2).
4. CE0, UB, LB, and ADS = VIL; CE1, CNTEN, and CNTRST = V IH.
5. OE = VIL for the Right Port, which is being read from. OE = VIH for the Left Port, which is being written to.
6. If tCCS < maximum specified, then data from right port READ is not valid until the maximum specified for tCWDD .
If tCCS > maximum specified, then data from right port READ is not valid until tCCS + tCD1. tCWDD does not apply in this case.
10
6.42
IDT709279/69S/L
High-Speed 32/16K x 16 Synchronous Dual-Port Static RAM
Preliminary
Industrial and Commercial Temperature Ranges
Timing Waveform with Port-to-Port Flow-Through Read(1,2,3,5)
CLK "A"
tSW
tHW
tSA
tHA
R/W "A"
ADDRESS "A"
tSD
DATAIN "A"
NO
MATCH
MATCH
tHD
VALID
tCCS
(4)
CLK "B"
tCD1
R/W "B"
ADDRESS "B"
tSW
tHW
tSA
tHA
NO
MATCH
MATCH
tCWDD (4)
tCD1
DATAOUT "B"
VALID
VALID
tDC
tDC
3243 drw 10
NOTES:
1. Transition is measured 0mV from Low or High-impedance voltage with the Output Test Load (Figure 2).
2. CE 0, UB, LB, and ADS = VIL; CE1, CNTEN, and CNTRST = VIH .
3. OE = V IL for the Right Port, which is being read from. OE = VIH for the Left Port, which is being written to.
4. If t CCS < maximum specified, then data from right port READ is not valid until the maximum specified for tCWDD.
If t CCS > maximum specified, then data from right port READ is not valid until tCCS + t CD1. tCWDD does not apply in this case.
5. All timing is the same for both left and right ports. Port "A" may be either left or right port. Port "B" is the opposite of Port "A".
6.42
11
IDT709279/69S/L
High-Speed 32/16K x 16 Synchronous Dual-Port Static RAM
Preliminary
Industrial and Commercial Temperature Ranges
Timing Waveform of Pipelined Read-to-Write-to-Read (OE = VIL)(3)
tCYC2
tCH2
tCL2
CLK
CE0
tSC tHC
CE1
tSB
tHB
UB, LB
tSW tHW
R/W
(4)
ADDRESS
tSW tHW
An
tSA tHA
An +1
An + 2
An + 3
An + 2
An + 4
tSD tHD
DATAIN
Dn + 2
tCD2
(2)
tCKHZ
(1)
(1)
tCD2
tCKLZ
Qn + 3
Qn
DATAOUT
READ
NOP
(5)
WRITE
READ
3243 drw 11
Timing Waveforn of Pipelined Read-to-Write-to-Read (OE Controlled)(3)
tCH2
tCYC2
tCL2
CLK
CE0
tSC
tHC
tSB
tHB
CE1
UB, LB
tSW tHW
R/W
(4)
ADDRESS
tSW tHW
An
tSA tHA
An +1
An + 2
tSD
DATAIN
An + 4
An + 5
tHD
Dn + 2
tCD2
(2)
An + 3
Dn + 3
tCKLZ(1)
tCD2
Qn
DATAOUT
Qn + 4
tOHZ(1)
OE
READ
WRITE
READ
3243 drw 12
NOTES:
1. Transition is measured 0mV from Low or High-impedance voltage with the Output Test Load (Figure 2).
2. Output state (High, Low, or High-impedance) is determined by the previous cycle control signals.
3. CE0, UB, LB, and ADS = VIL; CE1, CNTEN, and CNTRST = V IH.
4. Addresses do not have to be accessed sequentially since ADS = VIL constantly loads the address on the rising edge of the CLK; numbers are for reference use
only.
5. "NOP" is "No Operation." Data in memory at the selected address may be corrupted and should be re-written to guarantee data integrity.
12
6.42
IDT709279/69S/L
High-Speed 32/16K x 16 Synchronous Dual-Port Static RAM
Preliminary
Industrial and Commercial Temperature Ranges
Timing Waveform of Flow-Through Read-to-Write-to-Read (OE = VIL)(3)
tCH1
tCYC1
tCL1
CLK
CE0
tSC
tHC
tSB
tHB
CE1
UB, LB
tSW tHW
R/W
tSW tHW
(4)
ADDRESS
tSA
An
tHA
An +1
An + 2
An + 4
An + 3
An + 2
tSD tHD
DATAIN
Dn + 2
tCD1
(2)
tCD1
tCD1
Qn
DATAOUT
tCD1
Qn + 3
Qn + 1
tDC
tCKHZ
(5)
NOP
READ
(1)
(1)
tCKLZ
WRITE
tDC
READ
3243 drw 13
Timing Waveform of Flow-Through Read-to-Write-to-Read (OE Controlled)(3)
tCYC1
tCH1
tCL1
CLK
CE0
tSC tHC
CE1
tSB
tHB
UB, LB
tSW tHW
R/W
tSW tHW
(4)
ADDRESS
tSA
An
tHA
An +1
An + 2
DATAIN
Dn + 2
(2)
DATAOUT
An + 3
An + 4
An + 5
tSD tHD
Dn + 3
tDC
tCD1
Qn
tOE
tCD1
(1)
tOHZ
tCKLZ
(1)
tCD1
Qn + 4
tDC
OE
READ
WRITE
READ
3243 drw 14
NOTES:
1. Transition is measured 0mV from Low or High-impedance voltage with the Output Test Load (Figure 2).
2. Output state (High, Low, or High-impedance is determined by the previous cycle control signals.
3. CE 0, UB, LB, and ADS = VIL; CE1, CNTEN, and CNTRST = VIH .
4. Addresses do not have to be accessed sequentially since ADS = VIL constantly loads the address on the rising edge of the CLK; numbers are for reference use
only.
5. "NOP" is "No Operation." Data in memory at the selected address may be corrupted and should be re-written to guarantee data integrity.
6.42
13
IDT709279/69S/L
High-Speed 32/16K x 16 Synchronous Dual-Port Static RAM
Preliminary
Industrial and Commercial Temperature Ranges
Timing Waveform of Pipelined Read with Address Counter Advance(1)
tCH2
tCYC2
tCL2
CLK
tSA
ADDRESS
tHA
An
tSAD tHAD
ADS
tSAD tHAD
CNTEN
tSCN tHCN
tCD2
DATAOUT
Qx - 1(2)
Qn + 2(2)
Qn + 1
Qn
Qx
Qn + 3
tDC
READ
EXTERNAL
ADDRESS
READ
WITH
COUNTER
COUNTER
HOLD
READ WITH COUNTER
3243 drw 15
Timing Waveform of Flow-Through Read with Address Counter Advance(1)
tCH1
tCYC1
tCL1
CLK
tSA
ADDRESS
tHA
An
tSAD tHAD
ADS
tSAD tHAD
tSCN tHCN
CNTEN
tCD1
DATAOUT
Qx(2)
Qn
Qn + 1
Qn + 2
Qn + 3(2)
Qn + 4
tDC
READ
EXTERNAL
ADDRESS
READ WITH COUNTER
COUNTER
HOLD
READ
WITH
COUNTER
3243 drw 16
NOTES:
1. CE0, OE, UB, and LB = VIL; CE1, R/W, and CNTRST = VIH.
2. If there is no address change via ADS = VIL (loading a new address) or CNTEN = VIL (advancing the address), i.e. ADS = VIH and CNTEN = VIH, then the data
output remains constant for subsequent clocks.
14
6.42
IDT709279/69S/L
High-Speed 32/16K x 16 Synchronous Dual-Port Static RAM
Preliminary
Industrial and Commercial Temperature Ranges
Timing Waveform of Write with Address Counter Advance
(Flow-Through or Pipelined Outputs)(1)
tCH2
tCYC2
tCL2
CLK
tSA
tHA
An
ADDRESS
INTERNAL(3)
ADDRESS
An(1)
An + 2
An + 1
An + 4
An + 3
tSAD tHAD
ADS
CNTEN
tSD tHD
Dn + 1
Dn
DATAIN
WRITE
EXTERNAL
ADDRESS
Dn + 1
Dn + 4
Dn + 3
Dn + 2
WRITE
WRITE
WITH COUNTER COUNTER HOLD
WRITE WITH COUNTER
3243 drw 17
Timing Waveform of Counter Reset (Pipelined Outputs)(2)
tCH2
tCYC2
tCL2
CLK
tSA tHA
(4)
An
ADDRESS
INTERNAL(3)
ADDRESS
Ax(6)
0
1
An + 2
An + 1
An + 1
An
tSW tHW
R/W
ADS
CNTEN
tSRST tHRST
CNTRST
tSD
tHD
D0
DATAIN
(5)
COUNTER
RESET
WRITE
ADDRESS 0
READ
ADDRESS 0
READ
ADDRESS 1
Qn
Q1
Q0
DATAOUT
READ
ADDRESS n
READ
ADDRESS n+1
3243 drw 18
NOTES:
1. CE 0, UB, LB, and R/W = VIL; CE1 and CNTRST = VIH.
2. CE 0, UB, LB = VIL; CE1 = VIH.
3. The "Internal Address" is equal to the "External Address" when ADS = VIL and equals the counter output when ADS = VIH.
4. Addresses do not have to be accessed sequentially since ADS = VIL constantly loads the address on the rising edge of the CLK; numbers are for reference use
only.
5. Output state (High, Low, or High-impedance) is determined by the previous cycle control signals.
6. No dead cycle exists during counter reset. A READ or WRITE cycle may be coincidental with the counter reset cycle. ADDR 0 will be accessed. Extra cycles
are shown here simply for clarification.
7. CNTEN = VIL advances Internal Address from ‘An’ to ‘An +1’. The transition shown indicates the time required for the counter to advance. The ‘An +1’Address is
written to during this cycle.
6.42
15
IDT709279/69S/L
High-Speed 32/16K x 16 Synchronous Dual-Port Static RAM
Preliminary
Industrial and Commercial Temperature Ranges
A Functional Description
Depth and Width Expansion
The IDT709279/69 provides a true synchronous Dual-Port Static
RAM interface. Registered inputs provide minimal set-up and hold times
on address, data, and all critical control inputs. All internal registers are
clocked on the rising edge of the clock signal, however, the self-timed
internal write pulse is independent of the LOW to HIGH transition of the clock
signal.
An asynchronous output enable is provided to ease asynchronous
bus interfacing. Counter enable inputs are also provided to stall the
operation of the address counters for fast interleaved memory applications.
A HIGH on CE0 or a LOW on CE1 for one clock cycle will power down
the internal circuitry to reduce static power consumption. Multiple chip
enables allow easier banking of multiple IDT709279/69's for depth
expansion configurations. When the Pipelined output mode is enabled, two
cycles are required with CE0 LOW and CE1 HIGH to re-activate the
outputs.
The IDT709279/69 features dual chip enables (refer to Truth Table
I) in order to facilitate rapid and simple depth expansion with no requirements for external logic. Figure 4 illustrates how to control the various chip
enables in order to expand two devices in depth.
The IDT709279/69 can also be used in applications requiring expanded width, as indicated in Figure 4. Since the banks are allocated at
the discretion of the user, the external controller can be set up to drive the
input signals for the various devices as required to allow for 32-bit
or wider applications.
A15/A14(1)
IDT709279/69
CE0
CE1
IDT709279/69
VCC
CE1
VCC
Control Inputs
Control Inputs
IDT709279/69
CE0
IDT709279/69
CE1
CE1
CE0
CE0
Control Inputs
Control Inputs
3243 drw 19
Figure 4. Depth and Width Expansion with IDT709279/69
NOTE:
1. A14 is for IDT709269.
16
6.42
,
CNTRST
CLK
ADS
CNTEN
R/W
OE
IDT709279/69S/L
High-Speed 32/16K x 16 Synchronous Dual-Port Static RAM
Preliminary
Industrial and Commercial Temperature Ranges
Ordering Information
IDT
XXXXX
A
99
A
A
Device
Type
Power
Speed
Package
Process/
Temperature
Range
Blank
I(1)
Commercial (0°C to +70°C)
Industrial (-40°C to +85°C)
PF
G
100-pin TQFP (PN100-1)
108-pin PGA (G108-1)
6
7
9
12
15
Commercial
Commercial
Commercial
Commercial
Commercial
S
L
Standard Power
Low Power
Only
Only
Only
& Industrial
Only
Speed in nanoseconds
,
709279 512K (32K x 16-Bit) Synchronous Dual-Port RAM
709269 256K (16K x 16-Bit) Synchronous Dual-Port RAM
3243 drw 20
NOTES:
1. Industrial temperature range is available.
For specific speeds, packages and powers contact your sales office.
Ordering Information for Flow-through Devices
Old Flow-through Part
New Combined Part
70927S/L20
709279S/L9
70927S/L25
709279S/L12
70927S/L30
709279S/L15
3243 tbl 12
IDT Clock Solution for IDT709279/69 Dual-Port
Dual-Port I/O Specitications
IDT Dual-Port
Part Number
Voltage
709279/69
5
Clock Specifications
I/O
Input
Capacitance
Input Duty
Cycle
Requirement
Maximum
Frequency
Jitter
Tolerance
IDT
PLL
Clock Device
IDT
Non-PLL
Clock Device
TTL
9pF
40%
100
150ps
FCT88915TT
49FCT805T
49FCT806T
74FCT807T
3243 tbl 13
6.42
17
IDT709279/69S/L
High-Speed 32/16K x 16 Synchronous Dual-Port Static RAM
Preliminary
Industrial and Commercial Temperature Ranges
Datasheet Document History
12/9/98:
06/03/99:
11/10/99:
03/31/00:
05/24/00:
08/24/01:
06/21/04:
Initiated datasheet document history
Converted to new format
Cosmetic and typographical corrections
Added additional notes to pin configurations
Pages 13 & 14 Updated timing waveforms
Page 15 Added Depth and Width Expansion section
Changed drawing format
Page 3 Deleted note 6 for Table II
Replaced IDT logo
Combined Pipelined 709279 family and Flow-through 70927 family offerings into one data sheet
Changed ±200mV in waveform notes to 0mV
Added corresponding part chart with ordering information
Page 1 Inserted diamond in copy
Page 4 Changed information in Truth Table II, Increased storage temperature parameter, clarified TA parameter
Page 5 Changed DC Electrical parameters–changed wording from "Open" to "Disabled"
Page 16 Fixed typeface in heading
Added Industrial Temperature Ranges and removed related notes
Pages 1, 16 and Page Header Removed Preliminary status
Page 5 & 7 Removed Industrial Temperature Ranges for 15ns speed from DC and AC Electrical Characteristics
Page 16 Removed Industrial Temperature from 15ns speed in ordering information
Consolidated multiple devices into one datasheet
Page 2 Added date revision to pin configuration
Page 4 Added Junction Temperature to Absolute Maximum Ratings Table
Added Ambient Temperature footnote
Page 5 & 6 Added 6ns & 7ns speed DC power numbers to the DC Electrical Characteristics Table
Page 8 Added 6ns & 7ns speed AC timing numbers to the AC Electrical Characteristics Table
Page 17 Added 6ns & 7ns speed grades to ordering information
Added IDT Clock Solution Table
Page 1 & 18 Replaced old  logo with new TM logo
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18
6.42
for Tech Support:
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