LM21305
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SNVS639F – DECEMBER 2009 – REVISED MARCH 2013
5A Adjustable Frequency Synchronous Buck Regulator
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FEATURES
APPLICATIONS
•
•
1
2
•
•
•
•
•
•
•
•
•
•
High Efficiency Switcher Core With Integrated
Low RDSon Power MOSFETs
Resistor Programmable Switching Frequency
With Frequency Synchronization
Internal Soft-Start With Monotonic and PreBiased Startup
Low Shutdown Quiescent Current
Precision Enable With Hysteresis
PGOOD Indicator Function
Input Under-Voltage Lock-Out (UVLO)
Output Over-Voltage Protection (OVP)
High-Bandwidth Load Transient Response
With Peak Current-Mode Control
Cycle-by-Cycle Current Limiting
Thermal Shutdown
KEY SPECIFICATIONS
•
•
•
•
3V to 18V Single-Rail Input Voltage
0.598V Feedback Voltage Reference
300 kHz to 1.5 MHz Switching Frequency
WQFN-28 Package (5 x 5 x 0.8 mm, 0.5 mm
Pitch)
•
•
POL Regulation From 3.3V, 5V, and 12V
Supply Rails
High Efficiency Supply for DSPs, FPGAs,
ASICs and Processors
Broadband, Networking and Optical
Communications Infrastructure
DESCRIPTION
The LM21305 is a full-featured 5A synchronous buck
POL regulator optimized for solution size, flexibilty,
and high conversion efficiency. High power density
LM21305 designs are achieved via monolithic
integration of the high-side and low-side power
MOSFETs, high switching frequency, current-mode
control, and optimized thermal design. The efficiency
of the LM21305 is elevated at light loads with diode
emulation mode operation and at heavy loads by
optimal design of the MOSFET gate drivers to
minimize switch dead-times and body-diode
conduction losses.
The LM21305 accepts a wide input voltage range of
3V to 18V, facilitating interface to all intermediate bus
voltages, including 3.3V, 5V and 12V rails. An output
voltage as low as 0.598V is supported with excellent
setpoint accuracy and low ripple and RMS noise.
Typical Application Circuit
VIN
PVIN
CBOOT
CIN
CBOOT
L
RF
VOUT
0.6V - 5V
SW
AVIN
CF
RFB1
REN1
COUT
FB
EN
REN2
C2V5
C5V0
LM21305
RFB2
Cc1
2V5
Rc
COMP
5V0
RPG
CFRQ
SYNC
FREQ
PGOOD
AGND PGND
RFRQ
1
2
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2009–2013, Texas Instruments Incorporated
LM21305
SNVS639F – DECEMBER 2009 – REVISED MARCH 2013
www.ti.com
DESCRIPTION (CONTINUED)
The LM21305 offers flexible system configuration with programmable switching frequency from 300 kHz to 1.5
MHz using one resistor or via external clock synchronization. On-chip bias supply sub-regulators alleviate the
need for external bias power and simplify PCB layout. The device also offers internal soft-start to limit inrush
current, pre-biased and monotonic startup capability, cycle-by-cycle current limiting, and thermal shutdown. Peak
current-mode control with a high-gain error amplifier maintains stability throughout the entire input voltage and
load current ranges and enables excellent line and load transient response.
Offered in a thermally enhanced WQFN-28 package, the LM21305 features internal output over-voltage and
over-current protection circuits for increased system reliability. A precision enable pin and integrated input UVLO
allow the turn-on of the device to be tightly controlled and sequenced. An integrated open-drain power good
indicator provides power rail sequencing capability and fault indication.
15
EN
16 FREQ
17 AGND
PGND 9
PGND 8
10
PGND
FB 13
12
PGOOD
COMP 11
AGND
14
Connection Diagram
PGND
SW
SW
PAD
18 AGND
19
AGND
20 AGND
SW
6
5
4
3
2
PVIN
1
PVIN
PVIN
28
AVIN
23
22
AVIN
21 2V5
24
AGND
25 5V0
26
CBOOT
27 PVIN
SW
7
Figure 1. WQFN-28 Package, Exposed Pad
Package Number RSG
2
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PIN DESCRIPTIONS
Number
Name
Type (1)
1,2,27,28
PVIN
P
Input voltage to the power switches inside the device.
3,4,5,6
SW
P
Switch node output of the power switches. Voltage swings from PVIN to GND on this
pin. SW also delivers current to the external inductor.
7,8,9,10
PGND
G
Power ground for the internal power switches.
Compensation pin to connect to external compensation network.
Pad Description
11
COMP
A
12
PGOOD
OD
13
FB
A
Voltage Feedback pin. This pin can be connected to the output voltage directly or
through a resistor divider to set the output voltage range.
14,17,18,19,20,24
AGND
G
Analog ground for the internal bias circuitry.
15
EN
I
Precision enable pin. An external divider can be used to set the device turn-on
threshold. If not used, the EN pin should be connected to AVIN.
16
FREQ
A
Frequency setting pin. This pin can be connected to a resistor to AGND to set the
internal oscillator frequency. It also can be connected to an external clock source via a
capacitor such that the switching frequency of the device is synchronized to the
external clock.
21
2V5
P
2.5V output of internal regulator. This pin is only for bypassing the internal LDO.
Loading this pin is not recommended.
22,23
AVIN
P
Analog power input. AVIN powers the internal 2.5V and 5.0V LDOs which provide bias
current and internal driver power. It can be connected to PVIN through a low pass RC
filter or can be supplied by a separate rail.
25
5V0
P
5.0V output of internal regulator. This pin is only for bypassing the internal LDO.
Loading this pin is not recommended.
26
CBOOT
A
Bootstrap pin to drive the high-side switch. A bootstrap capacitor should be connected
between this pin and the SW pin.
PAD
PAD
(1)
Power Good, open-drain output. If high, indicates the output voltage is regulated within
tolerance. A pull-up resistor (10 kΩ to 100 kΩ) is recommended for most applications.
Exposed pad at the back of the device. The PAD should be connected to PGND, but
cannot be used as primary ground connection. Use multiple vias under the PAD for
optimal thermal performance.
P: Power, A: Analog, I: Digital Input, OD: Open Drain, G: Ground
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
Absolute Maximum Ratings
(1) (2)
PVIN, AVIN, SW, EN, PGOOD to AGND
−0.3V to +20V
CBOOT to AGND
−0.3V to +25V
CBOOT to SW
−0.3V to +5.5V
−0.3V to +6V
5V0, FB, COMP, FREQ to AGND
−0.3V to +3V
2V5 to AGND
−0.3V to +0.3V
AGND to PGND
Junction Temperature (TJ-MAX)
150°C
−65°C to 150°C
Storage Temperature Range
Maximum Continuous Power Dissipation PD-MAX
(3)
Maximum Lead Temperature Lead-free Compatible
(1)
(2)
(3)
(4)
Internally limited
(4)
260°C
Absolute Maximum Ratings are limits beyond which damage to the device may occur. Operating Ratings are conditions under which
operation of the device is ensured. Operating Ratings do not imply specified performance limits. For specified performance limits and
associated test conditions, see the Electrical Characteristics tables.
If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/Distributors for availability and
specifications.
The amount of Absolute Maximum power dissipation allowed in the device depends on the ambient temperature and can be calculated
using the formula P = (TJ – TA)/θJA, where TJ is the junction temperature, TA is the ambient temperature and θJA is the junction-toambient thermal resistance. Junction-to-ambient thermal resistance is highly application and board-layout dependent. In applications
where high power dissipation exists, special care must be paid to thermal dissipation issues in PC board design. Internal thermal
shutdown circuitry protects the device from permanent damage.
For detailed soldering specifications, please refer to Application Note AN-1187: Leadless Leadframe Package (LLP) (literature number
SNOA401).
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LM21305
SNVS639F – DECEMBER 2009 – REVISED MARCH 2013
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ESD Ratings
All pins, Human Body Model
(1)
(1)
±2kV
The Human Body Model is a 100 pF capacitor discharged through a 1.5 kΩ resistor into each pin (MIL-STD-883 3015.7).
Operating Ratings
PVIN to PGND, AGND
3V to 18V
AVIN to PGND, AGND
3V to 18V
−40°C to 125°C
Junction Temperature
Ambient Temperature (1)
−40°C to 85°C
Junction-to-Ambient Thermal Resistance θJA (2)
(1)
(2)
32.4°C/W
In applications where high power dissipation and/or poor package thermal resistance is present, the maximum ambient temperature may
have to be de-rated. Maximum ambient temperature (TA-MAX) is dependent on the maximum operating junction temperature (TJ-MAX-OP =
125°C), the maximum power dissipation of the device in the application (PD-MAX), and the junction-to ambient thermal resistance of the
part/package in the application (θJA), as given by the following equation: TA-MAX = TJ-MAX-OP – (θJA × PD-MAX).
Junction-to-ambient thermal resistance (θJA) is taken from a thermal modeling result, performed under the conditions and guidelines set
forth in the JEDEC standard JESD51-7. The test board is a 4-layer standard JEDEC thermal test board or 4LJEDEC, 4" x 3" in size,
with a 3 by 3 array of thermal vias. The board has two embedded copper layers which cover roughly the same size as the board. The
copper thickness for the four layers, starting from the top one, is 2 oz./1oz./1oz./2 oz. For WQFN, thermal vias are placed between the
die attach pad in the 1st. copper layer and 2nd. copper layer. Detailed description of the board can be found in JESD 51-7. Ambient
temperature in the simulation is 22°C, still air. Power dissipation is 1W. The value of θJA of this product can vary significantly depending
on PCB material, layout, and environmental conditions. In applications with high power dissipation (e.g. high VOUT, high IOUT), special
care must be paid to thermal dissipation issues. For more information on these topics, please refer to Application Note AN-1187:
Leadless Leadframe Package (LLP) (literature number SNOA401).
Electrical Characteristics
(1) (2) (2)
Specifications with standard typeface are for TJ = 25°C, and those in boldface type apply over the full Operating
Temperature Range (TJ = -40°C to +125°C). Unless otherwise specified, VIN = VPVIN = VAVIN = 12V, VOUT = 3.3V, IOUT = 0A.
Symbol
Parameter
Remarks
Min
Typ
Max
Unit
0.588
0.598
0.608
V
VFB-default
Feedback pin factory-default
voltage
ΔVOUT/ΔIOUT
Load Regulation
IOUT = 0.1A to 5A
0.02
%/A
ΔVOUT/ΔVIN
Line Regulation
VPVIN = 3V to 18V
0.01
%/V
RDSonHS
High-Side Switch On
Resistance
IDS = 5A
44
mΩ
RDSonLS
Low-Side Switch On
Resistance
IDS = 5A
22
mΩ
ICL-HS
High-Side Switch Current Limit
High-side FET
ICL-LS
Low-Side Switch Current Limit
Low-side FET
INEG-CL-LS
Low-Side Switch Negative
Current Limit
Low-side FET
ISD
Quiescent Current, disabled
IQ
5.9
7.0
7.87
A
5.9
8.0
10.2
A
-7.0
-4.1
-1.64
A
VAVIN = V PVIN = 5V
0.1
2
VAVIN = V PVIN = 18V
1
4.1
Quiescent Current, enabled,
not switching
VAVIN = V PVIN = 18V
9
9.7
IFB
Feedback Pin Input Bias
Current
VFB = 0.598V
1
nA
GM
Error Amplifier
Transconductance
2400
µS
AVOL
Error Amplifier Voltage Gain
65
dB
(3)
VIH-OVP
OVP Tripping Threshold
Output voltage rising threshold,
percentage of VOUT
VHYST-OVP
OVP Hysteresis Window
Percentage of VOUT
(1)
(2)
(3)
4
103.5
109.5
-4.3
115
µA
mA
%
%
All limits are specified by design, test and/or statistical analysis. All electrical characteristics having room-temperature limits are tested
during production with TJ = 25°C. All hot and cold limits are specified by correlating the electrical characteristics to process and
temperature variations and applying statistical process control.
Capacitors: low ESR surface-mount ceramic capacitors (MLCCs) are used in setting electrical characteristics.
The low-side switch current limit is ensured to be higher than the high-side current limit.
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Electrical Characteristics (1) (2)(2) (continued)
Specifications with standard typeface are for TJ = 25°C, and those in boldface type apply over the full Operating
Temperature Range (TJ = -40°C to +125°C). Unless otherwise specified, VIN = VPVIN = VAVIN = 12V, VOUT = 3.3V, IOUT = 0A.
Min
Typ
Max
Unit
VUVLO-HI-AVIN
Symbol
AVIN UVLO Rising Threshold
Parameter
Remarks
2.84
2.93
2.987
V
VUVLO-LO-AVIN
AVIN UVLO Falling Threshold
2.66
2.73
2.83
VUVLO-HYS-AVIN
AVIN UVLO Hysteresis Window
V5V0
Internal LDO1 Output Voltage
Measured at 5V0 pin, 1kΩ load
COUT-CAP-5V0
Recommended Capacitance
connected to 5V0 pin
Ceramic capacitor
ISHORT-5V0
Short Circuit Current of 5V0 pin
V2V5
Internal LDO2 output voltage
Measured at 2V5 pin, 1kΩ load
COUT-CAP-2V5
Recommended Capacitance
connected to 2V5 pin
Ceramic capacitor
ISHORT-2V5
Short Circuit Current of 2V5 pin
VFCBOOT-D
Measured between 5V0 and
CBOOT Diode Forward Voltage
CBOOT @ 10 mA
ICBOOT
CBOOT Leakage Current
TSTARTUP-DELAY
Startup Time from EN high to
the beginning of internal softstart
SS
Internal Soft-Start
10% to 90% VFB
1.41
2.7
4.15
ms
FOSC-NOM
Oscillator Frequency, nominal
measured at SW pin
RFRQ = 61.9 kΩ, 0.025%
695
750
795
kHz
FOSC-MAX
Maximum Oscillator Frequency
measured at SW pin
RFRQ = 28.4 kΩ
1500
kHz
FOSC-MIN
Minimum Oscillator Frequency
measured at SW pin
RFRQ = 167.5 kΩ
300
kHz
TOFF-MIN
Minimum Off-Time measured at fS = 1.5 MHz, VIN = 3.3V, VFB =
SW pin
1V, voltage divider ratio = 3.3
50
ns
TON-MIN
Minimum On-Time measured at fS = 1.5 MHz, voltage divider
SW pin
ratio = 1
70
ns
VCBOOT = 5.5V, not switching
V
195
mV
4.88
V
1
µF
31
mA
2.47
V
100
nF
47
mA
0.76
V
0.65
µA
160
µs
OSCILLATOR
LOGIC
VIH-EN
EN Pin Rising Threshold
1.1
1.2
1.3
V
VHYST-EN
EN Pin Hysteresis Window
130
200
302
mV
IEN-IN
EN Pin Input Current
VEN = 12V
18
23
µA
VIH-UV-PGOOD
PGOOD UV Rising Threshold
Percentage of VOUT
93
97.5
%
VHYST-UV-PGOOD
PGOOD UV Hysteresis
Threshold
Percentage of VOUT
IOL- PGOOD
PGOOD Sink Current
VOL = 0.2V
IOH-
PGOOD Leakage Current
VOH = 18V
PGOOD
87.5
-4.2
%
3
mA
460
nA
THERMAL SHUTDOWN
TSD
Thermal Shutdown
TSD-HYS
(4)
(4)
Thermal Shutdown Hysteresis
(4)
160
°C
10
°C
Specified by design.
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Typical Performance Characteristics
Unless otherwise specified: VIN = 12V, VOUT = 3.3V, fS = 500 kHz, TA = 25°C, L = 3.3 µH, COUT = 100 µF ceramic.
Efficiency with PVIN = AVIN = 12V, fS = 300 kHz
100
100
95
95
90
90
EFFICIENCY (%)
EFFICIENCY (%)
Efficiency with PVIN = AVIN = 5V, fS = 300 kHz
85
80
75
70
65
85
80
75
70
65
VOUT = 3.3V
VOUT = 1.8V
VOUT = 1.2V
VOUT = 0.8V
60
55
50
0
1
2
3
4
LOAD CURRENT (A)
55
50
5
0
1
2
3
4
LOAD CURRENT (A)
5
Figure 3.
Efficiency with PVIN = AVIN = 5V, fS = 500 kHz
Efficiency with PVIN = AVIN = 12V, fS = 500 kHz
100
100
95
95
90
90
EFFICIENCY (%)
EFFICIENCY (%)
Figure 2.
85
80
75
70
65
55
50
0
80
75
70
65
1
2
3
4
LOAD CURRENT (A)
VOUT = 5V
VOUT = 3.3V
VOUT = 1.8V
VOUT = 1.2V
VOUT = 0.8V
60
55
50
5
0
1
2
3
4
LOAD CURRENT (A)
5
Figure 4.
Figure 5.
Efficiency with PVIN = AVIN = 5V, fS = 1 MHz
Efficiency with PVIN = AVIN = 12V, fS = 1 MHz
100
100
95
95
90
90
EFFICIENCY (%)
EFFICIENCY (%)
85
VOUT = 3.3V
VOUT = 1.8V
VOUT = 1.2V
VOUT = 0.8V
60
85
80
75
70
65
VOUT = 3.3V
VOUT = 1.8V
VOUT = 1.2V
VOUT = 0.8V
60
55
50
0
1
2
3
4
LOAD CURRENT (A)
85
80
75
70
65
VOUT = 5V
VOUT = 3.3V
VOUT = 1.8V
VOUT = 1.2V
VOUT = 0.8V
60
55
50
5
Figure 6.
6
VOUT = 5V
VOUT = 3.3V
VOUT = 1.8V
VOUT = 1.2V
VOUT = 0.8V
60
0
1
2
3
4
LOAD CURRENT (A)
5
Figure 7.
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Typical Performance Characteristics (continued)
Unless otherwise specified: VIN = 12V, VOUT = 3.3V, fS = 500 kHz, TA = 25°C, L = 3.3 µH, COUT = 100 µF ceramic.
Load Regulation (%)
Line Regulation (%)
0.10
LINE REGULATION (%)
LOAD REGULATION (%)
0.10
0.05
0.00
-0.05
-0.10
0.05
0.00
-0.05
-0.10
0
1
2
3
4
LOAD CURRENT (A)
5
3
6
9
12
15
INPUT VOLTAGE, PVIN (V)
Figure 8.
Figure 9.
VOUT Regulation (%) vs. Temperature
Quiescent Current, Not Switching
10
QUIESCENT CURRENT (mA)
VOUTREGULATION (%)
1.0
0.5
0.0
-0.5
9
8
7
6
-1.0
-40
-40°C
25°C
85°C
5
-20
0
20 40 60
TEMPERATURE (°C)
80
100
3
6
9
12
15
INPUT VOLTAGE (V)
Figure 10.
Switching Frequency vs. RFRQ
70
1800
High-Side RDSon(m )
FREQUENCY (kHz)
1600
50
RDSON(m )
18
Figure 11.
High-Side and Low-Side MOSFET RDSon vs. Temperature
60
18
40
30
20
1400
1200
1000
800
600
400
10
200
Low-Side RDSon(m )
0
0
-40
-20
0
20
40
60
TEMPERATURE (°C)
80
100
Figure 12.
-40°C
25°C
125°C
0 20 40 60 80 100 120 140 160 180
RFRQ(k )
Figure 13.
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Typical Performance Characteristics (continued)
Unless otherwise specified: VIN = 12V, VOUT = 3.3V, fS = 500 kHz, TA = 25°C, L = 3.3 µH, COUT = 100 µF ceramic.
Soft-Start, No Load
Soft-Start with Resistive Load
IOUT 1A/DIV
EN 1V/DIV
VOUT 1V/DIV
PGOOD 1V/DIV
PGOOD 1V/DIV
EN 1V/DIV
VOUT
1V/DIV
IOUT 1A/DIV
2 ms/DIV
2 ms/DIV
Figure 14.
Figure 15.
Soft-Start with 2V Pre-Bias Voltage, No Load
Switching Waveform with 0A Load (DCM Operation)
EN 1V/DIV
VOUT 1V/DIV
PGOOD 1V/DIV
IOUT 1A/DIV
2 ms/DIV
8
Figure 16.
Figure 17.
Switching Waveform with 5A Load
Load Transient 0.1A to 5A
Figure 18.
Figure 19.
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BLOCK DIAGRAM
C7
R1
C6
C5
AVIN
2V5
CBOOT
5V0
VIN
LDO1
5V
LDO2
2.5V
PVIN
C1
OTP
ISENSE
UVLO
HS
FET
OCP
C2
SS
Nonoverlap
EN
+
L1
VOUT
EA
REF
PWM
PWM Control Logic
1.2V
PGOOD
Slope
Comp
Input
UVLO
Output
UV, OV
AGND
OVP
SW
Z cross
LS FET OCP
Rev OCP
OTP
C3
Nonoverlap
FB
OSC/
Sync
COMP
FREQ
SYNC
PGND
R1
C5
R4
C4
OPERATION DESCRIPTION
The LM21305 employs peak current-mode control. The 0.598V reference is compared to the feedback signal at
the error amplifier (EA). The PWM modulator block compares the on-time current sense information with the
summation of the EA output (control voltage) and slope compensation. The PWM modulator outputs on/off
signals to the high-side and low-side MOSFET drivers. Adaptive dead-time control is applied to the PWM output
such that shoot through current is avoided. The drivers then amplify the PWM signals to control the integrated
high-side and low-side MOSFETs.
SWITCHING REGULATOR
The LM21305 employs a buck type (step-down) converter architecture. It utilizes many advanced features to
achieve excellent voltage regulation and efficiency. This easy-to-use regulator features two integrated switches
and is capable of supplying up to 5A of continuous output current. The regulator utilizes peak current-mode
control with slope compensation scaled with switching frequency to optimize stability and transient response over
the entire output voltage and switching frequency ranges. Peak current-mode control also provides inherent line
feed-forward, cycle-by-cycle current limiting, and easy loop compensation. The switching frequency can be
adjusted between 300 kHz and 1.5 MHz. The device can operate with a small external L-C filter and still provide
very low output voltage ripple. The precision internal voltage reference allows the output to be set as low as
0.598V. Using an external compensation circuit, the regulator bandwidth can be selected based on the switching
frequency to provide fast load transient response. The switching regulator is specially designed for high efficiency
operation throughout the load range. Synchronous rectification yields high efficiency for low voltage and heavy
load current situations, while discontinuous conduction and diode emulation modes enable high efficiency
conversion at lighter load currents. Fault protection features include: high-side and low-side switch current
limiting, negative current limiting on the low-side switch, over-voltage protection and thermal shutdown. The
device is available in the WQFN-28 package featuring an exposed pad to aid thermal dissipation. The LM21305
can be used in numerous applications to efficiently step-down from a wide range of input rails: 3V to 18V.
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PEAK CURRENT-MODE CONTROL
In most applications, the peak current-mode control architecture used in the LM21305 only requires two external
components to achieve a stable design. External compensation allows the user to set the crossover frequency
and phase margin, thus optimizing the transient performance of the device. For duty cycles above 50%, all peak
current-mode control buck converters require the addition of an artificial ramp to avoid sub-harmonic oscillation.
This linear ramp is commonly referred to as slope compensation. The amount of slope compensation in the
LM21305 will automatically change depending on the switching frequency: the higher the switching frequency,
the larger the slope compensation. This allows smaller inductors to be used with high switching frequency to
increase the power density.
SWITCHING FREQUENCY SETTING AND SYNCHRONIZATION
The LM21305 switching regulator can operate at a frequency ranging from 300 kHz to 1.5 MHz. The switching
frequency can be set / controlled in two ways. One is by selecting the external resistor attached to the FREQ pin
to set the internal oscillator frequency which controls the switching frequency. An external 100 pF capacitor,
CFRQ, should also be connected from the FREQ pin to analog ground as a noise filter, as shown in Figure 20.
LM21305
CFRQ
FREQ
RFRQ
Figure 20. Switching Frequency set by External Resistor
The other way is to synchronize the switching frequency to an external clock in the range of 300 kHz to 1.5 MHz.
The external clock should be applied through a 100 pF coupling capacitor, CFRQ, as shown in Figure 21.
LM21305
CFRQ
FREQ
External
Clock
RFRQ
Figure 21. Switching Frequency Synchronized to External Clock
The recommendations for the external clock include peak-to-peak voltage above 1.5V, duty cycle between 20%
and 80%, and the edge rate faster than 100 ns. Circuits that use an external clock should still have a resistor
connected from the FREQ pin to analog ground. The external clock frequency should be within -10% to +50% of
the frequency set by RFRQ. This allows the regulator to continue operating at approximately the same switching
frequency if the external clock fails and the coupling capacitor on the clock side is grounded or pulled to logic
high.
If the external clock fails low, timeout circuits will prevent the high-side FET from staying off for longer than 1.5
times the switching period (switching period Ts = 1/fs). At the end of this timeout period, the regulator will begin to
switch at the frequency set by RFRQ.
If the external clock fails high, timeout circuits will again prevent the high-side FET from staying off longer than
1.5 times the switching period. After this timeout period, the internal oscillator takes over and switches at a fixed
1 MHz until the voltage on the FREQ pin has decayed to approximately 0.6V. This decay follows the time
constant of CFRQ and RFRQ, and once it is complete the regulator will switch at the frequency set by RFRQ.
LIGHT-LOAD OPERATION
The LM21305 offers increased efficiency at light loads by allowing Discontinuous Conduction Mode (DCM).
When the load current is less than half of the inductor ripple current, the device will enter DCM thus preventing
negative inductor current. The current at which this occurs is the critical conduction boundary and can be
calculated according to the following equation:
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IBOUNDARY =
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VOUT (1 -D)
2LfS
(1)
Switchnode Voltage
where D is the duty cycle of the high-side switch, equal to the high-side switch on-time divided by the switching
period. For more details, please refer to the CALCULATING THE DUTY CYCLE section in the Design Guide
provided later. Several diagrams are shown in Figure 22 illustrating continuous conduction mode (CCM),
Discontinuous Conduction Mode (DCM), and the boundary condition. It can be seen that in DCM, whenever the
inductor current reaches zero, the SW node will become high impedance. Ringing will occur on this pin as a
result of the LC tank circuit formed by the inductor and the effective parasitic capacitance at the switch node. At
very light loads, usually below 100 mA, several pulses may be skipped in between switching cycles, effectively
reducing the switching frequency and further improving light-load efficiency.
Continuous Conduction Mode (CCM)
VIN
Time (s)
Inductor Current
Continuous Conduction Mode (CCM)
IAVERAGE
Inductor Current
Time (s)
DCM - CCM Boundary
IAVERAGE
Switchnode Voltage
Time (s)
Discontinuous Conduction Mode (DCM)
VIN
Inductor Current
Time (s)
Discontinuous Conduction Mode (DCM)
IPeak
Time (s)
Figure 22. CCM And DCM Operation
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PRECISION ENABLE
The enable (EN) pin allows the output of the device to be enabled or disabled with an external control signal.
This pin is a precision analog input that enables the device when the voltage exceeds 1.2V (typical). The EN pin
has 200 mV (typical) of hysteresis and will disable the output when the enable voltage falls below 1.0V (typical).
If the EN pin is not used, it should be pulled up to AVIN via a 10 kΩ to 100 kΩ resistor. Since the enable pin has
a precise turn-on threshold, it can be used along with an external resistor divider network from an external
voltage to configure the device to turn on at a precise voltage. The precision enable circuitry will remain active
even when the device is disabled. The turn-on voltage with a divider can be found by
§
©
§ REN1
VEN-EXT = 1.2 1 + R
©
EN2
(2)
VEN-EXT
LM21305
REN1
EN
REN2
Figure 23. Use External Resistor To Set The EN Threshold
DEVICE ENABLE, SOFT-START AND PRE-BIAS STARTUP CAPABILITY
The device output can be turned off by removing AVIN or pulling the EN pin low. To enable the device, EN pin
must be high with the presence of AVIN and PVIN. Once enabled, the device engages the internal soft-start. The
soft-start feature allows the regulator output to gradually reach the steady state operating point, thus reducing
stresses on the input supply and controlling startup current. Soft-start begins at the rising edge of EN with AVIN
above UVLO level. It is important to make sure PVIN is high when soft-start begins. The LM21305 allows AVIN
to be higher than PVIN, or PVIN higher than AVIN, as long as both of them are within their operating voltage
ranges.
Soft-start of the LM21305 is controlled internally. It typically takes 2.7 ms to finish the soft-start sequence.
PGOOD will be high after soft-start is finished.
The LM21305 is in a pre-biased state when the device initiates startup with an output voltage greater than zero.
This often occurs in many multi-rail applications such as when powering an FPGA, ASIC, or DSP. In these
applications, the output can be pre-biased through parasitic conduction paths from one supply rail to another.
Even though the LM21305 is a synchronous converter, it will not pull the output low when a pre-bias condition
exists. During startup, the LM21305 will be in diode emulation mode with low-side switch turned off when zero
crossing of the inductor current is detected.
PEAK CURRENT PROTECTION AND NEGATIVE CURRENT LIMITING
The LM21305 switching regulator detects the peak inductor current and limits it to a value of 7A typical. To
determine the average current from the peak current, the inductor size, input and output voltage, and switching
frequency must be known. The average current limit can be found by :
(3)
When the peak inductor current sensed from the high-side switch reaches the current limit threshold, an overcurrent event is triggered and the internal high-side FET turns off and the low-side FET turns on allowing the
inductor current to ramp down until the next switching cycle. When the high-side over-current condition persists,
the output voltage will be reduced by the reduced high-side switch on-time.
In cases such as output short circuit or when high-side switch minimum on-time conditions are reached, the highside switch current limiting may not be sufficient to limit the inductor current. The LM21305 features an additional
low-side switch current limit to prevent the inductor current from running away. The low-side switch current limit is
set higher than the high-side current limit, 8A typical. When the low-side switch current is higher than the limit
level, PWM pulses will be skipped until the low-side over-current event is not detected during the entire low-side
switch conduction time. Normal PWM switching subsequently occurs when the condition is removed. High-side
and low-side current protections result in a current limit that does not aggressively foldback for brief over-current
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events, while at the same time providing frequency and voltage foldback protection during hard short circuit
conditions. The low-side switch also has negative current limit (-4.1A typical) for secondary protection, and this
can engage duing response to over-voltage events. If the negative current limit is triggered, the low-side switch
will be turned off. The negative current will be forced to go through the high-side switch body diode and will
quickly reduce.
PGOOD AND OVER- / UNDER-VOLTAGE HANDLING
PGOOD should be pulled high with an external resistor (10kΩ to 100kΩ recommended). When the FB voltage is
typically within -7% to +9.5% of the reference voltage, PGOOD will be high. Otherwise, an internal open-drain
pull-down device will pull PGOOD low. PGOOD should be tied to ground if the function is not required.
The LM21305 has built-in under- and over-voltage comparators that control the power switches. Whenever there
is an excursion in output voltage above the set OVP threshold, the device will terminate the present on-pulse,
turn on the low-side FET, and pull PGOOD low. The low-side FET will remain on until either the FB voltage falls
back into regulation or the inductor current zero-cross is detected which in turn tri-states the FETs. If the output
reaches the UVP threshold, the part will continue switching and PGOOD will be asserted and go low. To avoid
false tripping during transient glitches, PGOOD has 16 μs of built-in deglitch time to both rising and falling edges.
OVP is disabled during soft-start to prevent false triggering.
UVLO
The LM21305 has a built-in under-voltage lockout (UVLO) protection circuit that prevents the device from
switching until the AVIN voltage reaches 2.93V (typical). The UVLO threshold has typically 190 mV of hysteresis
that keeps the device from responding to power-on glitches during startup.
INTERNAL REGULATORS
The LM21305 contains two internal low dropout (LDO) regulators to produce internal driving and bias voltage
rails from AVIN. One LDO produces 5V to power the internal MOSFET drivers, the other produces 2.5V to power
the internal bias circuitry. Both the 5V0 or 2V5 LDOs should be bypassed to analog ground (AGND) with an
external ceramic capacitor (1 μF and 0.1 μF recommended, respectively). Good bypassing is necessary to
supply the high transient currents required by the power MOSFET gate drivers. Applications with high input
voltage and high switching frequency will increase die temperature because of the higher power dissipation
within the LDOs. Connecting a load to the 5V0 or 2V5 pins is not recommended since it will degrade their driving
capability to internal circuitry, further pushing the LDOs into their RMS current ratings and increasing power
dissipation and die temperature.
The LM21305 allows AVIN to be as low as 3V which makes the voltage at the 5V0 LDO lower than 5V. Low
supply voltage at the MOSFET drivers can increase on-time resistance of the high-side and low-side MOSFETs
and reduce efficiency of the regulator. When AVIN is between 3V and 5.5V, the best practice is to short the 5V0
pin to AVIN to avoid the voltage drop on the internal LDO. However, the device can be damaged if the 5V0 pin is
pulled to a voltage higher than 5.5V. For efficiency considerations, it is best to use AVIN = 5V if possible. When
AVIN is above 5V, reduced efficiency can be observed at light load due to the power loss of the LDOs. When
AVIN is close to 3V, increased MOSFET on-state resistance can reduce efficiency at high load current levels.
MINIMUM ON-TIME CONSIDERATIONS
Minimum on-time, TON-MIN, is the smallest duration of time that the high-side MOSFET can be on. This time is
typically 70 ns in the LM21305. In CCM operation, the minimum on-time limit imposes a minimum duty cycle of
DMIN = fS x TON-MIN
(4)
For a given output voltage, minimum on-time imposes limits on the switching regulator when operating
simultaneously at high input voltage and high switching frequency. As the equation shows, reducing the
operating frequency will alleviate the minimum duty cycle constraint. With a given switching frequency and
desired output voltage, the maximum allowed PVIN can be approximated by
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VPVIN-max =
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1
VOUT
x
fS
TON-MIN
(5)
Similarly, if the PVIN input rail is fixed, the maximum switching frequency without imposing minimum on-time can
be found by:
fs-max =
1
VOUT
x
VPVIN-max TON-MIN
(6)
In rare cases where steady-state operation at minimum duty cycle is unavoidable, the regulator will automatically
skip cycles to keep VOUT regulated, similar to light-load DCM operation.
THERMAL PROTECTION
Internal thermal shutdown circuitry is provided to protect the integrated circuit in the event that the maximum
junction temperature is exceeded. When activated, typically at 160°C, the LM21305 tri-states the power
MOSFETs and resets soft-start. After the junction temperature cools to approximately 150°C, the LM21305 starts
up using the normal startup routine. This feature is provided to prevent catastrophic failures from due to device
overheating.
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DESIGN GUIDE
This section walks the designer through the steps necessary to select the external components to build a fully
functional efficient step-down power supply. As with any DC-DC converter, numerous tradeoffs are possible to
optimize the design for efficiency, size, and performance. These will be taken into account and highlighted
throughout this discussion. To facilitate component selection discussions, the typical application circuit shown
below may be used as a reference. Unless otherwise indicated, all formulae assume units of Amps (A) for
current, Farads (F) for capacitance, Henries (H) for inductance, Volts (V) for voltages and Hertz (Hz) for
frequencies.
VIN
PVIN
CIN1
CIN2
CBOOT
CBOOT
CIN3
VOUT
L
SW
RF
AVIN
RFB1
CF
FB
REN
LM21305
EN
C2V5
0.598V
COUT1 COUT2
RFB2
Cc1
2V5
Rc
COMP
5V0
RPG
C5V0
CFRQ
FREQ
PGOOD
AGND PGND
RFRQ
Figure 24. LM21305 Typical Application Circuit
SETTING THE OUTPUT VOLTAGE
The FB pin of the LM21305 can be connected to VOUT directly or through a resistor divider. With an external
resistor divider, the output voltage can be scaled up from the 0.598V feedback voltage. Figure 25 shows the
connection of the divider and the FB pin.
VOUT
LM21305
RFB1
FB
RFB2
Figure 25. Setting the Output Voltage by Resistor Divider
The output voltage can be found by:
(7)
For example, if the desired output voltage is 1.2V, RFB1 = 10 kΩ and RFB2 = 10 kΩ can be used.
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CALCULATING THE DUTY CYCLE
The first equation to calculate for any buck converter is duty cycle. In an ideal (no loss) buck converter, the duty
cycle can be found by:
§ VOUT
©VPVIN
§
©
Dideal =
(8)
In applications with low output voltage (<1.2V) and high load current (> 3A), the losses should not be ignored
when calculation the duty cycle. Considering the effect of conduction losses associated with the MOSFETs and
inductor, the duty cycle can be approximated by:
(9)
RDSonHS and RDSonLS are the on-state parasitic resistances of the high-side and low-side MOSFETs, respectively.
Rdcr is the equivalent DC resistance of the inductor used in the output filter. Other parasitics, such as PCB trace
resistance, can be included if desired. IOUT is the load current. It is also equal to the average inductor current.
The duty cycle will increase slightly with increase of load current.
SUPPLY POWER AND INPUT CAPACITORS
PVIN is the supply voltage for the switcher power stage. It is the input source that delivers the output power to
the load. The input capacitors on the PVIN rail supply the large AC switching current drawn by the switching
action of the internal power MOSFETs. The input current of a buck converter is discontinuous and the ripple
current supplied by the input capacitor can be quite large. The input capacitor must be rated to handle this
current. To prevent large voltage transients, a low ESR input capacitor sized for the maximum RMS current
should be used. The maximum RMS current is given by:
IRMS_CIN = IOUT
VOUT (VPVIN - VOUT)
(A)
VPVIN
(10)
I2RMS_CIN
The power dissipation of the input capacitor is given by: PD_CIN =
RESR_CIN(W) where RESR_CIN is the
ESR of the input capacitor. This equation has a maximum at PVIN = 2VOUT, where IRMS_CIN ≅ IOUT/2 and D ≅
50%. This simple worst-case condition is commonly used for design purposes because even significant
deviations from the worst case duty cycle operating point do not offer much relief. Note that ripple current ratings
from capacitor manufacturers are often based on only 2000 hours of life which makes it advisable to further
derate the capacitor, or choose a capacitor rated at a higher temperature than required. Several capacitors may
also be paralleled to meet size or height requirements in the design. For low input voltage applications, sufficient
bulk input capacitance is needed to minimize transient effects during output load current changes. A 1 µF
ceramic bypass capacitor is also recommended directly adjacent the IC between the PVIN and PGND pins.
Please refer to Figure 33 and the PCB LAYOUT CONSIDERATIONS section provided later in this document.
AVIN FILTER
An RC filter should be added to prevent any switching noise on PVIN from interfering with the internal analog
circuitry connected to AVIN. These can be seen on the schematic as components RF and CF. There is a practical
limit to the size of resistor RF as the AVIN pin will draw a short 60 mA burst of current during startup and if RF is
too large the resulting voltage drop can trigger the UVLO comparator. A recommended 1 μF capacitor coupled
with a 1Ω resistor provides approximately 10 dB of attenuation at 500 kHz switching frequency.
SWITCHING FREQUENCY SELECTION
The LM21305 supports a wide range of switching frequencies: 300 kHz to 1.5 MHz. The choice of switching
frequency is usually a compromise between conversion efficiency and the size of the circuit. Lower switching
frequency implies reduced switching losses (including gate charge losses, switch transition losses, etc.) and
usually results in higher overall efficiency. But higher switching frequency allows use of smaller LC output filters
and hence a more compact design. Lower inductance also helps transient response (higher large-signal slew
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rate of inductor current) and reduces the DCR losses. The optimal switching frequency is usually a tradeoff in a
given application and thus needs to be determined on a case-by-case basis. It is related to the input voltage,
output voltage, most common load current level, external component choices, and circuit size requirements. The
choice of switching frequency may also be limited if an operating condition triggers TON-MIN or TOFF-MIN. Please
refer to the aforementioned MINIMUM ON-TIME CONSIDERATIONS section.
The following equation or Figure 26 can be used to calculate the resistance to obtain a desired frequency of
operation:
fs [kHz] = 31000 x RFRQ-0.9[kΩ]
(11)
1800
1600
FREQUENCY (kHz)
1400
1200
1000
800
600
400
200
0
0
20
40
60
80 100 120 140 160 180
RFRQ (k:)
Figure 26. External Resistor Selection to Set
the Switching Frequency
INDUCTOR
A general recommendation for the filter inductor in an LM21305 application is to keep a peak-to-peak ripple
current between 20% and 40% of the maximum DC load current of 5A. It also should have a sufficiently high
saturation current rating and a DCR as low as possible.
The peak-to-peak current ripple can be calculated by:
V
(1 - D) x VOUT VOUT
(1 - OUT )
|
'iLp-p =
fS x L
fS x L
VPVIN
(12)
It is recommended to choose L such that:
(1 ± D) x VOUT
(1 ± D) x VOUT
7L7
fS x 0.4 x IL(MAX)
fS x 0.2 x IL(MAX)
(13)
The inductor should be rated to handle the maximum load current plus the ripple current:
IL(MAX) = ILOAD(MAX) + ΔiL(MAX)/2
(14)
An inductor with saturation current higher than the over-current protection limit is a safe choice. In general, it is
desirable to have lower inductance in switching power supplies, because it usually corresponds to faster
transient response, smaller DCR, and reduced size for more compact designs. But too low of an inductance can
generate too large of an inductor ripple current such that over-current protection at the full load could be falsely
triggered. It also generates more conduction loss, since the RMS inductor current is slightly higher relative to that
with lower current ripple at the same DC current. Larger inductor ripple current also implies larger output voltage
ripple with the same output capacitors. With peak current-mode control, it is recommended to not have too small
of an inductor current ripple so that the peak current comparator has enough signal-to-noise ratio.
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Once the inductance is determined, the type of inductor must be selected. Ferrite designs have very low core
losses and are preferred at high switching frequencies, so design goals can concentrate on copper loss and
preventing saturation. Ferrite core material saturates hard, which means that inductance collapses abruptly when
the saturation current is exceeded. The ‘hard’ saturation results in an abrupt increase in inductor ripple current
and consequent output voltage ripple. Do not allow the core to saturate!
OUTPUT CAPACITOR
The device is designed to be used with a wide variety of LC filters. It is generally desirable to use as little output
capacitance as possible to keep cost and size down. The output capacitor(s), COUT, should be chosen with care
since it directly affects the steady state output voltage ripple, loop stability and the voltage over/undershoot
during a load current transient.
The output voltage ripple is essentially composed of two parts. One is caused by the inductor current ripple going
through the equivalent series resistance (ESR) of the output capacitors: ΔVOUT-ESR = ΔiLp-p * ESR.
The other is caused by the inductor current ripple charging and discharging the output capacitors:
'iLp-p
üVOUT-C =
8fSCOUT
(15)
Figure 27 shows an illustration of the two ripple components. Since the two ripple components are not in phase,
the actual peak-to-peak ripple is smaller than the sum of the two peaks:
üVOUT <'iLp-p x (
1
+ ESR)
8fSCOUT
(16)
IL
üiLpp
üvout-
time
ESR
time
üvout-C
time
Figure 27. Two Components of VOUT Ripple
Output capacitance is usually limited by system transient performance specifications if the system requires tight
voltage regulation with presence of large current steps and fast slew rates. When a fast large load transient
occurs, output capacitors provide the required charge before the inductor current can slew to the appropriate
level. The initial output voltage step is equal to the load current step multiplied by the ESR. VOUT continues to
droop until the control loop response increases or decreases the inductor current to supply the load. To maintain
a small over- or undershoot during a transient, small ESR and large capacitance are desired. But these also
come with the penalty of higher cost and size. Thus, the motivation is to seek a fast control loop response to
reduce the output voltage deviation.
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One or more ceramic capacitors are generally recommended because they have very low ESR and remain
capacitive up to high frequencies. The capacitor dielectric should be X5R or X7R to maintain proper tolerance.
Other types of capacitors also can be used, particularly if large bulk capacitance is needed (such as tantalum,
POSCAP and OSCON). Such electrolytic capacitors have lower ESR zero {1/(2πESR *COUT} frequency than
ceramic capacitors. The lower ESR zero frequency can influence the control loop, particularly if it occurs close to
the desired crossover frequency. If high switching frequency and high loop crossover frequency are warranted,
an all ceramic design can be more appropriate.
EFFICIENCY CONSIDERATIONS
The efficiency of a switching regulator is defined as the output power divided by the input power times 100%.
Efficiency also can be found by:
Total Power Loss
= 1 Input Power
(17)
It is often useful to analyze individual losses to determine what is limiting the efficiency and what change would
produce the most improvement. Although all dissipative elements in the circuit produce losses, three main
sources usually account for most of the losses in LM21305-based converters: 1) conduction losses; 2) switching
and gate drive losses; 3) bias losses. Conduction losses are the I2R losses in parasitic resistances including onstate resistances of the internal switches RDSon, equivalent inductor DC resistance Rdcr, and PC board trace
resistances Rtrace. The conduction loss can be approximated by:
(18)
The total conduction loss can be reduced by reducing these parasitic resistances. For example, the LM21305 is
designed to have low RDSon internal MOSFET switches. The inductor DCR should be small. The traces that
conduct the current should be wide, thick and as short as possible. Obviously, the conduction losses affect the
efficiency more at heavier load.
Switching losses include all the losses generated by the switching action of the two power MOSFETs. Each time
the switch node swings from low to high or vice versa, charges are applied or removed from the parasitic
capacitance from the SW node to GND. Each time a power MOSFET gate is switched from low to high to low
again, a packet of charge moves from 5V0 to ground. Furthermore, each time a power MOSFET is turned on or
off, a transition loss is generated related to the overlap of voltage and current. MOSFET parasitic diodes
generate reverse recovery loss and dead time conduction loss. RMS currents through the input and output
capacitor ESR also generate loss. All of these losses should be evaluated and carefully considered to design a
high efficiency switching power converter. Since these losses only occur during ‘switching’, reducing the
switching frequency always helps to reduce the switching loss and the resultant improvement in efficiency is
more pronounced at lighter load.
Since the 5V0 rail is an LDO output from AVIN, the current drawn from AVIN is the same as iDrive and the
associated power loss is VAVIN * iDrive. The other portion of AVIN power loss is the bias current through the 2V5
rail which equals VAVIN* ibias. Powering AVIN from a 5V system rail provides an optimal tradeoff between bias
power loss and switching loss.
LOAD CURRENT DERATING WHEH DUTY CYCLE EXCEEDS 50%
The LM21305 is optimized for lower duty cycle operation, e.g. high input to output voltage ratio. The high-side
MOSFET is designed to be half the size of the low-side MOSFET thus optimizing the relative levels of switching
loss in the high-side switch and the conduction loss in the low-side switch. The continuous current rating of the
low-side switch is the maximum load current of 5A, while the high-side MOSFET is rated at 2.5A. If the LM21305
is operating with duty cycles higher than 50%, the maximum output current should be derated.
(19)
Derating of maximum load current when D > 50% is also illustrated in Figure 28.
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IOUT-MAX
5.0A
2.5A
0
50%
100%
D
Figure 28. LM21305 Maximum Load Current Derating when D > 50%
CONTROL LOOP COMPENSATION
VREF +
VOUT(s)
VC(s) +
Compensator
Fcomp(s)
-
Fp(s) x Fh(s)
Power Stage
Loop T(s)
H(s)
Feedback
Figure 29. Control Block Diagram of a Peak Current-Mode Controlled Buck Converter
This section will not provide a rigorous analysis of current-mode control, but rather a simplified yet relatively
accurate method to determine the control loop compensation network. The LM21305 employs a peak currentmode controller and therefore the control loop block diagram representation involves two feedback loops (see
Figure 29). The inner feedback loop derives its feedback from the sensed inductor current while the outer loop
monitors the output voltage. The LM21305 compensation components from COMP to AGND are shown in
Figure 30. The purpose of the compensator block is to stabilize the control loop and achieve high performance in
terms of the load transient response, audio susceptibility and output impedance. The LM21305 will typically
require only a single resistor Rc and capacitor Cc1 for compensation. However, depending on the location of the
power stage ESR zero, a second (small) capacitor, Cc2, may be required to create a high frequency pole.
LM21305
COMP
RC
CC1
Figure 30. LM21305 Compensation Network
The overall loop transfer function is a product of the power stage transfer function, internal amplifier gains and
the feedback network transfer function and can be expressed by:
T(s) = Gain0Fp(s)Fh(s)Fcomp(s)
where Gain0 includes all the DC gains in the loop, Fp(s) represents the power stage pole and zero (including the
inner current loop), Fh(s) represents the sampling effect in such a current-mode converter and Fcomp(s) is the
transfer function of the external compensator. Figure 31 shows an asymptotic approximation plot of the loop gain.
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Gain0/sCc1
fp
fzcomp
fc
0 dB
fs/2
fESR
(fpcomp)
Figure 31. LM21305 Loop Gain Asymptotic Approximation
The loop gain determines both static and dynamic performance of the converter. The power stage response is
fixed by the selection of the power components and the compensator is therefore designed around the power
stage response to achieve the desired loop response. The goal is to design a control loop characteristic with high
crossover frequency (or loop bandwidth) and adequate gain and phase margins under all operation conditions.
COMPENSATION COMPONENTS SELECTION
To select the compensation components, a desired crossover frequency needs to be selected. It is
recommended to select fc equal to or lower than 1/6 of the switching frequency. The effect of Fh(s) can be
ignored to simplify the design. The capacitor ESR zero is also assumed to be at least 3 times higher than fc. The
compensation resistor can be found by:
(20)
Cc1 does not affect the crossover frequency fc, but it sets the compensator zero fZcomp and affects the phase
margin of the loop. For a fast design, Cc1 = 4.7 nF gives adequate performance in most LM21305 applications.
Larger Cc1 capacitance gives higher phase margin but at the expense of longer transient response settling time.
It is recommended to set the compensation zero no higher than fc/3 to ensure enough phase margin, implying:
Cc1 8
3
2SRcfc
(21)
PLOTTING THE LOOP GAIN
To include the effect of Fh(s) and the ESR zero, the complete loop gain can be plotted using a software tool such
as MATLAB, Mathcad, or Excel. The components in the loop gain can be determined as follows. The DC gain of
the power stage can be found by:
(22)
where fs is the switching frequency,
mc = 1 +
4 x fS x L
VIN - VOUT
(23)
and D' = 1 − D.
Minimum ROUT should be used in the calculation ROUT = VOUT/IOUT. Fp(s) can be expressed by:
(24)
where the power stage pole considering the slope compensation effect is:
1
fp = 2SC
(
OUT
1
1
+
(mcD' - 0.5))
ROUT fs L
(25)
The high frequency behavior Fh(s) can be expressed by:
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LM21305
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Fh (s) =
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1
s2
s
+
1+
wn Qp wn2
(26)
where:
wn = Sfs
and
Qp =
1
S(mcD' ± 0.5)
(27)
The compensator network transfer function is:
(28)
With the above equations, the loop gain T(s) can be plotted and more accurate loop performance metrics
(crossover frequency and phase margin) can be determined.
HIGH FREQUENCY CONSIDERATIONS
Fh(s) represents the additional magnitude and phase drop around fs/2 caused by the switching behavior of the
current-mode converter. Fh(s) contains a pair of double poles with quality factor Qp at half of the switching
frequency. It is a good idea to check that Qp is between 0.15 and 2, ideally around 0.6. If Qp is too high, the
resonant peaking at fs/2 could become severe and coincide with subharmonic oscillations in the duty cycle and
inductor current. If Qp is too low, the two complex poles split, the converter begins to act like a voltage-mode
controlled converter and the compensation scheme used above should be changed.
Fp(s) also contains the ESR zero of the output capacitors:
1
fESR =
2SCOUTESR
(29)
In a typical ceramic capacitor design, fESR is at least three times higher than the desired crossover frequency fc. If
fESR is lower than fs/2, an additional capacitor Cc2 can be added between the COMP pin and AGND to give a
high-frequency pole:
1
Cc2 =
2SRc fESR
(30)
Cc2 should be much smaller than Cc1 to avoid affecting the compensation zero.
BOOTSTRAP CAPACITOR
A capacitor is needed between the CBOOT pin and the SW node to supply the gate drive charge when the highside switch is turning ON. The capacitor should be large enough to supply the charge without significant voltage
drop. A 0.1 µF ceramic bootstrap capacitor is recommended in LM21305 applications.
5V0 AND 2V5 CAPACITORS
5V0 and 2V5 pins are internal LDO outputs. As previously mentioned, the two LDOs are used for internal circuits
only and should not be substantially loaded. Output capacitors are needed to stabilize the LDOs. Ceramic
capacitors within a specified range should be used to meet stability requirements. The dielectric should be X5R,
X7R, or better and rated for the required operating temperature range. Use the following table to choose a
suitable LDO output capacitor:
Output Voltage NOMINAL
22
Capacitance (Recommended Value and Minimum Voltage Rating)
5V0
4.88V
1 µF ± 20% 16V
2V5
2.47V
0.1 µF ± 20% 10V
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PCB LAYOUT CONSIDERATIONS
PC board layout is an important and critical part of any DC-DC converter design. Poor PC board layout can
disrupt the performance of a DC-DC converter and surrounding circuitry by contributing to EMI, ground bounce,
resistive voltage loss in the traces, and thermal problems. Erroneous signals can reach the DC-DC converter,
possibly resulting in poor regulation or instability.
Good PCB layout with an LM21305-based converter can be implemented by following a few simple design rules.
1. Provide adequate device heat sinking by utilizing the PCB ground planes as the primary thermal path. As
such, the use of thermal vias facilitates the transfer of heat from the LM21305 into the system board. Use at
least a 4-layer PCB with the copper thickness for the four layers, starting from the top layer, of 2
oz/1oz/1oz/2 oz. Use a 3 by 3 array of 10mil thermal vias to connect the DAP to the system ground plane
heat sink. The vias should be evenly distributed under the DAP. The system ground planes should
predominately be PGND planes (representing input and output capacitor return paths, input and output DC
current return paths, etc.).
2. It is imperative that the input capacitors are located as close as possible to the PVIN and PGND pins; the
inductor should be placed as close as possible to the SW pins and output capacitors. This is to minimize the
area of switching current loops and reduce the resistive loss of the high current path. Based the LM21305
pinout, a 1 µF to 10 µF ceramic capacitor can be placed right by pins 1, 2 and pin 7, across the SW node
trace, as an addition to the bulk input capacitors. Using a size 1206 or 1210 capacitor allows enough copper
width for the switch node to be routed underneath the capacitor for good conduction (see LM21305
evaluation board layout detailed in Application Note AN-2042 (literature number SNVA432)).
3. The copper area of the switch node should be thick and short to both provide a good conduction path for the
switch node current to the inductor and to minimize radiated EMI. This also requires the inductor be placed
as close as possible to the SW pins.
4. The feedback trace from VOUT to the feedback divider resistors should be routed away from the SW pin and
inductor to avoid contaminating this feedback signal with switch noise. This is most important when high
resistances are used to set the output voltage. It is recommended to route the feedback trace on a different
layer than the inductor and SW node trace such that a ground plane exists between the feedback trace and
inductor/SW node polygon. This provides further cancellation of EMI on the feedback trace.
5. If voltage accuracy at the load is important, make sure feedback voltage sense is made directly at the load
terminals. Doing so will correct for voltage drops in the PCB planes and traces and provide optimal output
voltage setpoint accuracy and load regulation. It is always better to place the resistor divider closer to the FB
node, rather than close to the load, as the FB node is the input to the error amplifier and is thus noise
sensitive. COMP is also a noise sensitive node and the compensation components should be located as
close as possible to the IC.
6. Make input and output power bus connections as wide and short as possible. This reduces any voltage
drops on the input or output of the converter and can improve efficiency. Use copper plates/planes on top to
connect the multiple PVIN pins and PGND pins together.
7. The 0.1 µF boot capacitor connected between the CBOOT pin and SW node should be placed as close as
possible to the CBOOT and SW pins.
8. The frequency set resistor and its associated capacitor should be placed as close as possible to the FREQ
pin.
Thermal Considerations
The thermal characteristics of the LM21305 are specified using the parameter θJA, which relates junction
temperature to ambient temperature in a particular LM21305 application. Although the value of θJA is dependent
on many variables, it still can be used to approximate the operating junction temperature of the device.
To obtain an estimate of the device junction temperature, one may use the following relationship: TJ = PDθJA + TA
where
PD =
PIN x (1 − Efficiency) − 1.1 x IOUT2x Rdcr
TJ =
Junction temperature of the LM21305 in °C
PIN =
Input power in Watts (PIN = VIN x IIN)
θJA =
Junction-to-ambient thermal resistance of the LM21305 in °C/W
TA =
Ambient temperature in °C
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LM21305
SNVS639F – DECEMBER 2009 – REVISED MARCH 2013
IOUT =
Output (load) current
Rdcr =
Inductor parasitic DC resistance
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It is important to always keep the LM21305 operating junction temperature (TJ) below 125°C to assure reliable
operation. If the junction temperature exceeds 160°C, the device will cycle in and out of thermal shutdown. If
thermal shutdown occurs, it is a sign of inadequate heat-sinking and/or excessive power dissipation in the
device. PC board heat-sinking can be improved by using more thermal vias, a larger board, or more heatspreading layers within that board.
24
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SNVS639F – DECEMBER 2009 – REVISED MARCH 2013
Application Circuit Example
VIN = 12V
PVIN
CIN1
CIN2
CBOOT
CBOOT
CIN3
VOUT
L
SW
RF
AVIN
REN
RFB1
CF
LM21305
EN
RFB2
Rc
Cc
2V5
COMP
C2V5
RPG
COUT1 COUT2
FB
5V0
C5V0
CFRQ
FREQ
PGOOD
AGND PGND
RFRQ
Figure 32. LM21305 Application Circuit Example
Table 1. Bill Of Materials (500kHz Switching Frequency)
VOUT
1.2V
1.8V
2.5V
3.3V
5V
Package
CIN1
TANT 47 µF 25V
TANT 47 µF 25V
TANT 47 µF 25V
TANT 47 µF 25V
TANT 47 µF 25V
CASE D
CIN2
10 µF 25V
10 µF 25V
10 µF 25V
10 µF 25V
10 µF 25V
1210
CIN3
1.0 µF 25V
1.0 µF 25V
1.0 µF 25V
1.0 µF 25V
1.0 µF 25V
1206
CF
1.0 µF 25V
1.0 µF 25V
1.0 µF 25V
1.0 µF 25V
1.0 µF 25V
0603
C2V5, CBOOT
0.1 µF 16V
0.1 µF 16V
0.1 µF 16V
0.1 µF 16V
0.1 µF 16V
0603
C5V0
1.0 µF 16V
1.0 µF 16V
1.0 µF 16V
1.0 µF 16V
1.0 µF 16V
0603
CFRQ
100 pF 50V
100 pF 50V
100 pF 50V
100 pF 50V
100 pF 50V
0603
Cc
3300 pF 25V
3300 pF 25V
4700 pF 25V
4700 pF 25V
4700 pF 25V
0603
COUT1,
COUT2
47 µF 6.3V X5R
47 µF 6.3V X5R
47 µF 6.3V X5R
47 µF 10V X5R
47 µF 10V X5R
1210
L
1.5 µH 10A
2.2 µH 10A
2.2 µH 10A
3.3 µH 10A
3.3 µH 10A
SMD
RF
1Ω 1%
1Ω 1%
1Ω 1%
1Ω 1%
1Ω 1%
0603
RFRQ, RPG
100 kΩ 1%
100 kΩ 1%
100 kΩ 1%
100 kΩ 1%
100 kΩ 1%
0603
RFB2, REN
10 kΩ 1%
10 kΩ 1%
10 kΩ 1%
10 kΩ 1%
10 kΩ 1%
0603
Rc
3.32 kΩ 1%
4.22 kΩ 1%
5.10 kΩ 1%
7.15 kΩ 1%
8.2 kΩ 1%
0603
RFB1
10 kΩ 1%
20 kΩ 1%
31.6 kΩ 1%
45.3 kΩ 1%
73.2 kΩ 1%
0603
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LM21305
SNVS639F – DECEMBER 2009 – REVISED MARCH 2013
www.ti.com
PCB Layout
Figure 33. PCB Top Layer Copper and Silkscreen
An example of an LM21305 PCB layout is shown in Figure 33. Only the top layer copper and top silkscreen are
shown. For more details, please refer to Application Note AN-2042 (literature number SNVA432).
26
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SNVS639F – DECEMBER 2009 – REVISED MARCH 2013
REVISION HISTORY
Changes from Revision E (March 2013) to Revision F
•
Page
Changed layout of National Data Sheet to TI format .......................................................................................................... 26
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PACKAGE OPTION ADDENDUM
www.ti.com
27-Mar-2014
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
LM21305SQ/NOPB
ACTIVE
WQFN
RSG
28
1000
Green (RoHS
& no Sb/Br)
CU SN
Level-2A-260C-4
WEEK
-40 to 85
21305SQ
LM21305SQE/NOPB
ACTIVE
WQFN
RSG
28
250
Green (RoHS
& no Sb/Br)
CU SN
Level-2A-260C-4
WEEK
-40 to 85
21305SQ
LM21305SQX/NOPB
ACTIVE
WQFN
RSG
28
4500
Green (RoHS
& no Sb/Br)
CU SN
Level-2A-260C-4
WEEK
-40 to 85
21305SQ
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
27-Mar-2014
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
8-Apr-2013
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
LM21305SQ/NOPB
WQFN
RSG
28
LM21305SQE/NOPB
WQFN
RSG
LM21305SQX/NOPB
WQFN
RSG
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
1000
178.0
12.4
5.3
5.3
1.3
8.0
12.0
Q1
28
250
178.0
12.4
5.3
5.3
1.3
8.0
12.0
Q1
28
4500
330.0
12.4
5.3
5.3
1.3
8.0
12.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
8-Apr-2013
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
LM21305SQ/NOPB
WQFN
RSG
28
1000
213.0
191.0
55.0
LM21305SQE/NOPB
WQFN
RSG
28
250
213.0
191.0
55.0
LM21305SQX/NOPB
WQFN
RSG
28
4500
367.0
367.0
35.0
Pack Materials-Page 2
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