Rail-to-Rail, Very Fast, 2.5 V to 5.5 V, Single-Supply LVDS Comparator AD8465 Fully specified rail to rail at VCCI = 2.5 V to 5.5 V Input common-mode voltage from −0.2 V to VCCI + 0.2 V Low glitch LVDS-compatible output stage Propagation delay: 1.6 ns Power dissipation: 37 mW at 2.5 V Shutdown pin Single-pin control for programmable hysteresis and latch Power supply rejection > 60 dB −40°C to +125°C operation APPLICATIONS High speed instrumentation Clock and data signal restoration Logic level shifting or translation Pulse spectroscopy High speed line receivers Threshold detection Peak and zero-crossing detectors High speed trigger circuitry Pulse-width modulators Current-/voltage-controlled oscillators Automatic test equipment (ATE) Automotive FUNCTIONAL BLOCK DIAGRAM VCCO VCCI VP NONINVERTING INPUT Q OUTPUT AD8465 LVDS Q OUTPUT VN INVERTING INPUT LE/HYS INPUT SDN INPUT 07958-001 FEATURES Figure 1. GENERAL DESCRIPTION The AD8465 is a very fast comparator fabricated on the Analog Devices, Inc., proprietary XFCB2 process. This comparator is exceptionally versatile and easy to use. Features include an input range from VEE − 0.5 V to VCCI + 0.2 V, low noise, LVDScompatible output drivers, and TTL/CMOS latch inputs with adjustable hysteresis and/or shutdown inputs. A flexible power supply scheme allows the devices to operate with a single 2.5 V positive supply and a −0.5 V to +2.7 V input signal range up to a 5.5 V positive supply with a −0.5 V to +5.7 V input signal range. Split input/output supplies, with no sequencing restrictions, support a wide input signal range with greatly reduced power consumption. The device offers 1.6 ns propagation delay with 1 ps rms random jitter (RJ). Overdrive and slew rate dispersion are typically less than 50 ps. The LVDS-compatible output stage is designed to drive any standard LVDS input. The comparator input stage offers robust protection against large input overdrive, and the outputs do not phase reverse when the valid input signal range is exceeded. High speed latch and programmable hysteresis features are also provided in a unique single-pin control option. The AD8465 is available in a 12-lead LFCSP. Rev. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2009 Analog Devices, Inc. All rights reserved. AD8465 TABLE OF CONTENTS Features .............................................................................................. 1 Application Information ................................................................ 10 Applications ....................................................................................... 1 Power/Ground Layout and Bypassing ..................................... 10 Functional Block Diagram .............................................................. 1 LVDS-Compatible Output Stage .............................................. 10 General Description ......................................................................... 1 Using/Disabling the Latch Feature........................................... 10 Revision History ............................................................................... 2 Optimizing Performance........................................................... 10 Specifications..................................................................................... 3 Comparator Propagation Delay Dispersion ........................... 11 Electrical Characteristics ............................................................. 3 Comparator Hysteresis .............................................................. 11 Timing Information ......................................................................... 5 Crossover Bias Points ................................................................. 12 Absolute Maximum Ratings............................................................ 6 Minimum Input Slew Rate Requirement ................................ 12 Thermal Resistance ...................................................................... 6 Typical Application Circuits ......................................................... 13 ESD Caution .................................................................................. 6 Outline Dimensions ....................................................................... 14 Pin Configuration and Function Descriptions ............................. 7 Ordering Guide .......................................................................... 14 Typical Performance Characteristics ............................................. 8 REVISION HISTORY 4/09—Revision 0: Initial Version Rev. 0 | Page 2 of 16 AD8465 SPECIFICATIONS ELECTRICAL CHARACTERISTICS VCCI = VCCO = 2.5 V, TA = −40°C to +125°C, typical at TA = 25 °C, unless otherwise noted. Table 1. Parameter DC INPUT CHARACTERISTICS Voltage Range Common-Mode Range Differential Voltage Offset Voltage Bias Current Offset Current Capacitance Resistance, Differential Mode Resistance, Common Mode Active Gain Common-Mode Rejection Ratio Hysteresis LATCH ENABLE PIN CHARACTERISTICS VIH VIL IIH IIL HYSTERESIS MODE AND TIMING Hysteresis Mode Bias Voltage Minimum Resistor Value Hysteresis Current Latch Setup Time Latch Hold Time Latch-to-Output Delay Latch Minimum Pulse Width SHUTDOWN PIN CHARACTERISTICS VIH VIL IIH IIL Sleep Time Wake-Up Time DC OUTPUT CHARACTERISTICS Differential Output Voltage Level ΔVOD Common-Mode Voltage Peak-to-Peak Common-Mode Output Symbol Conditions Min VP, VN VCCI = 2.5 V to 5.5 V VCCI = 2.5 V to 5.5 V VCCI = 2.5 V to 5.5 V −0.5 −0.2 VOS IP, IN −5.0 −5.0 −2.0 ±2 −0.1 V to VCCI −0.5 V to VCCI + 0.5 V 200 100 1 750 370 62 VCCI = 2.5 V, VCCO = 2.5 V, VCM = −0.2 V to +2.7 V VCCI = 2.5 V, VCCO = 5.0 V RHYS = ∞ 50 Hysteresis is shut off Latch mode guaranteed VIH = VCCO + 0.2 V VIL = 0.4 V 2.0 −0.2 −6 −0.1 Current sink −1 μA Hysteresis = 120 mV Hysteresis = 120 mV VOD = 50 mV VOD = 50 mV VOD = 50 mV VOD = 50 mV 1.145 30 −25 Comparator is operating Shutdown guaranteed VIH = VCCO VIL = 0 V 10% output swing VOD = 50 mV, output valid VCCO = 2.5 V to 5.0 V RLOAD = 100 Ω RLOAD = 100 Ω RLOAD = 100 Ω RLOAD = 100 Ω 2.0 −0.2 −6 CP, CN AV CMRR tS tH tPLOH, tPLOL tPL tSD tH VOD VOCI VOC (p-p) Typ Rev. 0 | Page 3 of 16 Max Unit VCCI + 0.2 VCCI + 0.2 VCCI +5.0 +5.0 +2.0 V V V mV μA μA pF kΩ kΩ dB dB 7500 4000 50 dB mV <0.1 +0.4 1.25 VCCO +0.8 +6 +0.1 V V μA mA 1.40 110 −8 V kΩ μA ns ns ns ns VCCO +0.6 +6 −0.1 V V μA mA ns ns 445 50 1.375 50 mV mV V mV −2 2.7 20 24 +0.4 1.4 25 245 1.125 350 AD8465 Parameter AC PERFORMANCE 1 Rise Time/Fall Time Propagation Delay Propagation Delay Skew—Rising to Falling Transition Propagation Delay Skew—Q to Q Overdrive Dispersion Common-Mode Dispersion Input Bandwidth Minimum Pulse Width POWER SUPPLY Input Supply Voltage Range Output Supply Voltage Range Positive Supply Differential Input Section Supply Current Output Section Supply Current Power Dissipation Power Supply Rejection Ratio Shutdown Mode ICCI Shutdown Mode ICCO 1 Symbol Conditions tR, tF tPD 10% to 90% VCCI = VCCO = 2.5 V to 5.0 V, VOD = 50 mV VCCI = VCCO = 2.5 V, VOD = 10 mV VCCI = VCCO = 2.5 V to 5.0 V VCCI = VCCO = 2.5 V to 5.0 V 10 mV < VOD < 125 mV VCM = −0.2 V to VCCI + 0.2 V tPINSKEW PWMIN VCCI VCCO VCCI − VCCO VCCI − VCCO IVCCI IVCCO PD PSRR Min VCCI = VCCO = 2.5 V to 5.0 V, PWOUT = 90% of PWIN Operating Nonoperating VCCI = 2.5 V to 5.5 V VCCO = 2.5 V to 5.0 V VCCI = VCCO = 2.5 V VCCI = VCCO = 5.0 V VCCI = VCCO = 2.5 V to 5.0 V VCCI = VCCO = 2.5 V to 5.0 V VCCI = VCCO = 2.5 V to 5.0 V VIN = 100 mV square input at 50 MHz, VOD = 50 mV, VCM = 1.25 V, VCCI = VCCO = 2.5 V, unless otherwise noted. Rev. 0 | Page 4 of 16 Typ −30 Unit 600 1.6 ps ns 3.0 70 70 1.6 250 500 1.3 ns ps ps ns ps MHz ns 2.5 2.5 −3 −5.0 −50 Max 1.6 15 37 95 −60 0.92 5.5 5.0 +3 +5.0 3.0 23 55 120 1.1 +30 V V V V mA mA mW mW dB mA μA AD8465 TIMING INFORMATION Figure 2 illustrates the AD8465 latch timing relationships. Table 2 provides definitions of the terms shown in Figure 2. 1.1V LATCH ENABLE tS tPL tH DIFFERENTIAL INPUT VOLTAGE VIN VN ± VOS VOD tPDL tPLOH Q OUTPUT 50% tF tPDH tPLOL tR 07958-002 50% Q OUTPUT Figure 2. System Timing Diagram Table 2. Timing Descriptions Symbol tPDH Timing Input-to-Output High Delay tPDL Input-to-Output Low Delay tPLOH Latch Enable-to-Output High Delay tPLOL Latch Enable-to-Output Low Delay tH Minimum Hold Time tPL tS Minimum Latch Enable Pulse Width Minimum Setup Time tR Output Rise Time tF Output Fall Time VOD Voltage Overdrive Description Propagation delay measured from the time the input signal crosses the reference (± the input offset voltage) to the 50% point of an output low-to-high transition. Propagation delay measured from the time the input signal crosses the reference (± the input offset voltage) to the 50% point of an output high-to-low transition. Propagation delay measured from the 50% point of the latch enable signal low-to-high transition to the 50% point of an output low-to-high transition. Propagation delay measured from the 50% point of the latch enable signal high-to-low transition to the 50% point of an output high-to-low transition. Minimum time after the negative transition of the latch enable signal that the input signal must remain unchanged to be acquired and held at the outputs. Minimum time that the latch enable signal must be high to acquire an input signal change. Minimum time before the negative transition of the latch enable signal occurs that an input signal change must be present to be acquired and held at the outputs. Amount of time required to transition from a low-to-high output as measured at the 20% and 80% points. Amount of time required to transition from a high-to-low output as measured at the 20% and 80% points. Difference between the input voltages, VP and VN. Rev. 0 | Page 5 of 16 AD8465 ABSOLUTE MAXIMUM RATINGS Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Table 3. Parameter Supply Voltages Input Supply Voltage (VCCI to GND) Output Supply Voltage (VCCO to GND) Positive Supply Differential (VCCI − VCCO) Input Voltages Input Voltage Differential Input Voltage Maximum Input/Output Current Shutdown Control Pin Applied Voltage (SDN to GND) Maximum Input/Output Current Latch/Hysteresis Control Pin Applied Voltage (LE/HYS to GND) Maximum Input/Output Current Output Current Temperature Operating Temperature Range, Ambient Operating Temperature, Junction Storage Temperature Range Rating −0.5 V to +6.0 V −0.5 V to +6.0 V −6.0 V to +6.0 V −0.5 V to VCCI + 0.5 V ±(VCCI + 0.5 V) ±50 mA THERMAL RESISTANCE −0.5 V to VCCO + 0.5 V ±50 mA Table 4. Thermal Resistance −0.5 V to VCCO + 0.5 V ±50 mA ±50 mA θJA is specified for the worst-case conditions, that is, a device soldered in a circuit board for surface-mount packages. Package Type 12-Lead LFCSP_VQ (CP-12-3) 1 Measurement in still air. ESD CAUTION −40°C to +125°C 150°C −65°C to +150°C Rev. 0 | Page 6 of 16 θJA1 62 Unit °C/W AD8465 10 Q PIN 1 INDICATOR TOP VIEW (Not to Scale) 9 VEE 8 LE/HYS 7 SDN VN 6 VEE 3 VP 4 AD8465 VEE 5 VCCI 2 NOTES 1. FOR BEST THERMAL PERFORMANCE, EXPOSED PAD MUST BE SOLDERED TO THE PCB. 07958-003 VCCO 1 11 VEE 12 Q PIN CONFIGURATION AND FUNCTION DESCRIPTIONS Figure 3. Pin Configuration Table 5. Pin Function Descriptions Pin No. 1 2 3, 5, 9, 11 4 6 7 8 10 Mnemonic VCCO VCCI VEE VP VN SDN LE/HYS Q 12 Q Heat Sink Paddle VEE Description Output Section Supply. Input Section Supply. Negative Supply Voltages. Noninverting Analog Input. Inverting Analog Input. Shutdown. Drive this pin low to shut down the device. Latch/Hysteresis Control. Bias with resistor or current for hysteresis; drive low to latch. Inverting Output. Q is at logic low if the analog voltage at the noninverting input, VP, is greater than the analog voltage at the inverting input, VN, if the comparator is in compare mode. Noninverting Output. Q is at logic high if the analog voltage at the noninverting input, VP, is greater than the analog voltage at the inverting input, VN, if the comparator is in compare mode. The metallic back surface of the package is electrically connected to VEE. It can be left floating because Pin 3, Pin 5, Pin 9, and Pin 11 provide adequate electrical connection. It can also be soldered to the application board if improved thermal and/or mechanical stability is desired. Rev. 0 | Page 7 of 16 AD8465 TYPICAL PERFORMANCE CHARACTERISTICS VCCI = VCCO = 2.5 V, TA = 25°C, unless otherwise noted. 800 1.60 600 1.50 400 1.40 VCC = 5.5V 200 OUTPUT (V) 0 –200 1.30 OUTPUT VCM 1.20 1.10 –400 OUTPUT LOW 1.00 –600 0 1 2 3 4 LE/HYS PIN (V) 5 6 7 0.90 2.4 07958-004 –800 –1 Figure 4. LE/HYS Pin Current vs. Voltage 4.4 3.9 VCCO (V) 5.4 4.9 5.9 Figure 7. LVDS Output Level vs. VCCO 200 850 150 800 750 100 VCC = 2.5V VCC = 5.5V RISE/FALL (ps) CURRENT (µA) 3.4 2.9 07958-007 CURRENT (µA) VCC = 2.5V OUTPUT HIGH 50 0 –50 700 +125°C 650 600 +25°C 550 –40°C 500 –100 0 1 2 3 4 SDN PIN (V) 5 6 7 400 2.40 07958-005 –1 Figure 5. SDN Pin Current vs. Voltage 2.80 3.20 3.60 4.00 4.40 VCCO (V) 4.80 5.20 5.60 6.00 07958-008 450 –150 Figure 8. LVDS Output Rise/Fall Time vs. VCCO 250 10 +125°C 8 +25°C 6 200 –40°C HYSTERESIS (mV) 4 0 –2 –4 150 100 VCC = 2.5V –6 50 –8 VCC = 5.5V –0.5 0.0 0.5 1.0 1.5 2.0 VCM AT VCC = 2.5V (V) 2.5 3.0 3.5 0 50 100 150 200 250 300 350 400 HYSTERESIS RESISTOR (kΩ) Figure 9. Hysteresis vs. Hysteresis Resistor Figure 6. Input Bias Current vs. Input Common-Mode Voltage Rev. 0 | Page 8 of 16 450 500 07958-009 –10 –1.0 07958-006 IB (µA) 2 AD8465 0.44 350 0.43 +125°C 300 0.42 OUTPUT SWING (V) +25°C 200 150 100 0.40 0.39 0.38 –40°C 0 –2 –4 –6 –8 –10 –12 –14 LE/HYS PIN CURRENT (µA) 0.37 –16 –18 0.36 2.4 07958-010 50 0 0.41 Figure 10. Hysteresis vs. LE/HYS Pin Current 3.4 4.4 VCCO (V) 07958-013 HYSTERESIS (mV) 250 5.4 Figure 13. LVDS Output Swing vs. VCCO PROPAGATION DELAY (ns) 3.5 1.425V 3.0 Q 2.5 2.0 PROPAGATION DELAY 1.5 10 20 30 40 50 60 OVERDRIVE (mV) 70 80 90 100 Q 925.0mV Figure 11. Propagation Delay vs. Input Overdrive 1.000ns/DIV 07958-014 0 07958-011 1.0 Figure 14. 50 MHz Output Voltage Waveform at VCCO = 2.5 V 1.543V PROPAGATION DELAY RISE ns Q 1.5 PROPAGATION DELAY FALL ns 1.3 –0.6 –0.2 0.2 0.6 1.0 1.4 1.8 VCM AT VCC = 2.5V (V) 2.2 2.6 3.0 Q 1.043V Figure 12. Propagation Delay vs. Input Common-Mode Voltage 1.000ns/DIV 07958-015 1.4 07958-012 PROPAGATION DELAY (ns) 1.6 Figure 15. 50 MHz Output Voltage Waveform at VCCO = 5.5 V Rev. 0 | Page 9 of 16 AD8465 APPLICATION INFORMATION POWER/GROUND LAYOUT AND BYPASSING LVDS-COMPATIBLE OUTPUT STAGE The AD8465 comparator is a very high speed device. Despite the low noise output stage, it is essential to use proper high speed design techniques to achieve the specified performance. Because the comparator is an uncompensated amplifier, feedback in any phase relationship is likely to cause oscillations or undesired hysteresis. The use of low impedance supply planes is of critical importance particularly with the output supply plane (VCCO) and the ground plane (GND). Individual supply planes are recommended as part of a multilayer board. Providing the lowest inductance return path for switching currents ensures the best possible performance in the target application. Specified propagation delay dispersion performance is only achieved by keeping parasitic capacitive loads at or below the specified minimums. The outputs of the AD8465 are designed to directly drive any standard LVDS-compatible input. It is also important to adequately bypass the input and output supplies. Place multiple high quality 0.01 μF bypass capacitors as close as possible to each of the VCCI and VCCO supply pins and connect the capacitors to the GND plane with redundant vias. Place at least one capacitor to provide a physically short return path for output currents flowing back from ground to the VCCI pin and the VCCO pin. Carefully select high frequency bypass capacitors for minimum inductance and ESR. Parasitic layout inductance should also be strictly controlled to maximize the effectiveness of the bypass at high frequencies. The input and output supplies have been connected separately (VCCI ≠ VCCO); be sure to bypass each of these supplies separately to the GND plane. Do not connect a bypass capacitor between these supplies. It is recommended that the GND plane separate the VCCI and VCCO planes when the circuit board layout is designed to minimize coupling between the two supplies to take advantage of the additional bypass capacitance from each respective supply to the ground plane. This enhances the performance when split input/output supplies are used. If the input and output supplies are connected together for single-supply operation (VCCI = VCCO), coupling between the two supplies is unavoidable; however, careful board placement can help keep output return currents away from the inputs. USING/DISABLING THE LATCH FEATURE The latch input is designed for maximum versatility. It can safely be left floating or it can be driven low by any standard TTL/CMOS device as a high speed latch. In addition, the pin can be operated as a hysteresis control pin with a bias voltage of 1.25 V nominal and an input resistance of approximately 70 kΩ. This allows the comparator hysteresis to be easily controlled by either a resistor or an inexpensive CMOS DAC. Driving this pin high or floating the pin disables all hysteresis. Hysteresis control and latch mode can be used together if an open drain, an open collector, or a three-state driver is connected in parallel to the hysteresis control resistor or current source. Due to the programmable hysteresis feature, the logic threshold of the latch pin is approximately 1.1 V, regardless of VCCO. OPTIMIZING PERFORMANCE As with any high speed comparator, proper design and layout techniques are essential for obtaining the specified performance. Stray capacitance, inductance, inductive power and ground impedances, or other layout issues can severely limit performance and often cause oscillation. Large discontinuities along input and output transmission lines can also limit the specified pulse width dispersion performance. Minimize the source impedance as much as is practicable. High source impedance, in combination with the parasitic input capacitance of the comparator, causes an undesirable degradation in bandwidth at the input, thus degrading the overall response. Thermal noise from large resistances can easily cause extra jitter with slowly slewing input signals. Higher impedances encourage undesired coupling. Rev. 0 | Page 10 of 16 AD8465 COMPARATOR PROPAGATION DELAY DISPERSION COMPARATOR HYSTERESIS The AD8465 comparator is designed to reduce propagation delay dispersion over a wide input overdrive range of 5 mV to VCCI − 1 V. Propagation delay dispersion is the variation in propagation delay that results from a change in the degree of overdrive or slew rate (how far or how fast the input signal is driven past the switching threshold). Propagation delay dispersion is a specification that becomes important in high speed, time-critical applications, such as data communications, automatic test and measurement, and instrumentation. It is also important in event-driven applications, such as pulse spectroscopy, nuclear instrumentation, and medical imaging. Dispersion is defined as the variation in propagation delay as the input overdrive conditions are changed (see Figure 16 and Figure 17). The addition of hysteresis to a comparator is often desirable in a noisy environment, or when the differential input amplitudes are relatively small or slow moving. The transfer function for a comparator with hysteresis is shown in Figure 18. As the input voltage approaches the threshold (0 V, in this example) from below the threshold region in a positive direction, the comparator switches from low to high when the input crosses +VH/2. The new switching threshold becomes −VH/2. The comparator remains in the high state until the −VH/2 threshold is crossed from below the threshold region in a negative direction. In this manner, noise or feedback output signals centered on 0 V input cannot cause the comparator to switch states unless it exceeds the region bounded by ±VH/2. OUTPUT The AD8465 dispersion is typically <1.6 ns as the overdrive varies from 10 mV to 125 mV. This specification applies to both positive and negative signals because the AD8465 has substantially equal delays for positive-going and negativegoing inputs and very low output skews. VOH VOL INPUT VOLTAGE –VH 2 10mV OVERDRIVE 07958-016 Q/Q OUTPUT Figure 16. Propagation Delay—Overdrive Dispersion INPUT VOLTAGE VN ± VOS 07958-017 10V/ns DISPERSION INPUT The customary technique for introducing hysteresis into a comparator uses positive feedback from the output back to the input. One limitation of this approach is that the amount of hysteresis varies with the output logic levels, resulting in hysteresis that is not symmetric about the threshold. The external feedback network can also introduce significant parasitics that reduce high-speed performance and induce oscillation in some cases. 1V/ns Q/Q OUTPUT +VH 2 Figure 18. Comparator Hysteresis Transfer Function VN ± VOS DISPERSION 0V 07958-018 500mV OVERDRIVE Figure 17. Propagation Delay—Slew Rate Dispersion Rev. 0 | Page 11 of 16 AD8465 The AD8465 comparator offers a programmable hysteresis feature that significantly improves accuracy and stability. Connecting an external pull-down resistor or a current source from the LE/HYS pin to GND varies the amount of hysteresis in a predictable and stable manner. Leaving the LE/HYS pin disconnected or driving it high removes hysteresis. The maximum hysteresis that can be applied using this pin is approximately 160 mV. Figure 19 illustrates the amount of hysteresis applied as a function of external resistor value. Figure 10 illustrates hysteresis as a function of current. Rail-to-rail inputs of this type, in both op amps and comparators, have a dual front-end design. Certain devices are active near the VCCI rail and others are active near the VEE rail. At some predetermined point in the common-mode range, a crossover occurs. At this point, normally VCCI/2, the direction of the bias current reverses and there are changes in measured offset voltages and currents. The hysteresis control pin appears as a 1.25 V bias voltage seen through a series resistance of 70 kΩ ± 20% throughout the hysteresis control range. The advantages of applying hysteresis in this manner are improved accuracy, improved stability, reduced component count, and maximum versatility. An external bypass capacitor is not recommended on the LE/HYS pin because it would likely degrade the jitter performance of the device and impair the latch function. As described in the Using/Disabling the Latch Feature section, hysteresis control need not compromise the latch function. With the rated load capacitance and normal good PCB design practice, as discussed in the Optimizing Performance section, these comparators should be stable at any input slew rate with no hysteresis. Broadband noise from the input stage is observed in place of the violent chattering seen with most other high speed comparators. With additional capacitive loading or poor bypassing, oscillation is observed. This oscillation is due to the high gain bandwidth of the comparator in combination with feedback parasitics in the package and PCB. In many applications, chattering is not harmful. CROSSOVER BIAS POINTS MINIMUM INPUT SLEW RATE REQUIREMENT 250 150 100 VCC = 2.5V 50 VCC = 5.5V 0 50 100 150 200 250 300 350 400 450 HYSTERESIS RESISTOR (kΩ) 500 07958-019 HYSTERESIS (mV) 200 Figure 19. Hysteresis vs. RHYS Control Resistor Rev. 0 | Page 12 of 16 AD8465 TYPICAL APPLICATION CIRCUITS 2.5V 2.5V TO 5V 0.1µF 2kΩ 2kΩ CMOS OUTPUT AD8465 0.1µF LVDS PWM OUTPUT AD8465 INPUT 1.25V ±50mV 07958-020 INPUT Figure 20. Self-Biased, 50% Slicer INPUT 1.25V REF 2.5V TO 3.3V 10kΩ 10kΩ ADCMP601 LVDS 10kΩ 82pF 100kΩ Figure 24. Oscillator and Pulse-Width Modulator Figure 21. LVDS to Repeater 74VHC 1G07 CONTROL VOLTAGE 0V TO 2.5V 150kΩ 2.5V TO 5V 2.5V TO 5V AD8465 AD8465 LE/HYS 150kΩ 07958-022 DIGITAL INPUT Figure 22. Hysteresis Adjustment with Latch 10kΩ AD8465 LVDS OUTPUT 10kΩ 150kΩ 150kΩ 07958-023 LE/HYS CONTROL VOLTAGE 0V TO 2.5V DIGITAL INPUT 74AHC 1G07 HYSTERESIS CURRENT 10kΩ LE/HYS Figure 25. Hysteresis Adjustment with Latch 2.5V 82pF LE/HYS 07958-024 AD8465 Figure 23. Voltage-Controlled Oscillator Rev. 0 | Page 13 of 16 07958-025 100Ω 07958-021 LVDS AD8465 OUTLINE DIMENSIONS 1.00 0.85 0.80 12° MAX 10 9 0.50 0.40 0.30 0.80 MAX 0.65 TYP 0.05 MAX 0.02 NOM 0.30 0.23 0.18 SEATING PLANE 0.50 BSC 0.60 MAX 2.95 2.75 SQ 2.55 TOP VIEW PIN 1 INDICATOR 0.60 MAX 0.20 REF COPLANARITY 0.08 7 EXPOSED PAD (BOTTOM VIEW) 6 PIN 1 INDICATOR 12 1 3 *1.65 1.50 SQ 1.35 4 0.25 MIN FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. *COMPLIANT TO JEDEC STANDARDS MO-220-VEED-1 EXCEPT FOR EXPOSED PAD DIMENSION. 010809-B 3.15 3.00 SQ 2.85 Figure 26. 12-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 3 mm × 3 mm Body, Very Thin Quad (CP-12-3) Dimensions shown in millimeters ORDERING GUIDE Model AD8465WBCPZ-WP 1 AD8465WBCPZ-R71 1 Temperature Range −40°C to +125°C −40°C to +125°C Package Description 12-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 12-Lead Lead Frame Chip Scale Package [LFCSP_VQ] Z = RoHS Compliant Part. Rev. 0 | Page 14 of 16 Package Option CP-12-3 CP-12-3 Branding Y24 Y24 AD8465 NOTES Rev. 0 | Page 15 of 16 AD8465 NOTES ©2009 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D07958-0-4/09(0) Rev. 0 | Page 16 of 16