MOTOROLA Order this document by MCM6208C/D SEMICONDUCTOR TECHNICAL DATA MCM6208C 64K x 4 Fast Static RAM The MCM6208C is fabricated using Motorola’s high–performance silicon–gate CMOS technology. Static design eliminates the need for external clocks or timing strobes, while CMOS circuitry reduces power consumption and provides for greater reliability. This device meets JEDEC standards for functionality and pinout, and is available in plastic dual–in–line and plastic small–outline J–leaded packages. • • • • • • P PACKAGE 300 MIL PLASTIC CASE 724A–01 Single 5 V ± 10% Power Supply Fully Static — No Clock or Timing Strobes Necessary Fast Access Times: 12, 15, 20, 25, and 35 ns Equal Address and Chip Enable Access Times Low Power Operation: 135 –165 mA Maximum AC Fully TTL Compatible — Three–State Output J PACKAGE 300 MIL SOJ CASE 810A–02 PIN ASSIGNMENT BLOCK DIAGRAM A0 1 24 VCC A1 2 23 A15 A2 3 22 A14 A3 4 21 A13 A4 5 20 A12 A5 6 19 A11 A12 A6 7 18 A10 A13 A7 8 17 DQ0 A14 A8 9 16 DQ1 A9 10 15 DQ2 E 11 14 DQ3 VSS 12 13 W A1 A2 VCC A3 VSS A4 A6 MEMORY ARRAY 256 ROWS x 64 x 4 COLUMNS ROW DECODER COLUMN I/O DQ0 DQ1 DQ2 INPUT DATA CONTROL COLUMN DECODER PIN NAMES DQ3 A0 E A5 A7 A8 A9 A10 A11 A15 A0 – A15 . . . . . . . . . . . . . Address Input DQ0 – DQ3 . . . Data Input/Data Output W . . . . . . . . . . . . . . . . . . . . Write Enable E . . . . . . . . . . . . . . . . . . . . . . Chip Enable VCC . . . . . . . . . . . Power Supply (+ 5 V) VSS . . . . . . . . . . . . . . . . . . . . . . . Ground NC . . . . . . . . . . . . . . . . . No Connection W REV 4 6/95 Motorola, Inc. 1994 MOTOROLA FAST SRAM MCM6208C 1 TRUTH TABLE (X = Don’t Care) E W Mode VCC Current Output Cycle H L L X H L Not Selected Read Write ISB1, ISB2 ICCA ICCA High–Z Dout High–Z — Read Cycle Write Cycle ABSOLUTE MAXIMUM RATINGS (See Note) Rating Power Supply Voltage Voltage Relative to VSS For Any Pin Except VCC Symbol Value Unit VCC – 0.5 to + 7.0 V Vin, Vout – 0.5 to VCC + 0.5 V Iout ± 20 mA Output Current Power Dissipation PD 1.0 W Temperature Under Bias Tbias – 10 to + 85 °C Operating Temperature TA 0 to + 70 °C This device contains circuitry to protect the inputs against damage due to high static voltages or electric fields; however, it is advised that normal precautions be taken to avoid application of any voltage higher than maximum rated voltages to this high–impedance circuit. This CMOS memory circuit has been designed to meet the dc and ac specifications shown in the tables, after thermal equilibrium has been established. The circuit is in a test socket or mounted on a printed circuit board and transverse air flow of at least 500 linear feet per minute is maintained. Storage Temperature — Plastic Tstg – 55 to + 125 °C NOTE: Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to RECOMMENDED OPERATING CONDITIONS. Exposure to higher than recommended voltages for extended periods of time could affect device reliability. DC OPERATING CONDITIONS AND CHARACTERISTICS (VCC = 5.0 V ± 10%, TA = 0 to 70°C, Unless Otherwise Noted) RECOMMENDED OPERATING CONDITIONS Parameter Symbol Min Typ Max Unit Supply Voltage (Operating Voltage Range) VCC 4.5 5.0 5.5 V Input High Voltage VIH 2.2 — VCC + 0.3** V Input Low Voltage VIL – 0.5* — 0.8 V Symbol Min Max Unit Input Leakage Current (All Inputs, Vin = 0 to VCC) Ilkg(I) — ±1 µA Output Leakage Current (E1 = VIH, Vout = 0 to VCC) Ilkg(O) — ±1 µA Standby Current (E ≥ VCC – 0.2 V*, Vin ≤ VSS + 0.2 V, or ≥ VCC – 0.2 V, VCC = Max, f = 0 MHz) ISB2 — 20 mA Output Low Voltage (IOL = 8.0 mA) VOL — 0.4 V Output High Voltage (IOH = – 4.0 mA) VOH 2.4 — V * VIL (min) = – 0.5 V dc; VIL (min) = – 2.0 V ac (pulse width ≤ 20 ns) ** VIH (max) = VCC + 0.3 V dc; VIH (max) = VCC + 2.0 V ac (pulse width ≤ 20 ns) DC CHARACTERISTICS Parameter POWER SUPPLY CURRENTS Parameter Symbol – 12 – 15 – 20 – 25 – 35 Unit AC Supply Current (Iout = 0 mA, VCC = Max, f = fmax) ICCA 165 155 145 135 135 mA Standby Current (E = VIH, VCC = Max, f = fmax) ISB1 55 50 45 40 40 mA MCM6208C 2 MOTOROLA FAST SRAM CAPACITANCE (f = 1 MHz, dV = 3 V, TA = 25°C, Periodically Sampled Rather Than 100% Tested) Characteristic Symbol Max Unit Address Input Capacitance Cin 6 pF Control Pin Input Capacitance (E, G, W) Cin 6 pF I/O Capacitance CI/O 8 pF AC OPERATING CONDITIONS AND CHARACTERISTICS (VCC = 5.0 V ± 10%, TA = 0 to + 70°C, Unless Otherwise Noted) Output Timing Measurement Reference Level . . . . . . . . . . . . . 1.5 V Output Load . . . . . . . . . . . . . . . . Figure 1A Unless Otherwise Noted Input Timing Measurement Reference Level . . . . . . . . . . . . . . . 1.5 V Input Pulse Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 to 3.0 V Input Rise/Fall Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 ns READ CYCLE (See Notes 1 and 2) – 12 Parameter – 15 – 20 – 25 –35 Symbol Min Max Min Max Min Max Min Max Min Max Unit Notes Read Cycle Time tAVAV 12 — 15 — 20 — 25 — 35 — ns 2 Address Access Time tAVQV — 12 — 15 — 20 — 25 — 25 ns Enable Access Time tELQV — 12 — 15 — 20 — 25 — 25 ns Output Enable Access Time tGLQV — 6 — 8 — 10 — 12 — — ns Output Hold from Address Change tAXQX 4 — 4 — 4 — 4 — 4 — ns Enable Low to Output Active1 tELQX 4 — 4 — 4 — 4 — 4 — ns 4, 5, 6 Enable High to Output High–Z tEHQZ 0 6 0 8 0 9 0 10 0 10 ns 4, 5, 6 Output Enable Low to Output Active tGLQX 0 — 0 — 0 — 0 — 0 — ns 4, 5, 6 4, 5, 6 Output Enable High to Output High–Z tGHQZ 0 6 0 7 0 8 0 10 0 — ns Power Up Time tELICCH 0 — 0 — 0 — 0 — 0 — ns Power Down Time tEHICCL — 12 — 15 — 20 — 25 — 35 ns 3 NOTES: 1. W is high for read cycle. 2. All timings are referenced from the last valid address to the first transitioning address. 3. Addresses valid prior to or coincident with E going low. 4. At any given voltage and temperature, tEHQZ max is less than tELQX min, and tGHQZ max is less than tGLQX min, both for a given device and from device to device. 5. Transition is measured ± 500 mV from steady–state voltage with load of Figure 1B. 6. This parameter is sampled and not 100% tested. 7. Device is continuously selected (E1 ≤ VIL). TIMING LIMITS AC TEST LOADS +5V RL = 50 Ω OUTPUT 480 Ω OUTPUT Z0 = 50 Ω 255 Ω 5 pF VL = 1.5 V Figure 1A MOTOROLA FAST SRAM Figure 1B The table of timing values shows either a minimum or a maximum limit for each parameter. Input requirements are specified from the external system point of view. Thus, address setup time is shown as a minimum since the system must supply at least that much time (even though most devices do not require it). On the other hand, responses from the memory are specified from the device point of view. Thus, the access time is shown as a maximum since the device never provides data later than that time. MCM6208C 3 READ CYCLE 1 (See Note 8) tAVAV A (ADDRESS) tAXQX Q (DATA OUT) PREVIOUS DATA VALID DATA VALID tAVQV READ CYCLE 2 (See Notes 2 and 4) tAVAV A (ADDRESS) tELQV E (CHIP ENABLE) tELQX HIGH–Z Q (DATA OUT) tEHQZ HIGH–Z DATA VALID tAVQV VCC SUPPLY CURRENT MCM6208C 4 ICC tELICCH tEHICCL ISB MOTOROLA FAST SRAM WRITE CYCLE 1 (W Controlled, See Notes 1, 2, and 3) – 12 Parameter Write Cycle Time – 15 – 20 – 25 – 35 Symbol Min Max Min Max Min Max Min Max Min Max Unit Notes tAVAV 12 — 15 — 20 — 25 — 35 — ns 2 Address Setup Time tAVWL 0 — 0 — 0 — 0 — 0 — ns Address Valid to End of Write tAVWH 10 — 12 — 15 — 20 — 20 — ns Write Pulse Width tWLWH, tWLEH 10 — 12 — 15 — 20 — 20 — ns Write Pulse Width, E High tWLWH, tWLEH 8 — 10 — 12 — 15 — 15 — ns Data Valid to End of Write tDVWH 6 — 7 — 8 — 10 — 10 — ns Data Hold Time tWHDX 0 — 0 — 0 — 0 — 0 — ns Write Low to Output High–Z tWLQZ 0 7 0 7 0 8 0 10 0 10 ns 3, 4, 5 Write High to Output Active tWHQX 4 — 4 — 4 — 4 — 4 — ns 3, 4, 5 Write Recovery Time tWHAX 0 — 0 — 0 — 0 — 0 — ns NOTES: 1. A write occurs during the overlap of E low and W low. 2. All timings are referenced from the last valid address to the first transitioning address. 3. At any given voltage and temperature, tWLQZ max is less than tWHQX min, both for a given device and from device to device. 4. Transition is measured ± 500 mV from steady–state voltage with load of Figure 1B. 5. This parameter is sampled and not 100% tested. WRITE CYCLE 1 (W Controlled, See Notes 1 and 2) tAVAV A (ADDRESS) tWHAX tAVWH E (CHIP ENABLE) tWLWH tWLEH W (WRITE ENABLE) tAVWL tDVWH D (DATA IN) DATA VALID tWLQZ Q (DATA OUT) MOTOROLA FAST SRAM tWHDX HIGH–Z tWHQX HIGH–Z MCM6208C 5 WRITE CYCLE 2 (E Controlled, See Notes 1, 2, and 3) – 12 Parameter Write Cycle Time – 15 – 20 – 25 – 35 Symbol Min Max Min Max Min Max Min Max Min Max Unit Notes tAVAV 12 — 15 — 20 — 25 — 35 — ns 2 Address Setup Time tAVEL 0 — 0 — 0 — 0 — 0 — ns Address Valid to End of Write tAVEH 10 — 12 — 15 — 20 — 20 — ns Enable to End of Write tELEH, tELWH 8 — 10 — 12 — 15 — 15 — ns Data Valid to End of Write tDVEH 6 — 7 — 8 — 10 — 10 — ns Data Hold Time tEHDX 0 — 0 — 0 — 0 — 0 — ns Write Recovery Time tEHAX 0 — 0 — 0 — 0 — 0 — ns 3, 4 NOTES: 1. A write occurs during the overlap of E low and W low. 2. All timings are referenced from the last valid address to the first transitioning address. 3. If E goes low coincident with or after W goes low, the output will remain in a high impedance state. 4. If E goes high coincident with or before W goes high, the output will remain in a high impedance state. WRITE CYCLE 2 (E Controlled, See Notes 1 and 2) tAVAV A (ADDRESS) tAVEH E (CHIP ENABLE) tELEH tELWH tAVEL tEHAX tWLEH W (WRITE ENABLE) tDVEH D (DATA IN) tEHDX DATA VALID HIGH–Z Q (DATA OUT) ORDERING INFORMATION (Order by Full Part Number) MCM 6208C X XX XX Motorola Memory Prefix Shipping Method (R2 = Tape and Reel, Blank = Rails) Part Number Speed (12 = 12 ns, 15 = 15 ns, 20 = 20 ns, 25 = 25 ns, 35 = 35 ns) Package (P = Plastic DIP, J = Plastic SOJ) Full Part Numbers — MCM6208CP12 MCM6208CP15 MCM6208CP20 MCM6208CP25 MCM6208CP35 MCM6208C 6 MCM6208CJ12 MCM6208CJ15 MCM6208CJ20 MCM6208CJ25 MCM6208CJ35 MCM6208CJ12R2 MCM6208CJ15R2 MCM6208CJ20R2 MCM6208CJ25R2 MCM6208CJ35R2 MOTOROLA FAST SRAM PACKAGE DIMENSIONS P PACKAGE 300 MIL PLASTIC CASE 724A–01 -A- 24 13 1 12 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEAD WHEN FORMED PARALLEL. 4. DIMENSION A AND B DOES NOT INCLUDE MOLD FLASH. MAXIMUM MOLD FLASH 0.25 (0.010). -B- L C -T- DIM A B C D E F G J K L M N K SEATING PLANE E F N G M J 24 PL D 24 PL 0.25 (0.010) M T A 0.25 (0.010) S T B M S MILLIMETERS MIN MAX 29.47 29.71 7.12 7.62 3.81 4.57 0.39 0.53 1.27 BSC 1.15 1.39 2.54 BSC 0.21 0.30 3.18 3.42 7.62 BSC 0° 15° 0.51 1.01 INCHES MIN MAX 1.160 1.170 0.280 0.300 0.150 0.180 0.015 0.021 0.050 BSC 0.045 0.055 0.100 BSC 0.008 0.012 0.125 0.135 0.300 BSC 0° 15° 0.020 0.040 J PACKAGE 300 MIL SOJ CASE 810A–02 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. DIMENSION “A” AND “B” DO NOT INCLUDE MOLD PROTRUSION. MOLD PROTRUSION SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 3. CONTROLLING DIMENSION: INCH. 4. DIM “R” TO BE DETERMINED AT DATUM -T-. 5. 810A-01 IS OBSOLETE, NEW STANDARD 810A-02. F 24 13 1 DETAIL Z N D 24 PL 0.18 (0.007) 12 -A- M T A 0.18 (0.007) H BRK S S T B S P -B- L G M M E C 0.10 (0.004) K DETAIL Z -T- SEATING PLANE S RAD R 0.25 (0.010) S T B S DIM A B C D E F G H K L M N P R S MILLIMETERS MIN MAX 15.75 16.00 7.50 7.74 3.26 3.75 0.39 0.50 2.24 2.48 0.67 0.81 1.27 BSC — 0.50 0.89 1.14 0.64 BSC 0° 5° 0.76 1.14 8.51 8.76 6.61 7.11 0.77 1.01 INCHES MIN MAX 0.620 0.630 0.295 0.305 0.128 0.148 0.015 0.020 0.088 0.098 0.026 0.032 0.050 BSC — 0.020 0.035 0.045 0.025 BSC 5° 0° 0.030 0.045 0.335 0.345 0.260 0.280 0.030 0.040 Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. “Typical” parameters can and do vary in different applications. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. Motorola does not convey any license under its patent rights nor the rights of others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal injury or death may occur. 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Ltd.; Silicon Harbour Center, No. 2 Dai King Street, Tai Po Industrial Estate, Tai Po, N.T., Hong Kong. MCM6208C 8 ◊ CODELINE TO BE PLACED HERE *MCM6208C/D* MCM6208C/D MOTOROLA FAST SRAM