MCNIX MX26C4000BMC-15 4m-bit [512k x 8] cmos multiple-time-programmable-eprom Datasheet

ADVANCE INFORMATION
MX26C4000B
4M-BIT [512K x 8] CMOS
MULTIPLE-TIME-PROGRAMMABLE-EPROM
FEATURES
• 512Kx 8 organization
• Single +5V power supply
• +12V programming voltage
• Fast access time:70/90/100/120/150 ns
• Totally static operation
• Completely TTL compatible
• Operating current:30mA
• Standby current: 100uA
•
•
•
•
•
Chip erase time: 2s (typ.)
Chip program time: 25s (typ.)
100 minimum erase/program cycles
Typical fast programming cycle duration 100us/byte
Package type:
- 32 pin plastic DIP
- 32 pin PLCC
- 32 pin TSOP
- 32 pin SOP
GENERAL DESCRIPTION
by an EPROM programmer or on-board. The
MX26C4000B supports a intelligent fast programming
algorithm which can result in programming time of less
than one minute.
The MX26C4000B is a 5V only, 4M-bit, MTP EPROMTM
(Multiple Time Programmable Read Only Memory). It is
organized as 512K words by 8 bits per word, operates
from a single + 5 volt supply, has a static standby mode,
and features fast single address location programming.
All programming signals are TTL levels, requiring a
single pulse. It is design to be programmed and erased
This MTP EPROMTM is packaged in industry standard 32
pin dual-in-line packages, 32 lead PLCC, 32 lead SOP
and 32 lead TSOP packages.
PIN CONFIGURATIONS
A7
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
P/N: PM0768
32
A17
VCC
1
A18
VPP
4
30
29
A14
A6
A13
A5
A8
A9
A4
A3
9
MX26C4000B
25
A11
A2
OE
A1
A10
CE
A0
21
20
Q5
Q4
Q3
17
Q7
Q6
13
14
GND
Q0
32 TSOP
A11
A9
A8
A13
A14
A17
A18
VCC
VPP
A16
A15
A12
A7
A6
A5
A4
5
A16
A12
VCC
A18
A17
A14
A13
A8
A9
A11
OE
A10
CE
Q7
Q6
Q5
Q4
Q3
Q2
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
Q1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
MX26C4000B
VPP
A16
A15
A12
A7
A6
A5
A4
A3
A2
A1
A0
Q0
Q1
Q2
GND
A15
32 PLCC
32 PDIP/SOP
PIN DESCRIPTION
MX26C4000B
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
OE
A10
CE
Q7
Q6
Q5
Q4
Q3
GND
Q2
Q1
Q0
A0
A1
A2
A3
1
SYMBOL
PIN NAME
A0~A18
Address Input
Q0~Q7
Data Input/Output
CE
Chip Enable Input
OE
Output Enable Input
VPP
Program Supply Voltage
NC
No Internal Connection
VCC
Power Supply Pin (+5V)
GND
Ground Pin
REV. 0.6, JAN. 14, 2002
MX26C4000B
BLOCK DIAGRAM
WRITE
CONTROL
CE
OE
PROGRAM/ERASE
STATE
INPUT
LOGIC
HIGH VOLTAGE
MACHINE
(WSM)
LATCH
A0-A18
BUFFER
STATE
FLASH
REGISTER
ARRAY
ARRAY
Y-DECODER
AND
X-DECODER
ADDRESS
MX26C4000B
Y-PASS GATE
SOURCE
HV
COMMAND
DATA
DECODER
SENSE
AMPLIFIER
PGM
DATA
HV
COMMAND
DATA LATCH
PROGRAM
DATA LATCH
Q0-Q7
P/N: PM0768
I/O BUFFER
2
REV. 0.6, JAN. 14, 2002
MX26C4000B
FUNCTIONAL
DESCRIPTION
to the Read Mode. Robust design features prevent
inadvertent write cycles resulting from VCC power-up and
power-down transitions or system noise. To avoid initiation
of write cycle during VCC power-up, a write cycle is locked
out for VCC less than 4V. The two- command program and
erase write sequence to the command register provide
additional software protection against spurious data
changes.
When the MX26C4000B is delivered, or it is erased, the
chip has all 4M bits in the "ONE", or HIGH state.
"ZEROs" are loaded into the MX26C4000B through the
procedure of programming.
ERASE ALGORITHM
PROGRAM VERIFY MODE
The MX26C4000B do not required preprogramming
before an erase operation. The erase algorithm is a close
loop flow to simultaneously erase all bits in the entire
array. Erase operation starts with the initial erase
operation. Erase verification begins at address 0000H
by reading data FFH from each byte. If any byte fails
to erase. the entire chip is reerased. to a maximum for
10 pulse counts of 500ms duration for each pulse. The
maximum cumulative erase time is 3s. However. the
device is usually erased in no more than 3 pulses. Erase
verification time can be reduced by storing the address
of the last byte that failed. Following the next erase
operation verification may start at the stored address
location. JEDEC standard erase algorithm can also be
used. But erase time will increase by performing the
unnecessary preprogramming.
Verification should be performed on the programmed bits
to determine that they were correctly programmed.
Verification should be performed with OE and CE, at
VIL, and VPP at its programming voltage.
ERASE VERIFY MODE
Verification should be performed on the erased chip to
determine that the whole chip(all bits) was correctly
erased. Verification should be performed with OE and
CE at VIL, and VCC = 5V, VPP = 12.5V
AUTO IDENTIFY MODE
PROGRAM ALGORITHM
The auto identify mode allows the reading out of a binary
code from MTP EPROM that will identify its
manufacturer and device type. This mode is intended
for use by programming equipment for the purpose of
automatically matching the device to be programmed
with its corresponding programming algorithm. This
mode is functional in the 25°C ± 5°C ambient temperature
range that is required when programming the
MX26C4000B.
The device is programmed byte by byte. A maximum
of 25 pulses. each of 100us duration is allowed for each
byte being programmed. The byte may be programmed
sequentially or by random. After each program pulse,
a program verify is done to determine if the byte has
been successfully programmed.
Programming then proceeds to the next desired byte
location. JEDEC standard program algorithms can be
used.
To activate this mode, the programming equipment must
force 12.0 ± 0.5 V on address line A9 of the device.
Two identifier bytes may then be sequenced from the
device outputs by toggling address line A0 from VIL
to VIH. All other address lines must be held at VIL
during auto identify mode.
DATA WRITE PROTECTION
The design of the device protects against accidental
erasure or programming. The internal state machine is
automatically reset to the read mode on power-up. Using
control register architecture, alteration of memory can
only occur after completion of proper command
sequences. The command register is only active when V
is at high voltage. when V PP = V PPL , the device defaults
PP
P/N: PM0768
Byte 0 ( A0 = VIL) represents the manufacturer code,
and byte 1 (A0 = VIH), the device identifier code. For
the MX26C4000B, these two identifier bytes are given
in the Mode Select Table. All identifiers for manufacturer
and device codes will possess odd parity, with the MSB
(DQ7) defined as the parity bit.
3
REV. 0.6, JAN. 14, 2002
MX26C4000B
READ MODE
The MX26C4000B has two control functions, both of
which must be logically satisfied in order to obtain data
at the outputs. Chip Enable (CE) is the power control
and should be used for device selection. Output Enable
(OE) is the output control and should be used to gate
data to the output pins, independent of device selection.
Assuming that addresses are stable, address access
time (tACC) is equal to the delay from CE to output (tCE).
Data is available at the outputs tOE after the falling edge
of OE, assuming that CE has been LOW and addresses
have been stable for at least tACC - tOE.
STANDBY MODE
The MX26C4000B has a CMOS standby mode which
reduces the maximum VCC current to 100 uA. It is
placed in CMOS standby when CE is at VCC ± 0.3 V.
The MX26C4000B also has a TTL-standby mode which
reduces the maximum VCC current to 1.5 mA. It is
placed in TTL-standby when CE is at VIH. When in
standby mode, the outputs are in a high-impedance
state, independent of the OE input.
SYSTEM CONSIDERATIONS
During the switch between active and standby
conditions, transient current peaks are produced on the
rising and falling edges of Chip Enable. The magnitude
of these transient current peaks is dependent on the
output capacitance loading of the device. At a minimum,
a 0.1 uF ceramic capacitor (high frequency, low inherent
inductance) should be used on each device between
VCC and GND to minimize transient effects. In addition,
to overcome the voltage drop caused by the inductive
effects of the printed circuit board traces on EPROM
arrays, a 4.7 uF bulk electrolytic capacitor should be
used between VCC and GND for each of the eight
devices. The location of the capacitor should be close
to where the power supply is connected to the array.
OUTPUT DISABLE
Output is disabled when OE is at logre high. When in
output disabled all circuitry is enabled. Except the output
pins are in a high impedance state(Hi-Z).
P/N: PM0768
4
REV. 0.6, JAN. 14, 2002
MX26C4000B
Table 1: BUS OPERATIONS
Mode
VPP(1)
A0
A9
CE
OE
Q0~Q7
Read
VPPL
A0
A9
VIL
VIL
Data Out
Output Disable
VPPL
X
X
VIL
VIH
Hi-Z
Standby
VPPL
X
X
VIH
X
Hi-Z
Manufacturer Identification
VPPL
VIL
VID(2)
VIL
VIL
Data=C2H
Device Identification
VPPL
VIH
VID(2)
VIL
VIL
Data=C0H
Program
VPPH
A0
X
VIL
VIH
Data In
Verify
VPPH
A0
X
VIH
VIL
Data Out
Program Inhibit
VPPH
X
X
VIH
VIH
Hi-Z
Note:
1. Refer to DC Characteristics. When VPP=VPPL memory contents can be read but not written or erased.
2. VID is the intelligent identifier high voltage. Refer to DC Characteristics.
3. Read operations with VPP=VPPH may access array data or the intelligent identifier codes.
4. With VPP at high voltage the standby current equals ICC+IPP(standby).
5. Refer to Table 2 for vaild data-in during a write operation.
6. X can be VIL or VIH.
P/N: PM0768
5
REV. 0.6, JAN. 14, 2002
MX26C4000B
PROGRAMMING ALGORITHM FLOW CHART
VCC=6.25V
VPP=12.75V
n=0
CE=100us Pulse
Verify
NO
N=N+1
next
Address
YES
NO
n=25
Last
Address
NO
YES
YES
Failed
P/N: PM0768
Check All Bytes
1st:VCC=6V
2nd:VCC=4.2V
6
REV. 0.6, JAN. 14, 2002
MX26C4000B
ERASE ALGORITHM FLOW CHART
START
n=0
Erase:
A9=12.5V
VCC=5V
VPP=12.5V
Chip Erase pulse
Verify:
Yes
A9=VIL or VIH
VCC=5V
VPP=12.5V
Erase Verify
No
N=N+1
No
n=10
Yes
Faild
Passed
P/N: PM0768
7
REV. 0.6, JAN. 14, 2002
MX26C4000B
SWITCHING TEST CIRCUITS
DEVICE
UNDER
TEST
1.8K ohm
+5V
CL
6.2K ohm
DIODES = IN3064
OR EQUIVALENT
CL = 100 pF including jig capacitance
SWITCHING TEST WAVEFORMS
2.0V
2.0V
TEST POINTS
AC driving levels
0.8V
0.8V
OUTPUT
INPUT
AC TESTING: AC driving levels are 2.4V/0.4V for commercial grade.
Input pulse rise and fall times are equal to or less than 10ns.
P/N: PM0768
8
REV. 0.6, JAN. 14, 2002
MX26C4000B
NOTICE:
Stresses greater than those listed under ABSOLUTE
MAXIMUM RATINGS may cause permanent damage to
the device. This is a stress rating only and functional
operation of the device at these or any other conditions
above those indicated in the operational sections of this
specification is not implied. Exposure to absolute
maximum rating conditions for extended period may
affect reliability.
ABSOLUTE MAXIMUM RATINGS
RATING
VALUE
Ambient Operating Temperature -40oC to 85oC
Storage Temperature
-65oC to 125oC
Applied Input Voltage
-0.5V to 7.0V
Applied Output Voltage
-0.5V to VCC + 0.5V
VCC to Ground Potential
-0.5V to 7.0V
A9 & VPP
-0.5V to 13.5V
NOTICE:
Specifications contained within the following tables are
subject to change.
DC/AC OPERATING CONDITION FOR READ OPERATION
MX26C4000B
Operating Temperature Industrial
-90
-100
-120
-150
-40°C to 85°C
-40°C to 85°C
-40°C to 85°C
-40°C to 85°C
5V ± 10%
5V ± 10%
5V ± 10%
5V ± 10%
Vcc Power Supply
CAPACITANCE TA = 25oC, f = 1.0 MHz (Sampled only)
SYMBOL
PARAMETER
CIN
TYP.
MAX.
UNIT
CONDITIONS
Input Capacitance
6
pF
VIN = 0V
COUT
Output Capacitance
12
pF
VOUT = 0V
CVPP
VPP Capacitance
25
pF
VPP = 0V
18
DC CHARACTERISTICS TA = -45°C ~ 85°C, VCC=5V±10%
SYMBOL
PARAMETER
MIN.
MAX.
VIL
Input Low Voltage
-0.3
0.8
V
VIH
Input High Voltage
2.0
VCC + 1
V
VOL
Output Low Voltage
0.4
V
IOL = 2.1mA, VCC=VCC MIN
VOH
Output High Voltage (TTL)
2.4
V
IOH = -0.4mA
VOH
Output High Voltage (CMOS)
VCC-0.7V
V
IOH = -0.1mA
ICC1
VCC Active Current
30
mA
CE = VIL, OE=VIH, f=5MHz
ISB
VCC Standby Current (CMOS)
100
uA
CE=VCC+0.2V, VCC=VCC MAX
ISB
VCC Standby Current (TTL)
1
mA
CE=VIH, VCC=VCC MAX
IPP
VPP Supply Current (Program)
10
uA
CE=WE=VIL, OE=VIH
ILI
Input Leakage Current
-10
10
uA
VIN = 0 to 5.5V
ILO
Output Leakage Current
-10
10
uA
VOUT = 0 to 5.5V
VCC1
Fast Programming Supply Voltage
6.0
6.5
V
VPP1
Fast Programming Voltage
12.5
13.0
V
P/N: PM0768
9
UNIT CONDITIONS
REV. 0.6, JAN. 14, 2002
MX26C4000B
AC RAED CHARACTERISTICS OVER OPERATING RANGE WITH VPP=VCC
Symbol
Parameter
Jeded STD
70
90
100
120
150
Unit
MIN MAX MIN MAX MIN MAX MIN MAX MIN MAX
tAVAV TRC
Read Cycle Time
70
90
100
tELQV TCE
CE Access Time
0
70
0
90
0
100
0
120
0
150
ns
tAVQV TACC Address Access Time
0
70
0
90
0
100
0
120
0
150
ns
tGLQV TOE
OE Access Time
0
35
0
40
0
45
0
50
0
65
ns
tELQX TLZ
CE to Output in Low Z(Note 1)
0
tEHQZ TDF
Chip Disable to Output in
0
0
30
0
120
0
30
0
150
0
35
0
ns
0
35
0
ns
50
ns
High Z (Note 2)
tGLQX TOLZ OE to Output in Low Z (Note 1) 0
tGHQZ TDF
Output Disable to Output in
0
0
30
0
0
30
0
0
35
0
0
35
0
ns
50
ns
High Z (Note 1)
tAXQX TOH
Output Hold from Address,
0
0
0
0
0
ns
50
50
50
50
50
us
CE or OE, change
tVCS
TVCS VCC Setup Time to Valid Read
(Note 2)
Note:
1. Sampled: not 100% tested.
2. Guaranteed by design. not tested.
P/N: PM0768
10
REV. 0.6, JAN. 14, 2002
MX26C4000B
AC WAVEFORMS FOR READ OPERATIONS
Power-Up Standby
Outputs
enabled
Device and
Address Selection
Address
Data Valid
Standby Power-Up
Addresses Stable
tAVAV(tRC)
CE
tEHQZ(tDF)
OE
tGHQZ(tDF)
tGLQV(tOE)
tELQV(tCE)
tELQX(tLZ)
High Z
High Z
Data
tVCS
tAXQX(tOH)
tGLQX(tOLZ)
Output Valid
tAVQV(tACC)
5.0V
VCC
P/N: PM0768
0V
11
REV. 0.6, JAN. 14, 2002
MX26C4000B
AC WAVEFORMS FOR ERASE OPERATIONS
Valid
A9
tAVQ
Q0~Q7
VCC
5V
12V
VPP
tHE
tE
tGLQ
tEH
CE
tAVG
OE
All Matrix Verif
Chip Erase
Table 2. Erasing Mode AC Characteristics
(1)
(1)
±0.25V; VPP=12.5V±
±0.25V)
(TA=25°
°C; VCC=5V±
Symbol
Parameter
Min
Max
Unit
tA9HEL
A9 High to Chip Enable Low
2
us
tAVGL
Address Valid to Output Enable Low
2
us
tAVQV
Address Valid to Data Valid
tEHA9L
Chip Enable High to A9 Low
tER
First Erase Time
tGLQV
Output Enable Low to Data Valid
100
ns
2
us
500
ms
30
ns
VCC must be applied simultaneously with or before VPP and removed simultaneously or after VPP.
P/N: PM0768
12
REV. 0.6, JAN. 14, 2002
MX26C4000B
AC WAVEFORMS FOR PROGRAMMING OPERATIONS
VALID
A0-A18
tAVPL
Q0~Q7
DATA IN
DATA OUT
tQVEL
tEHQX
VCC
tGLQV
tVPHEL
tGHQZ
VPP
tGHAX
tVCHEL
CE
tELEH
tQXGL
OE
PROGRAM
VERIFY
Table 3. Programming Mode AC Characteristics (1)
°C; VCC=6.25V±
±0.25V; VPP=12.5V±
±0.25V)
(TA=25°
(1)
(2)
Symbol
Alt
Parameter
Min
Max
tAVPL
tAS
Address Valid to Chip Enable Low
2
us
TQVEL
tDS
Input Valid to Chip Enable Low
2
us
TVPHEL
tVPS
VPP High to Chip Enable Low
2
us
TVCHEL
tVCS
VCC High to Chip Enable Low
2
us
TELEH
tPW
Chip Enable Program Pulse Wodth
95
TEHQX
tDH
Chip Enable High to Input Transition
2
us
TQXGL
tOES
Input Transition to Output Enable Low
2
us
TGLQV
tOE
Output Enable Low to Output Valid
TGHQZ
tDFP
Output Enable High to Output Hi-Z
0
TGHAX
tAH
Output Enable High to Address Transition
0
105
Unit
us
100
ns
130
ns
ns
VCC must be applied simultaneously with or before VPP and removed simultaneously or after VPP.
Sampled only, not 100% tested.
P/N: PM0768
13
REV. 0.6, JAN. 14, 2002
MX26C4000B
ORDERING INFORMATION
PLASTIC PACKAGE
PART NO.
ACCESS TIME(ns)
OPERATING
STANDBY
Current MAX.(mA)
Current MAX.(uA)
OPERATING
PACKAGE
TEMPERATURE
MX26C4000BPC-90
90
30
100
0°C to 70°C
32 Pin DIP
MX26C4000BQC-90
90
30
100
0°C to 70°C
32 Pin PLCC
MX26C4000BMC-90
90
30
100
0°C to 70°C
32 Pin SOP
MX26C4000BTC-90
90
30
100
0°C to 70°C
32 Pin TSOP
MX26C4000BPC-10
100
30
100
0°C to 70°C
32 Pin DIP
MX26C4000BQC-10
100
30
100
0°C to 70°C
32 Pin PLCC
MX26C4000BMC-10
100
30
100
0°C to 70°C
32 Pin SOP
MX26C4000BTC-10
100
30
100
0°C to 70°C
32 Pin TSOP
MX26C4000BPC-12
120
30
100
0°C to 70°C
32 Pin DIP
MX26C4000BQC-12
120
30
100
0°C to 70°C
32 Pin PLCC
MX26C4000BMC-12
120
30
100
0°C to 70°C
32 Pin SOP
MX26C4000BTC-12
120
30
100
0°C to 70°C
32 Pin TSOP
MX26C4000BPC-15
150
30
100
0°C to 70°C
32 Pin DIP
MX26C4000BQC-15
150
30
100
0°C to 70°C
32 Pin PLCC
MX26C4000BMC-15
150
30
100
0°C to 70°C
32 Pin SOP
MX26C4000BTC-15
150
30
100
0°C to 70°C
32 Pin TSOP
MX26C4000BPI-90
90
30
100
-40°C to 85°C
32 Pin DIP
MX26C4000BQI-90
90
30
100
-40°C to 85°C
32 Pin PLCC
MX26C4000BMI-90
90
30
100
-40°C to 85°C
32 Pin SOP
MX26C4000BTI-90
90
30
100
-40°C to 85°C
32 Pin TSOP
MX26C4000BPI-10
100
30
100
-40°C to 85°C
32 Pin DIP
MX26C4000BQI-10
100
30
100
-40°C to 85°C
32 Pin PLCC
MX26C4000BMI-10
100
30
100
-40°C to 85°C
32 Pin SOP
MX26C4000BTI-10
100
30
100
-40°C to 85°C
32 Pin TSOP
MX26C4000BPI-12
120
30
100
-40°C to 85°C
32 Pin DIP
MX26C4000BQI-12
120
30
100
-40°C to 85°C
32 Pin PLCC
MX26C4000BMI-12
120
30
100
-40°C to 85°C
32 Pin SOP
MX26C4000BTI-12
120
30
100
-40°C to 85°C
32 Pin TSOP
MX26C4000BPI-15
150
30
100
-40°C to 85°C
32 Pin DIP
MX26C4000BQI-15
150
30
100
-40°C to 85°C
32 Pin PLCC
MX26C4000BMI-15
150
30
100
-40°C to 85°C
32 Pin SOP
MX26C4000BTI-15
150
30
100
-40°C to 85°C
32 Pin TSOP
P/N: PM0768
14
REV. 0.6, JAN. 14, 2002
MX26C4000B
PACKAGE INFORMATION
32-PIN PLASTIC DIP(600 mil)
P/N: PM0768
15
REV. 0.6, JAN. 14, 2002
MX26C4000B
32-PIN PLASTIC LEADED CHIP CARRIER (PLCC)
P/N: PM0768
16
REV. 0.6, JAN. 14, 2002
MX26C4000B
32-PIN PLASTIC TSOP
P/N: PM0768
17
REV. 0.6, JAN. 14, 2002
MX26C4000B
32-PIN PLASTIC SOP (450 mil)
P/N: PM0768
18
REV. 0.6, JAN. 14, 2002
MX26C4000B
REVISION HISTORY
Revision No. Description
0.1
To add erase/program cycle
Change title from MX26C4000A to MX26C4000B
0.2
To added 32SOP/TSOP types package and access time 150ns
Modify device ID old 32H-->New C0H
Modify read ID method
Modify erase/program cycle from 100 to 50
Modify VCC Standby Current(TTL) from 1mA to 1.5mA
0.3
To added VCC1 & VPP1 to DC Characteristics Table
Modify Package Information
0.4
To added chip erase time / chip program time
Modify Package Information
0.5
Modify the Programming Operations Timing Waveforms
0.6
1.Cancel the command mode
2.Modify the cycle time from 50-->100
3.Modify the erase/program operation timing waveform and
flowchart
P/N: PM0768
19
Page
P1
All
P1,10,11,16,18
P5
P4,5,6,12
P1
P10
P10
P17~20
P1
P17~20
P15
P12
P1
P6,7,12,13
Date
DEC/18/2000
MAR/27/2001
APR/23/2001
JUL/04/2001
OCT/04/2001
JAN/14/2002
REV. 0.6, JAN. 14, 2002
MX26C4000B
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