Elpida MC-4516CA727 16m-word by 72-bit synchronous dynamic ram module unbuffered type Datasheet

DATA SHEET
MOS INTEGRATED CIRCUIT
MC-4516CA727
16M-WORD BY 72-BIT SYNCHRONOUS DYNAMIC RAM MODULE
UNBUFFERED TYPE
EO
Description
The MC-4516CA727EF, MC-4516CA727PF and MC-4516CA727XF are 16,777,216 words by 72 bits synchronous
dynamic RAM module on which 9 pieces of 128M SDRAM: µPD45128841 are assembled.
This module provides high density and large quantities of memory in a small space without utilizing the surfacemounting technology on the printed circuit board.
Decoupling capacitors are mounted on power supply line for noise reduction.
Features
L
• 16,777,216 words by 72 bits organization (ECC Type)
• Clock frequency and access time from CLK
Part number
MC-4516CA727EF-A75
MC-4516CA727XF-A75
Clock frequency
Access time from CLK
(MAX.)
(MAX.)
CL = 3
133 MHz
5.4 ns
CL = 2
100 MHz
6.0 ns
CL = 3
133 MHz
5.4 ns
CL = 2
100 MHz
6.0 ns
u
od
Pr
MC-4516CA727PF-A75
/CAS latency
CL = 3
133 MHz
5.4 ns
CL = 2
100 MHz
6.0 ns
ct
• Fully Synchronous Dynamic RAM, with all signals referenced to a positive clock edge
• Pulsed interface
• Possible to assert random column address in every cycle
• Quad internal banks controlled by BA0 and BA1 (Bank Select)
• Programmable burst-length (1, 2, 4, 8 and full page)
• Programmable wrap sequence (sequential / interleave)
• Programmable /CAS latency (2, 3)
• Automatic precharge and controlled precharge
• CBR (Auto) refresh and self refresh
• All DQs have 10 Ω ±10 % of series resistor
• Single 3.3 V ± 0.3 V power supply
• LVTTL compatible
• 4,096 refresh cycles/64 ms
• Burst termination by Burst Stop command and Precharge command
• 168-pin dual in-line memory module (Pin pitch = 1.27 mm)
• Unbuffered type
• Serial PD
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all devices/types available in every country. Please check with local Elpida Memory, Inc. for
availability and additional information.
Document No. E0056N20 (Ver. 2.0)
Date Published March 2001 CP (K)
Printed in Japan
This product became EOL in September, 2002.
Elpida Memory, Inc. is a joint venture DRAM company of NEC Corporation and Hitachi, Ltd.
MC-4516CA727
Ordering Information
Part number
Clock frequency
Package
Mounted devices
(MAX.)
MC-4516CA727EF-A75
133 MHz
MC-4516CA727PF-A75
168-pin Dual In-line Memory Module
9 pieces of µPD45128841G5 (Rev. E)
(Socket Type)
(10.16 mm (400) TSOP (II))
Edge connector : Gold plated
9 pieces of µPD45128841G5 (Rev. P)
34.93 mm height
(10.16 mm (400) TSOP (II))
9 pieces of µPD45128841G5 (Rev. X)
MC-4516CA727XF-A75
L
EO
(10.16 mm (400) TSOP (II))
ct
u
od
Pr
2
Data Sheet E0056N20
MC-4516CA727
Pin Configuration
168-pin Dual In-line Memory Module Socket Type (Edge connector: Gold plated)
/xxx indicates active low signal.
VSS
DQ0
DQ1
DQ2
DQ3
Vcc
DQ4
DQ5
DQ6
DQ7
1
2
3
4
5
6
7
8
9
10
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
DQ40
DQ8
VSS
VSS
DQ41
DQ9
DQ42
DQ10
DQ43
DQ11
DQ44
DQ12
DQ45
DQ13
Vcc
Vcc
DQ46
DQ14
DQ47
DQ15
CB4
CB0
CB5
CB1
VSS
VSS
NC
NC
NC
NC
Vcc
Vcc
/WE
/CAS
DQMB0
DQMB4
DQMB1
DQMB5
/CS0
NC
NC
/RAS
VSS
VSS
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
BA0 (A13)
BA1 (A12)
A11
Vcc
Vcc
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
CLK1
NC
VSS
CKE0
NC
DQMB6
DQMB7
NC
Vcc
NC
NC
CB6
CB7
VSS
DQ48
DQ49
DQ50
DQ51
Vcc
DQ52
NC
NC
NC
VSS
DQ53
DQ54
DQ55
VSS
DQ56
DQ57
DQ58
DQ59
Vcc
DQ60
DQ61
DQ62
DQ63
VSS
CLK3
NC
SA0
SA1
SA2
Vcc
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
VSS
DQ32
DQ33
DQ34
DQ35
Vcc
DQ36
DQ37
DQ38
DQ39
L
EO
85
86
87
88
89
90
91
92
93
94
u
od
Pr
Data Sheet E0056N20
: Address Inputs
[Row: A0 - A11, Column: A0 – A9]
BA0 (A13),
BA1 (A12)
: SDRAM Bank Select
DQ0 - DQ63,
CB0 - CB7
: Data Inputs/Outputs
CLK0 - CLK3
: Clock Input
CKE0
: Clock Enable Input
/CS0, /CS2
: Chip Select Input
/RAS
: Row Address Strobe
/CAS
: Column Address Strobe
/WE
: Write Enable
DQMB0 - DQMB7 : DQ Mask Enable
SA0 - SA2
: Address Input for EEPROM
SDA
: Serial Data I/O for PD
SCL
: Clock Input for PD
VCC
: Power Supply
VSS
: Ground
WP
: Write Protect
NC
: No Connection
ct
Vcc
CLK0
VSS
NC
/CS2
DQMB2
DQMB3
NC
Vcc
NC
NC
CB2
CB3
VSS
DQ16
DQ17
DQ18
DQ19
Vcc
DQ20
NC
NC
NC
VSS
DQ21
DQ22
DQ23
VSS
DQ24
DQ25
DQ26
DQ27
Vcc
DQ28
DQ29
DQ30
DQ31
VSS
CLK2
NC
WP
SDA
SCL
Vcc
A0 - A11
3
MC-4516CA727
Block Diagram
/WE
/CS0
/CS2
DQMB0
DQMB2
DQ 7 DQM /CS
DQ 6
DQ 5
DQ 4
D0
DQ 3
DQ 2
DQ 1
DQ 0
/WE
DQ 7 DQM
/WE
EO
DQ 0
DQ 1
DQ 2
DQ 3
DQ 4
DQ 5
DQ 6
DQ 7
DQ 16
DQ 17
DQ 18
DQ 19
DQ 20
DQ 21
DQ 22
DQ 23
/CS
D1
DQ 4 DQM
/WE
DQ 7 DQM /CS
DQ 6
DQ 5
DQ 4
D7
DQ 3
DQ 2
DQ 1
DQ 0
/WE
DQ 7 DQM /CS
DQ 6
DQ 5
DQ 4
D8
DQ 3
DQ 2
DQ 1
DQ 0
/WE
DQMB6
/WE
DQ 48
DQ 49
DQ 50
DQ 51
DQ 52
DQ 53
DQ 54
DQ 55
D2
DQMB7
DQ 4 DQM /CS
DQ 7
DQ 6
DQ 5
D5
DQ 3
DQ 2
DQ 1
DQ 0
DQMB5
DQ 40
DQ 41
DQ 42
DQ 43
DQ 44
DQ 45
DQ 46
DQ 47
DQ 4 DQM /CS
DQ 7
DQ 6
DQ 5
D4
DQ 3
DQ 2
DQ 1
DQ 0
u
od
Pr
DQ 7
DQ 0
DQ 2
DQ 6
DQ 5
DQ 3
DQ 1
/CS
DQMB4
DQ 32
DQ 33
DQ 34
DQ 35
DQ 36
DQ 37
DQ 38
DQ 39
DQ 24
DQ 25
DQ 26
DQ 27
DQ 28
DQ 29
DQ 30
DQ 31
L
CB 0
CB 1
CB 2
CB 3
CB 4
CB 5
CB 6
CB 7
DQ 6
DQ 5
DQ 4
DQ 3
DQ 2
DQ 1
DQ 0
/WE
DQMB3
DQMB1
DQ 8
DQ 9
DQ 10
DQ 11
DQ 12
DQ 13
DQ 14
DQ 15
DQ 7 DQM /CS
DQ 6
DQ 5
DQ 4
D3
DQ 3
DQ 2
DQ 1
DQ 0
DQ 5 DQM /CS
DQ 7
DQ 6
DQ 4
D6
DQ 3
DQ 2
DQ 1
DQ 0
/WE
/WE
DQ 56
DQ 57
DQ 58
DQ 59
DQ 60
DQ 61
DQ 62
DQ 63
CLK0
CLK : D0, D1, D2, D5, D6
CLK2
CLK : D3, D4, D7, D8
3.3 pF
CLK1, CLK3
10 pF
A0 - A11
A0 - A11 : D0 - D8
BA0
A13 : D0 - D8
BA1
A12 : D0 - D8
/RAS
/RAS : D0 - D8
/CAS
/CAS : D0 - D8
CKE0
CKE : D0 - D8
SERIAL PD
D0 - D8
C
VSS
SDA
SCL
D0 - D8
ct
VCC
A0
A1
A2
WP
47 kΩ
SA0 SA1 SA2
Remarks 1. The value of all resistors is 10 Ω except WP.
2. D0 - D8: µPD45128841 (4M words × 8 bits × 4 banks)
4
Data Sheet E0056N20
MC-4516CA727
Electrical Specifications
• All voltages are referenced to VSS (GND).
• After power up, wait more than 100 µs and then, execute power on sequence and CBR (Auto) refresh before proper
device operation is achieved.
Absolute Maximum Ratings
Parameter
Symbol
Rating
Unit
VCC
–0.5 to +4.6
V
VT
–0.5 to +4.6
V
Short circuit output current
IO
50
mA
Power dissipation
PD
9
W
Operating ambient temperature
TA
0 to 70
°C
Storage temperature
Tstg
–55 to +125
°C
Voltage on power supply pin relative to GND
EO
Voltage on input pin relative to GND
Caution
Condition
Exposing the device to stress above those listed in Absolute Maximum Ratings could cause
permanent damage. The device is not meant to be operated under conditions outside the limits
described in the operational section of this specification. Exposure to Absolute Maximum Rating
L
conditions for extended periods may affect device reliability.
Recommended Operating Conditions
Parameter
High level input voltage
Low level input voltage
Operating ambient temperature
Condition
MIN.
TYP.
MAX.
Unit
VCC
3.0
3.3
VIH
2.0
3.6
V
VCC + 0.3
V
VIL
−0.3
+0.8
V
TA
0
70
°C
MAX.
Unit
26
66
pF
u
od
Pr
Supply voltage
Symbol
Capacitance (TA = 25 °C, f = 1 MHz)
Parameter
Input capacitance
Symbol
CI1
Test condition
A0 - A11, BA0(A13), BA1(A12), /RAS,
MIN.
TYP.
/CAS, /WE
Data input/output capacitance
CI2
CLK0, CLK2
20
40
CI3
CKE0
30
56
CI4
/CS0, /CS2
15
33
CI5
DQMB0 - DQMB7
3
17
CI/O
DQ0 - DQ63, CB0 - CB7
4
13
pF
ct
Data Sheet E0056N20
5
MC-4516CA727
DC Characteristics (Recommended Operating Conditions Unless Otherwise Noted)
Parameter
Operating current
Precharge standby current in
power down mode
Precharge standby current
Symbol
ICC1
ICC2P
EO
power down mode
Active standby current in
ICC2N
Burst length = 1
/CAS latency = 2
900
tRC ≥ tRC(MIN.), IO = 0 mA
/CAS latency = 3
945
CKE ≤ VIL(MAX.), tCK = 15 ns
ICC3P
Self refresh current
Output leakage current
High level output voltage
Low level output voltage
mA
1
mA
mA
72
CKE ≤ VIL(MAX.), tCK = 15 ns
45
mA
36
CKE ≥ VIH(MIN.), tCK = 15 ns, /CS ≥ VIH(MIN.),
270
mA
Input signals are changed one time during 30 ns.
ICC3NS CKE ≥ VIH(MIN.), tCK = ∞,
180
Input signals are stable.
ICC4
tCK ≥ tCK(MIN.), IO = 0 mA
ICC5
ICC6
tRC ≥ tRC(MIN.)
/CAS latency = 2
1,080
/CAS latency = 3
1,395
/CAS latency = 2
2,070
/CAS latency = 3
2,160
CKE ≤ 0.2 V
18
mA
2
mA
3
mA
–9
+9
µA
– 1.5
+ 1.5
µA
u
od
Pr
Input leakage current
180
ICC3PS CKE ≤ VIL(MAX.), tCK = ∞
ICC3N
Unit Notes
9
CKE ≥ VIH(MIN.), tCK = 15 ns, /CS ≥ VIH(MIN.),
Input signals are changed one time during 30 ns.
L
CBR (Auto) refresh current
9
ICC2NS CKE ≥ VIH(MIN.), tCK = ∞
Input signals are stable.
non power down mode
Operating current (Burst mode)
MIN. MAX.
ICC2PS CKE ≤ VIL(MAX.), tCK = ∞
in non power down mode
Active standby current in
Test condition
II(L)
VI = 0 to 3.6 V, All other pins not under test = 0 V
IO(L)
DOUT is disabled, VO = 0 to 3.6 V
VOH
IO = – 4 mA
VOL
IO = + 4 mA
2.4
V
0.4
V
Notes 1. ICC1 depends on output loading and cycle rates. Specified values are obtained with the output open. In
addition to this, ICC1 is measured on condition that addresses are changed only one time during tCK (MIN.).
2. ICC4 depends on output loading and cycle rates. Specified values are obtained with the output open. In
addition to this, ICC4 is measured on condition that addresses are changed only one time during tCK (MIN.).
3. ICC5 is measured on condition that addresses are changed only one time during tCK (MIN.).
ct
6
Data Sheet E0056N20
MC-4516CA727
AC Characteristics (Recommended Operating Conditions Unless Otherwise Noted)
Test Conditions
Parameter
AC high level input voltage / low level input voltage
Input timing measurement reference level
Transition time (Input rise and fall time)
Output timing measurement reference level
Value
Unit
2.4 / 0.4
V
1.4
V
1
ns
1.4
V
CLK
tCL
2.4 V
1.4 V
0.4 V
tSETUP tHOLD
2.4 V
1.4 V
L
EO
tCK
tCH
Input
0.4 V
tAC
tOH
Output
ct
u
od
Pr
Data Sheet E0056N20
7
MC-4516CA727
Synchronous Characteristics
Parameter
Symbol
-A75
MIN.
Clock cycle time
Access time from CLK
Unit
MAX.
/CAS latency = 3
tCK3
7.5
(133 MHz)
ns
/CAS latency = 2
tCK2
10
(100 MHz)
ns
/CAS latency = 3
tAC3
5.4
ns
1
/CAS latency = 2
tAC2
6.0
ns
1
CLK high level width
2.5
ns
tCL
2.5
ns
Data-out hold time
tOH
3.0
ns
Data-out low-impedance time
tLZ
0
ns
/CAS latency = 3
tHZ3
3.0
5.4
/CAS latency = 2
6.0
EO
tCH
CLK low level width
Data-out high-impedance time
tHZ2
3.0
tDS
1.5
ns
Data-in hold time
tDH
0.8
ns
Address setup time
tAS
1.5
ns
ns
Address hold time
L
tAH
0.8
ns
CKE setup time
tCKS
1.5
ns
CKE hold time
tCKH
0.8
ns
CKE setup time (Power down exit)
tCKSP
1.5
ns
Command (/CS0, /CS2, /RAS, /CAS, /WE,
tCMS
1.5
ns
u
od
Pr
Command (/CS0, /CS2, /RAS, /CAS, /WE,
DQMB0 - DQMB7) hold time
Note 1. Output load
1
ns
Data-in setup time
DQMB0 - DQMB7) setup time
Note
tCMH
0.8
ns
Z = 50 Ω
Output
50 pF
Remark These specifications are applied to the monolithic device.
ct
8
Data Sheet E0056N20
MC-4516CA727
Asynchronous Characteristics
Parameter
Symbol
-A75
MIN.
Unit
MAX.
ACT to REF/ACT command period (operation)
tRC
67.5
ns
REF to REF/ACT command period (refresh)
tRC1
67.5
ns
ACT to PRE command period
tRAS
45
PRE to ACT command period
tRP
20
ns
Delay time ACT to READ/WRITE command
Note
120,000
ns
20
ns
tRRD
15
ns
Data-in to PRE command period
tDPL
8
ns
ns
1
1
EO
tRCD
ACT(one) to ACT(another) command period
Data-in to ACT(REF) command
/CAS latency = 3
tDAL3
1CLK+22.5
period (Auto precharge)
/CAS latency = 2
tDAL2
1CLK+20
ns
tRSC
2
CLK
tT
0.5
Mode register set cycle time
Transition time
Refresh time (4,096 refresh cycles)
tREF
30
ns
64
ms
Note This device can satisfy the tDAL3 spec of 1CLK+20 ns for up to and including 125 MHz operation.
L
ct
u
od
Pr
Data Sheet E0056N20
9
MC-4516CA727
Serial PD
(1/2)
Byte No.
Function Described
Hex
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Notes
80H
1
0
0
0
0
0
0
0
128 bytes
Defines the number of bytes written into
serial PD memory
1
Total number of bytes of serial PD memory
08H
0
0
0
0
1
0
0
0
256 bytes
2
Fundamental memory type
04H
0
0
0
0
0
1
0
0
SDRAM
3
Number of rows
0CH
0
0
0
0
1
1
0
0
12 rows
4
Number of columns
0AH
0
0
0
0
1
0
1
0
10 columns
5
Number of banks
01H
0
0
0
0
0
0
0
1
1 bank
6
Data width
48H
0
1
0
0
1
0
0
0
72 bits
7
Data width (continued)
00H
0
0
0
0
0
0
0
0
0
8
Voltage interface
01H
0
0
0
0
0
0
0
1
LVTTL
9
CL = 3 Cycle time
75H
0
1
1
1
0
1
0
1
7.5 ns
10
CL = 3 Access time
54H
0
1
0
1
0
1
0
0
5.4 ns
11
DIMM configuration type
02H
0
0
0
0
0
0
1
0
ECC
12
Refresh rate/type
80H
1
0
0
0
0
0
0
0
Normal
13
SDRAM width
08H
0
0
0
0
1
0
0
0
×8
14
Error checking SDRAM width
08H
0
0
0
0
1
0
0
0
×8
15
Minimum clock delay
01H
0
0
0
0
0
0
0
1
1 clock
16
Burst length supported
8FH
1
0
0
0
1
1
1
1
1, 2, 4, 8, F
L
EO
0
Number of banks on each SDRAM
04H
0
0
0
0
0
1
0
0
4 banks
18
/CAS latency supported
06H
0
0
0
0
0
1
1
0
2, 3
19
/CS latency supported
20
21
u
od
Pr
17
01H
0
0
0
0
0
0
0
1
0
/WE latency supported
01H
0
0
0
0
0
0
0
1
0
SDRAM module attributes
00H
0
0
0
0
0
0
0
0
22
SDRAM device attributes : General
0EH
0
0
0
0
1
1
1
0
23
CL = 2 Cycle time
A0H
1
0
1
0
0
0
0
0
10 ns
24
CL = 2 Access time
6 ns
25-26
27
tRP(MIN.)
28
tRRD(MIN.)
29
tRCD(MIN.)
30
tRAS(MIN.)
31
Module bank density
60H
0
1
1
0
0
0
0
0
00H
0
0
0
0
0
0
0
0
14H
0
0
0
1
0
1
0
0
20 ns
0FH
0
0
0
0
1
1
1
1
15 ns
14H
0
0
0
1
0
1
0
0
20 ns
2DH
0
0
1
0
1
1
0
1
45 ns
20H
0
0
1
0
0
0
0
0
128M bytes
ct
10
Data Sheet E0056N20
MC-4516CA727
(2/2)
Byte No.
32
Function Described
Command and address signal input
Hex
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Notes
15H
0
0
0
1
0
1
0
1
1.5 ns
08H
0
0
0
0
1
0
0
0
0.8 ns
setup time
33
Command and address signal input
34
Data signal input setup time
15H
0
0
0
1
0
1
0
1
1.5 ns
35
Data signal input hold time
08H
0
0
0
0
1
0
0
0
0.8 ns
hold time
00H
0
0
0
0
0
0
0
0
62
SPD revision
12H
0
0
0
1
0
0
1
0
63
Checksum for bytes 0 - 62
C1H
1
1
0
0
0
0
0
1
EO
36-61
64-71
72
1.2
Manufacture’s JEDEC ID code
Manufacturing location
73-90
Manufacture’s P/N
91-92
Revision code
Manufacturing date
95-98
Assembly serial number
99-125
Mfg specific
L
93-94
126
Intel specification frequency
64H
0
1
1
0
0
1
0
0
127
Intel specification /CAS latency support
A7H
1
0
1
0
0
1
1
1
u
od
Pr
Timing Chart
Refer to the µPD45128441, 45128841, 45128163 Data sheet (E0031N).
ct
Data Sheet E0056N20
11
MC-4516CA727
Package Drawing
168-PIN DUAL IN-LINE MODULE (SOCKET TYPE)
A (AREA B)
Z1
Z2
Y1
Y2
R2
N
F2
F1
EO
Q
R1
L
A
B
H
S
(OPTIONAL HOLES)
K
C
J
I
B
U
T
E
D
G
A1 (AREA A)
L
ITEM
A
M2 (AREA A)
A1
MILLIMETERS
133.35
133.35±0.13
B
11.43
C
36.83
D
6.35
D1
2.0
D2
3.125
E
F1
54.61
2.44
u
od
Pr
M1 (AREA B)
M
detail of A part
detail of B part
D2
W
V
X
F2
3.18
G
6.35
H
I
1.27 (T.P.)
8.89
J
K
24.495
42.18
L
17.78
M
34.93±0.13
M1
15.15
M2
19.78
P
N
3.0 MAX.
D1
P
Q
1.0
R2.0
R1
4.0±0.10
R2
S
9.53
φ 3.0
1.27±0.1
4.0 MIN.
0.2±0.15
1.0±0.05
X
2.54±0.10
ct
T
U
V
W
Y1
3.0 MIN.
Y2
2.26
Z1
3.0 MIN.
Z2
2.26
M168S-50A109
12
Data Sheet E0056N20
MC-4516CA727
[ MEMO ]
L
EO
ct
u
od
Pr
Data Sheet E0056N20
13
MC-4516CA727
[ MEMO ]
L
EO
ct
u
od
Pr
14
Data Sheet E0056N20
MC-4516CA727
NOTES FOR CMOS DEVICES
1
PRECAUTION AGAINST ESD FOR SEMICONDUCTORS
Note:
Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and
ultimately degrade the device operation. Steps must be taken to stop generation of static electricity
as much as possible, and quickly dissipate it once, when it has occurred. Environmental control
must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using
EO
insulators that easily build static electricity. Semiconductor devices must be stored and transported
in an anti-static container, static shielding bag or conductive material. All test and measurement
tools including work bench and floor should be grounded. The operator should be grounded using
wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need
to be taken for PW boards with semiconductor devices on it.
2
HANDLING OF UNUSED INPUT PINS FOR CMOS
Note:
No connection for CMOS device inputs can be cause of malfunction. If no connection is provided
L
to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence
causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels
of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused
pin should be connected to V DD or GND with a resistor, if it is considered to have a possibility of
being an output pin. All handling related to the unused pins must be judged device by device and
3
u
od
Pr
related specifications governing the devices.
STATUS BEFORE INITIALIZATION OF MOS DEVICES
Note:
Power-on does not necessarily define initial status of MOS device. Production process of MOS
does not define the initial operation status of the device. Immediately after the power source is
turned ON, the devices with reset function have not yet been initialized. Hence, power-on does
not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the
reset signal is received. Reset operation must be executed immediately after power-on for devices
having reset function.
ct
Data Sheet E0056N20
15
MC-4516CA727
CAUTION FOR HANDLING MEMORY MODULES
When handling or inserting memory modules, be sure not to touch any components on the modules, such as
the memory IC, chip capacitors and chip resistors. It is necessary to avoid undue mechanical stress on these
components to prevent damaging them.
When re-packing memory modules, be sure the modules are NOT touching each other. Modules in contact
with other modules may cause excessive mechanical stress, which may damage the modules.
EO
L
• The information in this document is current as of March, 2001. The information is subject to change
without notice. For actual design-in, refer to the latest publications of Elpida's data sheets or data
books, etc., for the most up-to-date specifications of Elpida semiconductor products. Not all
products and/or types are available in every country. Please check with an Elpida Memory, Inc. for
availability and additional information.
• No part of this document may be copied or reproduced in any form or by any means without prior
written consent of Elpida. Elpida assumes no responsibility for any errors that may appear in this document.
• Elpida does not assume any liability for infringement of patents, copyrights or other intellectual property rights of
third parties by or arising from the use of Elpida semiconductor products listed in this document or any other
liability arising from the use of such products. No license, express, implied or otherwise, is granted under any
patents, copyrights or other intellectual property rights of Elpida or others.
• Descriptions of circuits, software and other related information in this document are provided for illustrative
purposes in semiconductor product operation and application examples. The incorporation of these
circuits, software and information in the design of customer's equipment shall be done under the full
responsibility of customer. Elpida assumes no responsibility for any losses incurred by customers or third
parties arising from the use of these circuits, software and information.
• While Elpida endeavours to enhance the quality, reliability and safety of Elpida semiconductor products,
customers agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. To
minimize risks of damage to property or injury (including death) to persons arising from defects in Elpida
semiconductor products, customers must incorporate sufficient safety measures in their design, such as
redundancy, fire-containment, and anti-failure features.
• Elpida semiconductor products are classified into the following three quality grades:
"Standard", "Special" and "Specific". The "Specific" quality grade applies only to semiconductor products
developed based on a customer-designated "quality assurance program" for a specific application. The
recommended applications of a semiconductor product depend on its quality grade, as indicated below.
Customers must check the quality grade of each semiconductor product before using it in a particular
application.
"Standard": Computers, office equipment, communications equipment, test and measurement equipment, audio
and visual equipment, home electronic appliances, machine tools, personal electronic equipment
and industrial robots
"Special": Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster
systems, anti-crime systems, safety equipment and medical equipment (not specifically designed
for life support)
"Specific": Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life
support systems and medical equipment for life support, etc.
The quality grade of Elpida semiconductor products is "Standard" unless otherwise expressly specified in
Elpida's data sheets or data books, etc. If customers wish to use Elpida semiconductor products in
applications not intended by Elpida, they must contact an Elpida Memory, Inc. in advance to determine
Elpida's willingness to support a given application.
(Note)
(1) "Elpida" as used in this statement means Elpida Memory, Inc. and also includes its majority-owned
subsidiaries.
(2) "Elpida semiconductor products" means any semiconductor product developed or manufactured by or
for Elpida (as defined above).
ct
u
od
Pr
M8E 00. 4