IDT2309 3.3V ZERO DELAY CLOCK BUFFER COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES IDT2309 3.3V ZERO DELAY CLOCK BUFFER FEATURES: DESCRIPTION: • Phase-Lock Loop Clock Distribution • 10MHz to 133MHz operating frequency • Distributes one clock input to one bank of five and one bankd of four outputs • Separate output enable for each output bank • Output Skew < 250ps • Low jitter <200 ps cycle-to-cycle • IDT2309-1 for Standard Drive • IDT2309-1H for High Drive • No external RC network required • Operates at 3.3V VDD • Available in SOIC and TSSOP packages The IDT2309 is a high-speed phase-lock loop (PLL) clock buffer, designed to address high-speed clock distribution applications. The zero delay is achieved by aligning the phase between the incoming clock and the output clock, operable within the range of 10 to 133MHz. The IDT2309 is a 16-pin version of the IDT2305. The IDT2309 accepts one reference input, and drives two banks of four low skew clocks. The -1H version of this device operates at up to 133MHz frequency and has higher drive than the -1 device. All parts have on-chip PLLs which lock to an input clock on the REF pin. The PLL feedback is on-chip and is obtained from the CLKOUT pad. In the absence of an input clock, the IDT2309 enters power down, and the outputs are tri-stated. In this mode, the device will draw less than 25µA. The IDT2309 is characterized for both Industrial and Commercial operation. FUNCTIONAL BLOCK DIAGRAM 16 1 2 PLL CLKOUT CLKA1 REF 3 14 15 S2 S1 CLKA2 CLKA3 CLKA4 8 9 Control Logic 6 7 10 11 CLKB1 CLKB2 CLKB3 CLKB4 The IDT logo is a registered trademark of Integrated Device Technology, Inc. COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES AUGUST 2012 1 c 2012 Integrated Device Technology, Inc. DSC 5175/7 IDT2309 3.3V ZERO DELAY CLOCK BUFFER COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES ABSOLUTE MAXIMUM RATINGS(1) PIN CONFIGURATION Symbol REF 1 16 CLKOUT CLKA1 2 15 CLKA4 CLKA2 3 14 CLKA3 VDD 4 13 VDD GND 5 12 GND CLKB1 6 Unit Supply Voltage Range Rating –0.5 to +4.6 V VI (2) Input Voltage Range (REF) –0.5 to +5.5 V VI Input Voltage Range –0.5 to V (except REF) Input Clamp Current –50 mA IO (VO = 0 to VDD) Continuous Output Current ±50 mA VDD or GND Continuous Current ±100 mA TA = 55°C Maximum Power Dissipation 0.7 W –65 to +150 °C 0 to +70 °C -40 to +85 °C CLKB4 CLKB3 TSTG Storage Temperature Range S1 Operating Commercial Temperature CLKB2 7 10 S2 8 9 (in still air) (3) Temperature Range Operating Industrial Temperature Temperature Range NOTES: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed. 3. The maximum package power dissipation is calculated using a junction temperature of 150°C and a board trace length of 750 mils. APPLICATIONS: SDRAM Telecom Datacom PC Motherboards/Workstations Critical Path Delay Designs PIN DESCRIPTION Pin Name Pin Number Type Functional Description REF 1 IN Input reference clock, 5 Volt tolerant input CLKA1(1) 2 Out Output clock for bank A Output clock for bank A CLKA2 3 Out VDD 4, 13 PWR GND (1) 3.3V Supply 5, 12 GND CLKB1(1) 6 Out Output clock for bank B CLKB2(1) 7 Out Output clock for bank B S2(2) 8 IN Select input Bit 2 S1 Ground 9 IN Select input Bit 1 CLKB3(1) 10 Out Output clock for bank B CLKB4(1) 11 Out Output clock for bank B CLKA3(1) 14 Out Output clock for bank A CLKA4 15 Out Output clock for bank A 16 Out Output clock, internal feedback on this pin (2) (1) CLKOUT(1) VDD+0.5 IIK (VI < 0) 11 SOIC/ TSSOP TOP VIEW • • • • • Max. VDD NOTES: 1. Weak pull down on all outputs. 2. Weak pull ups on these inputs. 2 IDT2309 3.3V ZERO DELAY CLOCK BUFFER COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES FUNCTION TABLE(1) S2 S1 CLKA CLKB CLKOUT (2) Output Source PLL Shut Down L L Tri-State Tri-State Driven PLL N L H Driven Tri-State Driven PLL N H L Driven Driven Driven REF Y H H Driven Driven Driven PLL N NOTES: 1. H = HIGH Voltage Level. L = LOW Voltage Level 2. This output is driven and has an internal feedback for the PLL. The load on this ouput can be adjusted to change the skew between the REF and the output. DC ELECTRICAL CHARACTERISTICS - COMMERCIAL Symbol Parameter Conditions VIL Input LOW Voltage Level VIH Input HIGH Voltage Level IIL Input LOW Current VIN = 0V IIH Input HIGH Current VIN = VDD VOL Output LOW Voltage VOH IDD_PD IDD Output HIGH Voltage Standard Drive IOL = 8mA High Drive IOL = 12mA (-1H) Standard Drive IOH = -8mA High Drive IOH = -12mA (-1H) Min. Max. Unit — 0.8 V 2 — V — 50 µA — 100 µA — 0.4 V 2.4 — V Power Down Current REF = 0MHz (S2 = S1 = H) — 12 µA Supply Current Unloaded Outputs at 66.66MHz, SEL inputs at VDD or GND — 32 mA OPERATING CONDITIONS - COMMERCIAL Symbol Min. Max. Unit VDD Supply Voltage 3 3.6 V TA Operating Temperature (Ambient Temperature) 0 70 °C CL Load Capacitance < 100MHz — 30 pF Load Capacitance 100MHz - 133MHz — 10 Input Capacitance — 7 CIN Parameter pF (1,2) SWITCHING CHARACTERISTICS (2309-1) - COMMERCIAL Symbol t1 Parameter Conditions Output Frequency Min. Typ. Max. Unit 10pF Load 10 — 133 MHz 30pF Load 10 — 100 Duty Cycle = t2 ÷ t1 Measured at 1.4V, FOUT = 66.66MHz 40 50 60 % t3 Rise Time Measured between 0.8V and 2V — — 2.5 ns t4 Fall Time Measured between 0.8V and 2V — — 2.5 ns t5 Output to Output Skew All outputs equally loaded — — 250 ps t6A Delay, REF Rising Edge to CLKOUT Rising Edge Measured at VDD/2 — 0 ±350 ps t6B Delay, REF Rising Edge to CLKOUT Rising Edge(2) Measured at VDD/2 in PLL bypass mode (IDT2309 only) 1 5 8.7 ns t7 Device-to-Device Skew Measured at VDD/2 on the CLKOUT pins of devices — 0 700 ps tJ Cycle-to-Cycle Jitter Measured at 66.66MHz, loaded outputs — — 200 ps PLL Lock Time Stable power supply, valid clock presented on REF pin — — 1 ms tLOCK (2) NOTES: 1. REF Input has a threshold voltage of VDD/2. 2. All parameters specified with loaded outputs. 3 IDT2309 3.3V ZERO DELAY CLOCK BUFFER COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES (1,2) SWITCHING CHARACTERISTICS (2309-1H) - COMMERCIAL Symbol Min. Typ. Max. Unit Output Frequency 10pF Load 30pF Load 10 10 — — 133 100 MHz Duty Cycle = t2 ÷ t1 Measured at 1.4V, FOUT = 66.66MHz 40 50 60 % Duty Cycle = t2 ÷ t1 Measured at 1.4V, FOUT <50MHz 45 50 55 % t3 Rise Time Measured between 0.8V and 2V — — 1.5 ns t4 Fall Time Measured between 0.8V and 2V — — 1.5 ns t5 Output to Output Skew All outputs equally loaded — — 250 ps t6A Delay, REF Rising Edge to CLKOUT Rising Edge Measured at VDD/2 — 0 ±350 ps t6B Delay, REF Rising Edge to CLKOUT Rising Edge Measured at VDD/2 in PLL bypass mode (IDT2309 only) 1 5 8.7 ns t7 Device-to-Device Skew Measured at VDD/2 on the CLKOUT pins of devices — 0 700 ps t8 Output Slew Rate Measured between 0.8V and 2V using Test Circuit 2 1 — — V/ns tJ Cycle-to-Cycle Jitter Measured at 66.66MHz, loaded outputs — — 200 ps PLL Lock Time Stable power supply, valid clock presented on REF pin — — 1 ms t1 tLOCK Parameter Conditions NOTES: 1. REF Input has a threshold voltage of VDD/2. 2. All parameters specified with loaded outputs. DC ELECTRICAL CHARACTERISTICS - INDUSTRIAL Symbol Parameter Conditions Min. Max. Unit VIL Input LOW Voltage Level — 0.8 V VIH Input HIGH Voltage Level 2 — V IIL Input LOW Current VIN = 0V — 50 µA IIH Input HIGH Current VIN = VDD VOL Output LOW Voltage Standard Drive VOH Output HIGH Voltage IDD_PD IDD IOL = 8mA High Drive IOL = 12mA (-1H) Standard Drive IOH = -8mA High Drive IOH = -12mA (-1H) — 100 µA — 0.4 V 2.4 — V Power Down Current REF = 0MHz (S2 = S1 = H) — 25 µA Supply Current Unloaded Outputs at 66.66MHz, SEL inputs at VDD or GND — 35 mA OPERATING CONDITIONS - INDUSTRIAL Symbol Parameter Min. Max. Unit 3 3.6 V VDD Supply Voltage TA Operating Temperature (Ambient Temperature) -40 +85 °C CL Load Capacitance < 100MHz — 30 pF Load Capacitance 100MHz - 133MHz — 10 Input Capacitance — 7 CIN 4 pF IDT2309 3.3V ZERO DELAY CLOCK BUFFER COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES (1,2) SWITCHING CHARACTERISTICS (2309-1) - INDUSTRIAL Symbol t1 Parameter Output Frequency Conditions Min. Typ. Max. Unit 10pF Load 10 — 133 MHz 30pF Load 10 — 100 Duty Cycle = t2 ÷ t1 Measured at 1.4V, FOUT = 66.66MHz 40 50 60 % t3 Rise Time Measured between 0.8V and 2V — — 2.5 ns t4 Fall Time Measured between 0.8V and 2V — — 2.5 ns t5 Output to Output Skew All outputs equally loaded — — 250 ps t6A Delay, REF Rising Edge to CLKOUT Rising Edge Measured at VDD/2 — 0 ±350 ps t6B Delay, REF Rising Edge to CLKOUT Rising Edge Measured at VDD/2 in PLL bypass mode (IDT2309 only) 1 5 8.7 ns t7 Device-to-Device Skew Measured at VDD/2 on the CLKOUT pins of devices — 0 700 ps tJ Cycle-to-Cycle Jitter Measured at 66.66MHz, loaded outputs — — 200 ps PLL Lock Time Stable power supply, valid clock presented on REF pin — — 1 ms tLOCK NOTES: 1. REF Input has a threshold voltage of VDD/2. 2. All parameters specified with loaded outputs. (1,2) SWITCHING CHARACTERISTICS (2309-1H) - INDUSTRIAL Symbol t1 Min. Typ. Max. Unit Output Frequency Parameter 10pF Load 30pF Load Conditions 10 10 — — 133 100 MHz Duty Cycle = t2 ÷ t1 Measured at 1.4V, FOUT = 66.66MHz 40 50 60 % Duty Cycle = t2 ÷ t1 Measured at 1.4V, FOUT <50MHz 45 50 55 % t3 Rise Time Measured between 0.8V and 2V — — 1.5 ns t4 Fall Time Measured between 0.8V and 2V — — 1.5 ns t5 Output to Output Skew All outputs equally loaded — — 250 ps t6A Delay, REF Rising Edge to CLKOUT Rising Edge Measured at VDD/2 — 0 ±350 ps t6B Delay, REF Rising Edge to CLKOUT Rising Edge Measured at VDD/2 in PLL bypass mode (IDT2309 only) 1 5 8.7 ns t7 Device-to-Device Skew Measured at VDD/2 on the CLKOUT pins of devices — 0 700 ps t8 Output Slew Rate Measured between 0.8V and 2V using Test Circuit 2 1 — — V/ns tJ Cycle-to-Cycle Jitter Measured at 66.66MHz, loaded outputs — — 200 ps PLL Lock Time Stable power supply, valid clock presented on REF pin — — 1 ms tLOCK NOTES: 1. REF Input has a threshold voltage of VDD/2. 2. All parameters specified with loaded outputs. 5 IDT2309 3.3V ZERO DELAY CLOCK BUFFER COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES ZERO DELAY AND SKEW CONTROL All outputs should be uniformly loaded in order to achieve Zero I/O Delay. Since the CLKOUT pin is the internal feedback for the PLL, its relative loading can affect and adjust the input/output delay. The Output Load Difference diagram illustrates the PLL's relative loading with respect to the other outputs that can adjust the Input-Output (I/O) Delay. For designs utilizing zero I/O Delay, all outputs including CLKOUT must be equally loaded. Even if the output is not used, it must have a capacitive load equal to that on the other outputs in order to obtain true zero I/O Delay. If I/O Delay adjustments are needed, use the Output Load Difference diagram to calculate loading differences between the CLKOUT pin and other outputs. For zero output-to-output skew, all outputs must be loaded equally. REF TO CLKA/CLKB RELAY vs. OUTPUT LOAD DIFFERENCE BETWEEN CLKOUT PIN AND CLKA/CLKB PINS 1500 REF to CLKA/CLKB Delay (ps) 1000 500 0 -30 -25 -20 -15 -10 -5 0 5 10 15 -500 -1000 -1500 OUTPUT LOAD DIFFERENCE BETWEEN CLKOUT PIN AND CLKA/CLKB PINS (pF) 6 20 25 30 IDT2309 3.3V ZERO DELAY CLOCK BUFFER COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES SWITCHING WAVEFORMS t1 1.4V Output t2 1.4V 1.4V 1.4V 1.4V Output t5 Output to Output Skew Duty Cycle Timing Output 0.8V 2V 2V 3.3V 0.8V V DD/2 R EF 0V t4 t3 V DD/2 Output t6 Input to Output Propagation Delay All Outputs Rise/Fall Time CLK OU T V DD /2 Device 1 CLK OU T Device 2 V DD /2 t7 Device to Device Skew TEST CIRCUITS V DD V DD 0.1 F OUTPUTS CLK OUT 0.1 F 1K CLK OUT OUTPUTS C LOAD 10pF 1K V DD V DD 0.1 F 0.1 F GND GND GND GND Test Circuit 2 (t8, Output Slew Rate On -1H Devices) Test Circuit 1 (all Parameters Except t8) 7 IDT2309 3.3V ZERO DELAY CLOCK BUFFER COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES TYPICAL DUTY CYCLE(1) AND IDD TRENDS(2) FOR IDT2309-1 Duty Cycle vs V DD (for 30pf loads over frequency - 3.3V, 25C) Duty C ycle vs V D D (for 10pF loads over freque ncy - 3.3V, 25C) 60 58 58 56 56 54 54 Duty Cycle (% ) Duty Cycle (% ) 60 52 33MH z 66MH z 100M H z 50 48 52 48 46 46 44 44 42 42 40 33M H z 66M H z 100M Hz 133M Hz 50 40 3 3.1 3.2 3.3 3.4 3.5 3 3.6 3.1 3.2 V DD (V) 3.5 3.6 D uty C ycle vs Frequ ency (for 10pF loads ove r tem perature - 3.3 V) 60 60 58 58 56 56 Duty Cycle (% ) Duty Cycle (% ) 3.4 V DD (V) Duty Cycle vs Frequency (for 30pf loads over temperature - 3.3V) 54 52 -40C 50 0C 25C 70C 85C 48 54 52 -40C 50 0C 25C 70C 85C 48 46 46 44 44 42 42 40 40 20 40 60 80 100 120 140 20 40 60 Frequency (MHz) 80 100 120 140 Frequency (MHz) ID D vs Number of Loaded Outputs (for 30pf loads over frequency - 3.3V, 25C) I D D vs Nu mb er of Loa ded O utputs (for 10pF load s over frequency - 3.3V, 2 5C) 140 140 120 120 100 100 80 I DD (mA) I D D (mA) 3.3 33MH z 66MH z 100M H z 60 80 60 40 40 20 20 0 33MH z 66MH z 100M H z 0 0 2 4 6 8 0 Number of Loaded Outputs 2 4 6 Number of Loaded Outputs NOTES: 1. Duty Cycle is taken from typical chip measured at 1.4V. 2. IDD data is calculated from IDD = ICORE + nCVf, where ICORE is the unloaded current. (n = Number of outputs; C = Capacitance load per output (F); V = Supply Voltage (V); f = Frequency (Hz)) 8 8 IDT2309 3.3V ZERO DELAY CLOCK BUFFER COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES TYPICAL DUTY CYCLE(1) AND IDD TRENDS(2) FOR IDT2309-1H Duty Cycle vs V D D (for 30pf loads over frequency - 3.3V, 25C) Duty Cycle vs V D D (for 10pF loads over frequency - 3.3V, 25C) 60 58 58 56 56 54 54 Duty Cycle (% ) Duty Cycle (% ) 60 52 33M H z 50 66M H z 100M Hz 48 52 33M H z 50 48 46 46 44 44 42 42 40 66M H z 100M H z 133M H z 40 3 3.1 3.2 3.3 3.4 3.5 3 3.6 3.1 3.2 V DD (V) 3.5 3.6 Duty Cycle vs Frequen cy (for 10pF loads ove r tem perature - 3.3V) 60 60 58 58 56 56 Duty Cycle (% ) Duty Cycle (% ) 3.4 V DD (V) Duty Cycle vs Frequency (for 30pf loads over tem perature - 3.3V) 54 52 -40C 50 0C 25C 70C 85C 48 54 52 -40C 0C 25C 70C 85C 50 48 46 46 44 44 42 42 40 40 20 40 60 80 100 120 140 20 40 60 Frequency (M Hz) 80 100 120 140 Frequency (M Hz) I DD vs Num ber of Loaded Outputs (for 30pf loads over frequency - 3.3V, 25C) I D D vs Nu m ber of Loade d O utputs (for 10pF load s over freque ncy - 3.3V, 2 5C) 160 160 140 140 120 120 100 100 80 I DD (m A) I DD (mA) 3.3 33M H z 66M H z 100M Hz 60 80 33M H z 66M H z 100M H z 60 40 40 20 20 0 0 0 2 4 6 0 8 2 4 6 8 Num ber of Loaded Outputs Num ber of Loaded Outputs NOTES: 1. Duty Cycle is taken from typical chip measured at 1.4V. 2. IDD data is calculated from IDD = ICORE + nCVf, where ICORE is the unloaded current. (n = Number of outputs; C = Capacitance load per output (F); V = Supply Voltage (V); f = Frequency (Hz)) 9 IDT2309 3.3V ZERO DELAY CLOCK BUFFER COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES ORDERING INFORMATION IDT XXXXX Device Type XX Package X Process Ordering Code Blank I Commercial (0oC to +70oC) Industrial (-40oC to +85oC) DC DCG PG PGG Small Outline SOIC - Green Thin Shrink Small Outline Package TSSOP - Green 2309-1 2309-1H Zero Delay Clock Buffer High Drive Output Package Type Operating Range IDT2309-1DCG 16-Pin SOIC Commercial IDT2309-1DCGI 16-Pin SOIC Industrial IDT2309-1HDCG 16-Pin SOIC Commercial IDT2309-1HDCGI 16-Pin SOIC Industrial IDT2309-1HPG 16-Pin TSSOP Commercial IDT2309-1HPGG 16-Pin TSSOP Commercial IDT2309-1HPGI 16-Pin TSSOP Industrial IDT2309-1HPGGI 16-Pin TSSOP Industrial CORPORATE HEADQUARTERS 6024 Silver Creek Valley Road San Jose, CA 95138 for SALES: 800-345-7015 or 408-284-8200 fax: 408-284-2775 www.idt.com 10 for Tech Support: [email protected]