Holt HI-8585CDT Arinc 429 lin driver Datasheet

HI-8585, HI-8586
ARINC 429 LINE DRIVER
January 2001
DESCRIPTION
PIN CONFIGURATION
The HI-8585 and HI-8586 are CMOS integrated circuits
designed to directly drive the ARINC 429 bus in an 8 pin
package. Two logic inputs control a differential voltage
between the output pins producing a +10 volt One, a
-10 volt Zero, and a 0 volt Null.
The CMOS/TTL control inputs are translated to ARINC
specified amplitudes using on board zeners. A logic input
is provided to control the slope of the differential output
signal. Timing is set by on-chip resistor and capacitor and
tested to be within ARINC requirements.
The HI-8585 has 37.5 ohms in series with each line driver
output. The HI-8586 provides the option to bypass most
of the output resistance so that series protection circuits
can add their resistances.
The HI-8585 or the HI-8586 along with the HI-8588 line
receiver offer the smallest options available to get on and
off the ARINC bus.
SLP1.5 1
On-chip zener to set output levels
!
!
!
Low current 12 to 15 volt supplies
!
!
7 TXBOUT
TX1IN 3
6 TXAOUT
5 V-
SUPPLY VOLTAGES
V+ = 12V to 15V
V- = -12V to -15V
FUNCTION TABLE
TX1IN
TX0IN
SLP1.5
TXAOUT
TXBOUT
SLOPE
0
0
X
0V
0V
N /A
0
1
0
-5V
5V
10µs
0
1
1
-5V
5V
1.5µs
1
0
0
5V
-5V
10µs
1
0
1
5V
-5V
1.5µs
1
1
X
0V
0V
N /A
Direct ARINC 429 line driver
interface in a small package
!
!
TX0IN 2
GND 4
FEATURES
!
8 V+
On-chip line driver slope control and
selection by logic input
CMOS / TTL logic pins
P IN
Plastic and ceramic package options surface mount and DIP
Themally enhanced SOIC packages
Mil processing available
(DS8585 Rev. D)
PIN DESCRIPTION TABLE
SYM B O L
FUNCTION
DESCRIP T ION
1
SLP1.5
LOGIC INPUT
CMOS OR TTL, V+ IS OK
2
TX0IN
LOGIC INPUT
CMOS OR TTL
3
TX1IN
LOGIC INPUT
CMOS OR TTL
4
GND
POWER
GROUND
5
V-
POWER
-12 TO -15 VOLTS
6
TXAOUT
LOGIC OUTPUT
LINE DRIVER TERMINAL A
7
TXBOUT
LOGIC OUTPUT
LINE DRIVER TERMINAL B
8
V+
POWER
+12 TO +15 VOLTS
HOLT INTEGRATED CIRCUITS
1
01/01
HI-8585, HI-8586
FUNCTIONAL DESCRIPTION
Figure 1 is a block diagram of the line driver. The +5V and
-5V levels are generated internally using on-chip zeners.
Currents for slope control are set by zener voltages across
on-chip resistors.
A unity gain buffer receives the internally generated slopes
and differentially drives the ARINC line. Current is limited
by the series output resistors at each pin. There are no
fuses at the outputs of the HI-8585 as exists on the HI-8382.
The TX0IN and TX1IN inputs receive logic signals from a
control transmitter chip such as the HI-6010 or HI-8282.
TXAOUT and TXBOUT hold each side of the ARINC bus at
Ground until one of the inputs becomes a One. If for example TX1IN goes high, a charging path is enabled to 5V on an
“A” side internal capacitor while the “B” side is enabled to
-5V. The charging current is selected by the SLP1.5 pin. If
the SLP1.5 pin is high, the capacitor is nominally charged
from 10% to 90% in 1.5µs. If SLP1.5 is low, the rise and fall
times are 10µs.
The HI-8585 has 37.5 ohms in series with each output. The
HI-8586 has 10 ohms in series. The HI-8586 is for applications where more series resistance is added externally,
typically for lightning protection devices.
5V
“A” SIDE
ONE
TXAOUT
CURRENT
CONTROL
NULL
HI-8585 = 37.5 OHMS
HI-8556 = 10.0 OHMS
ZERO
-5V
ESD
PROTECTION
AND
VOLTAGE
TRANSLATION
CONTROL
LOGIC
SLP1.5
5V
“B” SIDE
ONE
TXBOUT
CURRENT
CONTROL
NULL
HI-8585 = 37.5 OHMS
HI-8586 = 10.0 OHMS
ZERO
CONTROL
LOGIC
-5V
FIGURE 1 - LINE DRIVER BLOCK DIAGRAM
APPLICATION INFORMATION
1
Figure 2 shows a possible application
of the HI-8585/86 interfacing an ARINC
transmit channel from the HI-6010.
2
6
8
7
4
3
5
1
8
6
2
7
3
4
5
FIGURE 2 - APPLICATION DIAGRAM
HOLT INTEGRATED CIRCUITS
2
HI-8585, HI-8586
RECOMMENDED OPERATING CONDITIONS
ABSOLUTE MAXIMUM RATINGS
Supply Voltages
V+....................+12V ± 5% or +15V ±10%
V-..................... -12V ± 5% or -15V ±10%
Voltages referenced to Ground
Supply voltages
V+....................................................20V
V-....................................................-20V
Temperature Range
Industrial Screening.........-40°C to +85°C
Hi-Temp Screening........-55°C to +125°C
Military Screening..........-55°C to +125°C
DC current per input pin................ +10mA
Power dissipation at 25°C
plastic DIL............1.0W, derate 10mW/°C
ceramic DIL..........0.5W, derate 7mW/°C
NOTE: Stresses above absolute maximum
ratings or outside recommended operating
conditions may cause permanent damage to
the device. These are stress ratings only.
Operation at the limits is not recommended.
Solder Temperature ........275°C for 10 sec
Storage Temperature........-65°C to +150°C
DC ELECTRICAL CHARACTERISTICS
V+ = +12V to +15V, V- = -12V to -15V, TA = Operating Temperature Range (unless otherwise stated)
PARAMETERS
SYMBOL
Input voltage (TX1IN, TX0IN, SLP1.5)
high
low
VIH
VIL
Input current (TX1IN, TX0IN, SLP1.5)
source
sink
IIH
IIL
TEST CONDITIONS
VIN = 0V
VIN = 5V
MIN
TYP
MAX
UNITS
2.1
-
-
V+
0.5
volts
volts
-
-
0.1
0.1
µA
µA
10.00
-10.00
0
11.00
-9.00
0.50
volts
volts
volts
ARINC output voltage (Differential)
one
zero
null
VDIFF1
VDIFF0
VDIFFN
no load; TXAOUT - TXBOUT 9.00
no load; TXAOUT - TXBOUT -11.00
no load; TXAOUT - TXBOUT -0.50
ARINC output voltage (Ref. to GND)
one or zero
null
VDOUT
VNOUT
no load & magnitude at pin
no load
4.50
-0.25
5.00
0
5.50
0.25
volts
volts
SLP1.5 = V+
TX1IN & TX0IN = 0V: no load
TX0IN & TX1IN = 0V: no load
-14.0
6.0
-6.0
14.0
-
mA
mA
-
37.5
10
-
ohms
ohms
Operating supply current
V+
VARINC output impedence
HI-8585
HI-8586
IDD
IEE
ZOUT
Note1
NOTE :
1. The output resistance is checked by measuring the momentary short circuit current at each ARINC output pin.
HOLT INTEGRATED CIRCUITS
3
HI-8585, HI-8586
A
defined in Figure 3, no load
pin 1 = logic 1
pin 1 = logic 1
Notes:
1. Guaranteed but not tested
PACKAGE THERMAL CHARACTERISTICS
M AXIM U M ARINC LOAD
PACKAGE STYLE
ARINC 429
DATA RATE
1
8 Le a d Plastic DIP
8 Le a d Pla stic SOIC
5
8 Le a d Pla stic SOIC 6
9
SUPPLY CURRENT (mA) 2
JUNCTION TEMP, Tj (°C)
Ta = 25 oC
Ta = 85 oC
Ta=125 oC
Ta = 25 oC
Ta = 85 oC
Ta=125 oC
Low Speed
3
16.8
17.2
16.9
58
116
157
High Speed
4
27.3
26.7
25.9
75
132
169
Low Speed
17.4
17.5
16.9
68
126
166
High Speed
27.6
27.1
25.9
97
147
186
Low Speed
17.1
17.2
16.7
52
110
151
High Speed
27.3
27.1
26.2
57
112
157
TXAOUT and TXBOUT Shorted to Ground 7, 8, 9
PACKAGE STYLE
ARINC 429
DATA RATE
1
8 Le a d Plastic DIP
8 Le a d Pla stic SOIC
5
8 Le a d Pla stic SOIC 6
SUPPLY CURRENT (mA) 2
o
o
o
JUNCTION TEMP, Tj (°C)
Ta = 25 C
Ta = 85 C
Ta=125 C
Ta = 25 oC
Ta = 85 oC
Ta=125 oC
Low Speed
3
53.6
50.7
52.2
131
181
217
High Speed
Low Speed
4
46.9
38.7
42.5
135
181
219
46.4
47.6
68.1
167
191
221
High Speed
42.1
43.8
67.1
177
212
223
Low Speed
48.5
45.6
46.1
112
161
186
High Speed
46.8
41.1
40.5
116
168
197
Notes:
1. All data taken in still air on devices soldered to single layer copper PCB (3" X 4.5" X .062").
2. At 100% duty cycle, 15V power supplies. For 12V power supplies multiply all tabulated values by 0.8.
3. Low Speed: Data Rate = 12.5 Kbps, Load: R = 400 Ohms, C = 30 nF.
4. High Speed: Data Rate = 100 Kbps, Load: R = 400 Ohms, C = 10 nF. Data not presented for C = 30 nF
as this is considered unrealistic for high speed operation.
5. 8 Lead Plastic SOIC (Thermally enhanced with built in heat sink). Heat sink not soldered to the PCB.
6. 8 Lead Plastic SOIC (Thermally enhanced with built in heat sink). Heat sink soldered to the PCB.
7. Similar results would be obtained with TXAOUT shorted to TXBOUT.
8. For applications requiring survival with continuous short circuit, operation above Tj = 175°C is not recommended.
9. Data will vary depending on air flow and the method of heat sinking employed.
HOLT INTEGRATED CIRCUITS
4
HI-8585, HI-8586
5V
0V
pin 3
t phlx
t plhx
t plhx
5V
0V
pin 2
t phlx
t rx
t rx
10V
0V
-10V
90%
DIFF
10%
10%
90%
10%
t fx
t fx
FIGURE 3 - LINE DRIVER TIMING
PART
PACKAGE
TEMPERATURE
BURN
LEAD
NUMBER
HI-8585PDI
HI-8585PDT
HI-8585PSI
HI-8585PST
HI-8585CDI
HI-8585CDT
HI-8585CDM
HI-8585CRI
HI-8585CRT
HI-8585CRM
DESCRIPTION
8 PIN PLASTIC DIP
8 PIN PLASTIC DIP
8 PIN PLASTIC ESOIC - NB
8 PIN PLASTIC ESOIC - NB
8 PIN CERAMIC SIDE BRAZED DIP
8 PIN CERAMIC SIDE BRAZED DIP
8 PIN CERAMIC SIDE BRAZED DIP
8 PIN CERDIP
8 PIN CERDIP
8 PIN CERDIP
RANGE
-40°C TO +85°C
-55°C TO +125°C
-40°C TO +85°C
-55°C TO +125°C
-40°C TO +85°C
-55°C TO +125°C
-55°C TO +125°C
-40°C TO +85°C
-55°C TO +125°C
-55°C TO +125°C
FLOW
I
T
I
T
I
T
M
I
T
M
IN
NO
NO
NO
NO
NO
NO
YES
NO
NO
YES
FINISH
SOLDER
SOLDER
SOLDER
SOLDER
GOLD
GOLD
SOLDER
SOLDER
SOLDER
SOLDER
HI-8586PDI
HI-8586PDT
HI-8586PSI
HI-8586PST
HI-8586CDI
HI-8586CDT
HI-8586CDM
HI-8586CRI
HI-8586CRT
HI-8586CRM
8 PIN PLASTIC DIP
8 PIN PLASTIC DIP
8 PIN PLASTIC ESOIC - NB
8 PIN PLASTIC ESOIC - NB
8 PIN CERAMIC SIDE BRAZED DIP
8 PIN CERAMIC SIDE BRAZED DIP
8 PIN CERAMIC SIDE BRAZED DIP
8 PIN CERDIP
8 PIN CERDIP
8 PIN CERDIP
-40°C TO +85°C
-55°C TO +125°C
-40°C TO +85°C
-55°C TO +125°C
-40°C TO +85°C
-55°C TO +125°C
-55°C TO +125°C
-40°C TO +85°C
-55°C TO +125°C
-55°C TO +125°C
I
T
I
T
I
T
M
I
T
M
NO
NO
NO
NO
NO
NO
YES
NO
NO
YES
SOLDER
SOLDER
SOLDER
SOLDER
GOLD
GOLD
SOLDER
SOLDER
SOLDER
SOLDER
Legend: ESOIC - Thermally Enhanced Small Outline Package (SOIC w/built-in heat sink)
NB
- Narrow Body
HOLT INTEGRATED CIRCUITS
5
HI-8585 / HI-8586 PACKAGE DIMENSIONS
inches (millimeters)
8-PIN PLASTIC SMALL OUTLINE (ESOIC) - NB
(Narrow Body, Thermally Enhanced)
Top View
Bottom View
.1935 ± .0035
(4.915 ± .085)
.236 ± .008
(5.994 ± .203)
PIN 1
Package Type: 8HNE
.0085 ± .0015
(.2159 ± .0381)
.140 ± .010
(3.556 ± .254)
.100 ± .010
(2.540 ± .254)
.1535 ± .0035
(3.90 ± .09)
Heat sink stud
on bottom of
package
DETAIL A
.0165 ± .0035
(.4191 ± .0889)
.055 ± .005
(1.397 ± .127)
0° to 8°
.0025 ± .0015
(.0635 ± .0381)
.033 ± .017
(.8382 ± .4318)
.050 ± .010
(1.27 ± .254)
DETAIL A
8-PIN PLASTIC DIP
Package Type: 8P
.385 ± .015
(4.699 ± .381)
.250 ± .010
(6.350 ± .254)
.100 ± .010
(3.540 ± .254)
.300 ± .010
(7.620 ± .254)
7° TYP.
.135 ± .015
(3.429 ± .381)
.1375 ± .0125
(3.493 ± .318)
.025 ± .010
(.635 ± .254)
.0115 ± .0035
(.292 ± .089)
.019 ± .002
(.483 ± .102)
.055 ± .010
(1.397 ± .254)
HOLT INTEGRATED CIRCUITS
6
.335 ± .035
(8.509 ± .889)
HI-8585 / HI-8586 PACKAGE DIMENSIONS
inches (millimeters)
8-PIN CERAMIC SIDE-BRAZED DIP
Package Type: 8C
.405 ± MAX
(10.287 ± MAX)
.050 ± .007
(1.270 ± .178)
.250 ± .008
(7.366 ± .203)
.050 ± .005
(1.270 ± .127)
PIN 1
.200 MAX
(5.080 MAX)
.035 ± .010
(.889 ± .254)
BASE
PLANE
.163 ± .037
(4.140 ± .940)
.0105 ± .0015
(.267 ± .038)
SEATING
PLANE
.018 ± .002
(.457 ± .051)
.100 ± .003
(2.540 ± .076)
.300 ± .010
(7.620 ± .254)
8-PIN CERDIP
Package Type: 8D
.380 ± .004
(9.652 ± .102)
.005 MIN.
(.127 MIN.)
.248 ± .003
(6.299 ± .076)
.039 ± .006
(.991 ± .154)
.100 ± .008
(2.540 ± .203)
.015 MIN.
(.381 MIN.)
.200 MAX.
(5.080 MAX.)
.314 ± .003
(7.976 ± .076)
Base Plane
.010 ± .006
(.254 ± .152`)
Seating Plane
.163 ± .037
(4.140 ± .940)
.056 ± .006
(1.422 ± .152)
.018 ± .006
(.457 ± .152)
HOLT INTEGRATED CIRCUITS
7
.350 ± .030
(8.890 ± .762)
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