ICS86953I-147 Integrated Circuit Systems, Inc. LOW SKEW, 1-TO-9 DIFFERENTIAL-TO-LVCMOS / LVTTL ZERO DELAY BUFFER GENERAL DESCRIPTION FEATURES The ICS86953I-147 is a low voltage, low skew 1-to-9 Differential-to-LVCMOS/LVTTL Clock HiPerClockS™ Generator and a member of the HiPerClockS™ family of High Performance Clock Solutions from ICS. The PCLK, nPCLK pair can accept most standard differential input levels. With output frequencies up to 175MHz, the ICS86953I-147 is targeted for high performance clock applications. Along with a fully integrated PLL, the ICS86953I-147 contains frequency configurable outputs and an external feedback input for regenerating clocks with “zero delay”. • 9 single ended LVCMOS/LVTTL outputs; (8) clocks, (1) feedback ICS • PCLK, nPCLK pair can accept the following differential input levels: LVPECL, CML, SSTL • Maximum output frequency: PLL Mode, 175MHz • VCO range: 250MHz to 700MHz • Output skew: 75ps (maximum) • Cycle-to-cycle jitter: 50ps (maximum) • Static phase offset: 90ps ± 110ps • 3.3V supply voltage PIN ASSIGNMENT • -40°C to 85°C ambient operating temperature GND Q0 VDDO QFB GND PLL_SEL nBYPASS VCO_SEL • Pin compatible to the MPC953 32 31 30 29 28 27 26 25 VDDA 1 24 Q1 FB_CLK 2 23 VDDO nc 3 22 Q2 nc 4 21 GND nc 5 20 Q3 nc 6 19 VDDO GND 7 18 Q4 PCLK 8 17 GND ICS86953I-147 9 10 11 12 13 14 15 16 Q5 VDDO Q6 GND Q7 VDDO MR/nOE nPCLK 32-Lead LQFP 7mm x 7mm x 1.4mm package body Y package Top View BLOCK DIAGRAM PCLK nPCLK FB_CLK QFB 0 Phase Detector 0 0 LPF 1 VCO ÷4 ÷2 1 7 / Q0:Q6 1 Q7 VCO_SEL nBYPASS MR/nOE PLL_SEL 86953BYI-147 www.icst.com/products/hiperclocks.html 1 REV. B APRIL 23, 2004 ICS86953I-147 Integrated Circuit Systems, Inc. LOW SKEW, 1-TO-9 DIFFERENTIAL-TO-LVCMOS / LVTTL ZERO DELAY BUFFER TABLE 1. PIN DESCRIPTIONS Number Nam e Type 1 VDDA Power 2 FB_CLK Input 3, 4, 5, 6 7, 13, 17, 21, 25, 29 8 nc Unused GND Power PCLK Input Description Analog supply pin. Pullup Feedback clock input. LVCMOS / LVTTL interface levels. No connect. Power supply ground. Pullup Non-inver ting LVPECL differential clock input. Pullup/ Inver ting LVPECL differential clock input. 9 nPCLK Input Pulldown Internally biased to VDDO/2. Active HIGH Master Reset. Active LOW output enable. When logic High, the internal dividers are reset and the outputs are 10 MR/nOE Input Pulldown tri-stated (HiZ). When logic LOW, the internal dividers and the outputs are enabled. LVCMOS / LVTTL interface levels. Power Output supply pins. 11, 15, 19, 23, 27 VDDO 12, 14, 16, 18, Q7, Q6, Q5, Q4, Clock outputs. LVCMOS / LVTTL interface levels. Output 20, 22, 24, 26 Q3, Q2, Q1, Q0 14Ω typical output impedance. Feedback clock output. LVCMOS / LVTTL interface levels. 28 QFB Output 14Ω typical output impedance. Selects VCO when HIGH. When LOW, selects PCLK, 30 PLL_SEL Input Pullup nPCLK. LVCMOS / LVTTL interface levels. 31 nBYPASS Input Pullup Selects PLL when HIGH. When LOW, in Bypass mode. Selects VCO ÷2 when HIGH. Selects VCO ÷1 when LOW. 32 VCO_SEL Input Pullup LVCMOS / LVTTL interface levels. NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values. TABLE 2. PIN CHARACTERISTICS Symbol Parameter CIN Input Capacitance Test Conditions Minimum Typical Maximum 4 Units pF RPULLUP Input Pullup Resistor 51 KΩ RPULLDOWN Input Pulldown Resistor 51 KΩ CP D Power Dissipation Capacitance (per output) ROUT Output Impedance VDDA, VDDO = 3.465V 5 7 14 12 pF Ω TABLE 3A. OUTPUT CONTROL PIN FUNCTION TABLE Input Outputs MR/nOE QFB, Q0:Q7 1 HiZ 0 Enabled TABLE 3B. PROGRAMMABLE OUTPUT FREQUENCY FUNCTION TABLE Inputs Operation Outputs Bypass PLL_SEL VCO_SEL 0 X X Test Mode: PLL and divider bypass CL K 1 0 0 Test Mode: PLL bypass CLK/4 1 0 1 Test Mode: PLL bypass CLK/8 1 1 0 PLL Mode VCO/4 1 1 1 PLL Mode VCO/8 86953BYI-147 QFB, Q0:Q7 www.icst.com/products/hiperclocks.html 2 REV. B APRIL 23, 2004 ICS86953I-147 Integrated Circuit Systems, Inc. LOW SKEW, 1-TO-9 DIFFERENTIAL-TO-LVCMOS / LVTTL ZERO DELAY BUFFER ABSOLUTE MAXIMUM RATINGS Supply Voltage, VDD 4.6V Inputs, VI -0.5V to VDD + 0.5 V Outputs, VO -0.5V to VDDO + 0.5V Package Thermal Impedance, θJA 47.9°C/W (0 lfpm) Storage Temperature, TSTG -65°C to 150°C NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VDDA = VDDO = 3.3V±5%, TA = -40°C TO 85°C Symbol VDDA VDDO IDDA IDDO Parameter Analog Supply Voltage Output Supply Voltage Analog Supply Current Output Supply Current Test Conditions Minimum 3.135 3.135 Typical 3.3 3.3 Maximum 3.465 3.465 20 75 Units V V mA mA Maximum Units 2 VDD + 0.3 V 2 VDD + 0.3 V -0.3 0.8 V -0.3 1.3 V ±120 µA TABLE 4B. LVCMOS / LVTTL DC CHARACTERISTICS, VDDA = VDDO = 3.3V±5%, TA = -40°C TO 85°C Symbol VIH VIL Parameter Input High Voltage Input Low Voltage Test Conditions VCO_SEL, nBYPASS, PLL_SEL, MR/nOE FB_CLK VCO_SEL, nBYPASS, PLL_SEL, MR/nOE FB_CLK IIN Input Current VOH Output High Voltage; NOTE 1 IOH = -20mA VOL Output Low Voltage; NOTE 1 IOL = 20mA Minimum Typical VDD - 0.6 V 0.6 V NOTE: Outputs terminated with 50Ω to VDDO/2. See Parameter Measurement section, "3.3V Output Load Test Circuit". TABLE 4C. LVPECL DC CHARACTERISTICS, VDDA = VDDO = 3.3V±5%, TA = -40°C TO 85°C Symbol Parameter IIN Input Current V PP Peak-to-Peak Input Voltage Test Conditions Minimum Typical 0.15 Common Mode Input Voltage; NOTE 1, 2 GND + 0.5 VCMR NOTE 1: Common mode voltage is defined as VIH. NOTE 2: For single ended applications, the maximum input voltage for PCLK, nPCLK is VDD + 0.3V. 86953BYI-147 www.icst.com/products/hiperclocks.html 3 Maximum Units ±120 µA 1.3 V VDD - 0.85 V REV. B APRIL 23, 2004 ICS86953I-147 Integrated Circuit Systems, Inc. LOW SKEW, 1-TO-9 DIFFERENTIAL-TO-LVCMOS / LVTTL ZERO DELAY BUFFER TABLE 5. PLL INPUT REFERENCE CHARACTERISTICS, VDDA = VDDO = 3.3V±5%, TA = -40°C TO 85°C Symbol Parameter fREF Input Reference Frequency Test Conditions Minimum Typical Maximum Units 175 MHz Maximum Units 87.5 MHz TABLE 6. AC CHARACTERISTICS, VDDA = VDDO = 3.3V±5%, TA = -40°C TO 85°C Symbol fMAX Parameter Output Frequency Test Conditions Minimum PLL Mode VCO_SEL = 1 31.25 PLL Mode VCO_SEL = 0 62.50 Typical Bypass Mode tPD Propagation Delay; NOTE 1 tsk(o) Output Skew; NOTE 2, 4 tjitter(cc) Cycle-to-Cycle Jitter; NOTE 5 t(Ø) Static Phase Offset; NOTE 3, 5 tR / tF Output Rise/Fall Time PCLK, nPCLK 2.5 Measured on rising edge at VDD/2 -20 20% to 80% 90 100 47 50 175 MHz 200 MHz 4 ns 75 ps 50 ps 200 ps 700 ps odc Output Duty Cycle 53 % tLOCK PLL Lock Time 10 ms t EN Output Enable Time; NOTE 4 6 ns Output Disable Time; NOTE 4 7 tDIS NOTE: Termination of 50Ω to VDD/2. NOTE 1: Measured from the differential input crossing point to VDDO/2 of the output. NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at VDDO/2. NOTE 3: Defined as the time difference between the input reference clock and the average feedback input signal when the PLL is locked and the input reference frequency is stable. NOTE 4: These parameters are guaranteed by characterization. Not tested in production. NOTE 5: This parameter is defined in accordance with JEDEC Standard 65. 86953BYI-147 www.icst.com/products/hiperclocks.html 4 ns REV. B APRIL 23, 2004 ICS86953I-147 Integrated Circuit Systems, Inc. LOW SKEW, 1-TO-9 DIFFERENTIAL-TO-LVCMOS / LVTTL ZERO DELAY BUFFER PARAMETER MEASUREMENT INFORMATION 1.65V±5% V DD SCOPE VDDA, VDDO nPCLK Qx LVCMOS V Cross Points PP V CMR PCLK GND GND -1.65V±5% 3.3V OUTPUT LOAD AC TEST CIRCUIT V V DDO Q0:Q7, QFB DIFFERENTIAL INPUT LEVEL V DDO 2 ➤ tcycle ➤ n V DDO 2 DDO 2 tcycle n+1 Qx 2 ➤ ➤ V DDO t jit(cc) = tcycle n –tcycle n+1 Qy 2 t sk(o) 1000 Cycles CYCLE-TO-CYCLE JITTER OUTPUT SKEW nPCLK 80% 80% PCLK Clock Outputs 20% 20% tR tF VDDO 2 t Q0:Q7, QFB PD OUTPUT RISE/FALL TIME PROPAGATION DELAY nPCLK VOH PCLK VOL V DDO Q0:Q7 QFB 2 Pulse Width t VOH VDDO PERIOD 2 FB_CLK ➤ t (Ø) t PW ➤ odc = VOL tjit(Ø) = t (Ø) — t (Ø) mean = Phase Jitter t PERIOD (where t (Ø) is any random sample, and t (Ø) mean is the average of the sampled cycles measured on controlled edges) OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD 86953BYI-147 PHASE JITTER & STATIC PHASE OFFSET www.icst.com/products/hiperclocks.html 5 REV. B APRIL 23, 2004 Integrated Circuit Systems, Inc. ICS86953I-147 LOW SKEW, 1-TO-9 DIFFERENTIAL-TO-LVCMOS / LVTTL ZERO DELAY BUFFER APPLICATION INFORMATION WIRING THE DIFFERENTIAL INPUT TO ACCEPT SINGLE ENDED LEVELS Figure 1 shows how the differential input can be wired to accept single ended levels. The reference voltage V_REF = VDD/2 is generated by the bias resistors R1, R2 and C1. This bias circuit should be located as close as possible to the input pin. The ratio of R1 and R2 might need to be adjusted to position the V_REF in the center of the input voltage swing. For example, if the input clock swing is only 2.5V and VDD = 3.3V, V_REF should be 1.25V and R2/R1 = 0.609. VDD R1 1K Single Ended Clock Input PCLK V_REF nPCLK C1 0.1u R2 1K FIGURE 1. SINGLE ENDED SIGNAL DRIVING DIFFERENTIAL INPUT POWER SUPPLY FILTERING TECHNIQUES As in any high speed analog circuitry, the power supply pins are vulnerable to random noise. The ICS86953I-147 provides separate power supplies to isolate any high switching noise from the outputs to the internal PLL. VDDA and VDDO should be individually connected to the power supply plane through vias, and bypass capacitors should be used for each pin. To achieve optimum jitter performance, power supply isolation is required. Figure 2 illustrates how a 10Ω resistor along with a 10µF and a .01µF bypass capacitor should be connected to each VDDA pin. 3.3V VDDO .01µF 10Ω VDDA .01µF 10 µF FIGURE 2. POWER SUPPLY FILTERING 86953BYI-147 www.icst.com/products/hiperclocks.html 6 REV. B APRIL 23, 2004 ICS86953I-147 Integrated Circuit Systems, Inc. LOW SKEW, 1-TO-9 DIFFERENTIAL-TO-LVCMOS / LVTTL ZERO DELAY BUFFER PCLK/nPCLK CLOCK INPUT INTERFACE gested here are examples only. If the driver is from another vendor, use their termination recommendation. Please consult with the vendor of the driver component to confirm the driver termination requirements. The PCLK/ nPCLK accepts LVPECL, CML, SSTL and other differential signals. Both VSWING and VOH must meet the VPP and VCMR input requirements. Figures 3A to 3D show interface examples for the HiPerClockS PCLK/nPCLK input driven by the most common driver types. The input interfaces sug- 2.5V 3.3V 3.3V 3.3V 2.5V 3.3V R1 50 CML R3 120 R2 50 Zo = 60 Ohm SSTL Zo = 50 Ohm R4 120 PCLK PCLK Zo = 60 Ohm Zo = 50 Ohm nPCLK nPCLK HiPerClockS PCLK/nPCLK R1 120 FIGURE 3A. HIPERCLOCKS PCLK/NPCLK INPUT DRIVEN BY A CML DRIVER HiPerClockS PCLK/nPCLK R2 120 FIGURE 3B. HIPERCLOCKS PCLK/NPCLK INPUT DRIVEN BY AN SSTL IN DRIVER 3.3V 3.3V 3.3V 3.3V 3.3V R3 125 3.3V R4 125 Zo = 50 Ohm Zo = 50 Ohm C1 LVDS R3 1K R4 1K PCLK PCLK R5 100 Zo = 50 Ohm nPCLK LVPECL R1 84 nPCLK Zo = 50 Ohm HiPerClockS Input R1 1K R2 84 FIGURE 3C. HIPERCLOCKS PCLK/NPCLK INPUT DRIVEN BY A 3.3V LVPECL DRIVER 86953BYI-147 C2 HiPerClockS PC L K /n PC LK R2 1K FIGURE 3D. HIPERCLOCKS PCLK/NPCLK INPUT DRIVEN BY A 3.3V LVDS DRIVER www.icst.com/products/hiperclocks.html 7 REV. B APRIL 23, 2004 ICS86953I-147 Integrated Circuit Systems, Inc. LOW SKEW, 1-TO-9 DIFFERENTIAL-TO-LVCMOS / LVTTL ZERO DELAY BUFFER LAYOUT GUIDELINE depend on the selected component types, the density of the components, the density of the traces, and the stack up of the P.C. board. The schematic of the ICS86953I-147 layout example is shown in Figure 4A. The ICS86953I-147 recommended PCB board layout for this example is shown in Figure 4B. This layout example is used as a general guideline. The layout in the actual system will VDD R10 1K R8 1K R9 1K R1 Zo = 50 36 VDDA FB_CLK nc nc nc nc GND PCLK nPCLK MR/nOE VDDO Q7 GND Q6 VDDO Q5 VCC C11 0.01u 1 2 3 4 5 6 7 8 VCO_SEL nBYPASS PLL_SEL GND QFB VDDO Q0 GND U1 R7 10 - 15 C16 10u 32 31 30 29 28 27 26 25 VDD Zo = 50 Ohm Q1 VDDO Q2 GND Q3 VDDO Q4 GND 24 23 22 21 20 19 18 17 9 10 11 12 13 14 15 16 ICS86953I-147 Zo = 50 Ohm VDD LVPECL Driv er Zo = 50 R3 50 R4 50 C6 (Option) 0.1u R5 50 R6 1K (U1-11) VDD R2 (U1-15) (U1-19) C3 0.1uF C2 0.1uF 36 (U1-23) C4 0.1uF C5 0.1uF (U1-27) C1 0.1uF FIGURE 4A. ICS86953I-147 LVCMOS ZERO DELAY BUFFER SCHEMATIC EXAMPLE 86953BYI-147 www.icst.com/products/hiperclocks.html 8 REV. B APRIL 23, 2004 ICS86953I-147 Integrated Circuit Systems, Inc. LOW SKEW, 1-TO-9 DIFFERENTIAL-TO-LVCMOS / LVTTL ZERO DELAY BUFFER The following component footprints are used in this layout example: trace delay might be restricted by the available space on the board and the component location. While routing the traces, the clock signal traces should be routed first and should be locked prior to routing other signal traces. All the resistors and capacitors are size 0603. POWER AND GROUNDING • The 50Ω output traces should have same length. Place the decoupling capacitors as close as possible to the power pins. If space allows, placement of the decoupling capacitor on the component side is preferred. This can reduce unwanted inductance between the decoupling capacitor and the power pin caused by the via. • Avoid sharp angles on the clock trace. Sharp angle turns cause the characteristic impedance to change on the transmission lines. • Keep the clock traces on the same layer. Whenever possible, avoid placing vias on the clock traces. Placement of vias on the traces can affect the trace characteristic impedance and hence degrade signal integrity. Maximize the power and ground pad sizes and number of vias capacitors. This can reduce the inductance between the power and ground planes and the component power and ground pins. • To prevent cross talk, avoid routing other signal traces in parallel with the clock traces. If running parallel traces is unavoidable, allow a separation of at least three trace widths between the differential clock trace and the other signal trace. The RC filter consisting of R7, C11, and C16 should be placed as close to the VDDA pin as possible. CLOCK TRACES AND TERMINATION Poor signal integrity can degrade the system performance or cause system failure. In synchronous high-speed digital systems, the clock signal is less tolerant to poor signal integrity than other signals. Any ringing on the rising or falling edge or excessive ring back can cause system failure. The shape of the trace and the • Make sure no other signal traces are routed between the clock trace pair. • The series termination resistors should be located as close to the driver pins as possible. GND 50 Ohm Trace C1 R7 C16 VDD R1 VCCA VIA Other signals U1 Pin 1 C11 C5 C4 R2 C2 C3 50 Ohm Trace FIGURE 4B. PCB BOARD LAYOUT FOR ICS86953I-147 86953BYI-147 www.icst.com/products/hiperclocks.html 9 REV. B APRIL 23, 2004 ICS86953I-147 Integrated Circuit Systems, Inc. LOW SKEW, 1-TO-9 DIFFERENTIAL-TO-LVCMOS / LVTTL ZERO DELAY BUFFER RELIABILITY INFORMATION TABLE 7. θJAVS. AIR FLOW TABLE FOR 32 LEAD LQFP θJA by Velocity (Linear Feet per Minute) Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards 0 200 500 67.8°C/W 47.9°C/W 55.9°C/W 42.1°C/W 50.1°C/W 39.4°C/W NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs. TRANSISTOR COUNT The transistor count for ICS86953I-147 is: 1758 86953BYI-147 www.icst.com/products/hiperclocks.html 10 REV. B APRIL 23, 2004 ICS86953I-147 Integrated Circuit Systems, Inc. PACKAGE OUTLINE - Y SUFFIX LOW SKEW, 1-TO-9 DIFFERENTIAL-TO-LVCMOS / LVTTL ZERO DELAY BUFFER FOR 32 LEAD LQFP TABLE 8. PACKAGE DIMENSIONS JEDEC VARIATION ALL DIMENSIONS IN MILLIMETERS BBA SYMBOL MINIMUM NOMINAL MAXIMUM 32 N A -- -- 1.60 A1 0.05 -- 0.15 A2 1.35 1.40 1.45 b 0.30 0.37 0.45 c 0.09 -- 0.20 D 9.00 BASIC D1 7.00 BASIC D2 5.60 Ref. E 9.00 BASIC E1 7.00 BASIC E2 5.60 Ref. 0.80 BASIC e L 0.45 0.60 0.75 θ 0° -- 7° ccc -- -- 0.10 Reference Document: JEDEC Publication 95, MS-026 86953BYI-147 www.icst.com/products/hiperclocks.html 11 REV. B APRIL 23, 2004 ICS86953I-147 Integrated Circuit Systems, Inc. LOW SKEW, 1-TO-9 DIFFERENTIAL-TO-LVCMOS / LVTTL ZERO DELAY BUFFER TABLE 9. ORDERING INFORMATION Part/Order Number Marking Package Count Temperature ICS86953BYI-147 ICS6953BI147 32 Lead LQFP 250 per tray -40°C to 85°C ICS86953BYIT-147 ICS6953BI147 32 Lead LQFP on Tape and Reel 1000 -40°C to 85°C The aforementioned trademark, HiPerClockS™ is a trademark of Integrated Circuit Systems, Inc. or its subsidiaries in the United States and/or other countries. While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial and industrial applications. Any other applications such as those requiring high reliability or other extraordinary environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or critical medical instruments. 86953BYI-147 www.icst.com/products/hiperclocks.html 12 REV. B APRIL 23, 2004 Integrated Circuit Systems, Inc. ICS86953I-147 LOW SKEW, 1-TO-9 DIFFERENTIAL-TO-LVCMOS / LVTTL ZERO DELAY BUFFER REVISION HISTORY SHEET Rev Table T1 T2 Page 2 2 T2 7 8&9 2 B B 86953BYI-147 Description of Change Added Pullup/Pulldown to Pin 9. Pin Characteristics table - changed CIN limit from 4pF max. to 4pF typical. Added 5pF min. and 7pF typical to CPD. Updated Figure 3C and 3D. Added Layout Guideline and PCB Board layout. Pin Characteristics Table - added ROUT row. www.icst.com/products/hiperclocks.html 13 Date 10/28/03 4/23/04 REV. B APRIL 23, 2004