SEMICONDUCTOR TECHNICAL DATA The MPC949 is a low voltage CMOS, 15 output clock buffer. The 15 outputs can be configured into a standard fanout buffer or into 1X and 1/2X combinations. The device features a low voltage PECL input, in addition to its LVCMOS/LVTTL inputs, to allow it to be incorporated into larger clock trees which utilize low skew PECL devices (see the MC100LVE111 data sheet) in the lower branches of the tree. The fifteen outputs were designed and optimized to drive 50Ω series or parallel terminated transmission lines. With output to output skews of 300ps the MPC949 is an ideal clock distribution chip for synchronous systems which need a tight level of skew from a large number of outputs. For a similar product with a smaller fanout and package consult the MPC946 data sheet. • • • • • • • • • LOW VOLTAGE 1:15 PECL TO CMOS CLOCK DRIVER Clock Distribution for Pentium Systems with PCI Low Voltage PECL Clock Input 2 Selectable LVCMOS/LVTTL Clock Inputs 350ps Maximum Output to Output Skew Drives up to 30 Independent Clock Lines Maximum Output Frequency of 150MHz High Impedance Output Enable FA SUFFIX 52–LEAD TQFP PACKAGE CASE 848D–03 52–Lead TQFP Packaging 3.3V VCC Supply With an output impedance of approximately 7Ω, in both the HIGH and the LOW logic states, the output buffers of the MPC949 are ideal for driving series terminated transmission lines. More specifically each of the 15 MPC949 outputs can drive two series terminated transmission lines. With this capability, the MPC949 has an effective fanout of 1:30 in applications using point–to–point distribution schemes. The MPC949 has the capability of generating 1X and 1/2X signals from a 1X source. The design is fully static, the signals are generated and retimed inside the chip to ensure minimal skew between the 1X and 1/2X signals. The device features selectability to allow the user to select the ratio of 1X outputs to 1/2X outputs. Two independent LVCMOS/LVTTL compatible clock inputs are available. Designers can take advantage of this feature to provide redundant clock sources or the addition of a test clock into the system design. With the TCLK_Sel input pulled HIGH the TCLK1 input is selected. The PCLK_Sel input will select the PECL input clock when driven HIGH. All of the control inputs are LVCMOS/LVTTL compatible. The Dsel pins choose between 1X and 1/2X outputs. A LOW on the Dsel pins will select the 1X output. The MR/OE input will reset the internal flip flops and tristate the outputs when it is forced HIGH. The MPC949 is fully 3.3V compatible. The 52 lead TQFP package was chosen to optimize performance, board space and cost of the device. The 52–lead TQFP has a 10x10mm body size with a 0.65mm pin spacing. Pentium is a trademark of Intel Corporation. 10/96 Motorola, Inc. 1996 1 REV 1 MPC949 NC 0 4 1 Qc0:3 Dselc 0 6 1 Qd0:5 Dseld NC Qd5 GNDd GNDc Qc3 VCCc Qc2 GNDb 23 GNDd Qb1 44 22 Qd3 VCCb 45 21 VCCd Qb0 46 20 Qd2 GNDb 47 19 GNDd GNDa 48 18 Qd1 Qa1 49 17 VCCd VCCa 50 16 Qd0 Qa0 51 15 GNDd GNDa 52 14 NC FUNCTION TABLE MOTOROLA GNDc Qd4 43 MR/OE TCLK_Sel PCLK_Sel Dseln MR/OE Qc1 24 MPC949 1 2 3 4 5 6 7 8 9 10 11 12 13 GNDI Dselb 42 Dseld 1 Qb0:2 VCCd Qb2 Dselc 3 25 Dselb 0 41 Dsela Dsela NC VCCb PCLK PCLK_Sel 1 Qa0:1 PCLK 2 TCLK1 0 39 38 37 36 35 34 33 32 31 30 29 28 27 26 40 TCLK0 ÷2 R 1 PCLK PCLK PCLK_Sel Input VCCc ÷1 0 VCCI 1 TCLK_Sel TCLK1 (LVTTL) MR/OE 0 NC TCLK_Sel TCLK0 (LVTTL) Qc0 Figure 2. 52–Lead Pinout (Top View) GNDc Figure 1. Logic Diagram PIN DESCRIPTION 0 1 Pin Name TCLK0 TCLKn ÷1 Enabled TCLK1 PCLK ÷2 Hi–Z TCLK_Sel (Int Pulldown) Select pin to choose TCKL0 or TCLK1 TCLK0:1 (Int Pullup) LVCMOS/LVTTL clock inputs PCLK (Int Pulldown) True PECL clock input PCLK (Int Pullup) Compliment PECL clock input Dseln (Int Pulldown) 1x or 1/2x input divide select pins MR/OE (Int Pulldown) Internal reset and output tristate control pin PCLK_Sel (Int Pulldown) Select Pin to choose TCLK or PCLK 2 Function TIMING SOLUTIONS BR1333 — Rev 6 MPC949 ABSOLUTE MAXIMUM RATINGS* Symbol Parameter Min Max Unit VCC Supply Voltage –0.3 4.6 V VI Input Voltage –0.3 VDD + 0.3 V IIN Input Current TBD TBD mA TStor Storage Temperature Range –40 125 °C * Absolute maximum continuous ratings are those values beyond which damage to the device may occur. Exposure to these conditions or conditions beyond those indicated may adversely affect device reliability. Functional operation under absolute–maximum–rated conditions is not implied. DC CHARACTERISTICS (TA = 0° to 70°C, VCC = 3.3V ±5%) Symbol Characteristic Min Typ 2.0 Max Unit 3.60 V 0.8 V Condition VIH Input HIGH Voltage (Except PECL_CLK) VIL Input LOW Voltage (Except PECL_CLK) VPP Peak–to–Peak Input Voltage PECL_CLK 300 1000 mV VCMR Common Mode Range PECL_CLK VCC – 2.0 VCC – 0.6 V Note 1. VOH Output HIGH Voltage V IOH = –20mA (Note 2.) VOL Output LOW Voltage IIN Input Current CIN Input Capacitance Cpd Power Dissipation Capacitance 2.5 0.4 V IOL = 20mA (Note 2.) ±120 µA Note 3. 4 pF 25 pF Per Output ICC Maximum Quiescent Supply Current 70 85 mA 1. VCMR is the difference from the most positive side of the differential input signal. Normal operation is obtained when the “HIGH” input is within the VCMR range and the input swing lies within the VPP specification. 2. The MPC949 outputs can drive series or parallel terminated 50Ω (or 50Ω to VCC/2) transmission lines on the incident edge (see Applications Info section). 3. Inputs have pull–up/pull–down resistors which affect input current. AC CHARACTERISTICS (TA = 0° to 70°C, VCC = 3.3V ±5%) Symbol Characteristic Min Typ Fmax Maximum Input Frequency tPLH Propagation Delay PECL_CLK to Q TTL_CLK to Q 4.0 4.2 6.5 7.5 tPHL Propagation Delay PECL_CLK to Q TTL_CLK to Q 3.8 4.0 tsk(o) Output–to–Output Skew tsk(pr) Part–to–Part Skew tPZL,tPZH tPLZ,tPHZ Max 150 Unit Condition MHz Note 4. 9.0 10.6 ns Note 4. 6.2 7.2 8.6 10.5 ns Note 4. 300 350 ps Note 4. 1.5 2.0 2.75 4.0 ns Note 5. Output Enable Time 3 11 ns Note 4. Output Disable Time 3 11 ns Note 4. 1.0 ns 0.8V to 2.0V PECL_CLK to Q TTL_CLK to Q tr, tf Output Rise/Fall Time 4. Driving 50Ω transmission lines terminated to VCC/2. 5. Part–to–part skew at a given temperature and voltage. 0.10 TIMING SOLUTIONS BR1333 — Rev 6 3 MOTOROLA MPC949 APPLICATIONS INFORMATION line impedances. The voltage wave launched down the two lines will equal: Driving Transmission Lines The MPC949 clock driver was designed to drive high speed signals in a terminated transmission line environment. To provide the optimum flexibility to the user, the output drivers were designed to exhibit the lowest impedance possible. With an output impedance of less than 10Ω the drivers can drive either parallel or series terminated transmission lines. For more information on transmission lines the reader is referred to application note AN1091 in the Timing Solutions brochure (BR1333/D). VL = VS ( Zo / Rs + Ro +Zo) = 3.0 (25/53.5) = 1.40V At the load end the voltage will double, due to the near unity reflection coefficient, to 2.8V. It will then increment towards the quiescent 3.0V in steps separated by one round trip delay (in this case 4.0ns). 3.0 In most high performance clock networks point–to–point distribution of signals is the method of choice. In a point–to–point scheme either series terminated or parallel terminated transmission lines can be used. The parallel technique terminates the signal at the end of the line with a 50Ω resistance to VCC/2. This technique draws a fairly high level of DC current and thus only a single terminated line can be driven by each output of the MPC949 clock driver. For the series terminated case however there is no DC current draw, thus the outputs can drive multiple series terminated lines. Figure 3 illustrates an output driving a single series terminated line vs two series terminated lines in parallel. When taken to its extreme the fanout of the MPC949 clock driver is effectively doubled due to its capability to drive multiple lines. VOLTAGE (V) 2.5 OutA tD = 3.8956 2.0 In 1.5 1.0 0.5 0 2 MPC949 OUTPUT BUFFER IN 7Ω MPC949 OUTPUT BUFFER IN OutB tD = 3.9386 4 6 8 TIME (nS) 10 12 14 Figure 4. Single versus Dual Waveforms RS = 43Ω ZO = 50Ω Since this step is well above the threshold region it will not cause any false clock triggering, however designers may be uncomfortable with unwanted reflections on the line. To better match the impedances when driving multiple lines the situation in Figure 5 should be used. In this case the series terminating resistors are reduced such that when the parallel combination is added to the output buffer impedance the line impedance is perfectly matched. OutA RS = 43Ω ZO = 50Ω OutB0 7Ω RS = 43Ω ZO = 50Ω MPC949 OUTPUT BUFFER OutB1 ZO = 50Ω RS = 36Ω ZO = 50Ω 7Ω Figure 3. Single versus Dual Transmission Lines The waveform plots of Figure 4 show the simulation results of an output driving a single line vs two lines. In both cases the drive capability of the MPC949 output buffers is more than sufficient to drive 50Ω transmission lines on the incident edge. Note from the delay measurements in the simulations a delta of only 43ps exists between the two differently loaded outputs. This suggests that the dual line driving need not be used exclusively to maintain the tight output–to–output skew of the MPC949. The output waveform in Figure 4 shows a step in the waveform, this step is caused by the impedance mismatch seen looking into the driver. The parallel combination of the 43Ω series resistor plus the output impedance does not match the parallel combination of the MOTOROLA RS = 36Ω 7Ω + 36Ω k 36Ω = 50Ω k 50Ω 25Ω = 25Ω Figure 5. Optimized Dual Line Termination SPICE level output buffer models are available for engineers who want to simulate their specific interconnect schemes. In addition IV characteristics are in the process of being generated to support the other board level simulators in general use. 4 TIMING SOLUTIONS BR1333 — Rev 6 MPC949 OUTLINE DIMENSIONS FA SUFFIX TQFP PACKAGE CASE 848D–03 ISSUE C 4X –X– X=L, M, N 4X TIPS 0.20 (0.008) H L–M N 0.20 (0.008) T L–M N CL 52 AB 40 1 G 39 AB 3X VIEW Y –L– VIEW Y –M– B V B1 13 ÇÇÇÇ ÉÉÉÉ ÉÉÉÉ ÇÇÇÇ V1 J 27 14 26 0.13 (0.005) –N– A1 BASE METAL F PLATING M D T L–M U S N S SECTION AB–AB ROTATED 90_ CLOCKWISE S1 A S 4X C θ2 0.10 (0.004) T –H– –T– SEATING PLANE 4X θ3 VIEW AA 0.05 (0.002) S W θ1 2XR R1 0.25 (0.010) C2 θ GAGE PLANE K C1 E Z VIEW AA TIMING SOLUTIONS BR1333 — Rev 6 5 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DATUM PLANE –H– IS LOCATED AT BOTTOM OF LEAD AND IS COINCIDENT WITH THE LEAD WHERE THE LEAD EXITS THE PLASTIC BODY AT THE BOTTOM OF THE PARTING LINE. 4. DATUMS –L–, –M– AND –N– TO BE DETERMINED AT DATUM PLANE –H–. 5. DIMENSIONS S AND V TO BE DETERMINED AT SEATING PLANE –T–. 6. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. ALLOWABLE PROTRUSION IS 0.25 (0.010) PER SIDE. DIMENSIONS A AND B DO INCLUDE MOLD MISMATCH AND ARE DETERMINED AT DATUM PLANE -H-. 7. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. DAMBAR PROTRUSION SHALL NOT CAUSE THE LEAD WIDTH TO EXCEED 0.46 (0.018). MINIMUM SPACE BETWEEN PROTRUSION AND ADJACENT LEAD OR PROTRUSION 0.07 (0.003). DIM A A1 B B1 C C1 C2 D E F G J K R1 S S1 U V V1 W Z θ θ1 θ2 θ3 MILLIMETERS MIN MAX 10.00 BSC 5.00 BSC 10.00 BSC 5.00 BSC ––– 1.70 0.05 0.20 1.30 1.50 0.20 0.40 0.45 0.75 0.22 0.35 0.65 BSC 0.07 0.20 0.50 REF 0.08 0.20 12.00 BSC 6.00 BSC 0.09 0.16 12.00 BSC 6.00 BSC 0.20 REF 1.00 REF 0_ 7_ ––– 0_ 12 _ REF 5_ 13 _ INCHES MIN MAX 0.394 BSC 0.197 BSC 0.394 BSC 0.197 BSC ––– 0.067 0.002 0.008 0.051 0.059 0.008 0.016 0.018 0.030 0.009 0.014 0.026 BSC 0.003 0.008 0.020 REF 0.003 0.008 0.472 BSC 0.236 BSC 0.004 0.006 0.472 BSC 0.236 BSC 0.008 REF 0.039 REF 0_ 7_ ––– 0_ 12 _ REF 5_ 13 _ MOTOROLA MPC949 Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. “Typical” parameters which may be provided in Motorola data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. Motorola does not convey any license under its patent rights nor the rights of others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal injury or death may occur. Should Buyer purchase or use Motorola products for any such unintended or unauthorized application, Buyer shall indemnify and hold Motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part. Motorola and are registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal Opportunity/Affirmative Action Employer. How to reach us: USA / EUROPE / Locations Not Listed: Motorola Literature Distribution; P.O. Box 5405; Denver, Colorado 80217. 303–675–2140 or 1–800–441–2447 JAPAN: Nippon Motorola Ltd.; Tatsumi–SPD–JLDC, 6F Seibu–Butsuryu–Center, 3–14–2 Tatsumi Koto–Ku, Tokyo 135, Japan. 81–3–3521–8315 Mfax: [email protected] – TOUCHTONE 602–244–6609 INTERNET: http://www.mot.com/sps/ ASIA/PACIFIC: Motorola Semiconductors H.K. Ltd.; 8B Tai Ping Industrial Park, 51 Ting Kok Road, Tai Po, N.T., Hong Kong. 852–26629298 MOTOROLA ◊ 6 MPC949/D TIMING SOLUTIONS BR1333 — Rev 6