TI1 LMH6612MAX/NOPB Single supply 345 mhz rail-to-rail output amplifier Datasheet

LMH6611, LMH6612
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SNOSB00K – NOVEMBER 2007 – REVISED OCTOBER 2013
LMH6611/LMH6612 Single Supply 345 MHz Rail-to-Rail Output Amplifiers
Check for Samples: LMH6611, LMH6612
FEATURES
DESCRIPTION
•
The LMH6611 (single, with shutdown) and LMH6612
(dual) are 345 MHz rail-to-rail output amplifiers
consuming just 3.2 mA of quiescent current per
channel and designed to deliver high performance in
power conscious single supply systems. The
LMH6611 and LMH6612 have precision trimmed
input offset voltages with low noise and low distortion
performance as required for high accuracy video, test
and measurement, and communication applications.
The LMH6611 and LMH6612 are members of the
PowerWise family and have an exceptional power-toperformance ratio.
1
23
•
•
•
•
•
•
•
•
•
•
•
•
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•
•
VS = 5V, RL = 1 kΩ, TA = 25°C and AV = +1,
Unless Otherwise Specified.
Operating Voltage Range 2.7V to 11V
Supply Current Per Channel 3.2 mA
Small Signal Bandwidth 345 MHz
Open Loop Gain 103 dB
Input Offset Voltage (Limit at 25°C) ±1.5 mV
Slew Rate 460 V/µs
0.1 dB Bandwidth 45 MHz
Settling Time to 0.1% 67 ns
Settling Time to 0.01% 100 ns
SFDR (f = 100 kHz, AV = 2, VOUT = 2 VPP) 102
dBc
Low Voltage Noise 10 nV/√Hz
Output current ±100 mA
CMVR −0.2V to 3.8V
Rail-to-Rail Output
−40°C to +125°C Temperature Range
APPLICATIONS
•
•
•
•
•
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ADC Driver
DAC Buffer
Active Filters
High Speed Sensor Amplifier
Current Sense Amplifier
1080i and 720p Analog Video Amplifier
STB, TV Video Amplifier
Video Switching and Muxing
With a trimmed input offset voltage of 0.022 mV and
a high open loop gain of 103 dB the LMH6611 and
LMH6612 meet the requirements of DC sensitive high
speed applications such as low pass filtering in
baseband I and Q radio channels. These
specifications combined with a 0.01% settling time of
100 ns, a low noise of 10 nV/√Hz and better than 102
dBc SFDR at 100 kHz make these amplifiers
particularly suited to driving 10, 12 and 14-bit high
speed ADCs. The 45 MHz 0.1 dB bandwidth (AV = 2)
driving 2 VPP into 150Ω allows the amplifiers to be
used as output drivers in 1080i and 720p HDTV
applications.
The input common mode range extends from 200 mV
below the negative supply rail up to 1.2V from the
positive rail. On a single 5V supply with a ground
terminated 150Ω load the output swings to within 49
mV of the ground, while a mid-rail terminated 1 kΩ
load will swing to 77 mV of either rail.
1
2
3
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
WEBENCH is a registered trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2007–2013, Texas Instruments Incorporated
LMH6611, LMH6612
SNOSB00K – NOVEMBER 2007 – REVISED OCTOBER 2013
www.ti.com
DESCRIPTION (CONTINUED)
The amplifiers will operate on a 2.7V to 11V single supply or ±1.35V to ±5.5V split supply. The LMH6611 single
is available in 6-Pin SOT and has an independent active low disable pin which reduces the supply current to 120
µA. The LMH6612 is available in 8-Pin SOIC. Both the LMH6611 and LMH6612 are available in −40°C to
+125°C extended industrial temperature grade.
Typical Application
1 PF
R1
R2
549:
549:
IN
R5
C5
1.24 k:
150 pF
+
V
+
V
C2
+
V
1 nF
0.1 PF
5V
0.1 PF
1 PF
0.1 PF
RL
R6
14.3 k:
0.01 PF
10 PF
10 PF
-
22:
ADC121S101
LMH6611
GND
+
5.6 PF
0.1 PF
CL
U1
390 pF
R7
14.3 k:
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
Absolute Maximum Ratings (1) (2)
Human Body Model
ESD Tolerance (3)
For input pins only
2000V
For all other pins
2000V
Machine Model
200V
Charge Device Model
1000V
Supply Voltage (VS = V+ – V−)
Junction Temperature
(1)
(2)
(3)
(4)
12V
(4)
150°C max
Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for
which the device is intended to be functional, but specific performance is not ensured. For ensured specifications and the test
conditions, see the Electrical Characteristics.
If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/ Distributors for availability and
specifications.
Human Body Model, applicable std. MIL-STD-883, Method 3015.7. Machine Model, applicable std. JESD22-A115-A (ESD MM std. of
JEDEC)Field-Induced Charge-Device Model, applicable std. JESD22-C101-C (ESD FICDM std. of JEDEC).
The maximum power dissipation is a function of TJ(MAX), θJA. The maximum allowable power dissipation at any ambient temperature is
PD = (TJ(MAX)) – TA)/ θJA. All numbers apply for packages soldered directly onto a PC Board.
Operating Ratings (1)
Supply Voltage (VS = V+ – V−)
2.7V to 11V
Ambient Temperature Range (2)
Package Thermal Resistance (θJA)
(1)
(2)
2
−40°C to +125°C
6-Pin SOT
231°C/W
8-Pin SOIC
160°C/W
Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for
which the device is intended to be functional, but specific performance is not ensured. For ensured specifications and the test
conditions, see the Electrical Characteristics.
The maximum power dissipation is a function of TJ(MAX), θJA. The maximum allowable power dissipation at any ambient temperature is
PD = (TJ(MAX)) – TA)/ θJA. All numbers apply for packages soldered directly onto a PC Board.
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Copyright © 2007–2013, Texas Instruments Incorporated
Product Folder Links: LMH6611 LMH6612
LMH6611, LMH6612
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SNOSB00K – NOVEMBER 2007 – REVISED OCTOBER 2013
+3V Electrical Characteristics
Unless otherwise specified, all limits are specified for TJ = +25°C, V+ = 3V, V− = 0V, VS = V+ – V−, DISABLE = 3V, VCM = VO =
V+/2, AV = +1, RF = 0Ω, when AV ≠ +1 then RF = 560Ω, RL = 1 kΩ. Boldface limits apply at temperature extremes. (1)
Symbol
Parameter
Condition
Min (2)
Typ (3)
Max (2)
Units
Frequency Domain Response
SSBW
GBW
LSBW
–3 dB Bandwidth Small Signal
AV = 1, RL = 1 kΩ, VOUT = 0.2 VPP
305
AV = 2, −1, RL = 1 kΩ, VOUT = 0.2 VPP
115
Gain Bandwidth
(LMH6611)
AV = 10, RF = 2 kΩ, RG = 221Ω, RL = 1 kΩ,
VOUT = 0.2 VPP
115
Gain Bandwidth
(LMH6612)
AV = 10, RF = 2 kΩ, RG = 221Ω, RL = 1 kΩ,
VOUT = 0.2 VPP
130
−3 dB Bandwidth Large Signal
AV = 1, RL = 1 kΩ, VOUT = 1.5 VPP
90
AV = −1, RL = 150Ω, VOUT = 2 VPP
85
MHz
135
Peak
Peaking
AV = 1
1.0
0.1
dBBW
0.1 dB Bandwidth
AV = 1, VOUT = 0.5 VPP, RL = 1 kΩ
33
AV = 2, VOUT = 0.5 VPP, RL = 1 kΩ
RF = RG = 560Ω
65
AV = 2, VOUT = 1.5 VPP, RL = 150Ω,
RF = RG = 510Ω
47
MHz
MHz
dB
MHz
DG
Differential Gain
AV = 2, 4.43 MHz, 0.6V < VOUT < 2V,
RL = 150Ω to V+/2
0.03
%
DP
Differential Phase
AV = 2, 4.43 MHz, 0.6V < VOUT < 2V,
RL = 150Ω to V+/2
0.06
deg
Time Domain Response
tr/tf
Rise & Fall Time
1.5V Step, AV = 1
2.8
ns
SR
Slew Rate
2V Step, AV = 1
330
V/μs
ts_0.1
0.1% Settling Time
2V Step, AV = −1
74
ts_0.01
0.01% Settling Time
2V Step, AV = −1
116
fC = 100 kHz, AV = −1, VOUT= 2 VPP
109
fC = 1 MHz, AV = −1, VOUT = 2 VPP
97
fC = 5 MHz, AV = −1, VOUT = 2 VPP
80
10
nV/√Hz
ns
Noise and Distortion Performance
SFDR
Spurious Free Dynamic Range
dBc
en
Input Voltage Noise
f = 100 kHz
in
Input Current Noise
f = 100 kHz
2
pA/√Hz
CT
Crosstalk (LMH6612)
f = 5 MHz, VIN = 2 VPP
71
dB
Input, DC Performance
VOS
Input Offset Voltage (LMH6611)
VCM = 0.5V
0.022
±1.5
±2
Input Offset Voltage (LMH6612)
VCM = 0.5V
−0.015
±1.5
±2
TCVOS
Input Offset Voltage Average Drift
See (4)
IB
Input Bias Current
VCM = 0.5V
IO
mV
μV/°C
4
−5.9
−10.1
−11.1
μA
Input Offset Current
0.01
±0.5
±0.7
μA
CIN
Input Capacitance
2.5
pF
RIN
Input Resistance
6
MΩ
CMVR
Input Voltage Range
(1)
(2)
(3)
(4)
DC, CMRR ≥ 76 dB
−0.2
1.8
V
Boldface limits apply to temperature range of −40°C to 125°C
Limits are 100% production tested at 25°C. Limits over the operating temperature range are ensured through correlations using the
Statistical Quality Control (SQC) method.
Typical values represent the most likely parametric norm as determined at the time of characterization. Actual typical values may vary
over time and will also depend on the application and configuration. The typical values are not tested and are not ensured on shipped
production material.
Voltage average drift is determined by dividing the change in VOS by temperature change.
Copyright © 2007–2013, Texas Instruments Incorporated
Product Folder Links: LMH6611 LMH6612
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LMH6611, LMH6612
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+3V Electrical Characteristics (continued)
Unless otherwise specified, all limits are specified for TJ = +25°C, V+ = 3V, V− = 0V, VS = V+ – V−, DISABLE = 3V, VCM = VO =
V+/2, AV = +1, RF = 0Ω, when AV ≠ +1 then RF = 560Ω, RL = 1 kΩ. Boldface limits apply at temperature extremes.(1)
Symbol
Parameter
Condition
Min (2)
Typ (3)
CMRR
Common Mode Rejection Ratio
VCM Stepped from −0.1V to 1.7V
79
98
AOL
Open Loop Gain
RL = 1 kΩ, VOUT = 2.7V to 0.3V
89
101
RL = 150Ω, VOUT = 2.5V to 0.5V
78
85
Max (2)
Units
dB
dB
Output DC Characteristics
VO
Output Swing High (LMH6611)
(Voltage from V+ Supply Rail)
Output Swing Low (LMH6611)
(Voltage from V− Supply Rail)
Output Swing High (LMH6612)
(Voltage from V+ Supply Rail)
Output Swing Low (LMH6612)
(Voltage from V− Supply Rail)
RL = 1 kΩ to V+/2
59
72
76
RL = 150Ω to V+/2
133
169
182
RL = 1 kΩ to V+/2
59
74
80
RL = 150Ω to V+/2
133
171
188
RL = 150Ω to V−
42
52
56
RL = 1 kΩ to V+/2
58
68
73
RL = 150Ω to V+/2
131
157
172
RL = 1 kΩ to V+/2
61
71
79
RL = 150Ω to V+/2
139
168
187
RL = 150Ω to V−
43
51
56
mV
IOUT
Linear Output Current
VOUT = V+/2 (5)
±70
mA
RO
Output Resistance
f = 1 MHz
0.07
Ω
0.001
µA
Enable Pin Operation
Enable High Voltage Threshold
Enabled (6)
Enable Pin High Current
VDISABLE = 3V
Enable Low Voltage Threshold
Disabled (6)
Enable Pin Low Current
VDISABLE = 0V
2.0
V
1.0
V
0.8
µA
ton
Turn-On Time
18
ns
toff
Turn-Off Time
50
ns
Power Supply Performance
PSRR
Power Supply Rejection Ratio
DC, VCM = 0.5V, VS = 2.7V to 11V
IS
Supply Current (LMH6611)
RL = ∞
3.0
3.4
3.8
Supply Current (LMH6612)
(per channel)
RL = ∞
2.95
3.45
3.9
Disable Shutdown Current
(LMH6611)
DISABLE = 0V
101
132
ISD
(5)
(6)
4
81
96
dB
mA
μA
Do not short circuit the output. Continuous source or sink currents larger than the IOUT typical are not recommended as they may
damage the part.
This parameter is ensured by design and/or characterization and is not tested in production.
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Copyright © 2007–2013, Texas Instruments Incorporated
Product Folder Links: LMH6611 LMH6612
LMH6611, LMH6612
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SNOSB00K – NOVEMBER 2007 – REVISED OCTOBER 2013
+5V Electrical Characteristics
Unless otherwise specified, all limits are specified for TJ = +25°C, V+ = 5V, V− = 0V, VS = V+ – V−, DISABLE = 5V, VCM = VO =
V+/2, AV = +1, RF = 0Ω, when AV ≠ +1 then RF = 560Ω, RL = 1 kΩ. Boldface limits apply at temperature extremes.
Symbol
Parameter
Condition
Min
(1)
Typ
(2)
Max
(1)
Units
Frequency Domain Response
SSBW
GBW
LSBW
–3 dB Bandwidth Small Signal
AV = 1, RL = 1 kΩ, VOUT = 0.2 VPP
345
AV = 2, −1, RL = 1 kΩ, VOUT = 0.2 VPP
112
Gain Bandwidth (LMH6611)
AV = 10, RF = 2 kΩ, RG = 221Ω, RL = 1 kΩ,
VOUT = 0.2 VPP
115
Gain Bandwidth (LMH6612)
AV = 10, RF = 2 kΩ, RG = 221Ω, RL = 1 kΩ,
VOUT = 0.2 VPP
130
−3 dB Bandwidth Large Signal
AV = 1, RL = 1 kΩ, VOUT = 2 VPP
77
AV = 2, RL = 150Ω, VOUT = 2 VPP
85
MHz
135
Peak
Peaking
AV = 1
0.3
0.1
dBBW
0.1 dB Bandwidth
AV = 1, VOUT = 0.5 VPP, RL = 1 kΩ
45
AV = 2, VOUT = 0.5 VPP, RL = 1 kΩ
RF = RG = 680Ω
68
AV = 2, VOUT = 2 VPP, RL = 150Ω,
RF = RG = 665Ω
45
MHz
MHz
dB
MHz
DG
Differential Gain
AV = 2, 4.43 MHz, 0.6V < VOUT < 2V,
RL = 150Ω to V+/2
0.05
%
DP
Differential Phase
AV = 2, 4.43 MHz, 0.6V < VOUT < 2V,
RL = 150Ω to V+/2
0.06
deg
Time Domain Response
tr/tf
Rise & Fall Time
2V Step, AV = 1
3.6
ns
SR
Slew Rate
2V Step, AV = 1
460
V/μs
ts_0.1
0.1% Settling Time
2V Step, AV = −1
67
ts_0.01
0.01% Settling Time
2V Step, AV = −1
100
fC = 100 kHz, AV = 2, VOUT = 2 VPP
102
fC = 1 MHz, AV = 2, VOUT = 2 VPP
96
fC = 5 MHz, AV = 2, VO = 2 VPP
82
ns
Distortion and Noise Performance
SFDR
Spurious Free Dynamic Range
dBc
en
Input Voltage Noise
f = 100 kHz
10
nV/√Hz
in
Input Current Noise
f = 100 kHz
2
pA/√Hz
CT
Crosstalk (LMH6612)
f = 5 MHz, VIN = 2 VPP
71
dB
Input, DC Performance
VOS
Input Offset Voltage (LMH6611)
VCM = 0.5V
0.013
±1.5
±2
Input Offset Voltage (LMH6612)
VCM = 0.5V
0.022
±1.5
±2
TCVOS
Input Offset Voltage Average Drift See (3)
IB
Input Bias Current
IO
4
mV
µV/°C
−6.3
−10.1
−11.1
μA
Input Offset Current
0.01
±0.5
±0.7
μA
CIN
Input Capacitance
2.5
RIN
Input Resistance
CMVR
Input Voltage Range
(1)
(2)
(3)
VCM = 0.5V
pF
6
DC, CMRR ≥ 78 dB
−0.2
MΩ
3.8
V
Limits are 100% production tested at 25°C. Limits over the operating temperature range are ensured through correlations using the
Statistical Quality Control (SQC) method.
Typical values represent the most likely parametric norm as determined at the time of characterization. Actual typical values may vary
over time and will also depend on the application and configuration. The typical values are not tested and are not ensured on shipped
production material.
Voltage average drift is determined by dividing the change in VOS by temperature change.
Copyright © 2007–2013, Texas Instruments Incorporated
Product Folder Links: LMH6611 LMH6612
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LMH6611, LMH6612
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+5V Electrical Characteristics (continued)
Unless otherwise specified, all limits are specified for TJ = +25°C, V+ = 5V, V− = 0V, VS = V+ – V−, DISABLE = 5V, VCM = VO =
V+/2, AV = +1, RF = 0Ω, when AV ≠ +1 then RF = 560Ω, RL = 1 kΩ. Boldface limits apply at temperature extremes.
Symbol
Parameter
Condition
Min
(1)
Typ
(2)
CMRR
Common Mode Rejection Ratio
VCM Stepped from −0.1V to 3.7V
81
98
AOL
Open Loop Gain
RL = 1 kΩ, VOUT = 4.6V to 0.4V
92
103
RL = 150Ω, VOUT = 4.4V to 0.6V
80
86
Max
(1)
Units
dB
dB
Output DC Characteristics
VO
Output Swing High (LMH6611)
(Voltage from V+ Supply Rail)
Output Swing Low (LMH6611)
(Voltage from V− Supply Rail)
Output Swing High (LMH6612)
(Voltage from V+ Supply Rail)
Output Swing Low (LMH6612)
(Voltage from V− Supply Rail)
RL = 1 kΩ to V+/2
76
90
93
RL =150Ω to V+/2
195
239
256
RL = 1 kΩ to V+/2
74
92
98
RL =150Ω to V+/2
193
243
265
RL = 150Ω to V−
48
60
64
RL = 1 kΩ to V+/2
75
86
91
RL =150Ω to V+/2
195
223
241
RL = 1 kΩ to V+/2
77
88
98
RL =150Ω to V+/2
202
234
261
RL = 150Ω to V−
49
58
64
mV
IOUT
Linear Output Current
VOUT = V+/2 (4)
±100
mA
RO
Output Resistance
f = 1 MHz
0.07
Ω
1.2
µA
Enable Pin Operation
Enable High Voltage Threshold
Enabled (5)
Enable Pin High Current
VDISABLE = 5V
Enable Low Voltage Threshold
Disabled (5)
Enable Pin Low Current
VDISABLE = 0V
3.0
V
2.0
V
2.8
µA
ton
Turn-On Time
20
ns
toff
Turn-Off Time
60
ns
96
dB
Power Supply Performance
PSRR
Power Supply Rejection Ratio
DC, VCM = 0.5V, VS = 2.7V to 11V
IS
Supply Current (LMH6611)
RL = ∞
3.2
3.6
4.0
Supply Current (LMH6612)
(per channel)
RL = ∞
3.2
3.7
4.25
Disable Shutdown Current
(LMH6611)
DISABLE = 0V
120
162
ISD
(4)
(5)
6
81
mA
μA
Do not short circuit the output. Continuous source or sink currents larger than the IOUT typical are not recommended as they may
damage the part.
This parameter is ensured by design and/or characterization and is not tested in production.
Submit Documentation Feedback
Copyright © 2007–2013, Texas Instruments Incorporated
Product Folder Links: LMH6611 LMH6612
LMH6611, LMH6612
www.ti.com
SNOSB00K – NOVEMBER 2007 – REVISED OCTOBER 2013
±5V Electrical Characteristics
Unless otherwise specified, all limits are specified for TJ = +25°C, V+ = 5V, V− = −5V, VS = V+ – V−, DISABLE = 5V, VCM = VO
= 0V, AV = +1, RF = 0Ω, when AV ≠ +1 then RF = 560Ω, RL = 1 kΩ. Boldface limits apply at temperature extremes.
Symbol
Parameter
Condition
Min
(1)
Typ
(2)
Max
(1)
Units
Frequency Domain Response
SSBW
GBW
LSBW
–3 dB Bandwidth Small Signal
AV = 1, RL = 1 kΩ, VOUT = 0.2 VPP
365
AV = 2, −1, RL = 1 kΩ, VOUT = 0.2 VPP
110
Gain Bandwidth (LMH6611)
AV = 10, RF = 2 kΩ, RG = 221Ω, RL = 1 kΩ,
VOUT = 0.2 VPP
115
Gain Bandwidth (LMH6612)
AV = 10, RF = 2 kΩ, RG = 221Ω, RL = 1 kΩ,
VOUT = 0.2 VPP
130
−3 dB Bandwidth Large Signal
AV = 1, RL = 1 kΩ, VOUT = 2 VPP
85
AV = 2, RL = 150Ω, VOUT = 2 VPP
87
MHz
135
Peak
Peaking
AV = 1
0.1
dBBW
0.1 dB Bandwidth
AV = 1, VOUT = 0.5 VPP, RL = 1 kΩ
92
AV = 2, VOUT = 0.5 VPP, RL = 1 kΩ
RF = RG = 750Ω
65
AV = 2, VOUT = 2 VPP, RL = 150Ω,
RF = RG = 680Ω
45
MHz
MHz
0.01
dB
MHz
DG
Differential Gain
AV = 2, 4.43 MHz, 0.6V < VOUT < 2V,
RL = 150Ω to V+/2
0.05
%
DP
Differential Phase
AV = 2, 4.43 MHz, 0.6V < VOUT < 2V,
RL = 150Ω to V+/2
0.05
deg
Time Domain Response
tr/tf
Rise & Fall Time
2V Step, AV = 1
3.5
ns
SR
Slew Rate
2V Step, AV = 1
460
V/μs
ts_0.1
0.1% Settling Time
2V Step, AV = −1
60
ts_0.01
0.01% Settling Time
2V Step, AV = −1
100
fC = 100 kHz, AV = 2, VOUT = 2 VPP
102
fC = 1 MHz, AV = 2, VOUT = 2 VPP
100
fC = 5 MHz, AV = 2, VOUT = 2 VPP
81
ns
Noise and Distortion Performance
SFDR
Spurious Free Dynamic Range
dBc
en
Input Voltage Noise
f = 100 kHz
10
nV/√Hz
in
Input Current Noise
f = 100 kHz
2
pA/√Hz
CT
Crosstalk (LMH6612)
f = 5 MHz, VIN = 2 VPP
71
dB
Input DC Performance
VOS
Input Offset Voltage (LMH6611)
VCM = −4.5V
0.074
±1.5
±2
Input Offset Voltage (LMH6612)
VCM = −4.5V
0.095
±1.5
±2
TCVOS
Input Offset Voltage Average Drift See (3)
IB
Input Bias Current
IO
4
µV/°C
−6.5
−10.1
−11.1
μA
Input Offset Current
0.01
±0.5
±0.7
μA
CIN
Input Capacitance
2.5
RIN
Input Resistance
CMVR
Input Voltage Range
(1)
(2)
(3)
VCM = −4.5V
mV
pF
6
DC, CMRR ≥ 81 dB
−5.2
MΩ
3.8
V
Limits are 100% production tested at 25°C. Limits over the operating temperature range are ensured through correlations using the
Statistical Quality Control (SQC) method.
Typical values represent the most likely parametric norm as determined at the time of characterization. Actual typical values may vary
over time and will also depend on the application and configuration. The typical values are not tested and are not ensured on shipped
production material.
Voltage average drift is determined by dividing the change in VOS by temperature change.
Copyright © 2007–2013, Texas Instruments Incorporated
Product Folder Links: LMH6611 LMH6612
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±5V Electrical Characteristics (continued)
Unless otherwise specified, all limits are specified for TJ = +25°C, V+ = 5V, V− = −5V, VS = V+ – V−, DISABLE = 5V, VCM = VO
= 0V, AV = +1, RF = 0Ω, when AV ≠ +1 then RF = 560Ω, RL = 1 kΩ. Boldface limits apply at temperature extremes.
Symbol
Parameter
Condition
Min
(1)
Typ
(2)
CMRR
Common Mode Rejection Ratio
VCM Stepped from −5.1V to 3.7V
81
98
AOL
Open Loop Gain
RL = 1 kΩ, VOUT = +4.6V to −4.6V
96
103
RL = 150Ω, VOUT = +4.3V to −4.3V
80
87
Max
(1)
Units
dB
dB
Output DC Characteristics
VO
Output Swing High (LMH6611)
(Voltage from V+ Supply Rail)
Output Swing Low (LMH6611)
(Voltage from V− Supply Rail)
Output Swing High (LMH6612)
(Voltage from V+ Supply Rail)
Output Swing Low (LMH6612)
(Voltage from V− Supply Rail)
RL = 1 kΩ to GND
107
125
130
RL = 150Ω to GND
339
402
433
RL = 1 kΩ to GND
103
123
132
RL = 150Ω to GND
332
404
445
RL = 150Ω to V−
54
70
74
RL = 1 kΩ to GND
107
118
125
RL = 150Ω to GND
340
375
407
RL = 1 kΩ to GND
108
120
135
RL = 150Ω to GND
348
389
434
RL = 150Ω to V−
56
66
74
mV
IOUT
Linear Output Current
VOUT = GND (4)
±120
mA
RO
Output Resistance
f = 1 MHz
0.07
Ω
17.0
µA
Enable Pin Operation
Enable High Voltage Threshold
Enabled (5)
Enable Pin High Current
VDISABLE = +5V
Enable Low Voltage Threshold
Disabled (5)
Enable Pin Low Current
VDISABLE = −5V
0.5
V
−0.5
V
18.6
µA
ton
Turn-On Time
19
ns
toff
Turn-Off Time
60
ns
96
dB
Power Supply Performance
PSRR
Power Supply Rejection Ratio
DC, VCM = −4.5V, VS = 2.7V to 11V
IS
Supply Current (LMH6611)
RL = ∞
3.3
3.8
4.4
Supply Current (LMH6612)
(per channel)
RL = ∞
3.45
4.05
4.85
Disable Shutdown Current
(LMH6611)
DISABLE = −5V
160
212
ISD
(4)
(5)
8
81
mA
μA
Do not short circuit the output. Continuous source or sink currents larger than the IOUT typical are not recommended as they may
damage the part.
This parameter is ensured by design and/or characterization and is not tested in production.
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SNOSB00K – NOVEMBER 2007 – REVISED OCTOBER 2013
Connection Diagram
VOUT
1
6
+
V
OUT A
1
8
+
V
A
-IN A
V
5
- 2
+
+IN
3
-
+
7
OUT B
DISABLE
-
+IN A
4
2
3
6
B
+
-IN B
-
-IN
V
-
Figure 1. 6-Pin SOT
Top View
4
5
+IN B
Figure 2. 8-Pin SOIC
Top View
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Typical Performance Characteristics
At TJ = 25°C, AV = +1 (RF = 0Ω), otherwise RF = 560Ω for AV ≠ +1, unless otherwise specified.
Closed Loop Frequency Response for
Various Supplies
Closed Loop Frequency Response for
Various Supplies
3
3
±1.5V
0
0
NORMALIZED GAIN (dB)
±2.5V
-3
GAIN (dB)
±5V
-6
-9
-12
-15
A = +1
-18 VOUT = 0.2V
RL = 1 k:
-21
1
10
100
1000
-9
-12
A = +2
100
1000
FREQUENCY (MHz)
Figure 3.
Figure 4.
Closed Loop Frequency Response for
Various Supplies
Closed Loop Frequency Response for
Various Supplies (Gain = +2)
3
3
3V
NORMALIZED GAIN (dB)
10V
-6
-9
A = +1
VOUT = 0.2V
-12
10
1
100
5V
10V
-3
-6
-9
-12
A = +2
-15 V
OUT = 0.2V
-18 RL = 150:
RF = 560:
-21
1
10
RL = 150:
-15
3V
0
-3
GAIN (dB)
-6
FREQUENCY (MHz)
0
1000
100
1000
FREQUENCY (MHz)
FREQUENCY (MHz)
Figure 5.
Figure 6.
Closed Loop Gain
vs.
Frequency for Various Temperatures
Closed Loop Gain
vs.
Frequency for
Various Temperatures
9
6
125°C
25°C
-40°C
6
125°C
3
25°C
3
0
-40°C
GAIN (dB)
0
GAIN (dB)
±2.5V
±5V
-3
-15 VOUT = 0.2V
RL = 1 k:
-18
1
10
5V
-3
+
-6 V = +2.5V
V = -2.5V
-9
VOUT = 0.2V
-12 R = 1 k:
-15 CL = 6 pF
A = +1
-18
1
-3
-6
+
V = +2.5V
-9 V- = -2.5V
-12
VOUT = 0.2V
RL = 150:
L
10
±1.5V
10
100
1000
-15 CL = 6 pF
A = +1
-18
1
10
100
FREQUENCY (MHz)
FREQUENCY (MHz)
Figure 7.
Figure 8.
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SNOSB00K – NOVEMBER 2007 – REVISED OCTOBER 2013
Typical Performance Characteristics (continued)
At TJ = 25°C, AV = +1 (RF = 0Ω), otherwise RF = 560Ω for AV ≠ +1, unless otherwise specified.
Closed Loop Gain
vs.
Frequency for
Various Gains
Large Signal Frequency Response
3
3
A=1
±1.5V, VOUT = 1.5V
0
A=2
-3
-3
A=5
GAIN (dB)
NORMALIZED GAIN (dB)
0
-6
A = 10
-9
±5V, VOUT = 2V
+
-12
-15 RL = 1 k:
-15 A = +1
RL = 1 k:
-18
1
10
VOUT = 0.2V
1
10
100
1000
100
1000
FREQUENCY (MHz)
FREQUENCY (MHz)
Figure 9.
Figure 10.
Large Signal Frequency Response
±0.1 dB Gain Flatness for Various Supplies
3
VOUT = 2V
RL = 150:
0
-3
GAIN (dB
NORMALIZED GAIN (dB)
±2.5V, VOUT = 2V
-9
-12 V = +2.5V
V = -2.5V
-18
-6
-9
±5V, A = +2
-12
±1.5V, A = -1
-15
±2.5V, = A = +2
-18
1
10
100
1.0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0.0
-0.1
-0.2
-0.3
-0.4
-0.5
-0.6
-0.7
-0.8
-0.9
-1.0
1000
±1.5V
±2.5V
±5V
A = +1
VOUT = 0.5V
RL = 1 k:
10
1
100
1000
FREQUENCY (MHz)
FREQUENCY (MHz)
Figure 11.
Figure 12.
±0.1 dB Gain Flatness for Various Supplies
±0.1 dB Gain Flatness for Various Supplies
1.0
0.9 A = +2
0.8
0.7 VOUT = 0.5V
0.6 R = 1 k:
L
0.5
0.4
±2.5V, RF = RG = 680:
0.3
0.2
0.1
0.0
-0.1
±1.5V, RF = RG = 560:
-0.2
-0.3
-0.4
±5V, RF = RG = 750:
-0.5
-0.6
-0.7
-0.8
-0.9
-1.0
10
100
1
0.3
0.2
5V, RF = 604:
0.1
GAIN (dB)
NORMALIZED GAIN (dB
-6
0.0
-0.1
-0.2
10V, RF = 750:
-0.3
3V, RF = 560:
-0.4
-0.5
-0.6
-0.7 A = -1
-0.8 VOUT = 2V
-0.9 R = 150:
L
-1.0
1
10
100
FREQUENCY (MHz)
FREQUENCY (MHz)
Figure 13.
Figure 14.
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Typical Performance Characteristics (continued)
At TJ = 25°C, AV = +1 (RF = 0Ω), otherwise RF = 560Ω for AV ≠ +1, unless otherwise specified.
±0.1 dB Gain Flatness for Various Supplies
0.3
0.2
3V
GAIN (dB)
0
-0.1
-0.2
NORMALIZED GAIN (dB)
5V
0.1
10V
-0.3
-0.4
-0.5
-0.6
-0.7 A = +1
-0.8 VOUT = 2V
-0.9 RL = 150:
-1
±0.1 dB Gain Flatness for Various Supplies (Gain = +2)
10
1
100
0.3
0.2
3V, RF = 510:,
0.1
VOUT = 1.5V
0
-0.1 10V, R = 680:,
F
-0.2 V
OUT = 2V
-0.3
-0.6
-0.7
-0.8 A = +2
-0.9 RL = 150:
-1.0
1
10
1000
1000
Figure 15.
Figure 16.
Small Signal Frequency Response with
Various Capacitive Load
Small Signal Frequency Response with
Capacitive Load and Various RISO
9
CL = 10 pF
GAIN (dB)
0
CL = 2 pF
+
V = +2.5V
RL = 1 k:
1
100
1000
1000
Figure 18.
HD2 and HD3
vs.
Frequency and Supply Voltage
HD2 and HD3
vs.
Frequency and Load
0
+
-10 V = +2.5V
-20 V = -2.5V
VOUT = 2 VPP
HD2
V = +2.5V
+
HD2
-50
-70
100
Figure 17.
-40
-80
RISO = 30
FREQUENCY (MHz)
RL = 1 k:
-20 A = +1
-30
-60
-6 V+ = +2.5V
-9 V = -2.5V
FREQUENCY (MHz)
HD3
+
+
DISTORTION (dBc)
0
-10
10
-3
-12 AV = +1
VOUT = 0.1V
-15
CL = 100 pF
-18
RL = 1 k:
-21
1
10
-
-6 V = -2.5V
A = +1
-9 VOUT = 0.2V
-12
RISO = 25
0
CL = 3.3 pF
-3
RISO = 20
3
CL = 5.5 pF
3
RISO = 10
6
CL = 7 pF
6
GAIN (dB)
100
FREQUENCY MHz
9
DISTORTION (dBc)
VOUT = 2V
-0.4
-0.5
FREQUENCY (MHz)
-
V = -2.5V
V = +5V
-
V = +2.5V V = -5V
-
V = -2.5V
-90
HD3
-100
-110
-120
+
V = +5V
-
V = -5V
0.1
1
10
50
-30 VOUT = 2 VPP
A = +1
-40
-50
RL = 150:
-60
-70
HD2
-80
-90
-100
-110
-120
HD3
0.1
FREQUENCY (MHz)
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RL = 1 k:
1
10
50
FREQUENCY (MHz)
Figure 19.
12
5V, RF = 665:,
Figure 20.
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SNOSB00K – NOVEMBER 2007 – REVISED OCTOBER 2013
Typical Performance Characteristics (continued)
At TJ = 25°C, AV = +1 (RF = 0Ω), otherwise RF = 560Ω for AV ≠ +1, unless otherwise specified.
HD2 and HD3
vs.
Common Mode Voltage
HD2 and HD3
vs.
Common Mode Voltage
-50
-50
f = 1 MHz
f = 5 MHz
-60
-70
HD2
+
V = +2.5V
HD2
+
V = +5V
-
-80
DISTORTION (dBc)
DISTORTION (dBc)
-60
V = -2.5V
-
V = -5V
-90
HD3
-100
HD3
+
V = +5V
-
0
1
2
4
5
6
7
8
9
10
0
1
2
3
4
5
6
7
8
Figure 22.
HD2
vs.
Frequency and Gain
HD3
vs.
Frequency and Gain
0
+
-10 V = +2.5V
V = -2.5V
-20
-30 VOUT = 2 VPP
-40 RL = 1 k:
-50 RF = 560:
-40 RL = 1 k:
-50 RF = 560:
G = +1, HD2
-90
G = +2, HD2
1
-70
G = +1, HD3
-80
-90
10
50
G = +2, HD3
1
0.1
FREQUENCY (MHz)
10
Figure 24.
Open Loop Gain and Phase
HD2
vs.
Output Swing
120
-10
120
100
90
80
60
30
40
0
20
-30
-60
+
V = +2.5V
PHASE (°)
GAIN
60
DISTORTION (dBc)
PHASE
+
-20 V = +2.5V
V = -2.5V
-30
A = -1
-40 R = 1 k:
50 MHz
L
-50
20 MHz
-60
10 MHz
-70
5 MHz
-80
2 MHz
-90
-100
-
-90
1M
10M
50
FREQUENCY (MHz)
Figure 23.
-20 V = -2.5V
RL = 1 k:
-40
1k
10k 100k
10
G = +10, HD3
-60
-100
-110
-120
G = +10, HD2
0.1
9
INPUT COMMON MODE VOLTAGE
DISTORTION (dBc)
DISTORTION (dBc)
V = -5V
Figure 21.
-100
-110
-120
GAIN (dB)
-
-
V = -2.5V
-110
-60
0
HD3
+
V = +5V
+
0
+
-10 V = +2.5V
V = -2.5V
-20
-30 VOUT = 2 VPP
-70
V = -5V
HD3
INPUT COMMON MODE VOLTAGE
-80
-
V = -2.5V
-90
V = +2.5V
V = -5V
3
HD2
+
V = +5V
-
-
V = -2.5V
-110
HD2
+
V = +2.5V
-80
-100
+
V = +2.5V
-70
100M
-120
1G
1 MHz
-110
-120
0
1
2
3
4
5
VOUT (VPP)
FREQUENCY (Hz)
Figure 25.
Figure 26.
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Typical Performance Characteristics (continued)
At TJ = 25°C, AV = +1 (RF = 0Ω), otherwise RF = 560Ω for AV ≠ +1, unless otherwise specified.
HD3
vs.
Output Swing
-10
-10
+
V = +2.5V
-
50 MHz
V = -2.5V
-30 A = -1
-40 RL = 1 k:
DISTORTION (dBc)
-20
DISTORTION (dBc)
HD2
vs.
Output Swing
20 MHz
-50
-60
10 MHz
-70
5 MHz
-80
-90
2 MHz
1
2
L
20 MHz
-50
-60
10 MHz
-70
5 MHz
-80
1 MHz
3
4
-120
5
0
1
2
VOUT (VPP)
Figure 27.
Figure 28.
HD2
vs.
Output Swing
HD3
vs.
Output Swing
-10
+
-20 V- = +2.5V
V = -2.5V
-30
A = +2
-40 R = 150:
50 MHz
L
20 MHz
10 MHz
5 MHz
-70
2 MHz
-80
-90
1 MHz
-100
-120
3
-60
20 MHz
10 MHz
-70
-80
5 MHz
-90
2 MHz
4
5
1 MHz
0
1
2
Figure 29.
Figure 30.
HD3
vs.
Output Swing
Settling Time
vs.
Input Step Amplitude
90
0
+
-10 V = +2.5V
-20 V = -2.5V
A = +2
-30
RL = 150:
-40
FALLING, 0.1%
80
70
50 MHz
20 MHz
10 MHz
5 MHz
-60
-70
2 MHz
-80
-90
60
RISING, 0.1%
50
40
30
+
V = +2.5V
20
-100
1 MHz
-120
0
1
2
-
V = -2.5V
10
-110
3
4
5
AV = -1
0
0
VOUT (VPP)
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0.5
1
1.5
2
2.5
3
3.5
4
4.5
OUTPUT SWING (VPP)
Figure 31.
14
3
VOUT (VPP)
SETTLING TIME (ns)
DISTORTION (dBc)
VOUT (VPP)
-50
5
50 MHz
-40 RL = 1 k:
-50
-120
2
4
-
V = -2.5V
A = +2
-110
1
5
+
-100
-110
0
4
V = +2.5V
-20
-30
-50
-60
3
VOUT (VPP)
DISTORTION (dBc)
DISTORTION (dBc)
-10
2 MHz
-90
-110
1 MHz
0
50 MHz
-100
-100
-110
+
-20 V = +2.5V
V = -2.5V
-30
A = +2
-40 R = 1 k:
Figure 32.
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SNOSB00K – NOVEMBER 2007 – REVISED OCTOBER 2013
Typical Performance Characteristics (continued)
At TJ = 25°C, AV = +1 (RF = 0Ω), otherwise RF = 560Ω for AV ≠ +1, unless otherwise specified.
Settling Time
vs.
Input Step Amplitude
Input Noise
vs.
Frequency
140
1000
1000
+
V = +2.5V
-
100
80
RISING, 0.01%
60
40
+
V = +2.5V
100
100
VOLTAGE NOISE
10
10
-
20
0
V = -2.5V
V = -2.5V
AV = -1
0
0.5
1
1.5
2
2.5
3
3.5
CURRENT NOISE
4
1
10
4.5
10k
1k
100
OUTPUT SWING (VPP)
FREQUENCY (Hz)
Figure 34.
VOS
vs.
VOUT
VOS
vs.
VOUT
6.0
+
+
V = +2.5V
V = +2.5V
-
V = -2.5V
4.0
-
V = -2.5V
4.0
RL = 1 k:
RL = 150:
2.0
-40°C
25°C
VOS (mV)
VOS (mV)
2.0
0
125°C
-2.0
-40°C
25°C
0
125°C
-2.0
-4.0
-4.0
-6.0
-2.5 -2.0 -1.5 -1.0 -0.5 0 0.5 1.0 1.5 2.0 2.5
-6.0
-2.5 -2.0 -1.5 -1.0 -0.5 0 0.5 1.0 1.5 2.0 2.5
VOUT (V)
VOUT (V)
Figure 35.
Figure 36.
VOS
vs.
VCM
VOS
vs.
VS
0.1
0.0
0.2
VS = 5V
-40°C
0.1
VOS (mV)
-0.2
-40°C
0
-0.1
VOS (mV)
1
10M
1M
100k
Figure 33.
6.0
CURRENT NOISE (pA/ Hz)
FALLING, 0.01%
VOLTAGE NOISE (nV/ Hz)
SETTLING TIME (ns)
120
25°C
-0.3
25°C
-0.1
125°C
-0.2
-0.3
-0.4
-
125°C
V = -0.5V
-0.5
-0.4
-0.6
-0.5 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0
-0.5
+
-
VS = V - V
VCM = 0V
0
VCM (V)
2
4
6
8
10
12
VS (V)
Figure 37.
Figure 38.
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Typical Performance Characteristics (continued)
At TJ = 25°C, AV = +1 (RF = 0Ω), otherwise RF = 560Ω for AV ≠ +1, unless otherwise specified.
VOS
vs.
IOUT
0.4
VOS Distribution
3.0
+
V = +2.5V
0.2 V- = -2.5V
-40°C
2.5
0
VOS (mV)
25°C
2.0
-0.2
-0.4
1.5
125°C
-0.6
1.0
-0.8
0.5
-1.0
-1.2
-150
-100
-50
50
0
150
100
0
-1.0
IS
vs.
VS
+
-
VS = V - V
-5.0
3.4
3.2
25°C
IS (mA)
IBIAS (PA)
-5.2
-5.6
-5.8
25°C
3.0
2.8
-40°C
2.6
2.4
-40°C
-6.4
-6.6
6
8
10
-
V = -0.5
2.2
2.0
1.8
1.6
-6.2
4
125°C
3.8
3.6
VCM = 0V
125°C
12
+
0
2
4
Figure 41.
Figure 42.
VOUT
vs.
VS
VOUT
vs.
VS
500
+
12
+
BELOW V SUPPLY
300
RL = 150:
to MID-RAIL
200
-40°C
0
25°C
VOUT (mV)
VOUT (mV)
10
VOLTAGE VOUT IS
400
BELOW V SUPPLY
50
125°C
RL = 1 k: to
MID-RAIL
50
100
0
25°C
-40°C
125°C
100
200
300
100
VOLTAGE VOUT IS
ABOVE V SUPPLY
150
2
3
4
5
6
VOLTAGE VOUT IS
400
-
-
ABOVE V SUPPLY
500
7
8
9
10 11 12
2
VS (V)
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3
4
5
6
7
8
9
10 11 12
VS (V)
Figure 43.
16
8
6
VS (V)
VOLTAGE VOUT IS
100
-
VS = V - V
VCM = 0.5V
VS (V)
150
1.0
0.8
4.2
4.0
-
2
0.6
0.4
IB
vs.
VS
V = -0.5
0
0.2
Vos (mv)
Figure 40.
-4.8
-6.0
-0.2
-0.4
Figure 39.
-4.6
-5.4
-0.6
-0.8
IOUT (mA)
Figure 44.
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Typical Performance Characteristics (continued)
At TJ = 25°C, AV = +1 (RF = 0Ω), otherwise RF = 560Ω for AV ≠ +1, unless otherwise specified.
VOUT
vs.
VS
Closed Loop Output Impedance
vs.
Frequency AV = +1
20
100
V = +2.5V
-
-
ABOVE V SUPPLY
V = -2.5V
-
30
V = 0V
35
RL = 150: TO GND
40
OUTPUT IMPEDANCE (:)
VOUT (mV)
+
VOLTAGE VOUT IS
25
-40°C
45
50
25°C
55
60
125°C
10
1
0.1
0.01
65
70
2
3
4
5
6
7
8
9
0.001
0.0001 0.001 0.01
10 11 12
0.1
1
VS (V)
FREQUENCY (MHz)
Figure 45.
Figure 46.
Circuit for Positive (+) PSRR Measurement
+PSRR
vs.
Frequency
50:
+
-
+
1000 PF
0.1 PF
CABLE
1000 PF
50:
RG
a
560:
VIN
LMH6611
+
+PSRR (dB)
560:
VO
V = +5V
90
V = -5V
-
70 V+ = +2.5V
60 V- = -2.5V
+
V = +1.5V
50
-
V = -1.5V
40
30
20
-
V
0.1 PF
100
80
-
+
RF
100
110
+
V
0.1 PF
10
10
VIN = 225 mVPP
RF = 560:
0
10 100 1k
1000 PF
10k 100k 1M
10M 100M
FREQUENCY (Hz)
Figure 47.
Figure 48.
Circuit for Negative (−) PSRR Measurement
−PSRR
vs.
Frequency
+
120
V
RF
+
0.1 PF
560:
-
3
-
6
LMH6611
+
2
-
V = -2.5V
90
1
VO
50:
-
V
-
0.1 PF
1000 PF
+
+
80
+
70 V = +5V
60 V = -5V
V = +1.5V
50
V = -1.5V
+
-
40
30
0.1 PF
-
-PSRR (dB)
4
V = +2.5V
100
RG
560:
+
110
1000 PF
20
CABLE
1000 PF
50:
a
VIN
VIN = 225 mVPP
10 R = 560:
F
0
10 100 1k 10k
100k
1M
10M 100M
FREQUENCY (Hz)
Figure 49.
Figure 50.
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Typical Performance Characteristics (continued)
At TJ = 25°C, AV = +1 (RF = 0Ω), otherwise RF = 560Ω for AV ≠ +1, unless otherwise specified.
CMRR
vs.
Frequency
Crosstalk
vs.
Frequency
140
-40
+
+
V = +2.5V
-
-50 V = -2.5V
A = +1
-60 RL = 1 k:
V = -2.5V
CROSSTALK (dB)
100
CMRR (dB)
V = +2.5V
-
120
80
60
40
20
VOUT = 2 VPP
-70
-80
-90
-100
0
0.0001 0.001 0.01
0.1
1
10
100
-110
100k
1M
Figure 51.
Figure 52.
Small Signal Step Response
Small Signal Step Response
+
V = +1.5V
+
-
V = -2.5V
A = +1
V = -1.5V
A = +1
VOUT = 0.2V
VOUT = 0.2V
RL = 1 k:
RL = 1 k:
12.5 ns/DIV
12.5 ns/DIV
Figure 53.
Figure 54.
Small Signal Step Response
Small Signal Step Response
50 mV/DIV
50 mV/DIV
100M
V = +2.5V
-
+
V = +5V
+
V = +1.5V
-
V = -1.5V
A = -1
RF = 560:
-
V = -5V
A = +1
VOUT = 0.2V
VOUT = 0.2V
RL = 1 k:
RL = 1 k:
12.5 ns/DIV
12.5 ns/DIV
Figure 55.
18
10M
FREQUENCY (Hz)
50 mV/DIV
50 mV/DIV
FREQUENCY (MHz)
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Figure 56.
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Typical Performance Characteristics (continued)
At TJ = 25°C, AV = +1 (RF = 0Ω), otherwise RF = 560Ω for AV ≠ +1, unless otherwise specified.
Small Signal Step Response
50 mV/DIV
50 mV/DIV
Small Signal Step Response
+
V = +2.5V
-
V = -2.5V
A = -1
V+ = +5V
V- = -5V
A = -1
RF = 560:
RF = 560:
VOUT = 0.2V
VOUT = 0.2V
RL = 1 k:
RL = 1 k:
12.5 ns/DIV
Figure 57.
Figure 58.
Small Signal Step Response
Small Signal Step Response
50 mV/DIV
50 mV/DIV
12.5 ns/DIV
+
V = +1.5V
-
V = -1.5V
A = +2
RF = 560:
+
V = +2.5V
-
V = -2.5V
A = +2
RF = 560:
VOUT = 0.2V
VOUT = 0.2V
RL = 150:
RL = 150:
12.5 ns/DIV
Figure 59.
Figure 60.
Small Signal Step Response
Large Signal Step Response
500 mV/DIV
50 mV/DIV
12.5 ns/DIV
+
V = +5V
-
V = -5V
A = +2
RF = 560:
+
V = +2.5V
-
VOUT = 0.2V
V = -2.5V
A = +1
VOUT = 2V
RL = 150:
RL = 1 k:
12.5 ns/DIV
12.5 ns/DIV
Figure 61.
Figure 62.
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Typical Performance Characteristics (continued)
At TJ = 25°C, AV = +1 (RF = 0Ω), otherwise RF = 560Ω for AV ≠ +1, unless otherwise specified.
Large Signal Step Response
Overload Recovery Response
VIN
1V/DIV
500 mV/DIV
VOUT
+
V = +2.5V
-
+
V = +5V
V = -2.5V
A = +2
RF = 560:
-
V = -5V
AV = +5
VOUT = 2V
RF = 604:
RL = 150:
RL = 1 k:
12.5 ns/DIV
25 ns/DIV
Figure 63.
Figure 64.
IS
vs.
VDISABLE
4000
+
125°C
V = +2.5V
3500
-
V = -2.5V
25°C
3000
-40°C
IS (PA)
2500
2000
1500
1000
500
0
-2.5 -2.0 -1.5 -1.0 -0.5 0 0.5 1.0 1.5 2.0 2.5
VDISABLE (V)
Figure 65.
20
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APPLICATION INFORMATION
The LMH6611 and LMH6612 are based on proprietary VIP10 dielectrically isolated bipolar process. This device
family architecture features the following:
• Complimentary bipolar devices with exceptionally high ft (∼8 GHz) even under low supply voltage (2.7V) and
low bias current.
• Common emitter push-push output stage. This architecture allows the output to reach within millivolts of either
supply rail.
• Consistent performance with little variation from any supply voltage (2.7V - 11V) for the most important
specifications (BW, SR, IOUT, for example.)
• Significant power saving compared to competitive devices on the market with similar performance.
With 3V supplies and a common mode input voltage range that extends beyond either supply rail, the LMH6611
is well suited to many low voltage/low power applications. Even with 3V supplies, the −3 dB BW (at AV = +1) is
typically 305 MHz.
The LMH6611 and LMH6612 are designed to avoid output phase reversal. With input overdrive, the output is
kept near the supply rail (or as close to it as mandated by the closed loop gain setting and the input voltage).
Figure 66 shows the input and output voltage when the input voltage significantly exceeds the supply voltages.
2V/DIV
VIN
VOUT
+
V = +2.5V
-
V = -2.5V
AV = +1
RF = 560:
RL = 1 k:
25 ns/DIV
Figure 66. Input and Output Shown with CMVR Exceeded
If the input voltage range is exceeded by more than a diode drop beyond either rail, the internal ESD protection
diodes will start to conduct. The current flow in these ESD diodes should be externally limited.
SHUTDOWN CAPABILITY AND TURN ON/OFF BEHAVIOR
The LMH6611 can be shutdown by connecting the DISABLE pin to a voltage 0.5V below the supply midpoint
which will reduce the supply current to typically 120 µA. The DISABLE pin is “active low” and can be connected
through a resistor to V+ or left floating for normal operation. Shutdown is specified when the DISABLE pin is 0.5V
below the supply midpoint at any operating supply voltage and temperature. Typical turn on time is 20 ns and the
turn off time is 60 ns.
In the shutdown mode, essentially all internal device biasing is turned off in order to minimize supply current flow
and the output goes into high impedance mode. During shutdown, the input stage has an equivalent circuit as
shown in Figure 67.
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RS
50:
INVERTING
INPUT
D4
D1
D3
D2
NON-INVERTING
INPUT
Figure 67. Input Equivalent Circuit During Shutdown
When the LMH6611 is shutdown, there may be current flow through the internal diodes shown, caused by input
potential, if present. This current may flow through the external feedback resistor and result in an apparent output
signal. In most shutdown applications the presence of this output is inconsequential. However, if the output is
“forced” by another device, the other device will need to conduct the current described in order to maintain the
output potential.
To keep the output at or near ground during shutdown when there is no other device to hold the output low, a
switch using a transistor can be used to shunt the output to ground.
SELECTION OF RF AND EFFECT ON STABILITY AND PEAKING
The peaking of the LMH6611 depends on the value of the RF. From the graph shown in Figure 68, as the RF
value increases, the peaking increases.
For AV = 2, at RF = 1 kΩ, the −3 dB bandwidth is 113 MHz and peaking is about 0.6 dB whereas at RF = 665Ω,
the −3 dB bandwidth is about 110 MHz and peaking is 0 dB. RF and the input capacitance form a pole in the
amplifier’s response. If the time constant is too big, it will cause peaking and ringing.
Except for AV = 1 when RF should be 0Ω, across all other gain settings it is recommended that RF remain
between 500Ω and 1 kΩ to ensure optimum performance.
3
NORMALIZED GAIN (dB)
RF = RG = 1000:
0
RF = RG = 665:
-3 V+ = +2.5V
-
V = -2.5V
VOUT = 0.2V
RL = 1 k:
-6
1
10
100
1000
FREQUENCY (MHz)
Figure 68. Closed Loop Gain vs. Frequency and RF = RG
22
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RF = RG
f −3 dB (MHz)
665
110
0
1000
113
0.6
Peaking (dB)
MINIMIZING NOISE
With a low input voltage noise of 10 nV/√Hz and an input current noise of 2 pA√Hz the LMH6611 and LMH6612
are suitable for high accuracy applications. Still being able to reduce the frequency band of operation of the
various noise sources (that is, op amp noise voltage, resistor thermal noise, input noise current) can further
improve the noise performance of a system. In a non-inverting amplifier configuration inserting a capacitor, CG, in
series with the gain setting resistor, RG, will reduce the gain of the circuit below frequency, f = 1/2πRGCG. This
can be set to reduce the contribution of noise from the 1/f region. Alternatively applying a feedback capacitor, CF,
in parallel with the feedback resistor, RF, will introduce a pole into your system at f = 1/2πRFCF and create a low
pass filter. This filter can be set to reduce high frequency noise and harmonics. Finally remember to keep resistor
values as small as possible for a given application in order to reduce resistor thermal noise.
POWER SUPPLY BYPASS
Since the LMH6611 and LMH6612 are wide bandwidth amplifiers, proper power supply bypassing is critical for
optimum performance. Improper power supply bypassing can result in large overshoot, ringing or oscillation. 0.1
μF capacitors should be connected from the supply pins, V+ and V−, to ground, as close to the device as is
practical. Additionally, a 10 μF electrolytic capacitor should be connected from both supply pins to ground
reasonably close to the device. Finally, near the device a 0.1 μF ceramic capacitor between the supplies will
provide the best harmonic distortion performance.
INTERFACING HIGH PERFORMANCE OP AMPS WITH ADCs
These amplifiers are designed for ease of use in a wide range of applications requiring high speed, low supply
current, low noise, and the ability to drive complex ADC and video loads.
The source that drives the modern high resolution analog-to-digital converters (ADCs) sees a high frequency AC
load and a DC load of a few hundred ohms or more. Thus, a high performance op amp with high input
impedance of a few mega ohms and low output impedance would be an ideal choice as an input ADC driver.
The LMH6611/LMH6612 have the low output impedance of 0.07Ω at f = 1 MHz. The ADC driver acts as a buffer
and a low pass filter to reduce the overall system noise. To utilize the full dynamic range of the ADC, the ADC
input has to be driven to full scale input voltage.
As signals travel through the traces of a printed circuit board (PCB) and long cables, system noise accumulates
in the signals and a differential ADC rejects any signals noise that appears as a common mode voltage. There
are a couple of advantages to using differential signals rather than single-ended signals. First, differential signals
double the dynamic range of the ADC and second, they offer better harmonic distortion performance. There are
several ways to produce differential signals from a dual op amp configuration. One method is to utilize the singleended to differential conversion technique and the other is the differential to differential conversion technique.
The first method requires a single input source and the second method requires differential input source.
A real world input source can have non-ideal impedance thus the buffer amplifier, with very low output
impedance, is required to drive the input of the ADC. To minimize the droop in the input voltage, external shunt
capacitance (CL) should be about ten times larger than the internal input capacitance of the ADC and external
series resistance (RL) should be large enough to maintain the phase delay at the output of the op amp and
hence maintain the stability (See Figure 69). Most applications benefit from the inclusion of a series isolation
resistor connected between the op amp output and ADC input. This series resistor helps to limit the output
current of the op amp. The value chosen for this series resistor is very important, as a higher value will increase
the load impedance seen by the op amp and improve the total harmonic distortion (THD) performance of the op
amp; however, the ADC prefers a low impedance source driving it. Thus, the optimum value for this series
resistor must be found so that it will offer the best performance in terms of THD, SNR and SFDR of the combined
op amp and ADC.
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Important Specifications of Op Amp and ADC
When interfacing an ADC with an op amp it is imperative to understand the specifications that are important to
get the expected performance results. Modern ADC AC specifications such as THD, SNR, settling time and
SFDR are critical for filtering, test and measurement, video and reconstruction applications. The high
performance op amp’s settling time, THD, and noise performance must be better than that of the ADC it is driving
to maintain the proper system accuracy with minimal or no error.
Some system applications require low THD, low SFDR and wide dynamic range (SNR), whereas some system
applications require high SNR and they may sacrifice THD and SFDR to focus on the noise performance.
Noise is a very important specification for both the op amp and the ADC. There are three main sources of noise
that contribute to the overall performance of the ADC: Quantization noise, noise generated by the ADC itself
(particularly at higher frequencies) and the noise generated by the application circuit. The impedance of the input
source affects the noise performance of the op amp. Theoretically, an ADC’s signal to noise ratio (SNR) can be
found from the equation:
SNR (in dB) = 6.02*N+1.72
(1)
where N is the resolution of the ADC. For example, according to this equation a 12-bit ADC has an SNR of 74
dB. However, the practical SNR number would be about 72 dB. In order to achieve better SNR, the ADC driver
noise should be as small as possible. The LMH6611/LMH6612 have the low voltage noise of only 10 nV/√Hz.
The combined settling time of the op amp and the ADC must be within 1 LSB. The 0.01% settling time of the
LMH6611/LMH6612 is 100 ns.
The ADC driver’s THD should be inherently lower than that of the ADC. The LMH6611/LMH6612 have an SFDR
of 96 dBc at 2 VPP output and 1 MHz input frequency.
Signal to Noise and Distortion (SINAD) is a parameter which is the combination of the SNR and THD
specifications. SINAD is defined as the RMS value of the output signal to the RMS value of all of the other
spectral components below half the clock frequency, including harmonics but excluding DC. It can be calculated
from SNR and THD according to the equation:
-SNR
10
SINAD = 20 * LOG 10
THD
10
+ 10
(2)
Because SINAD compares all undesired frequency components with the input frequency, it is an overall measure
of an ADC’s dynamic performance. The following sections will discuss the three different ADC driver
architectures in detail.
SINGLE TO SINGLE ADC DRIVER
This architecture has a single-ended input source connected to the input of the op amp and the single-ended
output of the op amp is then fed to the single-ended input of the ADC. The low noise of only 10 nV/√Hz and a
wide bandwidth of 345 MHz make the LMH6611 an excellent choice for driving the 12-bit ADC121S101 500
KSPS to 1 MSPS ADC, which has a successive approximation architecture with internal sample and hold
circuits. Figure 67 shows the schematic of the LMH6611 in a 2nd order multiple-feedback with gain of −1
(inverting) configuration, driving an ADC121S101. The inverting configuration is preferred over the non-inverting
configuration, as it offers more linear output response. Table 1 shows the performance data of the LMH6611
combined with the ADC121S101. The ADC driver’s cutoff frequency of 500 kHz is found from the equation:
1
1
x
R 2 x R5 x C2 x C5
2S
(3)
The op amp’s gain is set by the equation:
R2
GAIN = R1
(4)
´
¶0
24
=
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1 PF
R1
R2
549:
549:
IN
R5
C5
1.24 k:
150 pF
+
V
+
V
C2
+
V
1 nF
0.1 PF
5V
0.1 PF
1 PF
0.1 PF
0.01 PF
10 PF
10 PF
RL
R6
14.3 k:
-
22:
ADC121S101
LMH6611
GND
+
5.6 PF
0.1 PF
CL
U1
390 pF
R7
14.3 k:
Figure 69. Single to Single ADC Driver
Table 1. Performance of the LMH6611 Combined with the ADC121S101
Amplifier
Output/ADC Input
SINAD
SNR
THD
SFDR
(dB)
(dB)
(dB)
(dBc)
4
70.2
71.6
−75.7
77.6
ENOB
Notes
11.4
ADC121S101 @ f = 200 kHz
When the op amp and the ADC are using the same supply, it is important that both devices are well bypassed. A
0.1 µF ceramic capacitor and a 10 µF tantalum capacitor should be located as close as possible to each supply
pin. A sample layout is shown in Figure 70. The 0.1 µF capacitors (C13 and C6) and the 10 µF capacitors (C11
and C5) are located very close to the supply pins of the LMH6611 and the ADC121S101.
The following are recommendations for the design of PCB layout in order to obtain the optimum high frequency
performance:
• Place ADC and amplifier as close together as possible.
• Put the supply bypassing capacitors as close as possible to the device (<1”).
• Utilize surface mount instead of through-hole components and ground and power planes.
• Keep the traces short where possible.
• Use terminated transmission lines for long traces.
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Figure 70. LMH6611 and ADC121S101 Layout
SINGLE-ENDED TO DIFFERENTIAL ADC DRIVER
The single-ended to differential ADC driver in Figure 68 utilizes an LMH6612 dual op amp to buffer a singleended source to drive an ADC with differential inputs. One of the op amps is configured as a unity gain buffer
that drives the inverting (IN−) input of the op amp U2 and non-inverting (IN+) input of the ADC121S625. U2
inverts the input signal and drives the inverting input of the ADC121S625. The ADC driver is configured for a
gain of +2 to reduce the noise without sacrificing THD performance. The common mode voltage of 2.5V is set up
at the non-inverting inputs of both op amps U1 and U2. This configuration produces differential ±2.5 VPP output
signals, when the single-ended input signal of 0 to VREF is AC coupled into the non-inverting terminal of the op
amp and each non-inverting terminal of the op amp is biased at the mid-scale of 2.5V. The two output RC antialiasing filters are used between both the outputs of U1 and U2 and the input of the ADC121S625 to minimize
the effect of undesired high frequency noise coming from the input source. Each RC filter has the cutoff
frequency of approximately 22 MHz.
+
V
V
+
0.1 PF
10 PF
-
560:
10 PF
33:
+
V
LMH6612
+
INPUT
220 pF
U1
560:
560:
0.1 PF
10 PF
560:
+
V
ADC121S625
+
V
560:
0.1 PF
10 PF
-
33:
LMH6612
+
U2
220 pF
560:
Figure 71. Single-Ended to Differential ADC Driver
26
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The performance of the LMH6612 with the ADC121S625 is shown in Table 2.
Table 2. Performance of the LMH6612 Combined with the ADC121S625
Amplifier
Output/ADC Input
SINAD
SNR
THD
SFDR
(dB)
(dB)
(dB)
(dBc)
2.5
68.8
69
−81.5
75.1
ENOB
Notes
11.2
ADC121S625 @ f = 20 kHz
DIFFERENTIAL TO DIFFERENTIAL ADC DRIVER
The LMH6612 dual op amp can be configured as a differential to differential ADC driver to buffer a differential
source to a differential input ADC as shown in Figure 72. The differential to differential ADC driver can be formed
using two single to single ADC drivers. Each output from these drivers goes to a separate input of the differential
ADC. Here, each single to single ADC driver uses the same components and is configured for a gain of -1
(inverting).
1 PF
549:
549:
+IN
150 pF
1.24 k:
+
V
V
1 nF
+
0.1 PF
10 PF
+
V
14.3 k:
-
22:
LMH6612
0.1 PF
+
5.6 PF
390 pF
10 PF
0.1 PF
14.3 k:
ADC121S705
1 PF
549:
549:
22:
-IN
390 pF
150 pF
1.24 k:
+
V
1 nF
+
V
0.1 PF
14.3 k:
10 PF
LMH6612
+
5.6 PF
0.1 PF
14.3 k:
Figure 72. Differential to Differential ADC Driver
The following table summarizes the performance of the LMH6612 combined with the ADC121S625 at two
different frequencies. In order to utilize the full dynamic range of the ADC, the maximum input of 2.5 VPP is
applied to the ADC input. Figure 73 shows the FFT plot of the LMH6612 and ADC121S625 combination tested at
f = 20 kHz input frequency.
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Table 3. Performance of the LMH6612 Combined with the ADC121S625
Amplifier
Output/ADC Input
SINAD
SNR
THD
SFDR
(dB)
(dB)
(dB)
(dBc)
ENOB
Notes
2.5
72.2
72.3
−87.7
92.1
11.7
ADC121S625 @ f = 20 kHz
2.5
72.2
72.2
−87.8
90.8
11.7
ADC121S625 @ f = 200 kHz
Figure 73. The FFT Plot of Differential to Differential ADC Driver
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SNOSB00K – NOVEMBER 2007 – REVISED OCTOBER 2013
DC LEVEL SHIFTING
Often a signal must be both amplified and level shifted while using a single supply for the op amp. The circuit in
Figure 74 can do both of these tasks. The procedure for specifying the resistor values is as follows.
1. Determine the input voltage.
2. Calculate the input voltage midpoint, VINMID = VINMIN + (VINMAX – VINMIN)/2.
3. Determine the output voltage needed.
4. Calculate the output voltage midpoint, VOUTMID = VOUTMIN + (VOUTMAX – VOUTMIN)/2.
5. Calculate the gain needed, gain = (VOUTMAX – VOUTMIN)/(VINMAX – VINMIN)
6. Calculate the amount the voltage needs to be shifted from input to output, ΔVOUT = VOUTMID – gain x VINMID.
7. Set the supply voltage to be used.
8. Calculate the noise gain, noise gain = gain + ΔVOUT/VS.
9. Set RF.
10. Calculate R1, R1 = RF/gain.
11. Calculate R2, R2 = RF/(noise gain-gain).
12. Calculate RG, RG= RF/(noise gain – 1).
Check that both the VIN and VOUT are within the voltage ranges of the LMH6611.
V
+
+
V
R2
R1
VIN
+
LMH6611
VOUT
-
RG
RF
Figure 74. DC Level Shifting
The following example is for a VIN of 0V to 1V with a VOUT of 2V to 4V.
1. VIN = 0V to 1V
2. VINMID = 0V + (1V – 0V)/2 = 0.5V
3. VOUT = 2V to 4V
4. VOUTMID = 2V + (4V – 2V)/2 = 3V
5. Gain = (4V – 2V)/(1V – 0V) = 2
6. ΔVOUT = 3V – 2 x 0.5V = 2
7. For the example the supply voltage will be +5V.
8. Noise gain = 2 + 2/5V = 2.4
9. RF = 2 kΩ
10. R1 = 2 kΩ/2 = 1 kΩ
11. R2 = 2 kΩ/(2.4-2) = 5 kΩ
12. RG = 2 kΩ/(2.4 – 1) = 1.43 kΩ
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4th ORDER MULTIPLE FEEDBACK LOW-PASS FILTER
Figure 75 shows the LMH6612 used as the amplifier in a multiple feedback low pass filter. This filter is set up to
have a gain of +1 and a −3 dB point of 1 MHz. Values can be determined by using the WEBENCH® Active Filter
Designer found at www.ti.com/amplifiers
1.05 k:
1.02 k:
150 pF
62 pF
+
V
+
V
0.1 PF
1.05 k:
1 PF
523:
0.1 PF
-
INPUT
330 pF
1.02 k:
LMH6612
-
+
LMH6612
820 pF
0.1 PF
1 PF
510:
OUTPUT
+
1 PF
0.1 PF
1 PF
-
V
-
V
Figure 75. 4th Order Multiple Feedback Low-Pass Filter
CURRENT SENSE AMPLIFIER AND OPTIMIZING ACCURACY IN PRECESION APPLICATIONS
With it’s rail-to-rail output capability, low VOS, and low IB the LMH6611 is an ideal choice for a current sense
amplifier application. Figure 76 shows the schematic of the LMH6611 set up in a low-side sense configuration
which provides a conversion gain of 2V/A. Voltage error due to VOS can be calculated to be VOS x (1 + RF/RG) or
1.5 mV x 21 = 31.5 mV. Voltage error due to IO is IO x RF or 0.5 µA x 1 kΩ = 0.5 mV. Hence worst case total
voltage error is 12.6 mV + 0.5 mV or 13.1 mV which translates into a current error of 13.1 mV/(2 V/A) = 6.55 mA.
This circuit employs DC source resistance matching at the two input terminals in order to minimize the output DC
error caused by input bias current. Another technique to reduce output offset in a non-inverting amplifier
configuration is to introduce a DC offset current into the inverting input of the amplifier. To ensure minimal impact
on frequency response be sure to inject the DC offset current through large resistors. Conversely if optimizing an
inverting amplifier configuration simply apply offset adjustment to the non-inverting input.
+5V
0A to 1A
51:
+
1 k:
0.1:
LMH6611
51:
1 k:
Figure 76. Current Sense Amplifier
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SNOSB00K – NOVEMBER 2007 – REVISED OCTOBER 2013
TRANSIMPEDANCE AMPLIFIER
By definition, a photodiode produces either a current or voltage output from exposure to a light source. A
Transimpedance Amplifier (TIA) is utilized to convert this low-level current to a usable voltage signal. The TIA
often will need to be compensated to insure proper operation.
CF
RF
VS
LMH6611
CIN
CPD
+
Figure 77. Photodiode Modeled with Capacitance Elements
Figure 77 shows the LMH6611 modeled with photodiode and the internal op amp capacitances. The LMH6611
allows circuit operation of a low intensity light due to its low input bias current by using larger values of gain (RF).
The total capacitance (CT) on the inverting terminal of the op amp includes the photodiode capacitance (CPD) and
the input capacitance of the op amp (CIN). This total capacitance (CT) plays an important role in the stability of
the circuit. The noise gain of this circuit determines the stability and is defined by:
1 + sRF (CT + CF)
NG =
1 + sCFRF
(5)
Where, fZ #
1
1
and fP =
2SRFCF
2SRFCT
(6)
OP AMP OPEN
LOOP GAIN
GAIN (dB)
I-V GAIN (:)
NOISE GAIN (NG)
1 + sRF (CT + CF)
1 + sRFCF
1+
CIN
CF
0 dB
FREQUENCY
fz #
1
2SRFCT
fP =
1
GBWP
2SRFCF
Figure 78. Bode Plot of Noise Gain Intersecting with Op Amp Open Loop Gain
Figure 78 shows the bode plot of the noise gain intersecting the op amp open loop gain. With larger values of
gain, CT and RF create a zero in the transfer function. At higher frequencies the circuit can become unstable due
to excess phase shift around the loop.
A pole at fP in the noise gain function is created by placing a feedback capacitor (CF) across RF. The noise gain
slope is flattened by choosing an appropriate value of CF for optimum performance.
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Theoretical expressions for calculating the optimum value of CF and the expected −3 dB bandwidth are:
CF =
CT
2SRF(GBWP)
(7)
GBWP
f-3 dB = 2SR C
F T
(8)
Equation 8 indicates that the −3 dB bandwidth of the TIA is inversely proportional to the feedback resistor.
Therefore, if the bandwidth is important then the best approach would be to have a moderate transimpedance
gain stage followed by a broadband voltage gain stage.
Table 4 shows the measurement results of the LMH6611 with different photodiodes having various capacitances
(CPD) and a feedback resistance (RF) of 1 kΩ.
Table 4. TIA (Figure 66) Compensation and Performance Results (1)
(1)
CPD
CT
CF
(pF)
(pF)
(pF)
22
24
5.42
47
49
100
222
330
CF
f −3 dB CAL
f −3 dB MEAS
Peaking
(pF)
(MHz)
(MHz)
(dB)
5.6
29.3
27.1
0.5
7.75
8
20.5
21
0.5
102
11.15
12
14.2
15.2
0.5
224
20.39
18
9.6
10.7
0.5
332
20.2
22
7.9
9
0.8
CAL
USED
GBWP = 130 MHz, CT = CPD + CIN, CIN = 2 pF, VS = ±2.5V
Figure 79 shows the frequency response for the various photodiodes in Table 4.
3
CPD = 22 pF,
NORMALIZED I-V GAIN (dB)
0
-3
-6
CF = 5.6 pF
CPD = 47 pF,
CF = 8 pF
-9
-12
-15
-18
-21
-24
-27
1M
CPD = 100 pF,
CF = 12 pF
CPD = 222 pF,
CF = 18 pF
CPD = 330 pF,
CF = 22 pF
10M
100M
FREQUENCY (Hz)
Figure 79. Frequency Response for Various Photodiode and Feedback Capacitors
When analyzing the noise at the output of the TIA, it is important to note that the various noise sources (that is,
op amp noise voltage, feedback resistor thermal noise, input noise current, photodiode noise current) do not all
operate over the same frequency band. Therefore, when the noise at the output is calculated, this should be
taken into account. The op amp noise voltage will be gained up in the region between the noise gain’s zero and
pole (fZ and fP in Figure 78). The higher the values of RF and CT, the sooner the noise gain peaking starts and
therefore its contribution to the total output noise will be larger. It is advantageous to minimize CIN by proper
choice of op amp or by applying a reverse bias across the diode but this will be at the expense of excess dark
current and noise.
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SNOSB00K – NOVEMBER 2007 – REVISED OCTOBER 2013
EVALUATION BOARD
TI provides the following evaluation board as a guide for high frequency layout and as an aid in device testing
and characterization. Many of the datasheet plots were measured with this board:
Device
Package
Board Part #
LMH6611MK
SOT
LMH730216
LMH6612MA
SOIC
LMH730036
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REVISION HISTORY
Changes from Revision I (March 2013) to Revision J
•
Page
Changed layout of National Data Sheet to TI format .......................................................................................................... 33
Changes from Revision J (September 2013) to Revision K
Page
•
Changed from 0.1 uV/°C to 4 μV/°C ..................................................................................................................................... 3
•
Changed from 0.1 uV/°C to 4 μV/°C ..................................................................................................................................... 5
•
Changed from 0.4 uV/°C to 4 μV/°C ..................................................................................................................................... 7
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PACKAGE OPTION ADDENDUM
www.ti.com
23-Jul-2013
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
(2)
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
LMH6611MK/NOPB
ACTIVE
SOT
DDC
6
1000
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
-40 to 125
AX4A
LMH6611MKE/NOPB
ACTIVE
SOT
DDC
6
250
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
-40 to 125
AX4A
LMH6611MKX/NOPB
ACTIVE
SOT
DDC
6
3000
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
-40 to 125
AX4A
LMH6612MA/NOPB
ACTIVE
SOIC
D
8
95
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
-40 to 125
LMH66
12MA
LMH6612MAX/NOPB
ACTIVE
SOIC
D
8
2500
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
-40 to 125
LMH66
12MA
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
23-Jul-2013
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
23-Jul-2013
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
LMH6611MK/NOPB
SOT
DDC
6
LMH6611MKE/NOPB
SOT
DDC
LMH6611MKX/NOPB
SOT
DDC
LMH6612MAX/NOPB
SOIC
D
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
1000
178.0
8.4
3.2
3.2
1.4
4.0
8.0
Q3
6
250
178.0
8.4
3.2
3.2
1.4
4.0
8.0
Q3
6
3000
178.0
8.4
3.2
3.2
1.4
4.0
8.0
Q3
8
2500
330.0
12.4
6.5
5.4
2.0
8.0
12.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
23-Jul-2013
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
LMH6611MK/NOPB
SOT
DDC
6
1000
210.0
185.0
35.0
LMH6611MKE/NOPB
SOT
DDC
6
250
210.0
185.0
35.0
LMH6611MKX/NOPB
SOT
DDC
6
3000
210.0
185.0
35.0
LMH6612MAX/NOPB
SOIC
D
8
2500
367.0
367.0
35.0
Pack Materials-Page 2
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