Renesas HD74HC597 8-bit latch / shift register Datasheet

HD74HC597
8-bit Latch / Shift Register
REJ03D0635-0200
(Previous ADE-205-515)
Rev.2.00
Mar 30, 2006
Description
The HD74HC597 consists of an 8-bit storage latch feeding a parallel-in, serial-out 8-bit shift register. Both the storage
register and shift register have positive-edge triggered clocks. The shift register also has direct load (from storage) and
clear inputs.
Features
• High Speed Operation: tpd (SCK to QH’) = 14 ns typ (CL = 50 pF)
• High Output Current: Fanout of 10 LSTTL Loads
• Wide Operating Voltage: VCC = 2 to 6 V
• Low Input Current: 1 µA max
• Low Quiescent Supply Current: ICC (static) = 4 µA max (Ta = 25°C)
• Ordering Information
Part Name
Package Type
HD74HC597P
DILP-16 pin
HD74HC597FPEL
SOP-16 pin (JEITA)
HD74HC597RPEL
SOP-16 pin (JEDEC)
Package Code
(Previous Code)
PRDP0016AE-B
(DP-16FV)
PRSP0016DH-B
(FP-16DAV)
PRSP0016DG-A
(FP-16DNV)
Package
Abbreviation
Taping Abbreviation
(Quantity)
P
—
FP
EL (2,000 pcs/reel)
RP
EL (2,500 pcs/reel)
Note: Please consult the sales office for the above package availability.
Function Table
Inputs
SCK
X
SLoad
X
SCLR
X
X
X
X
L
L
H
H
Data loaded from inputs to shift register
Data transferred from input latches to shift register
X
X
X
X
L
H
L
L
Invalid logic, state of shift register indeterminate when signals removed
Shift register cleared
H
H
Shift register clocked Qn = Qn – 1, QA = SER
RCK
X
Rev.2.00 Mar 30, 2006 page 1 of 9
Function
Data loaded to input latches
HD74HC597
Pin Arrangement
B 1
16 VCC
C 2
15 A
D 3
14 SER
E 4
13 S Load
F 5
12 RCK
G 6
11 SCK
H 7
10 SCLR
GND 8
9 Q'H
(Top view)
Logic Diagram
SCLR
SER
SCK
SLoad
RCK
A
DQ
C
SC
D
Q
R
B
DQ
C
SC
D
Q
R
DQ
C
SC
D
Q
R
C
D
E
F
G
H
Q'H
Rev.2.00 Mar 30, 2006 page 2 of 9
HD74HC597
Absolute Maximum Ratings
Item
Symbol
Ratings
Unit
Supply voltage range
Input / Output voltage
VCC
VIN, VOUT
–0.5 to 7.0
–0.5 to VCC +0.5
V
V
IIK, IOK
IOUT
±20
±25
mA
mA
ICC or IGND
PT
±50
500
mA
mW
Input / Output diode current
Output current
VCC, GND current
Power dissipation
Storage temperature
Tstg
–65 to +150
°C
Note: The absolute maximum ratings are values, which must not individually be exceeded, and furthermore, no two of
which may be realized at the same time.
Recommended Operating Conditions
Item
Supply voltage
Symbol
VCC
Ratings
2 to 6
Unit
V
Input / Output voltage
Operating temperature
VIN, VOUT
Ta
0 to VCC
–40 to 85
V
°C
tr , tf
0 to 1000
0 to 500
Input rise / fall time
Note:
*1
ns
0 to 400
1. This item guarantees maximum limit when one input switches.
Waveform: Refer to test circuit of switching characteristics.
Conditions
VCC = 2.0 V
VCC = 4.5 V
VCC = 6.0 V
Electrical Characteristics
Item
Input voltage
Symbol VCC (V)
VIH
VIL
Output voltage
VOH
VOL
Input current
Quiescent supply
current
Iin
ICC
Min
Ta = 25°C
Typ
Max
Ta = –40 to+85°C
Unit
Min
Max
2.0
4.5
1.5
3.15
—
—
—
—
1.5
3.15
—
—
6.0
2.0
4.2
—
—
—
—
0.5
4.2
—
—
0.5
4.5
6.0
—
—
—
—
1.35
1.8
—
—
1.35
1.8
2.0
4.5
1.9
4.4
2.0
4.5
—
—
1.9
4.4
—
—
6.0
4.5
5.9
4.18
6.0
—
—
—
5.9
4.13
—
—
6.0
2.0
5.68
—
—
0.0
—
0.1
5.63
—
—
0.1
4.5
6.0
—
—
0.0
0.0
0.1
0.1
—
—
0.1
0.1
4.5
6.0
—
—
—
—
0.26
0.26
—
—
0.33
0.33
6.0
6.0
—
—
—
—
±0.1
4.0
—
—
±1.0
40
Rev.2.00 Mar 30, 2006 page 3 of 9
Test Conditions
V
V
V
Vin = VIH or VIL IOH = –20 µA
IOH = –4 mA
V
IOH = –5.2 mA
Vin = VIH or VIL IOL = 20 µA
IOL = 4 mA
IOL = 5.2 mA
µA Vin = VCC or GND
µA Vin = VCC or GND, Iout = 0 µA
HD74HC597
Switching Characteristics (CL = 50 pF, Input tr = tf = 6 ns)
Ta = 25°C
Item
Symbol VCC (V)
Maximum clock
frequency
fmax
Propagation delay
time
tPLH
tPHL
Removal time
Setup time
Hold time
Pulse width
trem
tsu
th
tw
Output rise/fall
time
tTLH
tTHL
Input capacitance
Cin
Ta = –40 to +85°C
2.0
Min
—
Typ
—
Max
5
Min
—
Max
4
4.5
6.0
—
—
—
—
27
31
—
—
21
24
2.0
4.5
—
—
—
14
175
35
—
—
220
44
6.0
2.0
—
—
—
—
30
210
—
—
37
265
4.5
6.0
—
—
17
—
42
36
—
—
53
45
2.0
4.5
100
20
—
—
—
–
125
25
—
—
6.0
2.0
17
100
—
—
—
—
21
125
—
—
4.5
6.0
20
17
—
—
—
—
25
21
—
—
2.0
4.5
100
20
—
1
—
—
125
25
—
—
6.0
2.0
17
100
—
—
—
—
21
125
—
—
4.5
6.0
20
17
0
—
—
—
25
21
—
—
2.0
4.5
5
5
—
—
—
—
5
5
—
—
6.0
2.0
5
5
—
—
—
—
5
5
—
—
4.5
6.0
5
5
—
—
—
—
5
5
—
—
2.0
4.5
80
16
—
7
—
—
100
20
—
—
6.0
2.0
14
—
—
—
—
75
17
—
—
95
4.5
6.0
—
—
4
—
15
13
—
—
19
16
—
—
5
10
—
10
Rev.2.00 Mar 30, 2006 page 4 of 9
Unit
Test Conditions
MHz
ns
SCK or SLoad or SCLR to QH’
ns
RCK to QH’
ns
ns
RCK to SCK
ns
SER to SCK
ns
Data to RCK
ns
SCK to SA
ns
LCK to Data
ns
ns
pF
HD74HC597
Test Circuit
VCC
VCC
Output
SCLR
Pulse Generator
Zout = 50 Ω
Input
Pulse Generator
Zout = 50 Ω
See Function Table
Input
SLoad
QH'
CL = 50pF
RCK
A to H
SER
SCK
Note : 1. CL includes probe and jig capacitance.
Waveforms
• Waveform – 1 (RCK to QH')
tf
tr
VCC
90 %
50 % 50 %
Input RCK
10 %
50 %
10 %
tw(H)
t PLH
t PHL
90 %
Output QH'
0V
tw(L)
VOH
90 %
50 %
10 %
50 %
10 %
t TLH
VOL
t THL
Note : 1. Input waveform : PRR ≤ 1 MHz, duty cycle 50%, tr ≤ 6 ns, tf ≤ 6 ns
• Waveform – 2 (RCK to Q)
tf
tr
10 %
tw(H)
t PLH
50 %
10 %
t TLH
50 %
10 %
0V
tw(L)
t PHL
90 %
Output QH'
VCC
90 %
50 % 50 %
Input SCK
VOH
90 %
50 %
10 %
VOL
t THL
Note : 1. Input waveform : PRR ≤ 1 MHz, duty cycle 50%, tr ≤ 6 ns, tf ≤ 6 ns
Rev.2.00 Mar 30, 2006 page 5 of 9
HD74HC597
• Waveform – 3 (SCLR to QH')
tf
Input SCLR
tr
90 %
50 %
VCC
90 %
50 %
10 %
10 %
0V
tw
t PHL
VOH
90 %
Output QH'
50 %
10 %
VOL
t THL
t rem
90 %
Input SCK
50 %
10 %
VCC
0V
t TLH
Note : 1. Input waveform : PRR ≤ 1 MHz, duty cycle 50%, tr ≤ 6 ns, tf ≤ 6 ns
• Waveform – 4 (SLoad to QH')
tf
Input SLoad
tr
90 %
50 %
90 %
50 %
10 %
10 %
tw
VCC
50 %
0V
t PLH
t PHL
90 %
90 %
Output QH'
50 %
10 %
t THL
50 %
10 %
VOH
VOL
t TLH
Note : 1. Input waveform : PRR ≤ 1 MHz, duty cycle 50%, tr ≤ 6 ns, tf ≤ 6 ns
Rev.2.00 Mar 30, 2006 page 6 of 9
HD74HC597
• Waveform – 5 (Data to RCK)
tr/tf
Input A to H
90 %
tr/tf
90 %
90 %
50 %
10 %
50 %
10 %
50 %
10 %
t su
0V
th
90 %
Input RCK
VCC
90 %
50 %
10 %
VCC
90 %
50 %
10 %
10 %
tr
0V
tf
Note : 1. Input waveform : PRR ≤ 1 MHz, duty cycle 50%, tr ≤ 6 ns, tf ≤ 6 ns
• Waveform – 6 (SER to SCK)
tr/tf
Input SER
90 %
tr/tf
90 %
90 %
50 %
10 %
50 %
10 %
50 %
10 %
t su
0V
th
90 %
Input SCK
VCC
90 %
50 %
10 %
VCC
90 %
50 %
10 %
10 %
tr
0V
tf
Note : 1. Input waveform : PRR ≤ 1 MHz, duty cycle 50%, tr ≤ 6 ns, tf ≤ 6 ns
• Waveform – 7 (SLoad to SCK)
tr
tf
10 %
10 %
t su
0V
th
90 %
Input SCK
VCC
90 %
50 %
90 %
50 %
Input SLoad
VCC
90 %
50 %
10 %
10 %
tr
tf
Note : 1. Input waveform : PRR ≤ 1 MHz, duty cycle 50%, tr ≤ 6 ns, tf ≤ 6 ns
Rev.2.00 Mar 30, 2006 page 7 of 9
0V
HD74HC597
Package Dimensions
JEITA Package Code
P-DIP16-6.3x19.2-2.54
RENESAS Code
PRDP0016AE-B
Previous Code
DP-16FV
MASS[Typ.]
1.05g
D
9
E
16
1
8
b3
0.89
A1
A
Z
L
Reference
Symbol
θ
bp
e
e1
D
E
A
A1
bp
b3
c
θ
e
Z
L
c
e1
( Ni/Pd/Au plating )
JEITA Package Code
P-SOP16-5.5x10.06-1.27
RENESAS Code
PRSP0016DH-B
*1
Previous Code
FP-16DAV
Dimension in Millimeters
Min
Nom Max
7.62
19.2 20.32
6.3 7.4
5.06
0.51
0.40 0.48 0.56
1.30
0.19 0.25 0.31
0°
15°
2.29 2.54 2.79
1.12
2.54
MASS[Typ.]
0.24g
D
F
16
NOTE)
1. DIMENSIONS"*1 (Nom)"AND"*2"
DO NOT INCLUDE MOLD FLASH.
2. DIMENSION"*3"DOES NOT
INCLUDE TRIM OFFSET.
9
c
HE
*2
E
bp
Index mark
Terminal cross section
( Ni/Pd/Au plating )
1
Z
8
e
*3
bp
x
Reference
Symbol
M
A
L1
A1
θ
y
L
Detail F
Rev.2.00 Mar 30, 2006 page 8 of 9
D
E
A2
A1
A
bp
b1
c
c1
θ
HE
e
x
y
Z
L
L1
Dimension in Millimeters
Min Nom Max
10.06 10.5
5.50
0.00 0.10 0.20
2.20
0.34 0.40 0.46
0.15 0.20 0.25
0°
8°
7.50 7.80 8.00
1.27
0.12
0.15
0.80
0.50 0.70 0.90
1.15
HD74HC597
JEITA Package Code
P-SOP16-3.95x9.9-1.27
RENESAS Code
PRSP0016DG-A
*1
Previous Code
FP-16DNV
MASS[Typ.]
0.15g
D
F
16
NOTE)
1. DIMENSIONS"*1 (Nom)"AND"*2"
DO NOT INCLUDE MOLD FLASH.
2. DIMENSION"*3"DOES NOT
INCLUDE TRIM OFFSET.
9
c
*2
Index mark
HE
E
bp
Terminal cross section
( Ni/Pd/Au plating )
1
Z
Reference
Symbol
8
e
*3
bp
x
M
A
L1
A1
θ
L
y
Detail F
Rev.2.00 Mar 30, 2006 page 9 of 9
D
E
A2
A1
A
bp
b1
c
c1
θ
HE
e
x
y
Z
L
L1
Dimension in Millimeters
Min Nom Max
9.90 10.30
3.95
0.10 0.14 0.25
1.75
0.34 0.40 0.46
0.15 0.20 0.25
0°
8°
5.80 6.10 6.20
1.27
0.25
0.15
0.635
0.40 0.60 1.27
1.08
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