TI1 AM4384CZDNA100S Sitara processors technical brief Datasheet

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AM4382, AM4384, AM4388
SPRT726A – MARCH 2017 – REVISED APRIL 2017
AM438x Sitara™ Processors Technical Brief
1 Device Overview
1.1
Features
• Highlights
– Sitara™ ARM® Cortex®-A9 32-Bit RISC
Processor With Processing Speed up to
1000 MHz
– NEON™ SIMD Coprocessor and Vector
Floating Point (VFPv3) Coprocessor
– 32KB of Both L1 Instruction and Data Cache
– 256KB of L2 Cache or L3 RAM
– 32-Bit LPDDR2, DDR3, and DDR3L Support
– General-Purpose Memory Support (NAND,
NOR, SRAM) Supporting up to 16-Bit ECC
– SGX530 Graphics Engine
– Display Subsystem
– Programmable Real-Time Unit Subsystem and
Industrial Communication Subsystem (PRUICSS)
– Real-Time Clock (RTC)
– Up to Two USB 2.0 High-Speed Dual-Role
(Host or Device) Ports With Integrated PHY
– 10, 100, and 1000 Ethernet Switch
– Serial Interfaces:
– Six UARTs, Two McASPs, Five McSPIs,
Three I2C Ports, One QSPI, and One HDQ or
1-Wire
– Up to Two ISO7816 (Smart Card) Interfaces
– Security
– Crypto Hardware Accelerators (AES, SHA,
PKA, RNG, DES, and 3DES) With Crypto
DMA
– Secure Boot
– Physical (Enclosure) Protection
– 12 Tamper I/Os
– Wire Mesh
– Tamper Protection
– Voltage Monitoring
– Temperature Monitoring
– Crystal Monitoring
– Erasable Secure Memory for Encryption
Keys
– Configurable Tamper Response
– Tamper Events Log
– Partial ARM TrustZone With Secure RunTime Environment for Secure Applications
– On-the-Fly-Encryption (OTFE) of the DDR
Memory Bus Interface
– Touch Screen Controller, ADC0
1
– 12-Bit Successive Approximation Register
(SAR) ADC0
– Up to 867K Samples Per Second
– Input Can be Selected from Any of the Eight
Analog Inputs Multiplexed through an 8:1
Analog Switch
– Can Be Configured to Operate as a 4-, 5-, or
8-Wire Resistive Touch Screen Controller
(TSC) Interface
– Magnetic Card Reader, ADC1
– Up to Three 32-Bit Enhanced Capture (eCAP)
Modules
– Up to Three Enhanced Quadrature Encoder
Pulse (eQEP) Modules
– Up to Six Enhanced High-Resolution PWM
(eHRPWM) Modules
• MPU Subsystem
– ARM Cortex-A9 32-Bit RISC Microprocessor
With Processing Speed up to 1000 MHz
– 32KB of Both L1 Instruction and Data Cache
– 256KB of L2 Cache (Option to Configure as L3
RAM)
– 256KB of On-Chip Boot ROM
– 64KB of On-Chip RAM
– Secure Control Module (SCM)
– Emulation and Debug
– JTAG
– Embedded Trace Buffer
– Interrupt Controller
• On-Chip Memory (Shared L3 RAM)
– 256KB of General-Purpose On-Chip Memory
Controller (OCMC) RAM
– 8KB Erasable Memory
– Accessible to All Masters
– Supports Retention for Fast Wakeup
– Up to 512KB of Total Internal RAM
(256KB of ARM Memory Configured as L3 RAM
+ 256KB of OCMC RAM)
• External Memory Interfaces (EMIFs)
– DDR Controllers:
– LPDDR2: 266-MHz Clock (LPDDR2-533 Data
Rate)
– DDR3 and DDR3L: 400-MHz Clock (DDR800 Data Rate)
– 32-Bit Data Bus
– 2GB of Total Addressable Space
– Supports One x32, Two x16, or Four x8
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. ADVANCE INFORMATION for pre-production products; subject to
change without notice.
ADVANCE INFORMATION
1
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SPRT726A – MARCH 2017 – REVISED APRIL 2017
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ADVANCE INFORMATION
Memory Device Configurations
• General-Purpose Memory Controller (GPMC)
– Flexible 8- and 16-Bit Asynchronous Memory
Interface With up to Seven Chip Selects (NAND,
NOR, Muxed-NOR, and SRAM)
– Uses BCH Code to Support 4-, 8-, or 16-Bit
ECC
– Uses Hamming Code to Support 1-Bit ECC
• Error Locator Module (ELM)
– Used With the GPMC to Locate Addresses of
Data Errors From Syndrome Polynomials
Generated Using a BCH Algorithm
– Supports 4-, 8-, and 16-Bit Per 512-Byte Block
Error Location Based on BCH Algorithms
• Programmable Real-Time Unit Subsystem and
Industrial Communication Subsystem (PRU-ICSS)
– Two Programmable Real-Time Units (PRUs)
Subsystems With Two PRU Cores Each
– Each Core is a 32-Bit Load and Store RISC
Processor Capable of Running at 200 MHz
– 12KB (PRU-ICSS1), 4KB (PRU-ICSS0) of
Instruction RAM With Single-Error Detection
(Parity)
– 8KB (PRU-ICSS1), 4KB (PRU-ICSS0) of
Data RAM With Single-Error Detection
(Parity)
– Single-Cycle 32-Bit Multiplier With 64-Bit
Accumulator
– Enhanced GPIO Module Provides Shift-In
and Shift-Out Support and Parallel Latch on
External Signal
– 12KB (PRU-ICSS1 Only) of Shared RAM With
Single-Error Detection (Parity)
– Three 120-Byte Register Banks Accessible by
Each PRU
– Interrupt Controller Module (INTC) for Handling
System Input Events
– Local Interconnect Bus for Connecting Internal
and External Masters to the Resources Inside
the PRU-ICSS
– Peripherals Inside the PRU-ICSS
– One UART Port With Flow Control Pins,
Supports up to 12 Mbps
– One eCAP Module
– Two MII Ethernet Ports that Support Industrial
Ethernet, such as EtherCAT
– One MDIO Port
• Power, Reset, and Clock Management (PRCM)
Module
– Controls the Entry and Exit of Deep-Sleep
Modes
– Responsible for Sleep Sequencing, Power
Domain Switch-Off Sequencing, Wake-Up
Sequencing, and Power Domain Switch-On
Sequencing
2
– Clocks
– Integrated High-Frequency Oscillator Used to
Generate a Reference Clock (19.2, 24, 25,
and 26 MHz) for Various System and
Peripheral Clocks
– Supports Individual Clock Enable and Disable
Control for Subsystems and Peripherals to
Facilitate Reduced Power Consumption
– Five ADPLLs to Generate System Clocks
(MPU Subsystem, DDR Interface, USB, and
Peripherals [MMC and SD, UART, SPI, I2C],
L3, L4, Ethernet, GFX [SGX530], and LCD
Pixel Clock)
– Power
– Three Nonswitchable Power Domains (RTC,
Wake-Up Logic [WAKE-UP], and Physical or
Tamper [TPM])
– Three Switchable Power Domains (MPU
Subsystem, SGX530 [GFX], Peripherals and
Infrastructure [PER])
– Dynamic Voltage Frequency Scaling (DVFS)
• Real-Time Clock (RTC)
– Real-Time Date (Day, Month, Year, and Day of
Week) and Time (Hours, Minutes, and Seconds)
Information
– Internal 32.768-kHz Oscillator, RTC Logic, and
1.1-V Internal LDO
– Independent Power-On-Reset
(RTC_PWRONRSTn) Input
– Dedicated Input Pin (TPM_WAKEUP) for
External Wake Events
– Programmable Alarm Can Generate Internal
Interrupts to the PRCM for Wakeup or CortexA9 for Event Notification
– Programmable Alarm Can Be Used With
External Output (RTC_PMIC_EN) to Enable the
Power-Management IC to Restore Non-RTC
Power Domains
• Peripherals
– Up to Two USB 2.0 High-Speed Dual-Role
(Host or Device) Ports With Integrated PHY
– Up to Two Industrial Gigabit Ethernet MACs
(10, 100, and 1000 Mbps)
– Integrated Switch
– Each MAC Supports MII, RMII, and RGMII
and MDIO Interfaces
– Ethernet MACs and Switch Can Operate
Independent of Other Functions
– IEEE 1588v2 Precision Time Protocol (PTP)
– Up to Two Multichannel Audio Serial Ports
(McASPs)
– Transmit and Receive Clocks up to 50 MHz
– Up to Four Serial Data Pins Per McASP Port
With Independent TX and RX Clocks
– Supports Time Division Multiplexing (TDM),
Inter-IC Sound (I2S), and Similar Formats
Device Overview
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–
–
–
–
–
–
–
–
–
–
–
–
–
–
SPRT726A – MARCH 2017 – REVISED APRIL 2017
– Supports Digital Audio Interface Transmission
(SPDIF, IEC60958-1, and AES-3 Formats)
– FIFO Buffers for Transmit and Receive
(256 Bytes)
Up to Six UARTs
– All UARTs Support IrDA and CIR Modes
– All UARTs Support RTS and CTS Flow
Control
– UART1 Supports Full Modem Control
Up to Five Master and Slave McSPIs
– McSPI0–McSPI2 Support up to Four Chip
Selects
– McSPI3 and McSPI4 Support up to Two Chip
Selects
– Up to 48 MHz
One Quad-SPI
– Supports eXecute In Place (XIP) from Serial
NOR FLASH
One Dallas 1-Wire® and HDQ Serial Interface
Up to Three MMC, SD, and SDIO Ports
– 1-, 4-, and 8-Bit MMC, SD, and SDIO Modes
– 1.8- or 3.3-V Operation on All Ports
– Up to 48-MHz Clock
– Supports Card Detect and Write Protect
– Complies With MMC4.3 and SD and SDIO
2.0 Specifications
Up to Two ISO7816 (Smart Card) Interfaces
– EMV-Compliant
– Supports T=0 and T=1 Protocols
One Magnetic Card Reader (ADC1)
– ISO7811-Compliant
– AFE Contains 12-bit, 867 kSPS ADC With
Four Differential Channels, Including PreAmplifier
– ADC Can Be Used For General Purposes
Up to Three I2C Master and Slave Interfaces
– Standard Mode (up to 100 kHz)
– Fast Mode (up to 400 kHz)
Up to Six Banks of General-Purpose I/O (GPIO)
– 32 GPIOs per Bank (Multiplexed With Other
Functional Pins)
– GPIOs Can be Used as Interrupt Inputs (up
to Two Interrupt Inputs per Bank)
Up to Three External DMA Event Inputs That
Can Also be Used as Interrupt Inputs
Twelve 32-Bit General-Purpose Timers
– DMTIMER1 is a 1-ms Timer Used for
Operating System (OS) Ticks
– DMTIMER4–DMTIMER7 are Pinned Out
One Public and One Secure Watchdog Timer
One Free-Running, High-Resolution 32-kHz
Counter (synctimer32K)
SGX530 3D Graphics Engine
– Tile-Based Architecture Delivering up to 20M
Poly/sec
– Universal Scalable Shader Engine is a
Multithreaded Engine Incorporating Pixel and
Vertex Shader Functionality
– Advanced Shader Feature Set in Excess of
Microsoft VS3.0, PS3.0, and OGL2.0
– Industry Standard API Support of Direct3D
Mobile, OGL-ES 1.1 and 2.0, and OpenVG
1.0
– Fine-Grained Task Switching, Load
Balancing, and Power Management
– Advanced Geometry DMA-Driven Operation
for Minimum CPU Interaction
– Programmable High-Quality Image AntiAliasing
– Fully Virtualized Memory Addressing for OS
Operation in a Unified Memory Architecture
– Display Subsystem
– Display Modes
– Programmable Pixel Memory Formats
(Palletized: 1-, 2-, 4-, and 8-Bits Per Pixel;
RGB 16- and 24-Bits Per Pixel; and YUV
4:2:2)
– 256- × 24-Bit Entries Palette in RGB
– Up to 2048 × 2048 Resolution
– Display Support
– Four Types of Displays Are Supported:
Passive and Active Colors; Passive and
Active Monochromes
– 4- and 8-Bit Monochrome Passive Panel
Interface Support (15 Grayscale Levels
Supported Using Dithering Block)
– RGB 8-Bit Color Passive Panel Interface
Support (3,375 Colors Supported for Color
Panel Using Dithering Block)
– RGB 12-, 16-, 18-, and 24-Bit Active
Panel Interface Support (Replicated or
Dithered Encoded Pixel Values)
– Remote Frame Buffer (Embedded in the
LCD Panel) Support Through the RFBI
Module
– Partial Refresh of the Remote Frame
Buffer Through the RFBI Module
– Partial Display
– Multiple Cycles Output Format on 8-, 9-,
12-, and 16-Bit Interface (TDM)
– Signal Processing
– Overlay and Windowing Support for One
Graphics Layer (RGB or CLUT) and Two
Video Layers (YUV 4:2:2, RGB16, and
RGB24)
– RGB 24-Bit Support on the Display
Interface, Optionally Dithered to RGB
18‑Bit Pixel Output Plus 6-Bit Frame Rate
Control (Spatial and Temporal)
Device Overview
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– Transparency Color Key (Source and
Destination)
– Synchronized Buffer Update
– Gamma Curve Support
– Multiple-Buffer Support
– Cropping Support
– Color Phase Rotation
– Up to Three 32-Bit eCAP Modules
– Configurable as Three Capture Inputs or
Three Auxiliary PWM Outputs
– Up to Six Enhanced eHRPWM Modules
– Dedicated 16-Bit Time-Base Counter With
Time and Frequency Controls
– Configurable as Six Single-Ended, Six DualEdge Symmetric, or Three Dual-Edge
Asymmetric Outputs
– Up to Three 32-Bit eQEP Modules
• Device Identification
– Factory Programmable Electrical Fuse Farm
(FuseFarm)
– Production ID
– Device Part Number (Unique JTAG ID)
– Device Revision (Readable by Host ARM)
– Security Keys
– Feature Identification
• Debug Interface Support
– JTAG and cJTAG for ARM (Cortex-A9 and
PRCM) and PRU-ICSS Debug
– Supports Real-Time Trace Pins (for Cortex-A9)
– 64-KB Embedded Trace Buffer (ETB)
– Supports Device Boundary Scan
– Supports IEEE 1500
1.2
•
•
•
•
4
• DMA
– On-Chip Enhanced DMA Controller (EDMA) Has
Three Third-Party Transfer Controllers (TPTCs)
and One Third-Party Channel Controller
(TPCC), Which Supports up to 64
Programmable Logical Channels and Eight
QDMA Channels
– EDMA is Used for:
– Transfers to and from On-Chip Memories
– Transfers to and from External Storage
(EMIF, GPMC, and Slave Peripherals)
– DMA for Crypto Data Paths and Transfers
(Crypto DMA)
• InterProcessor Communication (IPC)
– Integrates Hardware-Based Mailbox for IPC and
Spinlock for Process Synchronization Between
the Cortex-A9, PRCM, and PRU-ICSS
• Boot Modes
– Boot Mode is Selected Through Boot
Configuration Pins Latched on the Rising Edge
of the PWRONRSTn Reset Input Pin
• Camera
– Dual Port 8- and 10-Bit BT656 Interface
– Dual Port 8- and 10-Bit Including External Syncs
– Single Port 12-Bit
– YUV422/RGB422 and BT656 Input Format
– RAW Format
– Pixel Clock Rate up to 75 MHz
• Package
– 491-Pin BGA Package (17-mm × 17-mm) (ZDN
Suffix), 0.65-mm Ball Pitch With Via Channel
Array Technology to Enable Low-Cost Routing
Applications
Electronic Financial Transaction Terminals
Point of Sale Terminals
Fuel Dispensers
Vending Machines
•
•
•
•
Electric Vehicle Charging Stations
Automated Teller Machines
Fiscal Printers
Voting Machines
Device Overview
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1.3
SPRT726A – MARCH 2017 – REVISED APRIL 2017
Description
The TI AM438x high-performance processors are based on the ARM Cortex-A9 core.
The processors are enhanced with payment card peripherals and logical and physical security to help
customers meet payment card industry (PCI) requirements. The devices support high-level operating
systems (HLOS). Linux® is available free of charge from TI.
The devices offer an upgrade to systems based on lower performance ARM cores, provide updated
peripherals, including memory options such as QSPI-NOR and LPDDR2, and support the security features
discussed below.
The processors contain the subsystems shown in the Functional Block Diagram, and a brief description of
each follows.
The programmable real-time unit subsystem and industrial communication subsystem (PRU-ICSS) is
separate from the ARM core and allows independent operation and clocking for greater efficiency and
flexibility. The programmable nature of the PRU-ICSS, along with their access to pins, events and all
system-on-chip (SoC) resources, provides flexibility in implementing fast real-time responses, specialized
data handling operations, custom peripheral interfaces, and in off-loading tasks from the other processor
cores of the SoC.
High-performance interconnects provide high-bandwidth data transfers for multiple initiators to the internal
and external memory controllers and to on-chip peripherals. The device also offers a comprehensive
clock-management scheme.
The on-chip analog to digital converter (ADC0) can couple with the display subsystem to provide an
integrated touch-screen solution. There is also an EMV-compliant ISO7816 interface (Smart Card)
interface and magnetic card controller (ADC1).
The RTC provides a clock reference on a separate power domain. The clock reference enables a batterybacked clock reference.
The camera interface offers configuration for a single- or dual-camera parallel port.
The physical protection subsystem adds enclosure protection to the secure features offered by the
AM438x processors which include cryptography acceleration and secure boot. Enclosure protection helps
customers design products that detect when the casing is opened, and protect sensitive parts of the circuit
with a wire mesh. Tamper protection monitors voltage, temperature, and crystal frequency so system
designers can detect external attacks.
In addition, the partial ARM TrustZone allows system designers to configure memory for secure storage
and protect against software attacks.
Table 1-1. Device Information (1)
PART NUMBER
PACKAGE
BODY SIZE
AM4382ZDN
NFBGA (491)
17.0 mm × 17.0 mm
AM4384ZDN
NFBGA (491)
17.0 mm × 17.0 mm
AM4388ZDN
NFBGA (491)
17.0 mm × 17.0 mm
(1)
For more information, see Section 5, Mechanical, Packaging, and Orderable Information.
Device Overview
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ADVANCE INFORMATION
The processor subsystem is based on the ARM Cortex-A9 core, and the PowerVR SGX™ graphics
accelerator subsystem provides 3D graphics acceleration to support display and advanced user interfaces.
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1.4
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Functional Block Diagram
ARM
Cortex-A9
Up to 1000 MHz
Graphics
Display
PowerVR
TM
SGX
3D GFX
20 MTri/s
24-bit LCDCtrl (WXGA)
Touchscreen Controller (TSC)
(A)
Processing: Overlay,
Resizing,Color Space
Conversion, and more
Quad Core
PRU-ICSS
Security
32KB, 32KB L1
256KB L2, L3 RAM
64KB RAM
256KB
L3 RAM
Enclosure Protect
Secure Boot
Tamper Protection
On-the-Fly
Encryption
Crypto Blocks
Secure Storage
L3 and L4 Interconnect
ADVANCE INFORMATION
System Interface
UART x6
EDMA
SPI x5
Timers x12
QSPI
WDT
2
RTC
I C x3
HDQ, 1-Wire
eHRPWM x6
McASP x2 (4ch)
eQEP, eCAP x3
GPIO
ISO7816 Interface
x2
JTAG, ETB
ADC0 (8 inputs)
(A)
12-bit SAR
Camera Interface
(2x Parallel)
MMC, SD,
SDIO x3
USB 2.0 Dual-Role
+ PHY x2
EMAC switch
10, 100, 1G with
1588 (MII, RMII,
RGMII,
and MDIO)
Memory Interface
32b LPDDR2, DDR3, DDR3L
On-the-Fly Encryption
Magnetic Card
Reader
(B)
NAND, NOR, Async
(16-bit ECC)
Copyright © 2017, Texas Instruments Incorporated
A.
B.
Use of TSC limits available ADC0 inputs.
Maximum clock: LPDDR2 = 266 MHz; DDR3/DDR3L = 400 MHz.
Figure 1-1. Functional Block Diagram
6
Device Overview
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Table of Contents
Device Overview ......................................... 1
4.3
Documentation Support ............................. 12
1.1
Features .............................................. 1
4.4
Related Links ........................................ 13
1.2
Applications ........................................... 4
4.5
Community Resources .............................. 13
1.3
Description ............................................ 5
4.6
Trademarks.......................................... 13
1.4
Functional Block Diagram ............................ 6
4.7
Electrostatic Discharge Caution ..................... 13
2
3
Revision History ......................................... 8
Device Comparison ..................................... 9
4.8
Glossary ............................................. 13
4
Device and Documentation Support ............... 11
5.1
Via Channel ......................................... 14
4.1
Device Nomenclature ............................... 11
5.2
Packaging Information
4.2
Tools and Software
1
Related Products .................................... 10
.................................
Mechanical, Packaging, and Orderable
Information .............................................. 14
..............................
14
12
ADVANCE INFORMATION
3.1
5
Table of Contents
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2 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Original (March 2017) to Revision A
•
Changed paragraphs discussing security features in Section 1.3, Description
Page
..............................................
5
ADVANCE INFORMATION
8
Revision History
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3 Device Comparison
Table 3-1 shows the features supported across different AM438x devices.
FUNCTION
ARM Cortex-A9
Frequency
MIPS
AM4382
AM4384
AM4388
Yes
Yes
Yes
300 MHz
600 MHz
1000 MHz
600 MHz
1000 MHz
600 MHz
1000 MHz
750
1500
2500
1500
2500
1500
2500
On-chip L1 cache
64KB
64KB
64KB
On-chip L2 cache
256KB
256KB
256KB
Graphics accelerator (SGX530)
Hardware acceleration
Programmable real-time unit subsystem and
industrial communication subsystem (PRU-ICSS)
On-chip memory
Display options
General-purpose memory
DRAM(1)
Universal serial bus (USB)
—
Yes
Yes
Crypto accelerator
Crypto accelerator
Crypto accelerator
—
—
Yes
256KB
256KB
256KB
DSS
DSS
DSS
1 16-bit (GPMC, NAND flash,
NOR flash, SRAM)
1 16-bit (GPMC, NAND flash,
NOR flash, SRAM)
1 16-bit (GPMC, NAND flash,
NOR flash, SRAM)
1 32-bit (DDR3-800, DDR3L-800,
LPDDR2-532)
1 32-bit (DDR3-800, DDR3L-800,
LPDDR2-532)
1 32-bit (DDR3-800, DDR3L-800,
LPDDR2-532)
2 ports
2 ports
2 ports
10/100/1000
2 ports
10/100/1000
2 ports
10/100/1000
2 ports
Multimedia card (MMC)
3
3
3
Controller-area network (CAN)
2
2
2
Universal asynchronous receiver and transmitter
(UART)
6
6
6
Ethernet media access controller (EMAC) with 2port switch
Analog-to-digital converter (ADC)
2 8-ch 12-bit
2 8-ch 12-bit
2 8-ch 12-bit
Enhanced high-resolution PWM modules
(eHRPWM)
6
6
6
Enhanced capture modules (eCAP)
3
3
3
Enhanced quadrature encoder pulse (eQEP)
3
3
3
Real-time clock (RTC)
1
1
1
Inter-integrated circuit (I2C)
3
3
3
Multichannel audio serial port (McASP)
2
2
2
Multichannel serial port interface (McSPI)
5
5
5
Enhanced direct memory access (EDMA)
64-Ch
64-Ch
64-Ch
Camera (VPFE)
12-bit
12-bit
12-bit
Sync timer (32K)
1
1
1
HDQ/1-Wire
1
1
1
QSPI
1
1
1
Device Comparison
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Table 3-1. Device Features Comparison
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www.ti.com
Table 3-1. Device Features Comparison (continued)
FUNCTION
Timers
DEV_FEATURE register value(2)
Input/output (I/O) supply
Operating temperature range
AM4382
AM4384
12
12
AM4388
12
0x0FFC7CFE
0x2FFC7CFE
0x2FFD7CFF
1.8 V, 3.3 V
1.8 V, 3.3 V
1.8 V, 3.3 V
–40 to 105°C
–40 to 105°C
–40 to 105°C
(1) DRAM speeds listed are data rates.
(2) For more details about the DEV_FEATURE register, see the Device Features section of the AM438x Sitara Processors Technical
Reference Manual.
3.1
Related Products
For information about other devices in this family of products or related products, see the following link:
Sitara Processors Scalable processors based on ARM Cortex-A cores with flexible peripherals,
connectivity and unified software support – perfect for sensors to servers.
ADVANCE INFORMATION
10
Device Comparison
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4 Device and Documentation Support
4.1
Device Nomenclature
To designate the stages in the product development cycle, TI assigns prefixes to the part numbers of all
processors and support tools. Each device has one of three prefixes: X, P, or null (no prefix) (for example,
XAM4384xZDN). Texas Instruments recommends two of three possible prefix designators for its support
tools: TMDX and TMDS. These prefixes represent evolutionary stages of product development from
engineering prototypes (TMDX) through fully qualified production devices and tools (TMDS).
Device development evolutionary flow:
X
Experimental device that is not necessarily representative of the final device's electrical
specifications and may not use production assembly flow.
P
Prototype device that is not necessarily the final silicon die and may not necessarily meet
final electrical specifications.
null
Production version of the silicon die that is fully qualified.
TMDX
Development-support product that has not yet completed Texas Instruments internal
qualification testing.
TMDS
Fully-qualified development-support product.
X and P devices and TMDX development-support tools are shipped against the following disclaimer:
"Developmental product is intended for internal evaluation purposes."
Production devices and TMDS development-support tools have been characterized fully, and the quality
and reliability of the device have been demonstrated fully. TI's standard warranty applies.
Predictions show that prototype devices (X or P) have a greater failure rate than the standard production
devices. Texas Instruments recommends that these devices not be used in any production system
because their expected end-use failure rate still is undefined. Only qualified production devices are to be
used.
TI device nomenclature also includes a suffix with the device family name. This suffix indicates the
package type (for example, ZDN), the temperature range (for example, blank is the default commercial
temperature range), and the device speed range, in megahertz (for example, MHz). Figure 4-1 provides a
legend for reading the complete device name for any device.
For additional description of the device nomenclature markings on the die, see the AM438x Sitara
Processors Silicon Errata.
Device and Documentation Support
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11
ADVANCE INFORMATION
Support tool development evolutionary flow:
AM4382, AM4384, AM4388
SPRT726A – MARCH 2017 – REVISED APRIL 2017
X
AM4384
www.ti.com
(
)
ZDN
A
(
)
S
PREFIX
X = Experimental device
Blank = Qualified device
SUFFIX
S = High-Security device, Secure Boot Supported
DEVICE SPEED RANGE
30 = 300-MHz Cortex-A9
60 = 600-MHz Cortex-A9
100 = 1000-MHz Cortex-A9
(A)
DEVICE
ARM Cortex-A9 MPU:
AM4382
AM4384
AM4388
TEMPERATURE RANGE
A = -40°C to 105°C (extended junction temperature)
DEVICE REVISION CODE
A = silicon revision 1.1
B = silicon revision 1.2
C = silicon revision 1.3
A.
B.
(B)
PACKAGE TYPE
ZDN = 491-pin plastic BGA, with Pb-Free solder balls
The device shown in this device nomenclature example is one of several valid part numbers for this family of devices.
BGA = Ball Grid Array.
Figure 4-1. Device Nomenclature
ADVANCE INFORMATION
4.2
Tools and Software
TI offers an extensive line of development tools. Tools and software to evaluate the performance of the
device, generate code, and develop solutions are listed below.
Design Kits and Evaluation Modules
AM437x Evaluation Module Enables developers to immediately start evaluating the AM437x processor
family and begin building applications such as portable navigation, patient monitoring,
home/building automation, barcode scanners, portable data terminals and others.
4.3
Documentation Support
The current documentation that describes the processor, related peripherals, and other technical collateral
is listed below.
Errata
AM438x Sitara Processors Silicon Errata
Describes
specifications for this microprocessor.
the
known
exceptions
to
the
functional
User's Guide
AM438x Sitara Processors Technical Reference Manual Collection of documents providing detailed
information on the device including power, reset, and clock control, interrupts, memory map,
and switch fabric interconnect. Detailed information on the microprocessor unit (MPU)
subsystem as well as a functional description of the peripherals supported is also included.
The following documents are related to the processor. Copies of these documents can be obtained
directly from the internet or from your Texas Instruments representative. To determine the revision of the
Cortex-A9 core used on your device, see the device-specific errata.
Cortex-A9 Technical Reference Manual Technical reference manual for the Cortex-A9 processor.
ARM Core Cortex-A9 (AT400/AT401) Errata Notice Provides a list of advisories for the different
revisions of the Cortex-A9 processor. For a copy of this document, contact your TI
representative.
12
Device and Documentation Support
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Product Folder Links: AM4382 AM4384 AM4388
AM4382, AM4384, AM4388
www.ti.com
4.4
SPRT726A – MARCH 2017 – REVISED APRIL 2017
Related Links
Table 4-1 lists quick access links. Categories include technical documents, support and community
resources, tools and software, and quick access to sample or buy.
Table 4-1. Related Links
4.5
PARTS
PRODUCT FOLDER
ORDER NOW
TECHNICAL
DOCUMENTS
TOOLS &
SOFTWARE
SUPPORT &
COMMUNITY
AM4382
Click here
Click here
Click here
Click here
Click here
AM4384
Click here
Click here
Click here
Click here
Click here
AM4388
Click here
Click here
Click here
Click here
Click here
Community Resources
TI E2E™ Online Community The TI engineer-to-engineer (E2E) community was created to foster
collaboration among engineers. At e2e.ti.com, you can ask questions, share knowledge,
explore ideas and help solve problems with fellow engineers.
TI Embedded Processors Wiki Established to help developers get started with Embedded Processors
from Texas Instruments and to foster innovation and growth of general knowledge about the
hardware and software surrounding these devices.
4.6
Trademarks
Sitara, E2E are trademarks of Texas Instruments.
NEON is a trademark of ARM Ltd or its subsidiaries.
ARM, Cortex are registered trademarks of ARM Ltd or its subsidiaries.
PowerVR SGX is a trademark of Imagination Technologies Limited.
Linux is a registered trademark of Linus Torvalds.
1-Wire is a registered trademark of Maxim Integrated Products, Inc.
All other trademarks are the property of their respective owners.
4.7
Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
4.8
Glossary
TI Glossary This glossary lists and explains terms, acronyms, and definitions.
Device and Documentation Support
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13
ADVANCE INFORMATION
The following links connect to TI community resources. Linked contents are provided "AS IS" by the
respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views;
see TI's Terms of Use.
AM4382, AM4384, AM4388
SPRT726A – MARCH 2017 – REVISED APRIL 2017
www.ti.com
5 Mechanical, Packaging, and Orderable Information
5.1
Via Channel
The ZDN package has been specially engineered with Via Channel technology. This technology allows
larger than normal PCB via and trace sizes and reduced PCB signal layers to be used in a PCB design
with the 0.65-mm pitch package, and substantially reduces PCB costs. It allows PCB routing in only two
signal layers (four layers total) due to the increased layer efficiency of the Via Channel BGA technology.
NOTE
Via Channel technology implemented on the this package makes it possible to build a
product with a 4-layer PCB, but a 4-layer PCB may not meet system performance goals.
Therefore, system performance using a 4-layer PCB design must be evaluated during
product design.
5.2
Packaging Information
ADVANCE INFORMATION
The following packaging information and addendum reflect the most current data available for the
designated device. This data is subject to change without notice and without revision of this document.
The following figure is a preliminary package drawing for the ZDN package option.
Note: The ZDN package is shown with a 17-mm × 17-mm array of 491 solder balls with 0.65-mm pitch,
with via channel array (VCA) technology.
14
Mechanical, Packaging, and Orderable Information
Copyright © 2017, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: AM4382 AM4384 AM4388
PACKAGE OPTION ADDENDUM
www.ti.com
25-Apr-2017
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
AM4382CZDNA100S
PREVIEW
NFBGA
ZDN
491
90
Green (RoHS
& no Sb/Br)
SNAGCU
Level-3-260C-168 HR
-40 to 105
AM4382CZDNA100S
AM4384CZDNA100S
PREVIEW
NFBGA
ZDN
491
90
Green (RoHS
& no Sb/Br)
SNAGCU
Level-3-260C-168 HR
-40 to 105
AM4384CZDNA100S
AM4388CZDNA100S
PREVIEW
NFBGA
ZDN
491
90
Green (RoHS
& no Sb/Br)
SNAGCU
Level-3-260C-168 HR
-40 to 105
AM4388CZDNA100S
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
25-Apr-2017
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
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