TI BQ2058T Lithium ion pack supervisor for 2-cell pack Datasheet

bq2058T
Lithium Ion Pack Supervisor
For 2-Cell Packs
Features
General Description
➤ Protects and individually monitors two Li-Ion series cells for
overvoltage, undervoltage
The bq2058T Lithium Ion Pack Supervisor is designed to control the
charge and discharge cell voltage limits for two lithium-ion (Li-Ion) series
cells, accommodating battery packs
containing series/parallel configurations. The low operating current does
not overdischarge the cells during periods of storage and does not significantly increase the system discharge
load. The bq2058T can be part of a
low-cost Li-Ion charge control system
within the battery pack.
➤ Monitors pack for overcurrent
➤ Designed for battery pack integration
➤ Minimal external components
➤ Drives external FET switches
➤ Selectable overvoltage (V OV )
thresholds
-
Mask programmable by
Benchmarq
-
Standard version–4.25V
➤ Supply current: 12µA typical
➤ Sleep current: 0.7µA typical
➤ 16-pin 150-mil narrow SOIC
The bq2058T controls two external
FETs to limit the charge and discharge
potentials. The bq2058T allows charging when each individual cell voltage is
below VOV (overvoltage limit). If the
voltage on any cell exceeds VOV for a
user-configurable delay period (tOVD),
the open-drain CHG pin goes to the
high-impedance state, shutting off
charge to the battery pack. This safety
feature prevents overcharge of any cell
within the battery pack. After an overvoltage condition occurs, each cell must
fall below VCE (charge enable voltage)
for the bq2058T to re-enable charging.
The bq2058T protects batteries from
overdischarge. If the voltage on any
cell falls below VUV (undervoltage
limit) for a user-configurable delay period (tUVD), the DSG output is driven
low, shutting off the battery discharge.
This safety feature prevents overdischarge of any cell within the battery
pack.
The bq2058T also stops discharge on
detection of an overcurrent condition,
such as a short circuit. If an overcurrent condition occurs for a userconfigurable delay period (tOCD), the
DSG output is driven low, disconnecting the load from the pack. DSG remains low until removal of the short
circuit or overcurrent condition.
Pin Names
Pin Connections
CHG
Charge control output
CTL
Pack disable input
CHG
1
16
DSG
CTL
2
15
VCC
VSS
3
14
UVD
VSS
Low potential input
CSL
4
13
OVD
CSL
BAT2N
5
12
OCD
Overcurrent sense low-side
input
BAT2N
6
11
VCC
BAT2N
7
10
CSH
BAT1N
8
9
BAT2N
Battery 2 negative input
BAT1N
Battery 1 negative input
BAT1P
16-Pin Narrow SOIC
PN2058T1.eps
July 1997
1
DSG
Discharge control output
UVD
Undervoltage delay input
OVD
Overvoltage delay input
OCD
Overcurrent delay input
VCC
High potential input
CSH
Overcurrent sense high-side
input
BAT1P
Battery 1 positive input
bq2058T
UVD
Pin Descriptions
CHG
This input uses an external capacitor to VCC
to set the undervoltage delay timing.
Charge control output
This open-drain output controls the charge
path to the battery pack. Charging is allowed
when high.
CTL
OVD
OCD
When high, this input allows an external
source to disable the pack by making both
DSG and CHG inactive. For normal operation, the CTL pin is low.
Low potential input
CSL
Overcurrent sense low-side input
VCC
High potential inputs (2 pins)
CSH
Overcurrent sense high-side input
T h i s i n p u t i s co n n e cte d b e tw e e n the
high-side discharge FET (or sense resistor)
and BAT1P to enable overcurrent sense in
the battery pack’s positive supply path.
BAT1P
Battery 2 negative inputs (3 pins)
Battery 1 positive input
This input is connected to the positive terminal
of the cell designated BAT1 in Figure 2.
These pins are connected to the negative terminal of the cell designated BAT2 in Figure 2.
BAT1N
Overcurrent delay input
This input uses an external capacitor to VCC
to set the overcurrent delay timing.
This input is connected between the low-side
discharge FET (or sense resistor) and BAT2N to
enable overcurrent sensing in the battery
pack’s ground path.
BAT2N
Overvoltage delay input
This input uses an external capacitor to VCC
to set the overvoltage delay timing.
Pack disable input
VSS
Undervoltage delay input
Battery 1 negative input
This input is connected to the negative terminal of the cell designated BAT1 in Figure 2.
DSG
Discharge control output
This push-pull output controls the discharge
path to the battery pack. Discharge is allowed when high.
July 1997
2
bq2058T
Sel2
Sel1
Cell Inputs
Pin 9 B1P
Pin 8 B1N
+
-
Pin 7 B2N
Pin 3
VOV
+
D
CK
D Q
Chip Negative
Supply
Sel2
CK
Any_Above_VOV
Sel1
Out
Edge
QB
Reset
Non-Retrigger
Oneshot
Reset
D Q
CK
Over_charge
Pin 1
QB
CHG
Charge Control
Output (open drain)
Capacitor
Pin 13 OVD
Discharge Off Delay Capacitor Input
QB
All_Below_VCE
Any_Below_VUV
+
VCE
Sleep
D
CK
D Q
Sel2
QB
D Q
Sel1
Pin 10 CSH
Pin 9
Pin 4
Pin 7
Sel2
CSL
B2N
CK
Overcurrent Delay
Capacitor Input
D Q
CK
QB
Reset
DSG
Discharge Control
Output (totem pole)
70mV
+
70mV
+
Out
Edge
QB
Sel1
Non-Retrigger
Oneshot
Reset
B1P
D Q
VUV
QB
Capacitor
UVD
Pin 14
Charge Off Delay Capacitor Input
CK
QB
+
Pin 16
Out
Edge
CK
Pin 10 CSH
Pin 9
Pin 4
Pin 7
Pin 12 OCD
Non-Retrigger
Oneshot
Reset
D
CK Q
QB
Over_current
Reset
Capacitor
160mV
B1P
+
CSL
160mV
B2N
+
Pin 2
CTL
External Output Control
Figure 1. Block Diagram
July 1997
3
BD2058T1.eps
bq2058T
The bq2058T samples a cell every 60ms (typical). Every
sample is a fully differential measurement of each cell.
During this sample period, the bq2058T compares the
measurements with these thresholds to determine if any
of the these conditions exist: VOV, VUV, and VCE.
Functional Description
Figure 1 is a block diagram outlining the major components of the bq2058T. Figure 2 shows a low-side control
connection diagram. The following sections detail the
various functional aspects of the bq2058T.
Overcurrent and charge detect are conditions that are
not sampled, but are continuously monitored.
Thresholds
Initialization
The bq2058T monitors the lithium ion pack for the conditions listed below. Shown with these conditions are
the respective thresholds used to determine if that condition exists:
■
Overvoltage (VOV)
■
Undervoltage (VUV)
■
Overcurrent (VOCH, VOCL)
■
Charge Enable (VCE)
■
Charge Detect (VCD)
On initial power-up, such as connecting the battery pack
for the first time to the bq2058T, the bq2058T enters the
low-power sleep mode, disabling the DSG output. It is
recommended that a top to bottom cell connection
be made at pack assembly for proper initialization. A charging supply must be applied to the bq2058T
circuit to enable the pack. See Low-Power Sleep Mode
and Charge Detect sections.
POS
R2
CHG
DSG
CTL
VCC
VSS
UVD
CSL
OVD
BAT2N
OCD
BAT2N
VCC
BAT2N
BAT1N
CSH
C1
C2
C3
BAT1
C4
BAT1P
bq2058T
R1
BAT2
C5
C7
Q1
NEG
Q2
C6
FG2058T1.eps
Figure 2. 2-Cell Connection Diagram, Low-Side Control
July 1997
4
bq2058T
Table 1. Overvoltage Threshold Options
Low-Power Sleep Mode
The bq2058T enters the low-power sleep mode in two
different ways:
1.
On initial power-up.
2.
After the detection of an undervoltage condition–VUV.
Part #
VOV Limit
bq2058T
4.25V
bq2058TR
4.35V
The overvoltage threshold limits are programmed
at Benchmarq. The bq2058T is the standard option that is more readily available for sampling
and prototyping purposes. Please contact Benchmarq for other voltage threshold and tolerance
options.
When the bq2058T enters the low-power sleep mode,
DSG is driven low and the device consumes 0.7µA (typical). The bq2058T only comes out of low-power sleep
mode when a valid charge detect condition exists.
Charge Detect
Charge Enable
The bq2058T continuously monitors for a charge detect
condition. A valid charge detect condition exists when either of the conditions is true:
A valid charge enable indicates that an overvoltage
(overcharge) condition no longer exists and that the
pack is ready to accept further charge. Once overvoltage
protection is asserted, charging will not be enabled until all cell voltages fall below VCE. The VCE threshold is
a function of VOV, and changes with different VOV limits.
CSL < BAT2N - 70mV (VCD)
CSH > BAT1P + 70mV (VCD)
A valid charge detect enables the DSG output, allowing
charging of the lithium ion cells. This is accomplished
by applying the charging supply to the pack.
VCE = VOV - 150mV
Undervoltage
Overcurrent
Undervoltage (or overdischarge) protection is asserted
when any cell voltage drops below the VUV threshold
and remains below the V UV threshold for a time
exceeding a user-configurable delay (tUVD). The DSG
output is driven low, disabling the discharge of the pack.
The bq2058T then enters the low-power sleep mode.
VUV is defined as follows:
The bq2058T detects an overcurrent (or short circuit)
condition only in the discharge direction. Overcurrent
protection is asserted when either of the conditions occu rs a n d re ma i n f o r a ti me e x ce e d i n g a u s erconfigurable delay (tOCD):
CSL > BAT2N + VOCL
CSH < BAT1P - VOCH
VUV = 2.25V
where:
Overvoltage
VOCL = 160mV (low-side detect)
Overvoltage (or overcharge) protection is asserted when
any cell voltage exceeds the VOV threshold and remains
above the VOV threshold for a time exceeding a userconfigurable delay (tOVD). The CHG pin goes to the
high impedance state, disabling charge into the battery
pack. Since the charge control output is an open drain
output, a pull-down resistor is needed from the CHG pin
to the negative side of the pack. This pulls the gate of
the charge FET low when the CHG pin goes to high impedance. Charging is disabled until a valid charge enable exists. See Charge Enable section.
VOCH = 160mV (high-side detect)
When either of these conditions occurs, DSG is driven
low, disconnecting the load from the pack. DSG remains
low until both of the voltage conditions are false, indicating removal of the short-circuit condition. The user
can facilitate clearing these conditions by inserting the
battery pack into a charger.
Important note: If any battery pin floats (BAT1P,
BAT1N, BAT2N), the bq2058T assumes an overvoltage has occurred.
The high-side overcurrent sense can be disabled by connecting CSH to BAT1P. This ensures that CSH is never
greater than BAT1P. If high-side detection is disabled,
low-side detection must be used with CSL.
Because of different manufacturers’ specifications for
overvoltage thresholds, the bq2058T can be available
with different VOV options. Table 1 summarizes these
different voltage thresholds.
The FETs in the charge/discharge path controlled by the
CHG and DSG pins affect the overcurrent level. The
on-resistance of these FETs need to be taken into account when determining overcurrent levels.
July 1997
5
bq2058T
Important note: If CTL floats, it is internally
pulled high making both DSG and CHG inactive,
thus disabling the pack. If CTL is not used, it
should be tied to VSS.
CHG and DSG States
The CHG and DSG output truth table is shown below:
Condition
Normal operation
Overvoltage
Undervoltage
Overcurrent
Floating battery input
CTL = high
CHG pin
High
Z
High
High
Z
Z
DSG pin
High
High
Low
Low
Indeterminate
Low
The polarity of CTL is mask-programmable at Benchmarq. Please contact Benchmarq for other polarity options.
Protection Delay Timers
The delay time between the detection of an overcurrent,
overvoltage, or undervoltage condition and the deactivation of the CHG and/or DSG outputs is user-configurable
by the selection of capacitor values between VCC and OCD,
OVD, and UVD pins (respectively. See Table 2 below.
The polarities of CHG and DSG are mask programmable
at Benchmarq. Push-pull vs. open-drain configuration is
also mask-configurable at Benchmarq. Please contact
Benchmarq for availability of these variations.
The fault condition must persist through the entire delay period, or the bq2058T may not deactivate either
FET control output.
Pack Disable Input–CTL
Figure 3 shows a step-by-step event cycle for the
bq2058T.
The CTL pin is used to electrically disconnect the battery from the pack terminals through an externally supplied signal. When CTL is taken high, CHG goes to the
high impedance state and DSG is driven low. Any load
on the pack terminals will be interpreted as an overcurrent condition by the bq2058T with the overcurrent delay timer held in reset. When the CTL pin is driven low,
the overcurrent delay timer is allowed to start. If the
programmed delay (tOCD) is too short, the overcurrent
recovery circuit, if implemented, will be unable to correct the overcurrent situation prior to the delay timeout. It is recommended that a delay time of greater than
10ms (COCD ≥ 0.01µF) be used if the CTL pin function
is to be utilized.
Table 2. Protection Delay Timers
Protection
Feature
Typical
Delay
Period
Capacitor from
VCC to:
Overcurrent
tOCD
OCD
0.010µF
12ms
±40%
Overvoltage
tOVD
OVD
0.100µF
950ms
±40%
Undervoltage
tUVD
UVD
0.100µF
950ms
±40%
Notes:
Capacitor
Time
Tolerance
1. The delay time versus capacitance can be approximated by the following equations:.
For tOCD:
For tOVD, tUVD:
t(s) ≈ 1.2 ∗ C(µf),
t(s) ≈ 9.5 ∗ C(µf),
where 0.001µF ≤ C ≤ 0.1µF
where 0.01µF ≤ C ≤ 1µF
2. Overvoltage and undervoltage conditions are sampled by the bq2058T. The delay in Table 2 is in
addition to the time required for the bq2058T to detect the violation, which may vary from 0 to
120 ms depending on where in the sampling period the violation occurs. Overcurrent is continuously
monitored and is subject to a delay of approximately 1.5ms.
July 1997
6
bq2058T
0
1
2
3
VOV
4
5
6
7 8
9 10
11 12
VCE
VUV
Cell Voltage
BAT2N + 160mV (VOCL)
CSL
BAT2N - 70mV (VCD)
DSG
tOCD
tUVD
CHG
tOVD
CTL
TD2058T1.eps
Figure 3. Protector Event Diagram
Event Definition:
0:
The bq2058T is in the low-power sleep mode because one or more of the cell voltages are below VUV.
1:
A charger is applied to the pack, causing the difference between CSL and BAT2N to become greater
than 70mV. This awakens the bq2058T, and the discharge pin DSG goes high.
2:
One or more cells charge to a voltage equal to VOV, initiating the overvoltage delay timer.
3:
The overvoltage delay time expires, causing CHG to go to high impedance (pulled low externally).
4:
All cell voltages fall below VCE, causing CHG to go high.
5:
Stop charging, apply a load.
6:
An overcurrent condition is detected, initiating the overcurrent delay timer.
7:
The overcurrent delay time expires, causing DSG to go low.
8:
The overcurrent condition is no longer present. DSG is driven high.
9:
Pin CTL is driven high; both DSG and CHG go inactive.
10:
Pin CTL is driven low; both DSG and CHG go active resuming their normal function.
11:
One or more cells fall below VUV, initiating the overdischarge delay timer.
12:
Once the overdischarge delay timer expires, if any of the cells is below VUV, the bq2058T drives
DSG low and enters the low-power sleep mode.
July 15, 1997
7
bq2058T
Absolute Maximum Ratings
Symbol
Parameter
Value
Unit
18
V
Conditions
VCC
Supply voltage
TOPR
Operating temperature
-30 to +70
°C
TSTG
Storage temperature
-55 to +125
°C
TSOLDER
Soldering temperature
260
°C
For 10 seconds
IIN
Maximum input current
±100
µA
All pins except VCC, VSS
Notes:
Relative to VSS
1 Permanent device damage may occur if Absolute Maximum Ratings are exceeded. Functional
operation should be limited to the Recommended DC Operating Conditions detailed in this data sheet.
Exposure to conditions beyond the operational limits for extended periods of time may affect device
reliability.
2. Internal protection diodes are in place on every pin relative to VCC and VSS. See picture below.
VCC
VCC
Any pin
CHG pin
(except CHG)
VSS
FG2058tx .eps
July 1997
8
bq2058T
DC Electrical Characteristics (TA = TOPR)
Symbol
Parameter
Minimum
Typical
Maximum
Unit
Conditions/Notes
VOH
Output high voltage
VCC - 0.5
-
-
V
IOH = 10µA, CHG, DSG
VOL
Output low voltage
-
-
VSS + 0.5
V
IOL = 10µA, CHG, DSG
VOP
Operating voltage
0
-
9.0
V
VCC relative to VSS
VIL
Input low voltage
-
-
VSS + 0.5
V
Pin CTL
VIH
Input high voltage
VSS + 2.0
-
-
V
Pin CTL
ICCA
Active current
-
12
25
µA
ICCS
Sleep current
-
0.7
1.5
µA
RCELL
Input impedance
-
10
-
MΩ
Pins BAT2N, BAT1N, and BAT1P
DC Thresholds (TA = TOPR)
Symbol
VOV
Parameter
Overvoltage threshold
Value
Unit
Tolerance
4.25
V
±55mV
Table 1
Conditons
See note 1
Customer option
VCE
Charge enable threshold
VOV - 150mV
V
±55mV
VUV
Undervoltage threshold
2.25
V
±100mV
VOCH
Overcurrent detect
high-side
160
mV
±35mV
VOCL
Overcurrent detect
low-side
160
mV
±35mV
VCD
Charge detect threshold
70
mV
-60mV, +80mV
tOVD
Overvoltage delay
threshold
950
ms
±40%
COVD = 0.100µF
TA = 30°C
See note 2
tUVD
Undervoltage delay
threshold
950
ms
±40%
CUVD = 0.100µF
TA = 30°C
See note 2
tOCD
Overcurrent delay threshold
12
ms
±40%
COCD = 0.01µF
TA = 30°C
Notes:
1. Standard device. Contact Benchmarq for different thresholds and tolerance options
2. Does not include cell sampling delay, which may add up to 120ms of additional delay until the
condition is detected.
July 1997
9
bq2058T
Typical Characteristics
bq2058T 4.25V OVERVOLTAGE THRESHOLD
VS
FREE-AIR TEMPERATURE
4.280
VOV – Overvoltage – V
4.270
4.260
4.250
4.240
4.230
Measurement accuracy ± 2mV
4.220
4.210
-30 -20 -10
0
10
20
30
40
50
60
70
TA – Free-Air Temperature – ˚C
Figure 4
July 1997
10
bq2058T
Data Sheet Revision History
Change No.
1
Page No.
5
Description
CHG pin output state
Nature of Change
CHG pin state at overvoltage and floating battery
input was low, is now Z
1
9
Overcurrent limits
1
9
Charge detect threshold
2
2
4
4
Overvoltage options, Table 1
Figure 2
Was: VOCL = 100mV ±25mV
Is: VOCL = 150mV ±25mV
Was: 70mV +10mV, +80mV
Is: 70mV -60mV, +80mV
Added bq2058TR
Corrected schematic
2
6, 9
2
7
DSG and CHG timing diagram
2
7
Timing Diagram
2
8
Maximum input current
2
9
VOV tolerance
2
9
Overcurrent limits
2
9
VOP
Note:
Delay thresholds
Was: tOCD = 10ms ±30%
tOVD = 800ms ±30%
tUVD = 800ms ±30%
Is: tOCD = 12ms ±40%
tOVD = 950ms ±40%
tUVD = 950ms ±40%
Inverted lines for proper logic levels
Was: CSH timing
Is: CSL timing
Added IIN
Was: ±50mV
Is: ±55mV
Was: VOCH = 160mV +25mV
VOCL = 150mV +25mV
Is: VOCH = 160mV +35mV
VOCL = 160mV +35mV
Was: 0V min, 18V max
Is: 4V min, 9V max
Change 1 = June 19, 1997 changes from April 22, 1997.
Change 2 = July 1997 changes from June 19, 1997
July 1997
11
bq2058T
SN: 16-Pin SN (0.150" SOIC)
16-Pin SN (0.150" SOIC)
Inches
D
e
E
H
A
C
Min.
Max.
Min.
Max.
A
0.060
0.070
1.52
1.78
A1
0.004
0.010
0.10
0.25
B
0.013
0.020
0.33
0.51
C
0.007
0.010
0.18
0.25
D
0.385
0.400
9.78
10.16
E
0.150
0.160
3.81
4.06
Dimension
B
A1
.004
Millimeters
e
0.045
0.055
1.14
1.40
H
0.225
0.245
5.72
6.22
L
0.015
0.035
0.38
0.89
L
July 1997
12
bq2058T
Ordering Information
bq2058T
XXXX
Standard Device:
Blank = Standard device
XXXX = Customer code assigned by Benchmarq
Package Option:
SN = 16-pin narrow SOIC
Overvoltage Threshold
Blank = 4.25V (Standard device)
Contact factory for availability of other thresholds
Device:
bq2058T Lithium Ion Pack Supervisor
TA
-30°C to
+70°C
Note:
Package Devices
VOV Threshold
16-pin Narrow SOIC (SN)
4.25V
bq2058TSN
4.35V
bq2058TRSN
bq2058TSN is Standard Device
Contact factory for availability of other thresholds and tolerances.
July 1997
13
Notes
July 1997
14
Notes
July 1997
15
bq2058T
BENCHMARQ Microelectronics, Inc.
17919 Waterview Parkway
Dallas, Texas 75252
Fax: (972) 437-9198
Tel: (972) 437-9195
E-mail: benchmarq @ benchmarq.com
World Wide Web: http://www.benchmarq.com
Copyright © 1997, BENCHMARQ Microelectronics, Inc. All rights reserved.
No part of this data sheet may be reproduced in any form or means, without express permission from Benchmarq.
Benchmarq reserves the right to make changes in its products without notice.
Benchmarq assumes no responsibility for use of any products or circuitry described within. No license for use of intellectual property (patents, copyrights, or other rights) owned by Benchmarq or other parties is granted or implied.
Benchmarq does not authorize the use of its components in life-support systems where failure or malfunction may
cause injury to the user. If Benchmarq components are used in life-support systems, the user assumes all responsibilities and indemnifies Benchmarq from all liability or damages.
Benchmarq is a registered trademark of BENCHMARQ Microelectronics, Inc.
Printed in U.S.A.
July 1997
16
PACKAGE OPTION ADDENDUM
www.ti.com
30-Mar-2005
PACKAGING INFORMATION
Orderable Device
Status (1)
Package
Type
Package
Drawing
Pins Package Eco Plan (2)
Qty
BQ2058TRSN-C2
OBSOLETE
SOIC
D
16
TBD
Call TI
Call TI
BQ2058TSN-C2
OBSOLETE
SOIC
D
16
TBD
Call TI
Call TI
Lead/Ball Finish
MSL Peak Temp (3)
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
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incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
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Addendum-Page 1
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logic.ti.com
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microcontroller.ti.com
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