< SLVS552 − OCTOBER 2004
D Available in the Texas Instruments
D
D
D
D
D
D
D
D
D
D
D
NanoStar and NanoFree Wafer Chip
Scale Packages
Output Tolerance of:
− 1% (A Grade)
− 1.5% (Standard Grade)
Ultra Low Dropout, Typically
280 mV at Full Load of 150 mA
Wide VIN Range . . . 16 V (Max)
Low IQ . . . 850 µA at Full Load at 150 mA
Shutdown Current . . . 0.01 µA Typ
Low Noise . . . 30 µVRMS With 10-nF Bypass
Capacitor
Stable With Low ESR Capacitors, Including
Ceramic
Over-Current and Thermal Protection
High Peak Current Capability
For VOUT Options .2.5 V, See LP2985 Data
Sheet
Portable Applications
− Cellular Phones
− Palmtop and Laptop Computers
− Personal Digital Assistants (PDAs)
− Digital Cameras and Camcorders
− CD Players
− MP3 Players
DBV (SOT-23) PACKAGE
(TOP VIEW)
VIN
GND
ON/OFF
1
5
VOUT
4
BYPASS
2
3
YEQ, YEU, YZQ, OR YZU (WCSP) PACKAGE
(TOP VIEW)
VIN
C3 C1
BYPASS
B2
ON/OFF
VOUT
A3
A1
GND
description/ordering information
The LP2985LV family of fixed-output, low-dropout regulators offers exceptional, cost-effective performance for
both portable and nonportable applications. Available in voltages of 1.25 V, 1.35 V, 1.5 V, 1.7 V, 1.8 V, and
2 V, the family has an output tolerance of 1% for the A version (1.5% for the non-A version), and is capable of
delivering 150-mA continuous load current. Standard regulator features, such as over-current and
over-temperature protection, are included.
The LP2985LV has a host of features that makes the regulator an ideal candidate for a variety of portable
applications:
•
•
•
•
Low dropout: A PNP pass element allows a typical dropout of 280 mV at 150-mA load current.
Low quiescent current: The use of a vertical PNP process allows for quiescent currents that are
considerably lower than those associated with traditional lateral PNP regulators.
Shutdown: A shutdown feature is available, allowing the regulator to consume only 0.01 µA when the
ON/OFF pin is pulled low.
Low-ESR-capacitor friendly: The regulator is stable with low ESR capacitors, allowing for the use of
small, inexpensive ceramic capacitors in cost-sensitive applications.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
NanoStar and NanoFree are trademarks of Texas Instruments.
Copyright 2004, Texas Instruments Incorporated
!"# $%" & '(##)% $& "! *(+,'$%" -$%)
#"-('%& '"!"# %" &*)'!'$%"& *)# %.) %)# & "! )/$& &%#( )%&
&%$-$#- 0$##$%1 #"-('%" *#"')&&2 -")& "% )')&&$#,1 ',(-)
%)&%2 "! $,, *$#$ )%)#&
POST OFFICE BOX 655303
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1
< SLVS552 − OCTOBER 2004
description/ordering information (continued)
•
•
2
Low noise: The BYPASS pin allows for low noise operation, with a typical output noise of 30 µV (RMS)
with the use of a 10-nF bypass capacitor.
Small packaging: For the most space-constraint needs, the regulator is available in SOT-23 package,
as well as NanoStar wafer chip scale packaging, offering an even smaller size with improved thermal
and electrical characteristics. NanoStar package technology is a major breakthrough in IC packaging
concepts, using the die as the package.
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ORDERING INFORMATION
TJ
PART
GRADE
VOUT
(NOM)
PACKAGE†
1.25 V
1.35 V
1.5 V
SOT23-5 (DBV)
1.7 V
1.8 V
2V
LP2985A-12DBVR
Reel of 250
LP2985A-12DBVT
Reel of 3000
LP2985A-13DBVR
Reel of 250
LP2985A-13DBVT
Reel of 3000
LP2985A-15DBVR
Reel of 250
LP2985A-15DBVT
Reel of 3000
LP2985A-17DBVR
Reel of 250
LP2985A-17DBVT
Reel of 3000
LP2985A-18DBVR
Reel of 250
LP2985A-18DBVT
Reel of 3000
LP2985A-20DBVR
Reel of 250
LP2985A-20DBVT
LP2985A-12YEQR
1.35 V
LP2985A-13YEQR
1.7 V
A grade:
1% tolerance
Reel of 3000
1.25 V
1.5 V
−40°C to 125°C
ORDERABLE
PART NUMBER
NanoStar − WCSP
NanoStar
0.17-mm Bump (YEQ)
LP2985A-15YEQR
Reel of 3000
LP2985A-17YEQR
1.8 V
LP2985A-18YEQR
2V
LP2985A-20YEQR
1.25 V
LP2985A-12YZQR
1.35 V
1.5 V
1.7 V
LP2985A-13YZQR
NanoFree − WCSP
NanoFree
0.17-mm Bump
(YZQ, Pb-free)
LP2985A-15YZQR
Reel of 3000
LP2985A-17YZQR
1.8 V
LP2985A-18YZQR
2V
LP2985A-20YZQR
1.25 V
LP2985A-12YEUR
1.35 V
1.5 V
1.7 V
LP2985A-13YEUR
NanoStar − WCSP
NanoStar
0.30-mm Bump (YEU)
LP2985A-15YEUR
Reel of 3000
LP2985A-17YEUR
1.8 V
LP2985A-18YEUR
2V
LP2985A-20YEUR
1.25 V
LP2985A-12YZUR
1.35 V
1.5 V
1.7 V
LP2985A-13YZUR
NanoFree − WCSP
NanoFree
0.30-mm Bump
(YZU, Pb-free)
LP2985A-15YZUR
Reel of 3000
1.8 V
LP2985A-17YZUR
LP2985A-18YZUR
2V
TOP-SIDE
MARKING‡
PREVIEW
PREVIEW
PREVIEW
PREVIEW
LPT_
PREVIEW
PREVIEW
PREVIEW
PREVIEW
PREVIEW
PREVIEW
PREVIEW
PREVIEW
PREVIEW
PREVIEW
PREVIEW
PREVIEW
PREVIEW
PREVIEW
PREVIEW
PREVIEW
PREVIEW
PREVIEW
PREVIEW
PREVIEW
PREVIEW
PREVIEW
PREVIEW
PREVIEW
PREVIEW
LP2985A-20YZUR
† Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at
www.ti.com/sc/package.
‡ DBV: The actual top-side marking has one additional character that designates the assembly/test site.
YEQ/YZQ, YEU/YZU: The actual top-side marking has three preceding characters to denote year, month, and sequence code, and one
following character to designate the assembly/test site. Pin 1 identifier indicates solder-bump composition (1 = SnPb, • = Pb-free).
POST OFFICE BOX 655303
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< SLVS552 − OCTOBER 2004
description/ordering information (continued)
ORDERING INFORMATION
TJ
PART GRADE
VOUT
(NOM)
PACKAGE†
1.25 V
1.35 V
1.5 V
SOT-23 (DBV)
1.7 V
1.8 V
2V
LP2985-12DBVR
Reel of 250
LP2985-12DBVT
Reel of 3000
LP2985-13DBVR
Reel of 250
LP2985-13DBVT
Reel of 3000
LP2985-15DBVR
Reel of 250
LP2985-15DBVT
Reel of 3000
LP2985-17DBVR
Reel of 250
LP2985-17DBVT
Reel of 3000
LP2985-18DBVR
Reel of 250
LP2985-18DBVT
Reel of 3000
LP2985-20DBVR
Reel of 250
LP2985-20DBVT
LP2985-12YEQR
1.35 V
LP2985-13YEQR
1.7 V
Standard grade:
1.5% tolerance
Reel of 3000
1.25 V
1.5 V
−40°C to 125°C
ORDERABLE
PART NUMBER
NanoStar − WCSP
NanoStar
0.17-mm Bump (YEQ)
LP2985-15YEQR
Reel of 3000
LP2985-17YEQR
1.8 V
LP2985-18YEQR
2V
LP2985-20YEQR
1.25 V
LP2985-12YZQR
1.35 V
1.5 V
1.7 V
LP2985-13YZQR
NanoFree − WCSP
NanoFree
0.17-mm Bump
(YZQ, Pb free)
LP2985-15YZQR
Reel of 3000
LP2985-17YZQR
1.8 V
LP2985-18YZQR
2V
LP2985-20YZQR
1.25 V
LP2985-12YEUR
1.35 V
LP2985-13YEUR
1.5 V
1.7 V
NanoStar − WCSP
NanoStar
0.30-mm Bump (YEU)
LP2985-15YEUR
Reel of 3000
LP2985-17YEUR
1.8 V
LP2985-18YEUR
2V
LP2985-20YEUR
1.25 V
LP2985-12YZUR
1.35 V
1.5 V
1.7 V
LP2985-13YZUR
NanoFree − WCSP
NanoFree
0.30-mm Bump
(YZQ, Pb free)
Reel of 3000
1.8 V
LP2985-15YZUR
LP2985-17YZUR
LP2985-18YZUR
2V
TOP-SIDE
MARKING‡
PREVIEW
PREVIEW
PREVIEW
PREVIEW
LPH_
PREVIEW
PREVIEW
PREVIEW
PREVIEW
PREVIEW
PREVIEW
PREVIEW
PREVIEW
PREVIEW
PREVIEW
PREVIEW
PREVIEW
PREVIEW
PREVIEW
PREVIEW
PREVIEW
PREVIEW
PREVIEW
PREVIEW
PREVIEW
PREVIEW
PREVIEW
PREVIEW
PREVIEW
PREVIEW
LP2985-20YZUR
† Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at
www.ti.com/sc/package.
‡ DBV: The actual top-side marking has one additional character that designates the assembly/test site.
YEQ/YZQ, YEU/YZU: The actual top-side marking has three preceding characters to denote year, month, and sequence code, and one
following character to designate the assembly/test site. Pin 1 identifier indicates solder-bump composition
(1 = SnPb, • = Pb-free).
4
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< SLVS552 − OCTOBER 2004
functional block diagram
VIN
ON/OFF
VREF
1.23 V
−
+
BYPASS
VOUT
Over-Current/
Over-Temperature
Protection
basic application circuit
LP2985A−xxDBVR
VIN
1
VOUT
5
2.2 µF†
1 µF†
GND
2
ON/OFF}
3
4
BYPASS
10 nFw
† Minimum COUT value for stability (can be increased without limit for improved stability and transient response)
‡ ON/OFF must be actively terminated. Connect to VIN if shutdown feature is not used.
§ Optional BYPASS capacitor for low noise operation
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< SLVS552 − OCTOBER 2004
absolute maximum ratings over the virtual junction temperature range (unless otherwise noted)†
Continuous input voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to 16 V
ON/OFF input voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to 16 V
Output voltage range (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to 9 V
Input/output voltage differential, VIN-VOUT (see Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to 16 V
Output current, IO (see Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Internally limited (short-circuit protected)
Package thermal impedance, θJA (see Notes 3 and 4): DBV package . . . . . . . . . . . . . . . . . . . . . . . . 206°C/W
YEQ/YZQ package . . . . . . . . . . . . . . . . . . TBD°C/W
YEU/YZU package . . . . . . . . . . . . . . . . . . . TBD°C/W
Operating virtual junction temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150°C
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. If load is returned to a negative power supply in a dual supply system, the output must be diode clamped to GND.
2. The PNP pass transistor has a parasitic diode connected between the input and output. This diode is normally reversed bias
(VIN > VOUT) but will be forward biased if the output voltage exceeds the input voltage by a diode drop (see Application Information
for more details).
3. Maximum power dissipation is a function of TJ(max), θJA, and TA. The maximum allowable power dissipation at any allowable
ambient temperature is PD = (TJ(max) − TA)/θJA. Operating at the absolute maximum TJ of 150°C can affect reliability.
4. The package thermal impedance is calculated in accordance with JESD 51-7.
recommended operating conditions
VIN
VON/OFF
Supply input voltage
IOUT
Output current
TJ
Virtual junction temperature
6
ON/OFF input voltage
POST OFFICE BOX 655303
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MIN
MAX
2.2
16
V
−0.3
VIN
150
V
mA
−40
125
°C
UNIT
< SLVS552 − OCTOBER 2004
electrical characteristics at specified virtual junction temperature range,
VIN = VOUT (nominal) + 1 V, VON/OFF = 2 V, CIN = 1 mF, IL = 1 mA, COUT = 4.7 mF (unless otherwise noted)
LP2985A−XX
PARAMETER
TEST CONDITIONS
IL = 1mA
nVOUT
Output voltage
tolerance
1 mA ≤ IL ≤ 50 mA
1 mA ≤ IL ≤ 150 mA
Line regulation
VIN(MIN)
TJ
MIN
Dropout voltage
(see Note 5)
1
−1.5
1.5
−2.5
2.5
−40°C to 125°C
−2.5
2.5
−3.5
25°C
−2.5
2.5
−3.0
3.5 %VNOM
3.0
−40°C to 125°C
−3.5
3.5
−4.0
0.007
0.014
0.032
%/V
2.05
V
2.2
IL = 50 mA
120
−40°C to 125°C
25°C
280
−40°C to 125°C
−40°C to 125°C
IL = 10 mA
−40°C to 125°C
−40°C to 125°C
IL = 150 mA
−40°C to 125°C
VON/OFF < 0.3 V (OFF)
VON/OFF < 0.15 V (OFF)
VON/OFF= HIGH !
(ON)
VON/OFF = LOW !
(OFF)
120
850
350
65
95
125
110
75
110
170
220
120
220
400
600
350
600
1500
850
1500
2500
25°C
0.01
0.8
0.01
0.8
−40°C to 105°C
0.05
2
0.05
2
5
25°C
−40°C to 125°C
5
1.4
1.4
1.6
25°C
1.6
0.55
−40°C to 125°C
V
0.55
0.15
0.01
−40°C to 125°C
−40°C to 125°C
µA
1000
2500
−40°C to 125°C
mV
600
95
1000
25°C
VON/OFF = 5 V
280
400
350
150
250
350
170
25°C
VON/OFF = 0
120
125
75
25°C
IL = 50 mA
150
600
65
−40°C to 125°C
IL = 1 mA
2.2
250
25°C
ION/OFF
4.0
0.007
2.05
25°C
ON/OFF input
current
0.014
0.032
25°C
VON/OFF
UNIT
1.5
−40°C to 125°C
IL = 0
ON/OFF input
voltage
(see Note 6)
MAX
−1
25°C
Ground pin current
TYP
−1.5
25°C
IL = 150 mA
IGND
MIN
25°C
25°C
VIN-VOUT
MAX
25°C
25°C
VIN =
[VOUT(NOM) + 1 V] to 16 V −40°C to 125°C
Minimum VIN to
maintain output
regulation
(see Note 5)
TYP
LP2985−XX
0.15
0.01
−2
5
−2
5
15
µA
A
15
NOTES: 5. Dropout voltage is defined as the input-to-output differential at which the output voltage drops 2% below the value measured
with a 1-V differential. Dropout limits may not apply because VIN must be the greater of a) 2.2 V, or
b) VOUT(nom) + dropout voltage (Max) in order to maintain output regulation.
6. The ON/OFF input must be properly driven for reliable operation (see Application Information).
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< SLVS552 − OCTOBER 2004
electrical characteristics at specified virtual junction temperature range,
VIN = VOUT (nominal) + 1 V, VON/OFF = 2 V, CIN = 1 mF, IL = 1 mA, COUT = 4.7 mF (unless otherwise noted)
(continued)
LP2985A−XX
PARAMETER
TEST CONDITIONS
TJ
MIN
TYP
MAX
LP2985−XX
MIN
TYP
MAX
UNIT
Vn
Output noise
(RMS)
BW = 300 Hz to 50 kHz,
COUT = 10 µF,
CBYPASS = 10 nF,
VOUT = 1.8 V
25°C
30
30
µV
nVOUT/nVIN
Ripple
rejection
f = 1kHz,
COUT = 10 µF,
CBYPASS = 10 nF
25°C
45
45
dB
IOUT(PK)
Peak output
current
VOUT ≥ VO(NOM) − 5%
25°C
350
350
mA
IOUT(SC)
Short circuit
current
RL = 0 (steady state)
(see Note 7)
25°C
400
400
mA
NOTE 7: See Typical Characteristics Curve, Short-Circuit Current vs. VOUT
8
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< SLVS552 − OCTOBER 2004
APPLICATION INFORMATION
capacitors
input capacitor (CIN)
A minimum value of 1 F (over the entire operating temperature range) is required at the input of the LP2985LV.
In addition, this input capacitor should be located within 1 cm of the input pin and connected to a clean analog
ground. There are no Equivalent Series Resistance (ESR) requirements for this capacitor and the capacitance
can be increased without limit.
output capacitor (COUT)
As an advantage over other regulators, the LP2985LV permits the use of low ESR capacitors at the output,
including ceramic capacitors that can have an ESR as low as 5 mΩ. Of course, tantalum and film capacitors
can also be used if size and cost are not issues. The output capacitor should also be located within 1 cm of the
output pin and be returned to a clean analog ground.
As with other PNP LDOs, stability conditions require the output capacitor to have a minimum capacitance and
an ESR that falls within a certain range.
Minimum COUT: 2.2 µF (can be increased without limit to improve transient response stability margin)
ESR range: See Figures 1 and 2
Figure 1. 2.2-µF Stable ESR Curves
Figure 2. 4.7-µF Stable ESR Curves
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< SLVS552 − OCTOBER 2004
APPLICATION INFORMATION
output capacitor (COUT) (continued)
It is critical that both the minimum capacitance and ESR requirement be met over the entire operating
temperature range. Depending on the type of capacitors used, both these parameters can vary significantly with
temperature (see Capacitor Characteristics section).
noise bypass capacitor (CBYPASS)
The LP2985LV allows for low noise performance with the use of a bypass capacitor that is connected to the
internal band-gap reference via the BYPASS pin. This high-impedance band-gap circuitry is biased in the
microampere range and, thus, cannot be loaded significantly, else its output − and correspondingly the output
of the regulator − will change. Thus, for best output accuracy, dc leakage current through CBYPASS should be
minimized as much as possible and should never exceed 100 nA.
A 10-nF capacitor is recommended for CBYPASS; ceramic and film capacitors are well suited for this purpose.
capacitor characteristics
ceramic
Ceramic capacitors are ideal choices for use on the output of the LP2985LV for several reasons. For
capacitances in the range of 2.2 µF to 4.7 µF, ceramic capacitors have the lowest cost and the lowest ESR,
making them choice candidates for filtering high-frequency noise. For instance, a typical 2.2-µF ceramic
capacitor has an ESR in the range of 10 mΩ to 20 mΩ and satisfies minimum ESR requirements of the regulator.
Ceramic capacitors have one glaring disadvantage that must be taken into account − a poor temperature
coefficient, where the capacitance can vary significantly with temperature. For instance, a large-value ceramic
capacitor (≥2.2 µF) can lose more than half of its capacitance as temperature rises from 25°C to 85°C. Thus,
a 2.2 µF at 25°C will drop well below the minimum COUT required for stability as ambient temperature rises. For
this reason, select an output capacitor that maintains the minimum 2.2 µF required for stability over the entire
operating temperature range. Note that there are some ceramic capacitors that can maintain a ±15%
capacitance tolerance over temperature.
tantalum
Tantalum capacitors can be used at the output of the LP2985LV, but there are significant disadvantages that
could prohibit their use.
•
•
•
10
In the 1-µF to 4.7-µF range, tantalum capacitors are more expensive than ceramics of the equivalent
capacitance and voltage ratings.
Tantalum capacitors have higher ESRs than their equivalent-sized ceramic counterparts. Thus, to meet
the ESR requirements, a higher-capacitance tantalum may be required, at the expense of larger size
and higher cost.
The ESR of a tantalum capacitor increases as temperature drops, as much as double from 25°C to
−40°C. Thus, ESR margins must be maintained over the temperature range in order to prevent
regulator instability.
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APPLICATION INFORMATION
ON/OFF operation
The LP2985LV allows for a shutdown mode via the ON/OFF pin. Driving the pin LOW (≤0.3 V) turns the device
OFF, conversely, a HIGH (≥1.6 V) turns the device ON. If the shutdown feature is not used, the ON/OFF pin
should be connected to the input to ensure that the regulator is on at all times. For proper operation, do not leave
the ON/OFF pin unconnected and apply a signal with a slew rate of ≥40 mV/µs.
reverse input-output voltage
There is an inherent diode present across the PNP pass element of the LP2985LV.
VIN
VOUT
With the anode connected to the output, this diode is reverse biased during normal operation since the input
voltage is higher than the output. However, if the output is pulled higher than the input for any reason, this diode
will be forward biased and can cause a parasitic silicon-controlled rectifier (SCR) to latch, resulting in high
current flowing from the output to the input. Thus, to prevent possible damage to the regulator in any application
where the output may be pulled above the input, an external Schottky diode must be connected between the
output and input. With the anode on output, this Schottky limits the reverse voltage across the output and input
pins to 0.3 V, preventing the regulator’s internal diode from forward biasing.
Schottky
VIN
VOUT
LP2985LV
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< SLVS552 − OCTOBER 2004
WAFER CHIP SCALE INFORMATION
LP2985x-xxYEQ NanoStar (0.17-mm Bump)
LP2985x-xxYZQ NanoFree (0.17-mm Pb-Free Bump)
987
1,037
1,287
1,337
Pin A1 Index Area
0,625 Max
0,15
0,10
NOTES: A.
B.
C.
D.
12
All linear dimensions are in millimeters.
This drawing is subject to change without notice.
NanoStar package configuration
This package is tin-lead (SnPb), consult the factory for availability of lead-free material.
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0,19
0,15
< SLVS552 − OCTOBER 2004
WAFER CHIP SCALE INFORMATION
LP2985x-xxYEU NanoStar (0.30-mm Bump)
LP2985x-xxYZU NanoFree (0.30-mm Pb-Free Bump)
987
1,037
1,287
1,337
Pin A1 Index Area
0,35
0,25
0,75 Max
0,30
0,20
NOTES: A.
B.
C.
D.
All linear dimensions are in millimeters.
This drawing is subject to change without notice.
NanoStar package configuration
This package is tin-lead (SnPb), consult the factory for availability of lead-free material.
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13
IMPORTANT NOTICE
Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications,
enhancements, improvements, and other changes to its products and services at any time and to discontinue
any product or service without notice. Customers should obtain the latest relevant information before placing
orders and should verify that such information is current and complete. All products are sold subject to TI’s terms
and conditions of sale supplied at the time of order acknowledgment.
TI warrants performance of its hardware products to the specifications applicable at the time of sale in
accordance with TI’s standard warranty. Testing and other quality control techniques are used to the extent TI
deems necessary to support this warranty. Except where mandated by government requirements, testing of all
parameters of each product is not necessarily performed.
TI assumes no liability for applications assistance or customer product design. Customers are responsible for
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amplifier.ti.com
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