ICS840002-01 Integrated Circuit Systems, Inc. FEMTOCLOCKS™ CRYSTAL-TOLVCMOS/LVTTL FREQUENCY SYNTHESIZER GENERAL DESCRIPTION FEATURES The ICS840002-01 is a 2 output LVCMOS/LVTTL Synthesizer optimized to generate Ethernet HiPerClockS™ reference clock frequencies and is a member of the HiPerClocksTM family of high performance clock solutions from ICS. Using a 25MHz 18pF parallel resonant crystal, the following frequencies can be generated based on the 2 frequency select pins (F_SEL1:0): 156.25MHz, 125MHz, and 62.5MHz. The ICS840002-01 uses ICS’ 3rd generation low phase noise VCO technology and can achieve 1ps or lower typical random rms phase jitter, easily meeting Ethernet jitter requirements. The ICS840002-01 is packaged in a small 16-pin TSSOP package. • Two LVCMOS/LVTTL outputs @ 3.3V, 17Ω typical output impedance ICS • Selectable crystal oscillator interface or LVCMOS/LVTTL single-ended input • Output frequency range: 56MHz - 175MHz • VCO range: 560MHz - 700MHz • Output skew: 12ps (maximum) • RMS phase jitter at 156.25MHZ (1.875MHz - 20MHz): 0.47ps (typical) Phase noise: Offset Noise Power 100Hz ............... -97.4 dBc/Hz 1kHz .............. -120.2 dBc/Hz 10kHz .............. -127.6 dBc/Hz 100kHz .............. -126.1 dBc/Hz • Full 3.3V or 3.3V core/2.5V output supply mode • -30°C to 85°C ambient operating temperature • Available in both standard and lead-free RoHS compliant packages FREQUENCY SELECT FUNCTION TABLE Inputs F_SEL1 F_SEL0 M Divider Value N Divider Value Output Frequency (25MHz Ref.) 0 0 25 4 156.25 0 1 25 5 125 1 0 25 10 62.5 1 1 25 5 125 BLOCK DIAGRAM OE PIN ASSIGNMENT Pullup F_SEL0 nXTAL_SEL TEST_CLK OE MR nPLL_SEL VDDA VDD 2 F_SEL1:0 Pullup:Pullup nPLL_SEL Pulldown nXTAL_SEL XTAL_IN Pulldown 25MHz OSC F_SEL1:0 0 1 00 01 10 11 XTAL_OUT TEST_CLK Pulldown 1 Phase Detector VCO 0 N ÷4 ÷5 ÷10 ÷5 M = ÷25 (fixed) MR 840002AG-01 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 F_SEL1 GND GND Q0 Q1 VDDO XTAL_IN XTAL_OUT Q0 ICS840002-01 Q1 16-Lead TSSOP 4.4mm x 5.0mm x 0.92mm package body G Package Top View Pulldown www.icst.com/products/hiperclocks.html 1 REV. B JANUARY 13, 2006 ICS840002-01 Integrated Circuit Systems, Inc. FEMTOCLOCKS™ CRYSTAL-TOLVCMOS/LVTTL FREQUENCY SYNTHESIZER TABLE 1. PIN DESCRIPTIONS Number Name 1 F_SEL0 Input Type Pullup Description 2 nXTAL_SEL Input Pulldown 3 TEST_CLK Input Pulldown 4 OE Input Pullup 5 MR Input Pulldown 6 nPLL_SEL Input Pulldown 7 VDDA Power 8 9, 10 11 VDD XTAL_OUT, XTAL_IN VDDO Power Power Core supply pin. Cr ystal oscillator interface. XTAL_OUT is the output. XTAL_IN is the input. Output supply pin. 12, 13 Q1, Q0 Output Single-ended clock outputs. LVCMOS/LVTTL interface levels. 14, 15 GND Power Power supply ground. 16 F_SEL1 Input Input Pullup Frequency select pin. LVCMOS/LVTTL interface levels. Selects between the cr ystal or TEST_CLK inputs as the PLL reference source. When HIGH, selects TEST_CLK. When LOW, selects XTAL inputs. LVCMOS/LVTTL interface levels. Single-ended LVCMOS/LVTTL clock input. Output enable pin. When HIGH, the outputs are active. When LOW, the outputs are in a high impedance state. LVCMOS/LVTTL interface levels. Active HIGH Master Reset. When logic HIGH, the internal dividers are reset causing active outputs to go low. When logic LOW, the internal dividers and the outputs are enabled. LVCMOS/LVTTL interface levels. PLL Bypass. When LOW, the output is driven from the VCO output. When HIGH, the PLL is bypassed and the output frequency = reference clock frequency/N output divider. LVCMOS/LVTTL interface levels. Analog supply pin. Frequency select pin. LVCMOS/LVTTL interface levels. NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values. TABLE 2. PIN CHARACTERISTICS Symbol Parameter CIN Input Capacitance Test Conditions Minimum Typical Maximum 4 Units pF CPD Power Dissipation Capacitance 8 pF RPULLUP Input Pullup Resistor 51 kΩ RPULLDOWN Input Pulldown Resistor 51 kΩ ROUT Output Impedance 840002AG-01 3.3V±5% 14 17 21 Ω 2.5V±5% 16 21 25 Ω www.icst.com/products/hiperclocks.html 2 REV. B JANUARY 13, 2006 ICS840002-01 Integrated Circuit Systems, Inc. FEMTOCLOCKS™ CRYSTAL-TOLVCMOS/LVTTL FREQUENCY SYNTHESIZER ABSOLUTE MAXIMUM RATINGS Supply Voltage, VDD 4.6V Inputs, VI -0.5V to VDD + 0.5 V Outputs, VO -0.5V to VDDO + 0.5V Package Thermal Impedance, θJA 89°C/W (0 lfpm) Storage Temperature, TSTG -65°C to 150°C NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. TABLE 3A. POWER SUPPLY DC CHARACTERISTICS, VDD = VDDA = 3.3V±5%, VDDO = 3.3V±5% OR 2.5V±5%, TA = 0°C TO 70°C Symbol VDD Parameter Core Supply Voltage VDDA Analog Supply Voltage Test Conditions Minimum 3.135 Typical 3.3 Maximum 3.465 Units V 3.135 3.3 3.465 V 3.135 3.3 3.465 V 2.375 2.5 VDDO Output Supply Voltage 2.625 V IDD Power Supply Current 100 mA IDDA IDDO Analog Supply Current Output Supply Current 12 5 mA mA TABLE 3B. LVCMOS/LVTTL DC CHARACTERISTICS, VDD = VDDA = 3.3V±5%, VDDO = 3.3V±5% OR 2.5V±5%, TA = -30°C TO 85°C Symbol Parameter Test Conditions VIH Input High Voltage VIL Input Low Voltage IIH Input High Current OE, F_SEL0, F_SEL1 nPLL_SEL, MR, nXTAL_SEL, TEST_CLK OE, F_SEL0, F_SEL1 IIL Input Low Current nPLL_SEL, MR, nXTAL_SEL, TEST_CLK VOH Output High Voltage; NOTE 1 VOL Output Low Voltage; NOTE 1 VDD = VIN = 3.465V or 2.625V VDD = VIN = 3.465V or 2.625V VDD = 3.465V or 2.625V, VIN = 0V Minimum Typical Maximum Units 2 VDD + 0.3 V -0.3 0.8 V 5 µA 150 µA -150 µA -5 µA VDDO = 3.465V±5% 2.6 V VDDO = 2.5V±5% 1.8 V VDD = 3.465V or 2.625V, VIN = 0V VDDO = 3.3V or 2.5V±5% 0.5 V NOTE 1: Outputs terminated with 50Ω to VDDO/2. See Parameter Measurement Information, Output Load Test Circuits. 840002AG-01 www.icst.com/products/hiperclocks.html 3 REV. B JANUARY 13, 2006 ICS840002-01 Integrated Circuit Systems, Inc. FEMTOCLOCKS™ CRYSTAL-TOLVCMOS/LVTTL FREQUENCY SYNTHESIZER TABLE 4. CRYSTAL CHARACTERISTICS Parameter Test Conditions Minimum Mode of Oscillation Typical Maximum Units Fundamental Frequency 25 MHz Equivalent Series Resistance (ESR) 50 Ω Shunt Capacitance 7 pF Drive Level 1 mW Maximum Units NOTE: Characterized using an 18pF parallel resonant cr ystal. TABLE 5A. AC CHARACTERISTICS, VDD = VDDA = VDDO = 3.3V±5%, TA = -30°C TO 85°C Symbol Parameter fOUT Output Frequency t sk(o) Output Skew; NOTE 1, 3 t jit(Ø) RMS Phase Jitter (Random); NOTE 2 tR / tF Output Rise/Fall Time Test Conditions Minimum Typical F_SEL[1:0] = 00 140 175 MHz F_SEL[1:0] = 01 112 140 MHz F_SEL[1:0] = 10 or 11 56 70 MHz 12 ps 156.25MHz (1.875MHz - 20MHz) 0.47 ps 125MHz (1.875MHz - 20MHz) 0.57 ps 62.5MHz (1.875MHz - 20MHz) 0.51 20% to 80% 200 odc Output Duty Cycle 46 NOTE 1: Defined as skew between outputs at the same supply voltages and with equal load conditions. Measured at VDDO/2. NOTE 2: Please refer to the Phase Noise Plot. NOTE 3: This parameter is defined in accordance with JEDEC Standard 65. ps 700 ps 54 % TABLE 5B. AC CHARACTERISTICS, VDD = VDDA = 3.3V±5%, VDDO = 2.5V±5%, TA = -30°C TO 85°C Symbol fOUT Parameter Output Frequency t sk(o) Output Skew; NOTE 1, 3 t jit(Ø) RMS Phase Jitter (Random); NOTE 2 Test Conditions Minimum Maximum Units F_SEL[1:0] = 00 140 175 MHz F_SEL[1:0] = 01 112 140 MHz F_SEL[1:0] = 10 or 11 56 68 MHz 12 ps 156.25MHz (1.875MHz - 20MHz) tR / tF Output Rise/Fall Time Typical 0.47 125MHz (1.875MHz - 20MHz) 0.55 ps 62.5MHz (1.875MHz - 20MHz) 0.49 ps 20% to 80% 200 odc Output Duty Cycle 46 NOTE 1: Defined as skew between outputs at the same supply voltages and with equal load conditions. Measured at VDDO/2. NOTE 2: Please refer to the Phase Noise Plot. NOTE 3: This parameter is defined in accordance with JEDEC Standard 65. 840002AG-01 ps www.icst.com/products/hiperclocks.html 4 700 ps 54 % REV. B JANUARY 13, 2006 ICS840002-01 Integrated Circuit Systems, Inc. FEMTOCLOCKS™ CRYSTAL-TOLVCMOS/LVTTL FREQUENCY SYNTHESIZER TYPICAL PHASE NOISE AT 62.5MHZ @3.3V ➤ 0 -10 -20 1Gb Ethernet Filter -40 62.5MHz -50 RMS Phase Jitter (Random) 1.875MHz to 20MHz = 0.51ps (typical) -60 -70 -80 -90 Raw Phase Noise Data -100 ➤ NOISE POWER dBc Hz -30 -110 -120 -130 -140 -150 ➤ -160 -170 -180 Phase Noise Result by adding 1Gb Ethernet Filter to raw data -190 100 1k 10k 100k 1M 10M 100M OFFSET FREQUENCY (HZ) TYPICAL PHASE NOISE AT 156.25MHZ @3.3V 0 ➤ -10 -20 10Gb Ethernet Filter -40 156.25MHz -50 RMS Phase Jitter (Random) 1.875MHz to 20MHz = 0.47ps (typical) -60 -70 -80 -90 Raw Phase Noise Data -100 -110 ➤ NOISE POWER dBc Hz -30 -120 -130 -140 -150 ➤ -160 -170 Phase Noise Result by adding 10Gb Ethernet Filter to raw data -180 -190 100 1k 10k 100k 1M 10M 100M OFFSET FREQUENCY (HZ) 840002AG-01 www.icst.com/products/hiperclocks.html 5 REV. B JANUARY 13, 2006 ICS840002-01 Integrated Circuit Systems, Inc. FEMTOCLOCKS™ CRYSTAL-TOLVCMOS/LVTTL FREQUENCY SYNTHESIZER PARAMETER MEASUREMENT INFORMATION 1.65V±5% 2.05V±5% 1.25V±5% SCOPE VDD, VDDA, VDDO VDD, VDDA Qx LVCMOS SCOPE VDDO Qx LVCMOS GND GND -1.65V±5% -1.25V±5% 3.3V CORE/3.3V OUTPUT LOAD AC TEST CIRCUIT 3.3V CORE/2.5V OUTPUT LOAD AC TEST CIRCUIT Phase Noise Plot Noise Power V DDO Qx 2 Phase Noise Mask V DDO Qy Offset Frequency f1 2 tsk(o) f2 RMS Jitter = Area Under the Masked Phase Noise Plot RMS PHASE JITTER OUTPUT SKEW V 80% DDO 80% 2 Q0, Q1 Clock Outputs t PW 20% 20% tR t tF odc = PERIOD t PW x 100% t PERIOD OUTPUT RISE/FALL TIME 840002AG-01 OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD www.icst.com/products/hiperclocks.html 6 REV. B JANUARY 13, 2006 ICS840002-01 Integrated Circuit Systems, Inc. FEMTOCLOCKS™ CRYSTAL-TOLVCMOS/LVTTL FREQUENCY SYNTHESIZER APPLICATION INFORMATION POWER SUPPLY FILTERING TECHNIQUES As in any high speed analog circuitry, the power supply pins are vulnerable to random noise. The ICS840002-01 provides separate power supplies to isolate any high switching noise from the outputs to the internal PLL. VDD, VDDA, and VDDO should be individually connected to the power supply plane through vias, and bypass capacitors should be used for each pin. To achieve optimum jitter performance, power supply isolation is required. Figure 1 illustrates how a 10Ω resistor along with a 10µF and a .01μF bypass capacitor should be connected to each VDDA. The 10Ω resistor can also be replaced by a ferrite bead. 3.3V VDD .01μF 10Ω VDDA .01μF 10μF FIGURE 1. POWER SUPPLY FILTERING CRYSTAL INPUT INTERFACE The ICS840002-01 has been characterized with 18pF parallel resonant crystals. The capacitor values shown in Figure 2 below were determined using a 25MHz 18pF parallel resonant crystal and were chosen to minimize the ppm error. XTAL_IN C1 22p X1 18pF Parallel Cry stal XTAL_OUT C2 22p ICS84332 ICS840002-01 Figure 2. CRYSTAL INPUt INTERFACE 840002AG-01 www.icst.com/products/hiperclocks.html 7 REV. B JANUARY 13, 2006 ICS840002-01 Integrated Circuit Systems, Inc. FEMTOCLOCKS™ CRYSTAL-TOLVCMOS/LVTTL FREQUENCY SYNTHESIZER RECOMMENDATIONS FOR UNUSED INPUT AND OUTPUT PINS INPUTS: OUTPUTS: CRYSTAL INPUT: For applications not requiring the use of the crystal oscillator input, both XTAL_IN and XTAL_OUT can be left floating. Though not required, but for additional protection, a 1kΩ resistor can be tied from XTAL_IN to ground. LVCMOS OUTPUT: All unused LVCMOS output can be left floating. We recommend that there is no trace attached. TEST_CLK INPUT: For applications not requiring the use of the test clock, it can be left floating. Though not required, but for additional protection, a 1kΩ resistor can be tied from the TEST_CLK to ground. LVCMOS CONTROL PINS: All control pins have internal pull-ups or pull-downs; additional resistance is not required but can be added for additional protection. A 1kΩ resistor can be used. LAYOUT GUIDELINE C2=22pF are recommended for frequency accuracy. For different board layout, the C1 and C2 may be slightly adjusted for optimizing frequency accuracy. 1KΩ pullup or pulldown resistors can be used for the logic control input pins. Figure 3 shows a schematic example of the ICS840002-01. An example of LVCMOS termination is shown in this schematic. Additional LVCMOS termination approaches are shown in the LVCMOS Termination Application Note. In this example, an 18 pF parallel resonant 25MHz crystal is used. The C1=22pF and Logic Control Input Examples Set Logic Input to '1' VDD RU1 1K Set Logic Input to '0' VDD R2 33 RU2 Not Install To Logic Input pins RD1 Not Install To Logic Input pins U1 RD2 1K VDD 1 2 3 4 5 6 7 8 VDDA R1 10 C3 10uF Zo = 50 Ohm VDD C4 0.01u LVCMOS FSEL0 XTAL_SEL TEST_CLK OE MR nPLL_SEL VDDA VDD 16 15 14 13 12 11 10 9 FSEL1 GND GND Q0 Q1 VDDO XTAL_IN XTAL_OUT VDD R3 100 C6 0.1u Zo = 50 Ohm C5 0.1u ICS840002-01 R4 100 XTAL2 If not using the crystal input, it can be left floating. For additional protection the XTAL_IN pin can be tied to ground. LVCMOS C2 22pF X1 XTAL1 Optional Termination C1 22pF Unused output can be left floating. There should no trace attached to unused output. Device characterized with all outputs terminated. FIGURE 3. ICS840002-01 SCHEMATIC EXAMPLE 840002AG-01 www.icst.com/products/hiperclocks.html 8 REV. B JANUARY 13, 2006 ICS840002-01 Integrated Circuit Systems, Inc. FEMTOCLOCKS™ CRYSTAL-TOLVCMOS/LVTTL FREQUENCY SYNTHESIZER RELIABILITY INFORMATION TABLE 6. θJAVS. AIR FLOW TABLE FOR 16 LEAD TSSOP θJA by Velocity (Linear Feet per Minute) Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards 0 200 500 137.1°C/W 89.0°C/W 118.2°C/W 81.8°C/W 106.8°C/W 78.1°C/W NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs. TRANSISTOR COUNT The transistor count for ICS840002-01 is: 3085 840002AG-01 www.icst.com/products/hiperclocks.html 9 REV. B JANUARY 13, 2006 ICS840002-01 Integrated Circuit Systems, Inc. PACKAGE OUTLINE - G SUFFIX FOR FEMTOCLOCKS™ CRYSTAL-TOLVCMOS/LVTTL FREQUENCY SYNTHESIZER 16 LEAD TSSOP TABLE 7. PACKAGE DIMENSIONS Millimeters SYMBOL Minimum N A Maximum 16 -- 1.20 A1 0.05 0.15 A2 0.80 1.05 b 0.19 0.30 c 0.09 0.20 D 4.90 5.10 E E1 6.40 BASIC 4.30 e 4.50 0.65 BASIC L 0.45 0.75 α 0° 8° aaa -- 0.10 Reference Document: JEDEC Publication 95, MO-153 840002AG-01 www.icst.com/products/hiperclocks.html 10 REV. B JANUARY 13, 2006 Integrated Circuit Systems, Inc. ICS840002-01 FEMTOCLOCKS™ CRYSTAL-TOLVCMOS/LVTTL FREQUENCY SYNTHESIZER TABLE 8. ORDERING INFORMATION Part/Order Number Marking Package Shipping Packaging Temperature ICS840002AG-01 40002A01 16 Lead TSSOP tube -30°C to 85°C ICS840002AG-01T 40002A01 16 Lead TSSOP 2500 tape & reel -30°C to 85°C ICS840002AG-01LF 0002A01L 16 Lead "Lead-Free" TSSOP tube -30°C to 85°C ICS840002AG-01LFT 0002A01L 16 Lead "Lead-Free" TSSOP 2500 tape & reel -30°C to 85°C NOTE: Par ts that are ordered with an "LF" suffix to the par t number are the Pb-Free configuration and are RoHS compliant. The aforementioned trademarks, HiPerClockS and FEMTOCLOCKS are trademarks of Integrated Circuit Systems, Inc. or its subsidiaries in the United States and/or other countries. While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or critical medical instruments. 840002AG-01 www.icst.com/products/hiperclocks.html 11 REV. B JANUARY 13, 2006 Integrated Circuit Systems, Inc. ICS840002-01 FEMTOCLOCKS™ CRYSTAL-TOLVCMOS/LVTTL FREQUENCY SYNTHESIZER REVISION HISTORY SHEET Rev B Table Page 1 T4 4 8 11 T8 840002AG-01 Description of Change Features Section - corrected the integration range from 1.875MHz - 175MHz to 1.875MHz - 20MHz in the RMS phase jitter bullet. Cr ystal Characteristics Table - added Drive Level. Added Recommendations for Unused Input and Output Pins. Ordering Information Table - corrected standard marking and added Lead-Free par t number, marking and note. www.icst.com/products/hiperclocks.html 12 Date 1/13/06 REV. B JANUARY 13, 2006