CS4361
20-pin, 24-bit, 192 kHz, 6-channel D/A Converter
Features
z Multi-bit
z 24-bit
Description
The CS4361 is a complete 6-channel digital-to-analog
output system including interpolation, multi-bit D/A
conversion, and output analog filtering in a small 20-pin
package. The CS4361 supports all major audio data
interface formats.
Delta-sigma Modulator
Conversion
z Automatically
detects sample rates up to
192 kHz.
z 105
dB Dynamic Range
z -95
dB THD+N
z Low
Clock Jitter Sensitivity
z +3.3
V or +5 V Core Power
z +1.8
V to +5 V Interface Power
z Filtered
Line Level Outputs
z On-chip
Digital De-emphasis
z Popguard™
z Mute
The CS4361 is based on a fourth order, multi-bit, deltasigma modulator with a linear analog low-pass filter. This
device also includes auto-speed mode detection using
both sample rate and master clock ratio as a method of
auto-selecting sampling rates between 2 kHz and
216 kHz.
The CS4361 contains on-chip digital de-emphasis, operates from a single +3.3 V or +5 V power supply with
separate built-in level shifter for the digital interface, and
requires minimal support circuitry. These features are
ideal for DVD players & recorders, digital televisions,
home theater and set top box products, and automotive
audio systems.
Technology
Output Control
z Small
20-pin TSSOP Package
ORDERING INFORMATION
See page 20
I
Serial Audio Port & Control Supply
(1.8 V to 5 V)
Analog & Digital Core Supply
(3.3 V to 5 V)
Internal Voltage
Reference
Mode Control
PCM Serial
Audio Input
Level Translator
Digital
De-emphasis
Auto-Speed
Detecting PCM Serial
Interface
6
Digital
Filters
Multi-bit ∆Σ
Modulators
External Mute
Control
+5 Volt-tolerant Reset
Advance Product Information
http://www.cirrus.com
Switch-Cap
DAC and
Analog Filters
6
Single-Ended
Outputs
(Six Channels)
Mute Control
This document contains information for a new product.
Cirrus Logic reserves the right to modify this product without notice.
Copyright © Cirrus Logic, Inc. 2005
(All Rights Reserved)
JAN ‘05
DS672A2
CS4361
Table 1. Revision History
Release
Date
A1
January 2005
A2
January 2005
Changes
Initial Release
Correction to PDF file size.
Contacting Cirrus Logic Support
For all product questions and inquiries contact a Cirrus Logic Sales Representative.
To find one nearest you go to www.cirrus.com
IMPORTANT NOTICE
"Advance" product information describes products that are in development and subject to development changes.
Cirrus Logic, Inc. and its subsidiaries ("Cirrus") believe that the information contained in this document is accurate and reliable. However, the information is subject
to change without notice and is provided "AS IS" without warranty of any kind (express or implied). Customers are advised to obtain the latest version of relevant
information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale
supplied at the time of order acknowledgment, including those pertaining to warranty, indemnification, and limitation of liability. No responsibility is assumed by
Cirrus for the use of this information, including use of this information as the basis for manufacture or sale of any items, or for infringement of patents or other rights
of third parties. This document is the property of Cirrus and by furnishing this information, Cirrus grants no license, express or implied under any patents, mask work
rights, copyrights, trademarks, trade secrets or other intellectual property rights. Cirrus owns the copyrights associated with the information contained herein and
gives consent for copies to be made of the information only for use within your organization with respect to Cirrus integrated circuits or other products of Cirrus. This
consent does not extend to other copying such as copying for general distribution, advertising or promotional purposes, or for creating any work for resale.
CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE ("CRITICAL APPLICATIONS"). CIRRUS PRODUCTS ARE NOT DESIGNED, AUTHORIZED OR WARRANTED FOR
USE IN AIRCRAFT SYSTEMS, MILITARY APPLICATIONS, PRODUCTS SURGICALLY IMPLANTED INTO THE BODY, AUTOMOTIVE SAFETY OR SECURITY
DEVICES, LIFE SUPPORT PRODUCTS OR OTHER CRITICAL APPLICATIONS. INCLUSION OF CIRRUS PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO BE FULLY AT THE CUSTOMER'S RISK AND CIRRUS DISCLAIMS AND MAKES NO WARRANTY, EXPRESS, STATUTORY OR IMPLIED, INCLUDING THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR PARTICULAR PURPOSE, WITH REGARD TO ANY CIRRUS PRODUCT THAT
IS USED IN SUCH A MANNER. IF THE CUSTOMER OR CUSTOMER'S CUSTOMER USES OR PERMITS THE USE OF CIRRUS PRODUCTS IN CRITICAL
APPLICATIONS, CUSTOMER AGREES, BY SUCH USE, TO FULLY INDEMNIFY CIRRUS, ITS OFFICERS, DIRECTORS, EMPLOYEES, DISTRIBUTORS AND
OTHER AGENTS FROM ANY AND ALL LIABILITY, INCLUDING ATTORNEYS' FEES AND COSTS, THAT MAY RESULT FROM OR ARISE IN CONNECTION
WITH THESE USES.
Cirrus Logic, Cirrus, and the Cirrus Logic logo designs are trademarks of Cirrus Logic, Inc. All other brand and product names in this document may be trademarks
or service marks of their respective owners.
2
DS672A2
CS4361
TABLE OF CONTENTS
1. PIN DESCRIPTIONS ................................................................................................................ 4
2. CHARACTERISTICS AND SPECIFICATIONS ........................................................................ 5
Specified Operating Conditions ................................................................................................ 5
Absolute Maximum Ratings ...................................................................................................... 5
DAC Analog Characteristics ..................................................................................................... 6
DAC Analog Characteristics - All Modes .................................................................................. 6
Combined Interpolation & On-chip Analog Filter Response ..................................................... 7
Digital Input Characteristics ...................................................................................................... 8
Power & Thermal Characteristics ............................................................................................. 8
Switching Characteristics - Serial Audio Interface .................................................................... 9
3. TYPICAL CONNECTION DIAGRAM ..................................................................................... 11
4. APPLICATIONS ..................................................................................................................... 12
4.1 Master Clock .................................................................................................................... 12
4.2 Serial Clock ..................................................................................................................... 12
4.2.1 External Serial Clock Mode ................................................................................. 12
4.2.2 Internal Serial Clock Mode .................................................................................. 13
4.3 De-Emphasis ................................................................................................................... 15
4.4 Mode Select ..................................................................................................................... 15
4.5 Initialization and Power-Down ......................................................................................... 15
4.6 Output Transient Control ................................................................................................. 17
4.6.1 Power-up ............................................................................................................. 17
4.6.2 Power-down ........................................................................................................ 17
4.7 Grounding and Power Supply Decoupling ....................................................................... 17
4.8 Analog Output and Filtering ............................................................................................. 17
4.9 Mute Control .................................................................................................................... 18
5. PARAMETER DEFINITIONS .................................................................................................. 19
6. ORDERING INFORMATION ..............................................................................................
20
7. PACKAGE DIMENSIONS ...................................................................................................... 20
8. APPENDIX
......................................................................................................................... 21
DS672A2
3
CS4361
1. PIN DESCRIPTIONS
VL
1
20
MUTEC
SDIN1
2
19
AOUT1
SDIN2
3
18
AOUT2
SDIN3
4
17
AOUT3
DEM/SCLK
5
AOUT4
LRCK
6
16
15
MCLK
7
14
GND
RST
8
13
AOUT5
MODE
9
12
AOUT6
FILT+
10
11
VQ
VA
Pin Name
#
Pin Description
SDIN1
SDIN2
SDIN3
2
3
4
Serial Audio Data Input (Input) - Input for two’s complement serial audio data.
DEM/SCLK
5
De-emphasis/External Serial Clock Input (Input) - used for de-emphasis filter control or external serial clock input.
LRCK
6
Left Right Clock (Input) - Determines which channel, Left or Right, is currently active on the
serial audio data line.
MCLK
7
Master Clock (Input) - Clock source for the delta-sigma modulator and digital filters.
VQ
11 Quiescent Voltage (Output) - Filter connection for internal quiescent voltage.
FILT+
10 Positive Voltage Reference (Output) - Positive reference voltage for the internal sampling
circuits.
AOUT1
AOUT2
AOUT3
AOUT4
AOUT5
AOUT6
19 Analog Output (Output) - The full scale analog output level is specified in the Analog Charac18 teristics specification table.
17
16
13
12
GND
14 Ground (Input) - ground reference.
VA
15 Analog Power (Input) - Positive power for the analog and core digital sections.
VL
1
Interface Power (Input) - Positive power for the digital interface level shifters.
RST
8
Reset (Input) - Applies reset to the internal circuitry when low.
MUTEC
20 Mute Control (Output) - Control signal for optional external muting circuitry.
MODE
9
4
Mode Control (Input) - Selects operational modes (see table 3).
DS672A2
CS4361
2.CHARACTERISTICS AND SPECIFICATIONS
All Min/Max characteristics and specifications are guaranteed over the specified operating conditions. Typical performance characteristics and specifications are derived from measurements taken at nominal supply voltage and
TA = 25°C.
SPECIFIED OPERATING CONDITIONS
AGND = 0 V; all voltages with respect to ground.
Parameters
Symbol
VA
VA
VL
DC Power Supply
Specified Temperature Range
-CZZ
-DZZ
TA
Min
4.75
3.0
1.7
-10
-40
Nom
5.0
3.3
3.3
-
Max
5.25
3.6
5.25
+70
+85
Units
V
V
°C
°C
ABSOLUTE MAXIMUM RATINGS
AGND = 0 V; all voltages with respect to ground.
Parameters
DC Power Supply
Input Current, Any Pin Except Supplies
Digital Input Voltage (pin 8, RST)
Digital Input Voltage (all other digital pins)
Ambient Operating Temperature (power applied)
Storage Temperature
Symbol
VA
VL
Iin
VIND
VIND
Top
Tstg
Min
-0.3
-0.3
-0.3
-0.3
-55
-65
Max
6.0
VA
±10
VA+0.4
VL+0.4
125
150
Units
V
V
mA
V
V
°C
°C
WARNING: Operation at or beyond these limits may result in permanent damage to the device. Normal operation is
not guaranteed at these extremes.
DS672A2
5
CS4361
DAC ANALOG CHARACTERISTICS
Full-scale output sine wave, 997 Hz (Note 1), Fs = 48/96/192 kHz; Test load RL = 3 kΩ, CL = 10 pF (see Figure 1).
Measurement bandwidth is 10 Hz to 20 kHz, unless otherwise specified.
5 V Nom
Parameter
Min
3.3 V Nom
Typ
Max
Min
Typ
Max
Unit
99
96
90
87
105
102
96
93
-
97
94
90
87
103
100
96
93
-
dB
dB
dB
dB
-
-95
-82
-42
-93
-73
-33
-89
-76
-36
-87
-67
-27
-
-95
-80
-40
-93
-73
-33
-89
-74
-34
-87
-67
-27
dB
dB
dB
dB
dB
dB
95
92
86
83
105
102
96
93
-
93
90
86
83
103
100
96
93
-
dB
dB
dB
dB
-
-95
-82
-42
-93
-73
-33
-85
-72
-32
-83
-63
-23
-
-95
-80
-40
-93
-73
-33
-85
-70
-30
-83
-63
-23
dB
dB
dB
dB
dB
dB
Dynamic Performance for CS4361-CZZ (-10 to 70°C)
Dynamic Range
18 to 24-Bit
16-Bit
A-weighted
unweighted
A-weighted
unweighted
Total Harmonic Distortion + Noise
18 to 24-Bit
0 dB
-20 dB
-60 dB
0 dB
-20 dB
-60 dB
16-Bit
Dynamic Performance for CS4361-DZZ (-40 to 85°C)
Dynamic Range
18 to 24-Bit
16-Bit
A-weighted
unweighted
A-weighted
unweighted
Total Harmonic Distortion + Noise
18 to 24-Bit
16-Bit
Note:
0 dB
-20 dB
-60 dB
0 dB
-20 dB
-60 dB
1. One-half LSB of triangular PDF dither added to data.
DAC ANALOG CHARACTERISTICS - ALL MODES
Parameter
Interchannel Isolation
Symbol
(1 kHz)
Min
Typ
Max
Unit
-
100
-
dB
DC Accuracy
Interchannel Gain Mismatch
-
0.1
0.25
dB
Gain Drift
-
100
-
ppm/°C
0.60•VA
0.65•VA
0.70•VA
Vpp
Analog Output
Full Scale Output Voltage
Quiescent Voltage
Max DC Current draw from an AOUT pin
Max Current draw from VQ
Min AC-Load Resistance (see Figure 2 on page 8)
Max Load Capacitance (see Figure 2)
Output Impedance
6
VQ
-
0.5•VA
-
VDC
IOUTmax
-
10
-
µA
IQmax
-
100
-
µA
RL
-
3
-
kΩ
CL
-
100
-
pF
ZOUT
-
100
-
Ω
DS672A2
CS4361
COMBINED INTERPOLATION & ON-CHIP ANALOG FILTER RESPONSE
The filter characteristics have been normalized to the sample rate (Fs) and can be referenced to the desired sample rate by multiplying the given characteristic by Fs. (See note 5)
Parameter
Symbol
Combined Digital and On-chip Analog Filter Response
Passband (Note 2)
StopBand
(Note 3)
Group Delay
De-emphasis Error (Note 4)
tgd
Fs = 44.1 kHz
Combined Digital and On-chip Analog Filter Response
Passband (Note 2)
to -0.1 dB corner
to -3 dB corner
StopBand
(Note 3)
Group Delay
tgd
Combined Digital and On-chip Analog Filter Response
Passband (Note 2)
to -0.1 dB corner
to -3 dB corner
StopBand
(Note 3)
Group Delay
Unit
0
0
-
.4780
.4996
Fs
Fs
-.01
-
+.08
dB
.5465
-
-
Fs
50
-
-
dB
-
10/Fs
-
s
-
-
+.05/-.25
dB
0
0
-
.4650
.4982
Fs
Fs
-.05
-
+.2
dB
.5770
-
-
Fs
55
-
-
dB
-
5/Fs
-
s
Quad Speed Mode
Frequency Response 10 Hz to 20 kHz
StopBand Attenuation
Max
Double Speed Mode
Frequency Response 10 Hz to 20 kHz
StopBand Attenuation
Typ
Single Speed Mode
to -0.05 dB corner
to -3 dB corner
Frequency Response 10 Hz to 20 kHz
StopBand Attenuation
Min
tgd
0
0
-
0.397
0.476
Fs
Fs
0
-
+0.00004
dB
0.7
-
-
Fs
51
-
-
dB
-
2.5/Fs
-
s
Notes: 2. Response is clock-dependent and will scale with Fs.
3. For Single Speed Mode, the measurement bandwidth is 0.5465 Fs to 3 Fs.
For Double Speed Mode, the measurement bandwidth is 0.577 Fs to 1.4 Fs.
For Quad Speed Mode, the measurement bandwidth is 0.7 Fs to 1 Fs.
4. De-emphasis is available only in Single Speed Mode.
5. Amplitude vs. Frequency plots of this data are available in “Appendix” on page 21.
DS672A2
7
CS4361
DIGITAL INPUT CHARACTERISTICS
Parameters
High-Level Input Voltage -all input Pins except RST
Low-Level Input Voltage -all input Pins except RST
High-Level Input Voltage -RST pin (Note 6)
Low-Level Input Voltage -RST pin
Input Leakage Current
Input Capacitance
Symbol
VIH
VIL
VIH
VIL
Iin
(% of VL)
(% of VL)
(% of VL)
(% of VL)
(Note 7)
Min
70%
90%
-
Typ
8
Max
30%
10%
±10
-
Units
V
V
V
V
µA
pF
6. RST pin has an input threshold relative to VL but is VA tolerant.
7. Iin for LRCK is ±20 µA max.
POWER & THERMAL CHARACTERISTICS
5 V Nom
Parameters
Symbol
Power Supplies
Power Supply Current
normal operation
IA
(Note 8)
IL
power-down state (Note 9)
IA
IL
Power Dissipation
normal operation
power-down state (Note 9)
Package Thermal Resistance
θJA
Power Supply Rejection Ratio (Note 10) (1 kHz) PSRR
(60 Hz)
3.3 V Nom
Min
Typ
Max
Min
Typ
Max
Units
-
66
0.1
300
26
331
1.63
72
60
40
90
1
455
-
-
48
0.1
180
24
159
0.67
72
60
40
63
1
211
-
mA
mA
µA
µA
mW
mW
°C/Watt
dB
dB
8. Current consumption increases with increasing FS and increasing MCLK. Typ and Max values are
based on highest FS and highest MCLK. Current variance between speed modes is small.
9. Power down mode is defined when all clock and data lines are held static.
10. Valid with the recommended capacitor values on VQ and FILT+ as shown in the typical connection
diagram in Section 3.
3.3 µF
V
o ut
AO U Tx
R
L
C
L
AG N D
Capacitive Load -- C L (pF)
125
100
75
25
2.5
3
Figure 1. Equivalent Output Test Load
8
Safe Operating
Region
50
5
10
15
20
Resistive Load -- RL (kΩ )
Figure 2. Maximum Loading
DS672A2
CS4361
SWITCHING CHARACTERISTICS - SERIAL AUDIO INTERFACE
Parameters
Symbol
Min
Typ
Max
Units
MCLK Frequency
0.512
-
50
MHz
MCLK Duty Cycle
45
-
55
%
216
54
134
67
34
108
216
216
kHz
kHz
kHz
kHz
kHz
kHz
kHz
kHz
Fs
2
2
84
42
30
50
100
168
45
50
55
%
SCLK Pulse Width Low
tsclkl
20
-
-
ns
SCLK Pulse Width High
tsclkh
20
-
-
ns
45
50
55
%
Input Sample Rate
(Note 11)
All MCLK/LRCK ratios combined
256x, 384x, 1024x
256x, 384x
512x, 768x
1152x
128x, 192x
64x, 96x
128x, 192x
External SCLK Mode
LRCK Duty Cycle (External SCLK only)
SCLK Duty Cycle
SCLK rising to LRCK edge delay
tslrd
20
-
-
ns
SCLK rising to LRCK edge setup time
tslrs
20
-
-
ns
SDIN valid to SCLK rising setup time
tsdlrs
20
-
-
ns
SCLK rising to SDIN hold time
tsdh
20
-
-
ns
-
50
-
%
-
-
ns
-
µs
-
-
ns
-
-
ns
-
-
ns
Internal SCLK Mode
LRCK Duty Cycle (Internal SCLK only)
(Note 12)
SCLK Period
(Note 13)
tsclkw
SCLK rising to LRCK edge
tsclkr
SDIN valid to SCLK rising setup time
tsdlrs
SCLK rising to SDIN hold time
MCLK / LRCK =1152, 1024, 512, 256, 128, or 64
tsdh
SCLK rising to SDIN hold time
MCLK / LRCK = 768, 384, 192, or 96
tsdh
10 9
----------------SCLK
-
tsclkw
-----------------2
10 9
---------------------- + 10
( 512 )Fs
10 9
---------------------- + 15
( 512 )Fs
10 9
---------------------- + 15
( 384 )Fs
Notes: 11. Not all sample rates are supported for all clock ratios. See table “Common Clock Frequencies” on
page 12 for supported ratios and frequencies.
12. In Internal SCLK Mode, the duty cycle must be 50% ± 1/2 MCLK period.
13. The SCLK / LRCK ratio may be either 32, 48, 64, or 72. This ratio depends on data format and
MCLK/LRCK ratio. (See figures 7-10)
DS672A2
9
CS4361
LRCK
t sclkh
t slrs
t slrd
t sclkl
SCLK
t sdh
t sdlrs
SDATA
Figure 3. External Serial Mode Input Timing
LR C K
t s clkr
S D A TA
t sclkw
t sdlrs
t sdh
*IN TE R N AL S C L K
Figure 4. Internal Serial Mode Input Timing
* The SCLK pulses shown are internal to the CS4361.
LRCK
MCLK
1
N
2
N
*INTERNAL SCLK
SDATA
Figure 5. Internal Serial Clock Generation
* The SCLK pulses shown are internal to the CS4361.
N equals MCLK divided by SCLK
10
DS672A2
CS4361
3. TYPICAL CONNECTION DIAGRAM
+1.8 V to +5 V
+3.3 V to +5 V
+
15
1
3
Audio
Data
Processor
4
5
6
1 µF
VA
VL
2
0.1 µF
Note*
SDIN1
AOUT1
AOUT2
AOUT3
AOUT4
AOUT5
AOUT6
SDIN2
SDIN3
DEM/SCLK
LRCK
MUTEC
19
18
17
16
13
12
3.3 µF
470Ω
Audio Output
+
C
10 kΩ
Optional
Muting
Circuit
Rext
20
CS4361
Rext + 470
For best 20 kHz response
4πFs(Rext 470)
Note* = This circuitry is intended for applications where the CS4361 connects
directly to an unbalanced output of the design. For internal routing applications
please see the DAC analog output characteristics for loading limitations.
C=
External Clock
µControler
7
8
MCLK
RST
FILT+
10
+
33 µF
VL I2S
LRCK
MCLK
RJ24
MODE
GND
14
GND LJ
VQ
11
+
RJ16
9
0.1 µF
*3.3 µF
or
*10 µF
*Popguard ramp can be adjusted by selecting
this capacitor value to be 3.3 µF to give 250 ms
ramp time or 10 µF to give a 420 ms ramp time.
Figure 6. Recommended Connection Diagram
DS672A2
11
CS4361
4.APPLICATIONS
The CS4361 accepts data at standard audio sample rates including 48, 44.1 and 32 kHz in SSM, 96, 88.2 and
64 kHz in DSM, and 192, 176.4 and 128 kHz in QSM. Audio data is input via the serial data input pin (SDIN). The
Left/Right Clock (LRCK) determines which channel is currently being input on SDIN, and the optional Serial Clock
(SCLK) clocks audio data into the input data buffer.
4.1 Master Clock
MCLK/LRCK must be an integer ratio as shown in Table 2. The LRCK frequency is equal to Fs, the frequency at
which words for each channel are input to the device. The MCLK-to-LRCK frequency ratio and speed mode is detected automatically during the initialization sequence by counting the number of MCLK transitions during a single
LRCK period and by detecting the absolute speed of MCLK. Internal dividers are set to generate the proper clocks.
Table 2 illustrates several standard audio sample rates and the required MCLK and LRCK frequencies. Please note
there is no required phase relationship, but MCLK, LRCK, and SCLK must be synchronous.
LRCK
64x
96x
128x
(kHz)
32
44.1
48
64
8.1920
88.2
11.2896
96
12.2880
128
8.1920 12.2880
176.4 11.2896 16.9344 22.5792
192
12.2880 18.4320 24.5760
Mode
QSM
192x
12.2880
16.9344
18.4320
33.8680
36.8640
MCLK (MHz)
256x
384x
8.1920 12.2880
11.2896 16.9344
12.2880 18.4320
22.5792 33.8680
24.5760 36.8640
32.7680 49.1520
DSM
512x
22.5792
24.5760
32.7680
-
768x
1024x
32.7680
33.8680 45.1580
36.8640 49.1520
49.1520
SSM
1152x
36.8640
-
Table 2. Common Clock Frequencies
4.2 Serial Clock
The serial clock controls the shifting of data into the input data buffers. The CS4361 supports both external and internal serial clock generation modes. Refer to Figures 7-10 for data formats.
4.2.1 External Serial Clock Mode
The CS4361 will enter the External Serial Clock Mode when 16 low-to-high transitions are detected on the
DEM/SCLK pin during any phase of the LRCK period. When this mode is enabled, the Internal Serial Clock
Mode and de-emphasis filter cannot be accessed. The CS4361 will switch to Internal Serial Clock Mode if no
low-to-high transitions are detected on the DEM/SCLK pin for two consecutive frames of LRCK. Refer to
Figure 12.
12
DS672A2
CS4361
4.2.2 Internal Serial Clock Mode
In the Internal Serial Clock Mode, the serial clock is internally derived and synchronous with MCLK and LRCK.
The SCLK/LRCK frequency ratio is either 32, 48, 64, or 72 depending upon data format. Operation in this mode
is identical to operation with an external serial clock synchronized with LRCK. This mode allows access to the
digital de-emphasis function. Refer to Figures 7 - 12 for details.
Le ft C ha n nel
LR C K
R ig h t C ha n nel
SCLK
SDATA
MSB -1 -2 -3 -4 -5
+5 +4 +3 +2 +1 LSB
MSB -1 -2 -3 -4
Internal SCLK Mode
+5 +4 +3 +2 +1 LSB
External SCLK Mode
2
I S, 16-Bit data and INT SCLK = 32 Fs if
MCLK/LRCK = 1024, 512, 256, 128, or 64
I2S, Up to 24-Bit data and INT SCLK = 48 Fs if
MCLK/LRCK = 768, 384, 192, or 96
I2S, Up to 24-Bit data and INT SCLK = 72 Fs if
MCLK/LRCK = 1152
2
I S, up to 24-Bit Data
Data Valid on Rising Edge of SCLK
Figure 7. CS4361 Data Format (I2S)
Le ft C ha n nel
LR C K
R ig h t C ha n nel
SCLK
SDATA
M SB -1 -2 -3 -4 -5
+5 +4 +3 +2 +1 LS B
Internal SCLK Mode
Left Justified, up to 24-Bit Data
INT SCLK = 64 Fs if
MCLK/LRCK = 1024, 512, 256, 128, or 64
INT SCLK = 48 Fs if
MCLK/LRCK = 768, 384, 192, or 96
INT SCLK = 72 Fs if
MCLK/LRCK = 1152
M SB -1 -2 -3 -4
+5 +4 +3 +2 +1 LS B
External SCLK Mode
Left Justified, up to 24-Bit Data
Data Valid on Rising Edge of SCLK
Figure 8. CS4361 Data Format (Left Justified)
DS672A2
13
CS4361
LR C K
R igh t C h ann el
Le ft C ha n nel
SCLK
SDATA
0
7
23 22 21 20 19 18
6
5
4
3
2
1
0
32 clocks
Internal SCLK Mode
7
23 22 21 20 19 18
6
5
4
3
2
1
0
External SCLK Mode
Right Justified, 24-Bit Data
Data Valid on Rising Edge of SCLK
SCLK Must Have at Least 48 Cycles per LRCK Period
Right Justified, 24-Bit Data
INT SCLK = 64 Fs if
MCLK/LRCK = 1024, 512, 256, 128, or 64
INT SCLK = 48 Fs if
MCLK/LRCK = 768, 384, 192, or 96
INT SCLK = 72 Fs if
MCLK/LRCK = 1152
Figure 9. CS4361 Data Format (Right Justified 24)
LR CK
R ig ht C h a n ne l
L e ft C h a nn e l
SCLK
SDATA
15 14 13 12 11 10
9
8
7
Internal32SCLK
Mode
clocks
Right Justified, 16-Bit Data
INT SCLK = 32 Fs if
MCLK/LRCK = 1024, 512, 256, 128, or 64
INT SCLK = 48 Fs if
MCLK/LRCK = 768, 384, 192, or 96
INT SCLK = 72 Fs if
MCLK/LRCK = 1152
6
5
4
3
2
1
0
15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
External SCLK Mode
Right Justified, 16-Bit Data
Data Valid on Rising Edge of SCLK
SCLK Must Have at Least 32 Cycles per LRCK Period
Figure 10. CS4361 Data Format (Right Justified 16)
14
DS672A2
CS4361
4.3 De-Emphasis
The CS4361 includes on-chip digital de-emphasis. Figure 11 shows the de-emphasis curve for Fs equal to 44.1 kHz.
The frequency response of the de-emphasis curve will scale proportionally with changes in sample rate, Fs.
The de-emphasis filter is active (inactive) if the DEM/SCLK pin is low (high) for five consecutive falling edges of
LRCK. This function is available only in the internal serial clock mode when LRCK < 50 kHz.
Gain
dB
T1=50 µs
0dB
T2 = 15 µs
-10dB
F1
3.183 kHz
F2
Frequency
10.61 kHz
Figure 11. De-Emphasis Curve (Fs = 44.1kHz)
4.4 Mode Select
Mode selection is determined by the Mode Select pin. The value of this pin is locked 1024 LRCK cycles after RST
is released. This pin requires a specific connection to supply, ground, MCLK, or LRCK as outlined in table 3.
.
Mode pin is:
Tied to VL
Tied to GND
Tied to LRCK
Tied to MCLK
Mode
I2S
Left Justified
Right Justified - 24 bit
Right Justified - 16bit
Figure
7
8
9
10
Table 3. Mode pin settings
4.5 Initialization and Power-Down
The initialization and power-down sequence flow chart is shown in Figure 12. The CS4361 enters the power-down
state upon initial power-up. The interpolation filters and delta-sigma modulators are reset, and the internal voltage
reference, multi-bit digital-to-analog converters, and switched-capacitor low-pass filters are powered down. The device will remain in the power-down mode until RST is released and MCLK and LRCK are present. Once MCLK and
LRCK are detected, MCLK occurrences are counted over one LRCK period to determine the MCLK/LRCK frequency
ratio. Power is then applied to the internal voltage reference. Finally, power is applied to the D/A converters and
switched-capacitor filters, and the analog outputs will ramp to the quiescent voltage, VQ.
DS672A2
15
CS4361
USER: Apply Power
VQ and outputs
ramp down
Power-Down State
VQ and outputs
ramp down
VQ and outputs low
USER: Apply MCLK, release RST
USER: Apply RST
USER: Apply RST
VQ and outputs ramp up
USER: Remove
LRCK or MCLK
USER: Remove
LRCK or MCLK
Wait State
USER: Apply LRCK and MCLK
USER: change
MCLK/LRCK ratio
MCLK/LRCK Ratio Detection
USER: change
MCLK/LRCK ratio
USER: No SCLK
USER: Applied SCLK
SCLK mode = internal
SCLK mode = external
Normal Operation
De-emphasis
available
Normal Operation
De-emphasis
not available
Analog Output
is Generated
Analog Output
is Generated
Figure 12. CS4361 Initialization and Power-Down Sequence
16
DS672A2
CS4361
4.6 Output Transient Control
The CS4361 uses Popguard™ technology to minimize the effects of output transients during power-up and powerdown. When implemented with external DC-blocking capacitors connected in series with the audio outputs, this feature eliminates the audio transients commonly produced by single-ended, single-supply converters. To make best
use of this feature, it is necessary to understand its operation.
4.6.1 Power-up
When the device is initially powered-up, the audio outputs, AOUT1-6 are clamped to VQ which is initially low.
After RST is released and MCLK is applied, the outputs begin to ramp with VQ towards the nominal quiescent
voltage. This ramp takes approximately 200 ms to complete. The gradual voltage ramping allows time for the
external DC-blocking capacitors to charge to VQ, effectively blocking the quiescent DC voltage. Audio output
begins approximately 2000 sample periods after valid LRCK and SDIN are supplied (and SCLK, if used).
4.6.2 Power-down
To prevent audio transients at power-down, the DC-blocking capacitors must fully discharge before turning off
the power. In order to do this RST should be held low for a period of about 250 ms before removing power. During this time voltage on VQ and the audio outputs discharge gradually to GND. If power is removed before this
250 ms time period has passed a transient will occur when the VA supply drops below that of VQ. There is no
minimum time for a power cycle, power may be re-applied at any time.
When changing clock ratio or sample rate it is recommended that zero data (or near zero data) be present on SDIN
for at least 10 LRCK samples before the change is made. During the clocking change the DAC outputs will always
be in a zero data state. If non-zero audio is present at the time of switching, a slight click or pop may be heard as
the DAC output automatically goes to its zero data state.
4.7 Grounding and Power Supply Decoupling
As with any high resolution converter, the CS4361 requires careful attention to power supply and grounding arrangements to optimize performance. Figure 6 shows the recommended power arrangement with VA connected to a clean
+3.3 V or +5 V supply. For best performance, decoupling and filter capacitors should be located as close to the device package as possible, with the smallest capacitors placed closest.
4.8 Analog Output and Filtering
The analog filter present in the CS4361 is a switched-capacitor filter followed by a continuous-time, low-pass filter.
Its response, combined with that of the digital interpolator, is given in Figures 14 - 21. The recommended external
analog circuitry is shown in the “Typical Connection Diagram” on page 11.
The analog outputs are named AOUT1-6. The SDIN1 feeds AOUT1 as the ‘Left’ marked data and AOUT2 as the
‘Right’ marked data. The SDIN2 feeds AOUT3 as the ‘Left’ marked data and AOUT4 as the ‘Right’ marked data. The
SDIN3 feeds AOUT5 as the ‘Left’ marked data and AOUT6 as the ‘Right’ marked data.
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CS4361
4.9 Mute Control
The MUTEC pin is intended to be used as control for an external mute circuit in order to add off-chip mute capability.
This pin becomes active under the following conditions.
1) during power-up initialization
2) upon reset
3) if the MCLK to LRCK ratio is incorrect
4) upon receipt of 8192 consecutive samples of zero
5) during power-down.
The MUTEC pin will only go active on static zero data only if all 6 channels satisfy the 8192 sample requirement. If
any channel receives non-zero data then the mute pin will return low (inactive).
Use of the mute control function is not mandatory but is recommended for designs requiring the absolute minimum
in extraneous clicks and pops. Also, use of the mute control function can enable the system designer to achieve idle
channel noise & signal-to-noise ratios which are only limited by the external mute circuit. The MUTEC pin is an active-high CMOS driver. See Figure 13 below for a suggested active-high mute circuit.
AC
Couple
470 Ω
A udio
O ut
AO UT
6
10 kΩ
Filter
Cap
47 kΩ
C S 4361
+V A
MMU N 2111LT1
2 kΩ
MU TE C
6
10 kΩ
(Low R on)
MMU N 2211LT1
-V
(if a va ila ble )
Figure 13. Suggested Active-low Mute Circuit
18
DS672A2
CS4361
5.PARAMETER DEFINITIONS
Total Harmonic Distortion + Noise (THD+N)
The ratio of the rms value of the signal to the rms sum of all other spectral components over the specified
bandwidth (typically 10 Hz to 20 kHz), including distortion components. Expressed in decibels.
Dynamic Range
The ratio of the full scale rms value of the signal to the rms sum of all other spectral components over the
specified bandwidth. Dynamic range is a signal-to-noise measurement over the specified bandwidth
made with a -60 dBFS signal. 60 dB is then added to the resulting measurement to refer the measurement
to full scale. This technique ensures that the distortion components are below the noise level and do not
effect the measurement. This measurement technique has been accepted by the Audio Engineering Society, AES17-1991, and the Electronic Industries Association of Japan, EIAJ CP-307.
Interchannel Isolation
A measure of crosstalk between the left and right channels. Measured for each channel at the converter's
output with all zeros to the input under test and a full-scale signal applied to the other channel. Units in
decibels.
Interchannel Gain Mismatch
The gain difference between left and right channels. Units in decibels.
Gain Error
The deviation from the nominal full scale analog output for a full scale digital input.
Gain Drift
The change in gain value with temperature. Units in ppm/°C.
DS672A2
19
CS4361
6.ORDERING INFORMATION
Model
CS4361-CZZ
CS4361-DZZ
Temperature
-10 to +70 °C
-40 to +85 °C
Package
20-pin Plastic TSSOP - Lead-Free
20-pin Plastic TSSOP - Lead-Free
7.PACKAGE DIMENSIONS
20L TSSOP (4.4 mm BODY) PACKAGE DRAWING
N
D
E11
A2
E
A
∝
e
b2
SIDE VIEW
A1
END VIEW
L
SEATING
PLANE
1 2 3
TOP VIEW
INCHES
DIM
A
A1
A2
b
D
E
E1
e
L
∝
MIN
-0.002
0.03346
0.00748
0.252
0.248
0.169
-0.020
0°
NOM
-0.004
0.0354
0.0096
0.256
0.2519
0.1732
-0.024
4°
MILLIMETERS
MAX
0.043
0.006
0.037
0.012
0.259
0.256
0.177
0.026
0.028
8°
MIN
-0.05
0.85
0.19
6.40
6.30
4.30
-0.50
0°
NOM
--0.90
0.245
6.50
6.40
4.40
-0.60
4°
NOTE
MAX
1.10
0.15
0.95
0.30
6.60
6.50
4.50
0.65
0.70
8°
2,3
1
1
JEDEC #: MO-153
Controlling Dimension is Millimeters.
Notes: 1. “D” and “E1” are reference datums and do not included mold flash or protrusions, but do include mold
mismatch and are measured at the parting line, mold flash or protrusions shall not exceed 0.20 mm per
side.
2. Dimension “b” does not include dambar protrusion/intrusion. Allowable dambar protrusion shall be
0.13 mm total in excess of “b” dimension at maximum material condition. Dambar intrusion shall not
reduce dimension “b” by more than 0.07 mm at least material condition.
3. These dimensions apply to the flat section of the lead between 0.10 and 0.25 mm from lead tips.
20
DS672A2
CS4361
8.APPENDIX
Figure 14. Single Speed Stopband Rejection
Figure 15. Single Speed Transition Band
Figure 16. Single Speed Transition Band
Figure 17. Single Speed Passband Ripple
DS672A2
21
CS4361
Figure 18. Double Speed Stopband Rejection
Figure 20. Double Speed Transition Band
22
Figure 19. Double Speed Transition Band
Figure 21. Double Speed Passband Ripple
DS672A2
CS4361
0
0
-10
-10
-20
-20
-30
Amplitude (dB)
Amplitude (dB)
-40
-50
-60
-30
-40
-70
-50
-80
-60
-90
-100
0
0.1
0.2
0.3
0.4
0.5
0.6
Frequency(normalized to Fs)
0.7
0.8
0.9
1
0.35
Figure 22. Quad Speed Stopband Rejection
0.4
0.45
0.5
0.55
0.6
Frequency(normalized to Fs)
0.65
0.7
0.75
Figure 23. Quad Speed Transition Band
0
0.2
-5
0.15
-10
0.1
0.05
-20
Amplitude (dB)
Amplitude (dB)
-15
-25
-30
0
-0.05
-35
-0.1
-40
-0.15
-45
-0.2
-50
0.4
0.45
0.5
0.55
0.6
Frequency(normalized to Fs)
0.65
Figure 24. Quad Speed Transition Band
DS672A2
0.7
0.05
0.1
0.15
0.2
0.25
0.3
Frequency(normalized to Fs)
0.35
0.4
0.45
Figure 25. Quad Speed Passband Ripple
23